2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
32 #include "c11/threads.h"
33 #include "compiler/shader_enums.h"
34 #include "compiler/nir/nir.h"
35 #include "util/bitscan.h"
41 /* driver param indices: */
42 enum ir3_driver_param
{
43 /* compute shader driver params: */
44 IR3_DP_NUM_WORK_GROUPS_X
= 0,
45 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
46 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
47 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
48 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
49 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
50 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
51 * glDispatchComputeIndirect() needs to load these from
52 * the info->indirect buffer. Keep that in mind when/if
53 * adding any addition CS driver params.
55 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
57 /* vertex shader driver params: */
58 IR3_DP_VTXID_BASE
= 0,
59 IR3_DP_VTXCNT_MAX
= 1,
60 /* user-clip-plane components, up to 8x vec4's: */
64 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
67 #define IR3_MAX_SHADER_BUFFERS 32
68 #define IR3_MAX_SHADER_IMAGES 32
69 #define IR3_MAX_SO_BUFFERS 4
70 #define IR3_MAX_SO_OUTPUTS 64
71 #define IR3_MAX_CONSTANT_BUFFERS 32
75 * Describes the layout of shader consts. This includes:
76 * + Driver lowered UBO ranges
78 * + Image sizes/dimensions
79 * + Driver params (ie. IR3_DP_*)
80 * + TFBO addresses (for generations that do not have hardware streamout)
81 * + Lowered immediates
83 * For consts needed to pass internal values to shader which may or may not
84 * be required, rather than allocating worst-case const space, we scan the
85 * shader and allocate consts as-needed:
87 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
90 * + Image dimensions: needed to calculate pixel offset, but only for
91 * images that have a image_store intrinsic
93 * Layout of constant registers, each section aligned to vec4. Note
94 * that pointer size (ubo, etc) changes depending on generation.
99 * if (vertex shader) {
100 * driver params (IR3_DP_*)
101 * if (stream_output.num_outputs > 0)
102 * stream-out addresses
103 * } else if (compute_shader) {
104 * driver params (IR3_DP_*)
108 * Immediates go last mostly because they are inserted in the CP pass
109 * after the nir -> ir3 frontend.
111 * Note UBO size in bytes should be aligned to vec4
113 struct ir3_const_state
{
115 unsigned num_driver_params
; /* scalar */
118 /* user const start at zero */
120 /* NOTE that a3xx might need a section for SSBO addresses too */
123 unsigned driver_param
;
125 unsigned primitive_param
;
126 unsigned primitive_map
;
131 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
132 uint32_t count
; /* number of consts allocated */
133 /* one const allocated per SSBO which has get_buffer_size,
134 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
137 uint32_t off
[IR3_MAX_SHADER_BUFFERS
];
141 uint32_t mask
; /* bitmask of images that have image_store */
142 uint32_t count
; /* number of consts allocated */
143 /* three const allocated per image which has image_store:
144 * + cpp (bytes per pixel)
146 * + array_pitch (z pitch)
148 uint32_t off
[IR3_MAX_SHADER_IMAGES
];
151 unsigned immediate_idx
;
152 unsigned immediates_count
;
153 unsigned immediates_size
;
160 * A single output for vertex transform feedback.
162 struct ir3_stream_output
{
163 unsigned register_index
:6; /**< 0 to 63 (OUT index) */
164 unsigned start_component
:2; /** 0 to 3 */
165 unsigned num_components
:3; /** 1 to 4 */
166 unsigned output_buffer
:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
167 unsigned dst_offset
:16; /**< offset into the buffer in dwords */
168 unsigned stream
:2; /**< 0 to 3 */
172 * Stream output for vertex transform feedback.
174 struct ir3_stream_output_info
{
175 unsigned num_outputs
;
176 /** stride for an entire vertex for each buffer in dwords */
177 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
180 * Array of stream outputs, in the order they are to be written in.
181 * Selected components are tightly packed into the output buffer.
183 struct ir3_stream_output output
[IR3_MAX_SO_OUTPUTS
];
188 * Starting from a4xx, HW supports pre-dispatching texture sampling
189 * instructions prior to scheduling a shader stage, when the
190 * coordinate maps exactly to an output of the previous stage.
194 * There is a limit in the number of pre-dispatches allowed for any
197 #define IR3_MAX_SAMPLER_PREFETCH 4
200 * This is the output stream value for 'cmd', as used by blob. It may
201 * encode the return type (in 3 bits) but it hasn't been verified yet.
203 #define IR3_SAMPLER_PREFETCH_CMD 0x4
206 * Stream output for texture sampling pre-dispatches.
208 struct ir3_sampler_prefetch
{
214 uint8_t half_precision
;
219 /* Configuration key used to identify a shader variant.. different
220 * shader variants can be used to implement features not supported
221 * in hw (two sided color), binning-pass vertex shader, etc.
223 struct ir3_shader_key
{
227 * Combined Vertex/Fragment shader parameters:
229 unsigned ucp_enables
: 8;
231 /* do we need to check {v,f}saturate_{s,t,r}? */
232 unsigned has_per_samp
: 1;
235 * Vertex shader variant parameters:
237 unsigned vclamp_color
: 1;
240 * Fragment shader variant parameters:
242 unsigned sample_shading
: 1;
244 unsigned color_two_side
: 1;
245 unsigned half_precision
: 1;
246 /* used when shader needs to handle flat varyings (a4xx)
247 * for front/back color inputs to frag shader:
249 unsigned rasterflat
: 1;
250 unsigned fclamp_color
: 1;
252 /* Indicates that this is a tessellation pipeline which requires a
253 * whole different kind of vertex shader. In case of
254 * tessellation, this field also tells us which kind of output
255 * topology the TES uses, which the TCS needs to know.
257 #define IR3_TESS_NONE 0
258 #define IR3_TESS_TRIANGLES 1
259 #define IR3_TESS_QUADS 2
260 #define IR3_TESS_ISOLINES 3
261 unsigned tessellation
: 2;
268 /* bitmask of sampler which needs coords clamped for vertex
271 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
273 /* bitmask of sampler which needs coords clamped for frag
276 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
278 /* bitmask of ms shifts */
279 uint32_t vsamples
, fsamples
;
281 /* bitmask of samplers which need astc srgb workaround: */
282 uint16_t vastc_srgb
, fastc_srgb
;
286 ir3_shader_key_equal(struct ir3_shader_key
*a
, struct ir3_shader_key
*b
)
288 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
289 if (a
->has_per_samp
|| b
->has_per_samp
)
290 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
291 return a
->global
== b
->global
;
294 /* will the two keys produce different lowering for a fragment shader? */
296 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
298 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
299 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
300 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
301 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
302 (last_key
->fsamples
!= key
->fsamples
) ||
303 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
307 if (last_key
->fclamp_color
!= key
->fclamp_color
)
310 if (last_key
->color_two_side
!= key
->color_two_side
)
313 if (last_key
->half_precision
!= key
->half_precision
)
316 if (last_key
->rasterflat
!= key
->rasterflat
)
319 if (last_key
->ucp_enables
!= key
->ucp_enables
)
325 /* will the two keys produce different lowering for a vertex shader? */
327 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
329 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
330 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
331 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
332 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
333 (last_key
->vsamples
!= key
->vsamples
) ||
334 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
338 if (last_key
->vclamp_color
!= key
->vclamp_color
)
341 if (last_key
->ucp_enables
!= key
->ucp_enables
)
347 /* clears shader-key flags which don't apply to the given shader
351 ir3_normalize_key(struct ir3_shader_key
*key
, gl_shader_stage type
)
354 case MESA_SHADER_FRAGMENT
:
355 if (key
->has_per_samp
) {
356 key
->vsaturate_s
= 0;
357 key
->vsaturate_t
= 0;
358 key
->vsaturate_r
= 0;
361 key
->has_gs
= false; /* FS doesn't care */
362 key
->tessellation
= IR3_TESS_NONE
;
365 case MESA_SHADER_VERTEX
:
366 case MESA_SHADER_GEOMETRY
:
367 key
->color_two_side
= false;
368 key
->half_precision
= false;
369 key
->rasterflat
= false;
370 if (key
->has_per_samp
) {
371 key
->fsaturate_s
= 0;
372 key
->fsaturate_t
= 0;
373 key
->fsaturate_r
= 0;
378 /* VS and GS only care about whether or not we're tessellating. */
379 key
->tessellation
= !!key
->tessellation
;
381 case MESA_SHADER_TESS_CTRL
:
382 case MESA_SHADER_TESS_EVAL
:
383 key
->color_two_side
= false;
384 key
->half_precision
= false;
385 key
->rasterflat
= false;
386 if (key
->has_per_samp
) {
387 key
->fsaturate_s
= 0;
388 key
->fsaturate_t
= 0;
389 key
->fsaturate_r
= 0;
392 key
->vsaturate_s
= 0;
393 key
->vsaturate_t
= 0;
394 key
->vsaturate_r
= 0;
406 * On a4xx+a5xx, Images share state with textures and SSBOs:
408 * + Uses texture (cat5) state/instruction (isam) to read
409 * + Uses SSBO state and instructions (cat6) to write and for atomics
411 * Starting with a6xx, Images and SSBOs are basically the same thing,
412 * with texture state and isam also used for SSBO reads.
414 * On top of that, gallium makes the SSBO (shader_buffers) state semi
415 * sparse, with the first half of the state space used for atomic
416 * counters lowered to atomic buffers. We could ignore this, but I
417 * don't think we could *really* handle the case of a single shader
418 * that used the max # of textures + images + SSBOs. And once we are
419 * offsetting images by num_ssbos (or visa versa) to map them into
420 * the same hardware state, the hardware state has become coupled to
421 * the shader state, so at this point we might as well just use a
422 * mapping table to remap things from image/SSBO idx to hw idx.
424 * To make things less (more?) confusing, for the hw "SSBO" state
425 * (since it is really both SSBO and Image) I'll use the name "IBO"
427 struct ir3_ibo_mapping
{
428 #define IBO_INVALID 0xff
429 /* Maps logical SSBO state to hw state: */
430 uint8_t ssbo_to_ibo
[IR3_MAX_SHADER_BUFFERS
];
431 uint8_t ssbo_to_tex
[IR3_MAX_SHADER_BUFFERS
];
433 /* Maps logical Image state to hw state: */
434 uint8_t image_to_ibo
[IR3_MAX_SHADER_IMAGES
];
435 uint8_t image_to_tex
[IR3_MAX_SHADER_IMAGES
];
437 /* Maps hw state back to logical SSBO or Image state:
439 * note IBO_SSBO ORd into values to indicate that the
440 * hw slot is used for SSBO state vs Image state.
442 #define IBO_SSBO 0x80
443 uint8_t ibo_to_image
[32];
444 uint8_t tex_to_image
[32];
447 uint8_t num_tex
; /* including real textures */
448 uint8_t tex_base
; /* the number of real textures, ie. image/ssbo start here */
451 /* Represents half register in regid */
452 #define HALF_REG_ID 0x100
454 struct ir3_shader_variant
{
457 /* variant id (for debug) */
460 struct ir3_shader_key key
;
462 /* vertex shaders can have an extra version for hwbinning pass,
463 * which is pointed to by so->binning:
467 struct ir3_shader_variant
*binning
;
468 struct ir3_shader_variant
*nonbinning
;
471 struct ir3_info info
;
474 /* Levels of nesting of flow control:
476 unsigned branchstack
;
481 /* the instructions length is in units of instruction groups
482 * (4 instructions for a3xx, 16 instructions for a4xx.. each
483 * instruction is 2 dwords):
487 /* the constants length is in units of vec4's, and is the sum of
488 * the uniforms and the built-in compiler constants
493 * + Let the frag shader determine the position/compmask for the
494 * varyings, since it is the place where we know if the varying
495 * is actually used, and if so, which components are used. So
496 * what the hw calls "outloc" is taken from the "inloc" of the
498 * + From the vert shader, we only need the output regid
501 bool frag_coord
, frag_face
, color0_mrt
;
503 /* NOTE: for input/outputs, slot is:
504 * gl_vert_attrib - for VS inputs
505 * gl_varying_slot - for VS output / FS input
506 * gl_frag_result - for FS output
509 /* varyings/outputs: */
510 unsigned outputs_count
;
515 } outputs
[32 + 2]; /* +POSITION +PSIZE */
516 bool writes_pos
, writes_smask
, writes_psize
;
518 /* attributes (VS) / varyings (FS):
519 * Note that sysval's should come *after* normal inputs.
521 unsigned inputs_count
;
526 /* location of input (ie. offset passed to bary.f, etc). This
527 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
528 * have the OUTLOCn value offset by 8, presumably to account
529 * for gl_Position/gl_PointSize)
532 /* vertex shader specific: */
533 bool sysval
: 1; /* slot is a gl_system_value */
534 /* fragment shader specific: */
535 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
536 bool rasterflat
: 1; /* special handling for emit->rasterflat */
537 bool use_ldlv
: 1; /* internal to ir3_compiler_nir */
539 enum glsl_interp_mode interpolate
;
540 } inputs
[32 + 2]; /* +POSITION +FACE */
542 /* sum of input components (scalar). For frag shaders, it only counts
543 * the varying inputs:
547 /* For frag shaders, the total number of inputs (not scalar,
548 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
552 /* Remapping table to map Image and SSBO to hw state: */
553 struct ir3_ibo_mapping image_mapping
;
555 /* number of samplers/textures (which are currently 1:1): */
558 /* is there an implicit sampler to read framebuffer (FS only).. if
559 * so the sampler-idx is 'num_samp - 1' (ie. it is appended after
560 * the last "real" texture)
564 /* do we have one or more SSBO instructions: */
567 /* do we need derivatives: */
570 /* do we have kill, image write, etc (which prevents early-z): */
575 /* for astc srgb workaround, the number/base of additional
576 * alpha tex states we need, and index of original tex states
579 unsigned base
, count
;
580 unsigned orig_idx
[16];
583 /* shader variants form a linked list: */
584 struct ir3_shader_variant
*next
;
586 /* replicated here to avoid passing extra ptrs everywhere: */
587 gl_shader_stage type
;
588 struct ir3_shader
*shader
;
590 /* texture sampler pre-dispatches */
591 uint32_t num_sampler_prefetch
;
592 struct ir3_sampler_prefetch sampler_prefetch
[IR3_MAX_SAMPLER_PREFETCH
];
595 static inline const char *
596 ir3_shader_stage(struct ir3_shader_variant
*v
)
599 case MESA_SHADER_VERTEX
: return v
->binning_pass
? "BVERT" : "VERT";
600 case MESA_SHADER_TESS_CTRL
: return "TCS";
601 case MESA_SHADER_TESS_EVAL
: return "TES";
602 case MESA_SHADER_GEOMETRY
: return "GEOM";
603 case MESA_SHADER_FRAGMENT
: return "FRAG";
604 case MESA_SHADER_COMPUTE
: return "CL";
606 unreachable("invalid type");
611 struct ir3_ubo_range
{
612 uint32_t offset
; /* start offset of this block in const register file */
613 uint32_t start
, end
; /* range of block that's actually used */
616 struct ir3_ubo_analysis_state
{
617 struct ir3_ubo_range range
[IR3_MAX_CONSTANT_BUFFERS
];
620 uint32_t lower_count
;
621 uint32_t cmdstream_size
; /* for per-gen backend to stash required cmdstream size */
626 gl_shader_stage type
;
628 /* shader id (for debug): */
630 uint32_t variant_count
;
632 /* so we know when we can disable TGSI related hacks: */
635 struct ir3_compiler
*compiler
;
637 struct ir3_ubo_analysis_state ubo_state
;
638 struct ir3_const_state const_state
;
640 struct nir_shader
*nir
;
641 struct ir3_stream_output_info stream_output
;
643 struct ir3_shader_variant
*variants
;
646 uint32_t output_size
; /* Size in dwords of all outputs for VS, size of entire patch for HS. */
648 /* Map from driver_location to byte offset in per-primitive storage */
649 unsigned output_loc
[32];
652 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
);
653 struct ir3_shader_variant
* ir3_shader_get_variant(struct ir3_shader
*shader
,
654 struct ir3_shader_key
*key
, bool binning_pass
, bool *created
);
655 struct ir3_shader
* ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
);
656 void ir3_shader_destroy(struct ir3_shader
*shader
);
657 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
658 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
661 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
);
668 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
672 for (j
= 0; j
< so
->outputs_count
; j
++)
673 if (so
->outputs
[j
].slot
== slot
)
676 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
677 * in the vertex shader.. but the fragment shader doesn't know this
678 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
679 * at link time if there is no matching OUT.BCOLOR[n], we must map
680 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
681 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
683 if (slot
== VARYING_SLOT_BFC0
) {
684 slot
= VARYING_SLOT_COL0
;
685 } else if (slot
== VARYING_SLOT_BFC1
) {
686 slot
= VARYING_SLOT_COL1
;
687 } else if (slot
== VARYING_SLOT_COL0
) {
688 slot
= VARYING_SLOT_BFC0
;
689 } else if (slot
== VARYING_SLOT_COL1
) {
690 slot
= VARYING_SLOT_BFC1
;
695 for (j
= 0; j
< so
->outputs_count
; j
++)
696 if (so
->outputs
[j
].slot
== slot
)
705 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
707 while (++i
< so
->inputs_count
)
708 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
713 struct ir3_shader_linkage
{
724 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid
, uint8_t compmask
, uint8_t loc
)
728 debug_assert(i
< ARRAY_SIZE(l
->var
));
730 l
->var
[i
].regid
= regid
;
731 l
->var
[i
].compmask
= compmask
;
733 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
737 ir3_link_shaders(struct ir3_shader_linkage
*l
,
738 const struct ir3_shader_variant
*vs
,
739 const struct ir3_shader_variant
*fs
)
743 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
744 j
= ir3_next_varying(fs
, j
);
746 if (j
>= fs
->inputs_count
)
749 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
752 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
754 ir3_link_add(l
, vs
->outputs
[k
].regid
,
755 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
759 static inline uint32_t
760 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
763 for (j
= 0; j
< so
->outputs_count
; j
++)
764 if (so
->outputs
[j
].slot
== slot
) {
765 uint32_t regid
= so
->outputs
[j
].regid
;
766 if (so
->outputs
[j
].half
)
767 regid
|= HALF_REG_ID
;
773 #define VARYING_SLOT_GS_HEADER_IR3 (VARYING_SLOT_MAX + 0)
774 #define VARYING_SLOT_GS_VERTEX_FLAGS_IR3 (VARYING_SLOT_MAX + 1)
775 #define VARYING_SLOT_TCS_HEADER_IR3 (VARYING_SLOT_MAX + 2)
778 static inline uint32_t
779 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
782 for (j
= 0; j
< so
->inputs_count
; j
++)
783 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
784 return so
->inputs
[j
].regid
;
788 /* calculate register footprint in terms of half-regs (ie. one full
789 * reg counts as two half-regs).
791 static inline uint32_t
792 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
794 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
797 #endif /* IR3_SHADER_H_ */