2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
32 #include "c11/threads.h"
33 #include "compiler/shader_enums.h"
34 #include "compiler/nir/nir.h"
35 #include "util/bitscan.h"
41 /* driver param indices: */
42 enum ir3_driver_param
{
43 /* compute shader driver params: */
44 IR3_DP_NUM_WORK_GROUPS_X
= 0,
45 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
46 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
47 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
48 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
49 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
50 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
51 * glDispatchComputeIndirect() needs to load these from
52 * the info->indirect buffer. Keep that in mind when/if
53 * adding any addition CS driver params.
55 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
57 /* vertex shader driver params: */
58 IR3_DP_VTXID_BASE
= 0,
59 IR3_DP_VTXCNT_MAX
= 1,
60 IR3_DP_INSTID_BASE
= 2,
61 /* user-clip-plane components, up to 8x vec4's: */
65 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
68 #define IR3_MAX_SHADER_BUFFERS 32
69 #define IR3_MAX_SHADER_IMAGES 32
70 #define IR3_MAX_SO_BUFFERS 4
71 #define IR3_MAX_SO_STREAMS 4
72 #define IR3_MAX_SO_OUTPUTS 64
73 #define IR3_MAX_CONSTANT_BUFFERS 32
77 * Describes the layout of shader consts. This includes:
78 * + User consts + driver lowered UBO ranges
80 * + Image sizes/dimensions
81 * + Driver params (ie. IR3_DP_*)
82 * + TFBO addresses (for generations that do not have hardware streamout)
83 * + Lowered immediates
85 * For consts needed to pass internal values to shader which may or may not
86 * be required, rather than allocating worst-case const space, we scan the
87 * shader and allocate consts as-needed:
89 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
92 * + Image dimensions: needed to calculate pixel offset, but only for
93 * images that have a image_store intrinsic
95 * Layout of constant registers, each section aligned to vec4. Note
96 * that pointer size (ubo, etc) changes depending on generation.
101 * if (vertex shader) {
102 * driver params (IR3_DP_*)
103 * if (stream_output.num_outputs > 0)
104 * stream-out addresses
105 * } else if (compute_shader) {
106 * driver params (IR3_DP_*)
110 * Immediates go last mostly because they are inserted in the CP pass
111 * after the nir -> ir3 frontend.
113 * Note UBO size in bytes should be aligned to vec4
115 struct ir3_const_state
{
117 unsigned num_reserved_user_consts
;
118 unsigned num_driver_params
; /* scalar */
121 /* user const start at zero */
123 /* NOTE that a3xx might need a section for SSBO addresses too */
126 unsigned driver_param
;
128 unsigned primitive_param
;
129 unsigned primitive_map
;
134 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
135 uint32_t count
; /* number of consts allocated */
136 /* one const allocated per SSBO which has get_buffer_size,
137 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
140 uint32_t off
[IR3_MAX_SHADER_BUFFERS
];
144 uint32_t mask
; /* bitmask of images that have image_store */
145 uint32_t count
; /* number of consts allocated */
146 /* three const allocated per image which has image_store:
147 * + cpp (bytes per pixel)
149 * + array_pitch (z pitch)
151 uint32_t off
[IR3_MAX_SHADER_IMAGES
];
154 unsigned immediate_idx
;
155 unsigned immediates_count
;
156 unsigned immediates_size
;
163 * A single output for vertex transform feedback.
165 struct ir3_stream_output
{
166 unsigned register_index
:6; /**< 0 to 63 (OUT index) */
167 unsigned start_component
:2; /** 0 to 3 */
168 unsigned num_components
:3; /** 1 to 4 */
169 unsigned output_buffer
:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
170 unsigned dst_offset
:16; /**< offset into the buffer in dwords */
171 unsigned stream
:2; /**< 0 to 3 */
175 * Stream output for vertex transform feedback.
177 struct ir3_stream_output_info
{
178 unsigned num_outputs
;
179 /** stride for an entire vertex for each buffer in dwords */
180 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
183 * Array of stream outputs, in the order they are to be written in.
184 * Selected components are tightly packed into the output buffer.
186 struct ir3_stream_output output
[IR3_MAX_SO_OUTPUTS
];
191 * Starting from a4xx, HW supports pre-dispatching texture sampling
192 * instructions prior to scheduling a shader stage, when the
193 * coordinate maps exactly to an output of the previous stage.
197 * There is a limit in the number of pre-dispatches allowed for any
200 #define IR3_MAX_SAMPLER_PREFETCH 4
203 * This is the output stream value for 'cmd', as used by blob. It may
204 * encode the return type (in 3 bits) but it hasn't been verified yet.
206 #define IR3_SAMPLER_PREFETCH_CMD 0x4
209 * Stream output for texture sampling pre-dispatches.
211 struct ir3_sampler_prefetch
{
217 uint8_t half_precision
;
222 /* Configuration key used to identify a shader variant.. different
223 * shader variants can be used to implement features not supported
224 * in hw (two sided color), binning-pass vertex shader, etc.
226 struct ir3_shader_key
{
230 * Combined Vertex/Fragment shader parameters:
232 unsigned ucp_enables
: 8;
234 /* do we need to check {v,f}saturate_{s,t,r}? */
235 unsigned has_per_samp
: 1;
238 * Vertex shader variant parameters:
240 unsigned vclamp_color
: 1;
243 * Fragment shader variant parameters:
245 unsigned sample_shading
: 1;
247 unsigned color_two_side
: 1;
248 unsigned half_precision
: 1;
249 /* used when shader needs to handle flat varyings (a4xx)
250 * for front/back color inputs to frag shader:
252 unsigned rasterflat
: 1;
253 unsigned fclamp_color
: 1;
255 /* Indicates that this is a tessellation pipeline which requires a
256 * whole different kind of vertex shader. In case of
257 * tessellation, this field also tells us which kind of output
258 * topology the TES uses, which the TCS needs to know.
260 #define IR3_TESS_NONE 0
261 #define IR3_TESS_TRIANGLES 1
262 #define IR3_TESS_QUADS 2
263 #define IR3_TESS_ISOLINES 3
264 unsigned tessellation
: 2;
271 /* bitmask of sampler which needs coords clamped for vertex
274 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
276 /* bitmask of sampler which needs coords clamped for frag
279 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
281 /* bitmask of ms shifts */
282 uint32_t vsamples
, fsamples
;
284 /* bitmask of samplers which need astc srgb workaround: */
285 uint16_t vastc_srgb
, fastc_srgb
;
289 ir3_shader_key_equal(struct ir3_shader_key
*a
, struct ir3_shader_key
*b
)
291 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
292 if (a
->has_per_samp
|| b
->has_per_samp
)
293 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
294 return a
->global
== b
->global
;
297 /* will the two keys produce different lowering for a fragment shader? */
299 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
301 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
302 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
303 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
304 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
305 (last_key
->fsamples
!= key
->fsamples
) ||
306 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
310 if (last_key
->fclamp_color
!= key
->fclamp_color
)
313 if (last_key
->color_two_side
!= key
->color_two_side
)
316 if (last_key
->half_precision
!= key
->half_precision
)
319 if (last_key
->rasterflat
!= key
->rasterflat
)
322 if (last_key
->ucp_enables
!= key
->ucp_enables
)
328 /* will the two keys produce different lowering for a vertex shader? */
330 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
332 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
333 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
334 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
335 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
336 (last_key
->vsamples
!= key
->vsamples
) ||
337 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
341 if (last_key
->vclamp_color
!= key
->vclamp_color
)
344 if (last_key
->ucp_enables
!= key
->ucp_enables
)
350 /* clears shader-key flags which don't apply to the given shader
354 ir3_normalize_key(struct ir3_shader_key
*key
, gl_shader_stage type
)
357 case MESA_SHADER_FRAGMENT
:
358 if (key
->has_per_samp
) {
359 key
->vsaturate_s
= 0;
360 key
->vsaturate_t
= 0;
361 key
->vsaturate_r
= 0;
364 key
->has_gs
= false; /* FS doesn't care */
365 key
->tessellation
= IR3_TESS_NONE
;
368 case MESA_SHADER_VERTEX
:
369 case MESA_SHADER_GEOMETRY
:
370 key
->color_two_side
= false;
371 key
->half_precision
= false;
372 key
->rasterflat
= false;
373 if (key
->has_per_samp
) {
374 key
->fsaturate_s
= 0;
375 key
->fsaturate_t
= 0;
376 key
->fsaturate_r
= 0;
381 /* VS and GS only care about whether or not we're tessellating. */
382 key
->tessellation
= !!key
->tessellation
;
384 case MESA_SHADER_TESS_CTRL
:
385 case MESA_SHADER_TESS_EVAL
:
386 key
->color_two_side
= false;
387 key
->half_precision
= false;
388 key
->rasterflat
= false;
389 if (key
->has_per_samp
) {
390 key
->fsaturate_s
= 0;
391 key
->fsaturate_t
= 0;
392 key
->fsaturate_r
= 0;
395 key
->vsaturate_s
= 0;
396 key
->vsaturate_t
= 0;
397 key
->vsaturate_r
= 0;
409 * On a4xx+a5xx, Images share state with textures and SSBOs:
411 * + Uses texture (cat5) state/instruction (isam) to read
412 * + Uses SSBO state and instructions (cat6) to write and for atomics
414 * Starting with a6xx, Images and SSBOs are basically the same thing,
415 * with texture state and isam also used for SSBO reads.
417 * On top of that, gallium makes the SSBO (shader_buffers) state semi
418 * sparse, with the first half of the state space used for atomic
419 * counters lowered to atomic buffers. We could ignore this, but I
420 * don't think we could *really* handle the case of a single shader
421 * that used the max # of textures + images + SSBOs. And once we are
422 * offsetting images by num_ssbos (or visa versa) to map them into
423 * the same hardware state, the hardware state has become coupled to
424 * the shader state, so at this point we might as well just use a
425 * mapping table to remap things from image/SSBO idx to hw idx.
427 * To make things less (more?) confusing, for the hw "SSBO" state
428 * (since it is really both SSBO and Image) I'll use the name "IBO"
430 struct ir3_ibo_mapping
{
431 #define IBO_INVALID 0xff
432 /* Maps logical SSBO state to hw tex state: */
433 uint8_t ssbo_to_tex
[IR3_MAX_SHADER_BUFFERS
];
435 /* Maps logical Image state to hw tex state: */
436 uint8_t image_to_tex
[IR3_MAX_SHADER_IMAGES
];
438 /* Maps hw state back to logical SSBO or Image state:
440 * note IBO_SSBO ORd into values to indicate that the
441 * hw slot is used for SSBO state vs Image state.
443 #define IBO_SSBO 0x80
444 uint8_t tex_to_image
[32];
446 uint8_t num_tex
; /* including real textures */
447 uint8_t tex_base
; /* the number of real textures, ie. image/ssbo start here */
450 /* Represents half register in regid */
451 #define HALF_REG_ID 0x100
453 struct ir3_shader_variant
{
456 /* variant id (for debug) */
459 struct ir3_shader_key key
;
461 /* vertex shaders can have an extra version for hwbinning pass,
462 * which is pointed to by so->binning:
466 struct ir3_shader_variant
*binning
;
467 struct ir3_shader_variant
*nonbinning
;
470 struct ir3_info info
;
473 /* Levels of nesting of flow control:
475 unsigned branchstack
;
480 /* the instructions length is in units of instruction groups
481 * (4 instructions for a3xx, 16 instructions for a4xx.. each
482 * instruction is 2 dwords):
486 /* the constants length is in units of vec4's, and is the sum of
487 * the uniforms and the built-in compiler constants
492 * + Let the frag shader determine the position/compmask for the
493 * varyings, since it is the place where we know if the varying
494 * is actually used, and if so, which components are used. So
495 * what the hw calls "outloc" is taken from the "inloc" of the
497 * + From the vert shader, we only need the output regid
500 bool frag_coord
, frag_face
, color0_mrt
;
502 /* NOTE: for input/outputs, slot is:
503 * gl_vert_attrib - for VS inputs
504 * gl_varying_slot - for VS output / FS input
505 * gl_frag_result - for FS output
508 /* varyings/outputs: */
509 unsigned outputs_count
;
514 } outputs
[32 + 2]; /* +POSITION +PSIZE */
515 bool writes_pos
, writes_smask
, writes_psize
;
517 /* attributes (VS) / varyings (FS):
518 * Note that sysval's should come *after* normal inputs.
520 unsigned inputs_count
;
525 /* location of input (ie. offset passed to bary.f, etc). This
526 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
527 * have the OUTLOCn value offset by 8, presumably to account
528 * for gl_Position/gl_PointSize)
531 /* vertex shader specific: */
532 bool sysval
: 1; /* slot is a gl_system_value */
533 /* fragment shader specific: */
534 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
535 bool rasterflat
: 1; /* special handling for emit->rasterflat */
536 bool use_ldlv
: 1; /* internal to ir3_compiler_nir */
538 enum glsl_interp_mode interpolate
;
539 } inputs
[32 + 2]; /* +POSITION +FACE */
541 /* sum of input components (scalar). For frag shaders, it only counts
542 * the varying inputs:
546 /* For frag shaders, the total number of inputs (not scalar,
547 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
551 /* Remapping table to map Image and SSBO to hw state: */
552 struct ir3_ibo_mapping image_mapping
;
554 /* number of samplers/textures (which are currently 1:1): */
557 /* is there an implicit sampler to read framebuffer (FS only).. if
558 * so the sampler-idx is 'num_samp - 1' (ie. it is appended after
559 * the last "real" texture)
563 /* do we have one or more SSBO instructions: */
566 /* do we need derivatives: */
569 bool need_fine_derivatives
;
571 /* do we have kill, image write, etc (which prevents early-z): */
576 /* for astc srgb workaround, the number/base of additional
577 * alpha tex states we need, and index of original tex states
580 unsigned base
, count
;
581 unsigned orig_idx
[16];
584 /* shader variants form a linked list: */
585 struct ir3_shader_variant
*next
;
587 /* replicated here to avoid passing extra ptrs everywhere: */
588 gl_shader_stage type
;
589 struct ir3_shader
*shader
;
591 /* texture sampler pre-dispatches */
592 uint32_t num_sampler_prefetch
;
593 struct ir3_sampler_prefetch sampler_prefetch
[IR3_MAX_SAMPLER_PREFETCH
];
596 static inline const char *
597 ir3_shader_stage(struct ir3_shader_variant
*v
)
600 case MESA_SHADER_VERTEX
: return v
->binning_pass
? "BVERT" : "VERT";
601 case MESA_SHADER_TESS_CTRL
: return "TCS";
602 case MESA_SHADER_TESS_EVAL
: return "TES";
603 case MESA_SHADER_GEOMETRY
: return "GEOM";
604 case MESA_SHADER_FRAGMENT
: return "FRAG";
605 case MESA_SHADER_COMPUTE
: return "CL";
607 unreachable("invalid type");
612 struct ir3_ubo_range
{
613 uint32_t offset
; /* start offset of this block in const register file */
614 uint32_t start
, end
; /* range of block that's actually used */
617 struct ir3_ubo_analysis_state
{
618 struct ir3_ubo_range range
[IR3_MAX_CONSTANT_BUFFERS
];
621 uint32_t lower_count
;
622 uint32_t cmdstream_size
; /* for per-gen backend to stash required cmdstream size */
627 gl_shader_stage type
;
629 /* shader id (for debug): */
631 uint32_t variant_count
;
633 struct ir3_compiler
*compiler
;
635 struct ir3_ubo_analysis_state ubo_state
;
636 struct ir3_const_state const_state
;
638 struct nir_shader
*nir
;
639 struct ir3_stream_output_info stream_output
;
641 struct ir3_shader_variant
*variants
;
644 uint32_t output_size
; /* Size in dwords of all outputs for VS, size of entire patch for HS. */
646 /* Map from driver_location to byte offset in per-primitive storage */
647 unsigned output_loc
[32];
650 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
);
651 struct ir3_shader_variant
* ir3_shader_get_variant(struct ir3_shader
*shader
,
652 struct ir3_shader_key
*key
, bool binning_pass
, bool *created
);
653 struct ir3_shader
* ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
);
654 void ir3_shader_destroy(struct ir3_shader
*shader
);
655 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
656 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
659 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
);
666 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
670 for (j
= 0; j
< so
->outputs_count
; j
++)
671 if (so
->outputs
[j
].slot
== slot
)
674 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
675 * in the vertex shader.. but the fragment shader doesn't know this
676 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
677 * at link time if there is no matching OUT.BCOLOR[n], we must map
678 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
679 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
681 if (slot
== VARYING_SLOT_BFC0
) {
682 slot
= VARYING_SLOT_COL0
;
683 } else if (slot
== VARYING_SLOT_BFC1
) {
684 slot
= VARYING_SLOT_COL1
;
685 } else if (slot
== VARYING_SLOT_COL0
) {
686 slot
= VARYING_SLOT_BFC0
;
687 } else if (slot
== VARYING_SLOT_COL1
) {
688 slot
= VARYING_SLOT_BFC1
;
693 for (j
= 0; j
< so
->outputs_count
; j
++)
694 if (so
->outputs
[j
].slot
== slot
)
703 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
705 while (++i
< so
->inputs_count
)
706 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
711 struct ir3_shader_linkage
{
722 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid
, uint8_t compmask
, uint8_t loc
)
726 debug_assert(i
< ARRAY_SIZE(l
->var
));
728 l
->var
[i
].regid
= regid
;
729 l
->var
[i
].compmask
= compmask
;
731 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
735 ir3_link_shaders(struct ir3_shader_linkage
*l
,
736 const struct ir3_shader_variant
*vs
,
737 const struct ir3_shader_variant
*fs
)
741 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
742 j
= ir3_next_varying(fs
, j
);
744 if (j
>= fs
->inputs_count
)
747 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
750 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
752 ir3_link_add(l
, vs
->outputs
[k
].regid
,
753 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
757 static inline uint32_t
758 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
761 for (j
= 0; j
< so
->outputs_count
; j
++)
762 if (so
->outputs
[j
].slot
== slot
) {
763 uint32_t regid
= so
->outputs
[j
].regid
;
764 if (so
->outputs
[j
].half
)
765 regid
|= HALF_REG_ID
;
771 #define VARYING_SLOT_GS_HEADER_IR3 (VARYING_SLOT_MAX + 0)
772 #define VARYING_SLOT_GS_VERTEX_FLAGS_IR3 (VARYING_SLOT_MAX + 1)
773 #define VARYING_SLOT_TCS_HEADER_IR3 (VARYING_SLOT_MAX + 2)
776 static inline uint32_t
777 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
780 for (j
= 0; j
< so
->inputs_count
; j
++)
781 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
782 return so
->inputs
[j
].regid
;
786 /* calculate register footprint in terms of half-regs (ie. one full
787 * reg counts as two half-regs).
789 static inline uint32_t
790 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
792 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
795 static inline uint32_t
796 ir3_shader_nibo(const struct ir3_shader_variant
*v
)
798 /* The dummy variant used in binning mode won't have an actual shader. */
802 return v
->shader
->nir
->info
.num_ssbos
+ v
->shader
->nir
->info
.num_images
;
805 #endif /* IR3_SHADER_H_ */