src/freedreno/perfcntrs/fd5_perfcntr.c

   1 /*
   2  * Copyright (C) 2018 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef FD5_PERFCNTR_H_
  28 #define FD5_PERFCNTR_H_
  29
  30 #include "util/u_half.h"
  31 #include "adreno_common.xml.h"
  32 #include "a5xx.xml.h"
  33
  34 #define REG(_x) REG_A5XX_ ## _x
  35 #include "freedreno_perfcntr.h"
  36
  37 static const struct fd_perfcntr_counter cp_counters[] = {
  38 //RESERVED: for kernel
  39 //      COUNTER(CP_PERFCTR_CP_SEL_0, RBBM_PERFCTR_CP_0_LO, RBBM_PERFCTR_CP_0_HI),
  40         COUNTER(CP_PERFCTR_CP_SEL_1, RBBM_PERFCTR_CP_1_LO, RBBM_PERFCTR_CP_1_HI),
  41         COUNTER(CP_PERFCTR_CP_SEL_2, RBBM_PERFCTR_CP_2_LO, RBBM_PERFCTR_CP_2_HI),
  42         COUNTER(CP_PERFCTR_CP_SEL_3, RBBM_PERFCTR_CP_3_LO, RBBM_PERFCTR_CP_3_HI),
  43         COUNTER(CP_PERFCTR_CP_SEL_4, RBBM_PERFCTR_CP_4_LO, RBBM_PERFCTR_CP_4_HI),
  44         COUNTER(CP_PERFCTR_CP_SEL_5, RBBM_PERFCTR_CP_5_LO, RBBM_PERFCTR_CP_5_HI),
  45         COUNTER(CP_PERFCTR_CP_SEL_6, RBBM_PERFCTR_CP_6_LO, RBBM_PERFCTR_CP_6_HI),
  46         COUNTER(CP_PERFCTR_CP_SEL_7, RBBM_PERFCTR_CP_7_LO, RBBM_PERFCTR_CP_7_HI),
  47 };
  48
  49 static const struct fd_perfcntr_countable cp_countables[] = {
  50         COUNTABLE(PERF_CP_ALWAYS_COUNT, UINT64, AVERAGE),
  51         COUNTABLE(PERF_CP_BUSY_GFX_CORE_IDLE, UINT64, AVERAGE),
  52         COUNTABLE(PERF_CP_BUSY_CYCLES, UINT64, AVERAGE),
  53         COUNTABLE(PERF_CP_PFP_IDLE, UINT64, AVERAGE),
  54         COUNTABLE(PERF_CP_PFP_BUSY_WORKING, UINT64, AVERAGE),
  55         COUNTABLE(PERF_CP_PFP_STALL_CYCLES_ANY, UINT64, AVERAGE),
  56         COUNTABLE(PERF_CP_PFP_STARVE_CYCLES_ANY, UINT64, AVERAGE),
  57         COUNTABLE(PERF_CP_PFP_ICACHE_MISS, UINT64, AVERAGE),
  58         COUNTABLE(PERF_CP_PFP_ICACHE_HIT, UINT64, AVERAGE),
  59         COUNTABLE(PERF_CP_PFP_MATCH_PM4_PKT_PROFILE, UINT64, AVERAGE),
  60         COUNTABLE(PERF_CP_ME_BUSY_WORKING, UINT64, AVERAGE),
  61         COUNTABLE(PERF_CP_ME_IDLE, UINT64, AVERAGE),
  62         COUNTABLE(PERF_CP_ME_STARVE_CYCLES_ANY, UINT64, AVERAGE),
  63         COUNTABLE(PERF_CP_ME_FIFO_EMPTY_PFP_IDLE, UINT64, AVERAGE),
  64         COUNTABLE(PERF_CP_ME_FIFO_EMPTY_PFP_BUSY, UINT64, AVERAGE),
  65         COUNTABLE(PERF_CP_ME_FIFO_FULL_ME_BUSY, UINT64, AVERAGE),
  66         COUNTABLE(PERF_CP_ME_FIFO_FULL_ME_NON_WORKING, UINT64, AVERAGE),
  67         COUNTABLE(PERF_CP_ME_STALL_CYCLES_ANY, UINT64, AVERAGE),
  68         COUNTABLE(PERF_CP_ME_ICACHE_MISS, UINT64, AVERAGE),
  69         COUNTABLE(PERF_CP_ME_ICACHE_HIT, UINT64, AVERAGE),
  70         COUNTABLE(PERF_CP_NUM_PREEMPTIONS, UINT64, AVERAGE),
  71         COUNTABLE(PERF_CP_PREEMPTION_REACTION_DELAY, UINT64, AVERAGE),
  72         COUNTABLE(PERF_CP_PREEMPTION_SWITCH_OUT_TIME, UINT64, AVERAGE),
  73         COUNTABLE(PERF_CP_PREEMPTION_SWITCH_IN_TIME, UINT64, AVERAGE),
  74         COUNTABLE(PERF_CP_DEAD_DRAWS_IN_BIN_RENDER, UINT64, AVERAGE),
  75         COUNTABLE(PERF_CP_PREDICATED_DRAWS_KILLED, UINT64, AVERAGE),
  76         COUNTABLE(PERF_CP_MODE_SWITCH, UINT64, AVERAGE),
  77         COUNTABLE(PERF_CP_ZPASS_DONE, UINT64, AVERAGE),
  78         COUNTABLE(PERF_CP_CONTEXT_DONE, UINT64, AVERAGE),
  79         COUNTABLE(PERF_CP_CACHE_FLUSH, UINT64, AVERAGE),
  80         COUNTABLE(PERF_CP_LONG_PREEMPTIONS, UINT64, AVERAGE),
  81 };
  82
  83 static const struct fd_perfcntr_counter ccu_counters[] = {
  84         COUNTER(RB_PERFCTR_CCU_SEL_0, RBBM_PERFCTR_CCU_0_LO, RBBM_PERFCTR_CCU_0_HI),
  85         COUNTER(RB_PERFCTR_CCU_SEL_1, RBBM_PERFCTR_CCU_1_LO, RBBM_PERFCTR_CCU_1_HI),
  86         COUNTER(RB_PERFCTR_CCU_SEL_2, RBBM_PERFCTR_CCU_2_LO, RBBM_PERFCTR_CCU_2_HI),
  87         COUNTER(RB_PERFCTR_CCU_SEL_3, RBBM_PERFCTR_CCU_3_LO, RBBM_PERFCTR_CCU_3_HI),
  88 };
  89
  90 static const struct fd_perfcntr_countable ccu_countables[] = {
  91         COUNTABLE(PERF_CCU_BUSY_CYCLES, UINT64, AVERAGE),
  92         COUNTABLE(PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN, UINT64, AVERAGE),
  93         COUNTABLE(PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN, UINT64, AVERAGE),
  94         COUNTABLE(PERF_CCU_STARVE_CYCLES_FLAG_RETURN, UINT64, AVERAGE),
  95         COUNTABLE(PERF_CCU_DEPTH_BLOCKS, UINT64, AVERAGE),
  96         COUNTABLE(PERF_CCU_COLOR_BLOCKS, UINT64, AVERAGE),
  97         COUNTABLE(PERF_CCU_DEPTH_BLOCK_HIT, UINT64, AVERAGE),
  98         COUNTABLE(PERF_CCU_COLOR_BLOCK_HIT, UINT64, AVERAGE),
  99         COUNTABLE(PERF_CCU_PARTIAL_BLOCK_READ, UINT64, AVERAGE),
 100         COUNTABLE(PERF_CCU_GMEM_READ, UINT64, AVERAGE),
 101         COUNTABLE(PERF_CCU_GMEM_WRITE, UINT64, AVERAGE),
 102         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG0_COUNT, UINT64, AVERAGE),
 103         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG1_COUNT, UINT64, AVERAGE),
 104         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG2_COUNT, UINT64, AVERAGE),
 105         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG3_COUNT, UINT64, AVERAGE),
 106         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG4_COUNT, UINT64, AVERAGE),
 107         COUNTABLE(PERF_CCU_COLOR_READ_FLAG0_COUNT, UINT64, AVERAGE),
 108         COUNTABLE(PERF_CCU_COLOR_READ_FLAG1_COUNT, UINT64, AVERAGE),
 109         COUNTABLE(PERF_CCU_COLOR_READ_FLAG2_COUNT, UINT64, AVERAGE),
 110         COUNTABLE(PERF_CCU_COLOR_READ_FLAG3_COUNT, UINT64, AVERAGE),
 111         COUNTABLE(PERF_CCU_COLOR_READ_FLAG4_COUNT, UINT64, AVERAGE),
 112         COUNTABLE(PERF_CCU_2D_BUSY_CYCLES, UINT64, AVERAGE),
 113         COUNTABLE(PERF_CCU_2D_RD_REQ, UINT64, AVERAGE),
 114         COUNTABLE(PERF_CCU_2D_WR_REQ, UINT64, AVERAGE),
 115         COUNTABLE(PERF_CCU_2D_REORDER_STARVE_CYCLES, UINT64, AVERAGE),
 116         COUNTABLE(PERF_CCU_2D_PIXELS, UINT64, AVERAGE),
 117 };
 118
 119 static const struct fd_perfcntr_counter tse_counters[] = {
 120         COUNTER(GRAS_PERFCTR_TSE_SEL_0, RBBM_PERFCTR_TSE_0_LO, RBBM_PERFCTR_TSE_0_HI),
 121         COUNTER(GRAS_PERFCTR_TSE_SEL_1, RBBM_PERFCTR_TSE_1_LO, RBBM_PERFCTR_TSE_1_HI),
 122         COUNTER(GRAS_PERFCTR_TSE_SEL_2, RBBM_PERFCTR_TSE_2_LO, RBBM_PERFCTR_TSE_2_HI),
 123         COUNTER(GRAS_PERFCTR_TSE_SEL_3, RBBM_PERFCTR_TSE_3_LO, RBBM_PERFCTR_TSE_3_HI),
 124 };
 125
 126 static const struct fd_perfcntr_countable tse_countables[] = {
 127         COUNTABLE(PERF_TSE_BUSY_CYCLES, UINT64, AVERAGE),
 128         COUNTABLE(PERF_TSE_CLIPPING_CYCLES, UINT64, AVERAGE),
 129         COUNTABLE(PERF_TSE_STALL_CYCLES_RAS, UINT64, AVERAGE),
 130         COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE, UINT64, AVERAGE),
 131         COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_ZPLANE, UINT64, AVERAGE),
 132         COUNTABLE(PERF_TSE_STARVE_CYCLES_PC, UINT64, AVERAGE),
 133         COUNTABLE(PERF_TSE_INPUT_PRIM, UINT64, AVERAGE),
 134         COUNTABLE(PERF_TSE_INPUT_NULL_PRIM, UINT64, AVERAGE),
 135         COUNTABLE(PERF_TSE_TRIVAL_REJ_PRIM, UINT64, AVERAGE),
 136         COUNTABLE(PERF_TSE_CLIPPED_PRIM, UINT64, AVERAGE),
 137         COUNTABLE(PERF_TSE_ZERO_AREA_PRIM, UINT64, AVERAGE),
 138         COUNTABLE(PERF_TSE_FACENESS_CULLED_PRIM, UINT64, AVERAGE),
 139         COUNTABLE(PERF_TSE_ZERO_PIXEL_PRIM, UINT64, AVERAGE),
 140         COUNTABLE(PERF_TSE_OUTPUT_NULL_PRIM, UINT64, AVERAGE),
 141         COUNTABLE(PERF_TSE_OUTPUT_VISIBLE_PRIM, UINT64, AVERAGE),
 142         COUNTABLE(PERF_TSE_CINVOCATION, UINT64, AVERAGE),
 143         COUNTABLE(PERF_TSE_CPRIMITIVES, UINT64, AVERAGE),
 144         COUNTABLE(PERF_TSE_2D_INPUT_PRIM, UINT64, AVERAGE),
 145         COUNTABLE(PERF_TSE_2D_ALIVE_CLCLES, UINT64, AVERAGE),
 146 };
 147
 148 static const struct fd_perfcntr_counter ras_counters[] = {
 149         COUNTER(GRAS_PERFCTR_RAS_SEL_0, RBBM_PERFCTR_RAS_0_LO, RBBM_PERFCTR_RAS_0_HI),
 150         COUNTER(GRAS_PERFCTR_RAS_SEL_1, RBBM_PERFCTR_RAS_1_LO, RBBM_PERFCTR_RAS_1_HI),
 151         COUNTER(GRAS_PERFCTR_RAS_SEL_2, RBBM_PERFCTR_RAS_2_LO, RBBM_PERFCTR_RAS_2_HI),
 152         COUNTER(GRAS_PERFCTR_RAS_SEL_3, RBBM_PERFCTR_RAS_3_LO, RBBM_PERFCTR_RAS_3_HI),
 153 };
 154
 155 static const struct fd_perfcntr_countable ras_countables[] = {
 156         COUNTABLE(PERF_RAS_BUSY_CYCLES, UINT64, AVERAGE),
 157         COUNTABLE(PERF_RAS_SUPERTILE_ACTIVE_CYCLES, UINT64, AVERAGE),
 158         COUNTABLE(PERF_RAS_STALL_CYCLES_LRZ, UINT64, AVERAGE),
 159         COUNTABLE(PERF_RAS_STARVE_CYCLES_TSE, UINT64, AVERAGE),
 160         COUNTABLE(PERF_RAS_SUPER_TILES, UINT64, AVERAGE),
 161         COUNTABLE(PERF_RAS_8X4_TILES, UINT64, AVERAGE),
 162         COUNTABLE(PERF_RAS_MASKGEN_ACTIVE, UINT64, AVERAGE),
 163         COUNTABLE(PERF_RAS_FULLY_COVERED_SUPER_TILES, UINT64, AVERAGE),
 164         COUNTABLE(PERF_RAS_FULLY_COVERED_8X4_TILES, UINT64, AVERAGE),
 165         COUNTABLE(PERF_RAS_PRIM_KILLED_INVISILBE, UINT64, AVERAGE),
 166 };
 167
 168 static const struct fd_perfcntr_counter lrz_counters[] = {
 169         COUNTER(GRAS_PERFCTR_LRZ_SEL_0, RBBM_PERFCTR_LRZ_0_LO, RBBM_PERFCTR_LRZ_0_HI),
 170         COUNTER(GRAS_PERFCTR_LRZ_SEL_1, RBBM_PERFCTR_LRZ_1_LO, RBBM_PERFCTR_LRZ_1_HI),
 171         COUNTER(GRAS_PERFCTR_LRZ_SEL_2, RBBM_PERFCTR_LRZ_2_LO, RBBM_PERFCTR_LRZ_2_HI),
 172         COUNTER(GRAS_PERFCTR_LRZ_SEL_3, RBBM_PERFCTR_LRZ_3_LO, RBBM_PERFCTR_LRZ_3_HI),
 173 };
 174
 175 static const struct fd_perfcntr_countable lrz_countables[] = {
 176         COUNTABLE(PERF_LRZ_BUSY_CYCLES, UINT64, AVERAGE),
 177         COUNTABLE(PERF_LRZ_STARVE_CYCLES_RAS, UINT64, AVERAGE),
 178         COUNTABLE(PERF_LRZ_STALL_CYCLES_RB, UINT64, AVERAGE),
 179         COUNTABLE(PERF_LRZ_STALL_CYCLES_VSC, UINT64, AVERAGE),
 180         COUNTABLE(PERF_LRZ_STALL_CYCLES_VPC, UINT64, AVERAGE),
 181         COUNTABLE(PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH, UINT64, AVERAGE),
 182         COUNTABLE(PERF_LRZ_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 183         COUNTABLE(PERF_LRZ_LRZ_READ, UINT64, AVERAGE),
 184         COUNTABLE(PERF_LRZ_LRZ_WRITE, UINT64, AVERAGE),
 185         COUNTABLE(PERF_LRZ_READ_LATENCY, UINT64, AVERAGE),
 186         COUNTABLE(PERF_LRZ_MERGE_CACHE_UPDATING, UINT64, AVERAGE),
 187         COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_MASKGEN, UINT64, AVERAGE),
 188         COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_LRZ, UINT64, AVERAGE),
 189         COUNTABLE(PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ, UINT64, AVERAGE),
 190         COUNTABLE(PERF_LRZ_FULL_8X8_TILES, UINT64, AVERAGE),
 191         COUNTABLE(PERF_LRZ_PARTIAL_8X8_TILES, UINT64, AVERAGE),
 192         COUNTABLE(PERF_LRZ_TILE_KILLED, UINT64, AVERAGE),
 193         COUNTABLE(PERF_LRZ_TOTAL_PIXEL, UINT64, AVERAGE),
 194         COUNTABLE(PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ, UINT64, AVERAGE),
 195 };
 196
 197 static const struct fd_perfcntr_counter hlsq_counters[] = {
 198         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_0, RBBM_PERFCTR_HLSQ_0_LO, RBBM_PERFCTR_HLSQ_0_HI),
 199         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_1, RBBM_PERFCTR_HLSQ_1_LO, RBBM_PERFCTR_HLSQ_1_HI),
 200         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_2, RBBM_PERFCTR_HLSQ_2_LO, RBBM_PERFCTR_HLSQ_2_HI),
 201         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_3, RBBM_PERFCTR_HLSQ_3_LO, RBBM_PERFCTR_HLSQ_3_HI),
 202         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_4, RBBM_PERFCTR_HLSQ_4_LO, RBBM_PERFCTR_HLSQ_4_HI),
 203         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_5, RBBM_PERFCTR_HLSQ_5_LO, RBBM_PERFCTR_HLSQ_5_HI),
 204         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_6, RBBM_PERFCTR_HLSQ_6_LO, RBBM_PERFCTR_HLSQ_6_HI),
 205         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_7, RBBM_PERFCTR_HLSQ_7_LO, RBBM_PERFCTR_HLSQ_7_HI),
 206 };
 207
 208 static const struct fd_perfcntr_countable hlsq_countables[] = {
 209         COUNTABLE(PERF_HLSQ_BUSY_CYCLES, UINT64, AVERAGE),
 210         COUNTABLE(PERF_HLSQ_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 211         COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_STATE, UINT64, AVERAGE),
 212         COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE, UINT64, AVERAGE),
 213         COUNTABLE(PERF_HLSQ_UCHE_LATENCY_CYCLES, UINT64, AVERAGE),
 214         COUNTABLE(PERF_HLSQ_UCHE_LATENCY_COUNT, UINT64, AVERAGE),
 215         COUNTABLE(PERF_HLSQ_FS_STAGE_32_WAVES, UINT64, AVERAGE),
 216         COUNTABLE(PERF_HLSQ_FS_STAGE_64_WAVES, UINT64, AVERAGE),
 217         COUNTABLE(PERF_HLSQ_QUADS, UINT64, AVERAGE),
 218         COUNTABLE(PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE, UINT64, AVERAGE),
 219         COUNTABLE(PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE, UINT64, AVERAGE),
 220         COUNTABLE(PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE, UINT64, AVERAGE),
 221         COUNTABLE(PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE, UINT64, AVERAGE),
 222         COUNTABLE(PERF_HLSQ_CS_INVOCATIONS, UINT64, AVERAGE),
 223         COUNTABLE(PERF_HLSQ_COMPUTE_DRAWCALLS, UINT64, AVERAGE),
 224 };
 225
 226 static const struct fd_perfcntr_counter pc_counters[] = {
 227         COUNTER(PC_PERFCTR_PC_SEL_0, RBBM_PERFCTR_PC_0_LO, RBBM_PERFCTR_PC_0_HI),
 228         COUNTER(PC_PERFCTR_PC_SEL_1, RBBM_PERFCTR_PC_1_LO, RBBM_PERFCTR_PC_1_HI),
 229         COUNTER(PC_PERFCTR_PC_SEL_2, RBBM_PERFCTR_PC_2_LO, RBBM_PERFCTR_PC_2_HI),
 230         COUNTER(PC_PERFCTR_PC_SEL_3, RBBM_PERFCTR_PC_3_LO, RBBM_PERFCTR_PC_3_HI),
 231         COUNTER(PC_PERFCTR_PC_SEL_4, RBBM_PERFCTR_PC_4_LO, RBBM_PERFCTR_PC_4_HI),
 232         COUNTER(PC_PERFCTR_PC_SEL_5, RBBM_PERFCTR_PC_5_LO, RBBM_PERFCTR_PC_5_HI),
 233         COUNTER(PC_PERFCTR_PC_SEL_6, RBBM_PERFCTR_PC_6_LO, RBBM_PERFCTR_PC_6_HI),
 234         COUNTER(PC_PERFCTR_PC_SEL_7, RBBM_PERFCTR_PC_7_LO, RBBM_PERFCTR_PC_7_HI),
 235 };
 236
 237 static const struct fd_perfcntr_countable pc_countables[] = {
 238         COUNTABLE(PERF_PC_BUSY_CYCLES, UINT64, AVERAGE),
 239         COUNTABLE(PERF_PC_WORKING_CYCLES, UINT64, AVERAGE),
 240         COUNTABLE(PERF_PC_STALL_CYCLES_VFD, UINT64, AVERAGE),
 241         COUNTABLE(PERF_PC_STALL_CYCLES_TSE, UINT64, AVERAGE),
 242         COUNTABLE(PERF_PC_STALL_CYCLES_VPC, UINT64, AVERAGE),
 243         COUNTABLE(PERF_PC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 244         COUNTABLE(PERF_PC_STALL_CYCLES_TESS, UINT64, AVERAGE),
 245         COUNTABLE(PERF_PC_STALL_CYCLES_TSE_ONLY, UINT64, AVERAGE),
 246         COUNTABLE(PERF_PC_STALL_CYCLES_VPC_ONLY, UINT64, AVERAGE),
 247         COUNTABLE(PERF_PC_PASS1_TF_STALL_CYCLES, UINT64, AVERAGE),
 248         COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_INDEX, UINT64, AVERAGE),
 249         COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR, UINT64, AVERAGE),
 250         COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM, UINT64, AVERAGE),
 251         COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_POSITION, UINT64, AVERAGE),
 252         COUNTABLE(PERF_PC_STARVE_CYCLES_DI, UINT64, AVERAGE),
 253         COUNTABLE(PERF_PC_VIS_STREAMS_LOADED, UINT64, AVERAGE),
 254         COUNTABLE(PERF_PC_INSTANCES, UINT64, AVERAGE),
 255         COUNTABLE(PERF_PC_VPC_PRIMITIVES, UINT64, AVERAGE),
 256         COUNTABLE(PERF_PC_DEAD_PRIM, UINT64, AVERAGE),
 257         COUNTABLE(PERF_PC_LIVE_PRIM, UINT64, AVERAGE),
 258         COUNTABLE(PERF_PC_VERTEX_HITS, UINT64, AVERAGE),
 259         COUNTABLE(PERF_PC_IA_VERTICES, UINT64, AVERAGE),
 260         COUNTABLE(PERF_PC_IA_PRIMITIVES, UINT64, AVERAGE),
 261         COUNTABLE(PERF_PC_GS_PRIMITIVES, UINT64, AVERAGE),
 262         COUNTABLE(PERF_PC_HS_INVOCATIONS, UINT64, AVERAGE),
 263         COUNTABLE(PERF_PC_DS_INVOCATIONS, UINT64, AVERAGE),
 264         COUNTABLE(PERF_PC_VS_INVOCATIONS, UINT64, AVERAGE),
 265         COUNTABLE(PERF_PC_GS_INVOCATIONS, UINT64, AVERAGE),
 266         COUNTABLE(PERF_PC_DS_PRIMITIVES, UINT64, AVERAGE),
 267         COUNTABLE(PERF_PC_VPC_POS_DATA_TRANSACTION, UINT64, AVERAGE),
 268         COUNTABLE(PERF_PC_3D_DRAWCALLS, UINT64, AVERAGE),
 269         COUNTABLE(PERF_PC_2D_DRAWCALLS, UINT64, AVERAGE),
 270         COUNTABLE(PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS, UINT64, AVERAGE),
 271         COUNTABLE(PERF_TESS_BUSY_CYCLES, UINT64, AVERAGE),
 272         COUNTABLE(PERF_TESS_WORKING_CYCLES, UINT64, AVERAGE),
 273         COUNTABLE(PERF_TESS_STALL_CYCLES_PC, UINT64, AVERAGE),
 274         COUNTABLE(PERF_TESS_STARVE_CYCLES_PC, UINT64, AVERAGE),
 275 };
 276
 277 static const struct fd_perfcntr_counter rb_counters[] = {
 278         COUNTER(RB_PERFCTR_RB_SEL_0, RBBM_PERFCTR_RB_0_LO, RBBM_PERFCTR_RB_0_HI),
 279         COUNTER(RB_PERFCTR_RB_SEL_1, RBBM_PERFCTR_RB_1_LO, RBBM_PERFCTR_RB_1_HI),
 280         COUNTER(RB_PERFCTR_RB_SEL_2, RBBM_PERFCTR_RB_2_LO, RBBM_PERFCTR_RB_2_HI),
 281         COUNTER(RB_PERFCTR_RB_SEL_3, RBBM_PERFCTR_RB_3_LO, RBBM_PERFCTR_RB_3_HI),
 282         COUNTER(RB_PERFCTR_RB_SEL_4, RBBM_PERFCTR_RB_4_LO, RBBM_PERFCTR_RB_4_HI),
 283         COUNTER(RB_PERFCTR_RB_SEL_5, RBBM_PERFCTR_RB_5_LO, RBBM_PERFCTR_RB_5_HI),
 284         COUNTER(RB_PERFCTR_RB_SEL_6, RBBM_PERFCTR_RB_6_LO, RBBM_PERFCTR_RB_6_HI),
 285         COUNTER(RB_PERFCTR_RB_SEL_7, RBBM_PERFCTR_RB_7_LO, RBBM_PERFCTR_RB_7_HI),
 286 };
 287
 288 static const struct fd_perfcntr_countable rb_countables[] = {
 289         COUNTABLE(PERF_RB_BUSY_CYCLES, UINT64, AVERAGE),
 290         COUNTABLE(PERF_RB_STALL_CYCLES_CCU, UINT64, AVERAGE),
 291         COUNTABLE(PERF_RB_STALL_CYCLES_HLSQ, UINT64, AVERAGE),
 292         COUNTABLE(PERF_RB_STALL_CYCLES_FIFO0_FULL, UINT64, AVERAGE),
 293         COUNTABLE(PERF_RB_STALL_CYCLES_FIFO1_FULL, UINT64, AVERAGE),
 294         COUNTABLE(PERF_RB_STALL_CYCLES_FIFO2_FULL, UINT64, AVERAGE),
 295         COUNTABLE(PERF_RB_STARVE_CYCLES_SP, UINT64, AVERAGE),
 296         COUNTABLE(PERF_RB_STARVE_CYCLES_LRZ_TILE, UINT64, AVERAGE),
 297         COUNTABLE(PERF_RB_STARVE_CYCLES_CCU, UINT64, AVERAGE),
 298         COUNTABLE(PERF_RB_STARVE_CYCLES_Z_PLANE, UINT64, AVERAGE),
 299         COUNTABLE(PERF_RB_STARVE_CYCLES_BARY_PLANE, UINT64, AVERAGE),
 300         COUNTABLE(PERF_RB_Z_WORKLOAD, UINT64, AVERAGE),
 301         COUNTABLE(PERF_RB_HLSQ_ACTIVE, UINT64, AVERAGE),
 302         COUNTABLE(PERF_RB_Z_READ, UINT64, AVERAGE),
 303         COUNTABLE(PERF_RB_Z_WRITE, UINT64, AVERAGE),
 304         COUNTABLE(PERF_RB_C_READ, UINT64, AVERAGE),
 305         COUNTABLE(PERF_RB_C_WRITE, UINT64, AVERAGE),
 306         COUNTABLE(PERF_RB_TOTAL_PASS, UINT64, AVERAGE),
 307         COUNTABLE(PERF_RB_Z_PASS, UINT64, AVERAGE),
 308         COUNTABLE(PERF_RB_Z_FAIL, UINT64, AVERAGE),
 309         COUNTABLE(PERF_RB_S_FAIL, UINT64, AVERAGE),
 310         COUNTABLE(PERF_RB_BLENDED_FXP_COMPONENTS, UINT64, AVERAGE),
 311         COUNTABLE(PERF_RB_BLENDED_FP16_COMPONENTS, UINT64, AVERAGE),
 312         COUNTABLE(RB_RESERVED, UINT64, AVERAGE),
 313         COUNTABLE(PERF_RB_2D_ALIVE_CYCLES, UINT64, AVERAGE),
 314         COUNTABLE(PERF_RB_2D_STALL_CYCLES_A2D, UINT64, AVERAGE),
 315         COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SRC, UINT64, AVERAGE),
 316         COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SP, UINT64, AVERAGE),
 317         COUNTABLE(PERF_RB_2D_STARVE_CYCLES_DST, UINT64, AVERAGE),
 318         COUNTABLE(PERF_RB_2D_VALID_PIXELS, UINT64, AVERAGE),
 319 };
 320
 321 static const struct fd_perfcntr_counter rbbm_counters[] = {
 322 //RESERVED: for kernel
 323 //      COUNTER(RBBM_PERFCTR_RBBM_SEL_0, RBBM_PERFCTR_RBBM_0_LO, RBBM_PERFCTR_RBBM_0_HI),
 324         COUNTER(RBBM_PERFCTR_RBBM_SEL_1, RBBM_PERFCTR_RBBM_1_LO, RBBM_PERFCTR_RBBM_1_HI),
 325         COUNTER(RBBM_PERFCTR_RBBM_SEL_2, RBBM_PERFCTR_RBBM_2_LO, RBBM_PERFCTR_RBBM_2_HI),
 326         COUNTER(RBBM_PERFCTR_RBBM_SEL_3, RBBM_PERFCTR_RBBM_3_LO, RBBM_PERFCTR_RBBM_3_HI),
 327 };
 328
 329 static const struct fd_perfcntr_countable rbbm_countables[] = {
 330         COUNTABLE(PERF_RBBM_ALWAYS_COUNT, UINT64, AVERAGE),
 331         COUNTABLE(PERF_RBBM_ALWAYS_ON, UINT64, AVERAGE),
 332         COUNTABLE(PERF_RBBM_TSE_BUSY, UINT64, AVERAGE),
 333         COUNTABLE(PERF_RBBM_RAS_BUSY, UINT64, AVERAGE),
 334         COUNTABLE(PERF_RBBM_PC_DCALL_BUSY, UINT64, AVERAGE),
 335         COUNTABLE(PERF_RBBM_PC_VSD_BUSY, UINT64, AVERAGE),
 336         COUNTABLE(PERF_RBBM_STATUS_MASKED, UINT64, AVERAGE),
 337         COUNTABLE(PERF_RBBM_COM_BUSY, UINT64, AVERAGE),
 338         COUNTABLE(PERF_RBBM_DCOM_BUSY, UINT64, AVERAGE),
 339         COUNTABLE(PERF_RBBM_VBIF_BUSY, UINT64, AVERAGE),
 340         COUNTABLE(PERF_RBBM_VSC_BUSY, UINT64, AVERAGE),
 341         COUNTABLE(PERF_RBBM_TESS_BUSY, UINT64, AVERAGE),
 342         COUNTABLE(PERF_RBBM_UCHE_BUSY, UINT64, AVERAGE),
 343         COUNTABLE(PERF_RBBM_HLSQ_BUSY, UINT64, AVERAGE),
 344 };
 345
 346 static const struct fd_perfcntr_counter sp_counters[] = {
 347 //RESERVED: for kernel
 348 //      COUNTER(SP_PERFCTR_SP_SEL_0,  RBBM_PERFCTR_SP_0_LO,  RBBM_PERFCTR_SP_0_HI),
 349         COUNTER(SP_PERFCTR_SP_SEL_1,  RBBM_PERFCTR_SP_1_LO,  RBBM_PERFCTR_SP_1_HI),
 350         COUNTER(SP_PERFCTR_SP_SEL_2,  RBBM_PERFCTR_SP_2_LO,  RBBM_PERFCTR_SP_2_HI),
 351         COUNTER(SP_PERFCTR_SP_SEL_3,  RBBM_PERFCTR_SP_3_LO,  RBBM_PERFCTR_SP_3_HI),
 352         COUNTER(SP_PERFCTR_SP_SEL_4,  RBBM_PERFCTR_SP_4_LO,  RBBM_PERFCTR_SP_4_HI),
 353         COUNTER(SP_PERFCTR_SP_SEL_5,  RBBM_PERFCTR_SP_5_LO,  RBBM_PERFCTR_SP_5_HI),
 354         COUNTER(SP_PERFCTR_SP_SEL_6,  RBBM_PERFCTR_SP_6_LO,  RBBM_PERFCTR_SP_6_HI),
 355         COUNTER(SP_PERFCTR_SP_SEL_7,  RBBM_PERFCTR_SP_7_LO,  RBBM_PERFCTR_SP_7_HI),
 356         COUNTER(SP_PERFCTR_SP_SEL_8,  RBBM_PERFCTR_SP_8_LO,  RBBM_PERFCTR_SP_8_HI),
 357         COUNTER(SP_PERFCTR_SP_SEL_9,  RBBM_PERFCTR_SP_9_LO,  RBBM_PERFCTR_SP_9_HI),
 358         COUNTER(SP_PERFCTR_SP_SEL_10, RBBM_PERFCTR_SP_10_LO, RBBM_PERFCTR_SP_10_HI),
 359         COUNTER(SP_PERFCTR_SP_SEL_11, RBBM_PERFCTR_SP_11_LO, RBBM_PERFCTR_SP_11_HI),
 360 };
 361
 362 static const struct fd_perfcntr_countable sp_countables[] = {
 363         COUNTABLE(PERF_SP_BUSY_CYCLES, UINT64, AVERAGE),
 364         COUNTABLE(PERF_SP_ALU_WORKING_CYCLES, UINT64, AVERAGE),
 365         COUNTABLE(PERF_SP_EFU_WORKING_CYCLES, UINT64, AVERAGE),
 366         COUNTABLE(PERF_SP_STALL_CYCLES_VPC, UINT64, AVERAGE),
 367         COUNTABLE(PERF_SP_STALL_CYCLES_TP, UINT64, AVERAGE),
 368         COUNTABLE(PERF_SP_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 369         COUNTABLE(PERF_SP_STALL_CYCLES_RB, UINT64, AVERAGE),
 370         COUNTABLE(PERF_SP_SCHEDULER_NON_WORKING, UINT64, AVERAGE),
 371         COUNTABLE(PERF_SP_WAVE_CONTEXTS, UINT64, AVERAGE),
 372         COUNTABLE(PERF_SP_WAVE_CONTEXT_CYCLES, UINT64, AVERAGE),
 373         COUNTABLE(PERF_SP_FS_STAGE_WAVE_CYCLES, UINT64, AVERAGE),
 374         COUNTABLE(PERF_SP_FS_STAGE_WAVE_SAMPLES, UINT64, AVERAGE),
 375         COUNTABLE(PERF_SP_VS_STAGE_WAVE_CYCLES, UINT64, AVERAGE),
 376         COUNTABLE(PERF_SP_VS_STAGE_WAVE_SAMPLES, UINT64, AVERAGE),
 377         COUNTABLE(PERF_SP_FS_STAGE_DURATION_CYCLES, UINT64, AVERAGE),
 378         COUNTABLE(PERF_SP_VS_STAGE_DURATION_CYCLES, UINT64, AVERAGE),
 379         COUNTABLE(PERF_SP_WAVE_CTRL_CYCLES, UINT64, AVERAGE),
 380         COUNTABLE(PERF_SP_WAVE_LOAD_CYCLES, UINT64, AVERAGE),
 381         COUNTABLE(PERF_SP_WAVE_EMIT_CYCLES, UINT64, AVERAGE),
 382         COUNTABLE(PERF_SP_WAVE_NOP_CYCLES, UINT64, AVERAGE),
 383         COUNTABLE(PERF_SP_WAVE_WAIT_CYCLES, UINT64, AVERAGE),
 384         COUNTABLE(PERF_SP_WAVE_FETCH_CYCLES, UINT64, AVERAGE),
 385         COUNTABLE(PERF_SP_WAVE_IDLE_CYCLES, UINT64, AVERAGE),
 386         COUNTABLE(PERF_SP_WAVE_END_CYCLES, UINT64, AVERAGE),
 387         COUNTABLE(PERF_SP_WAVE_LONG_SYNC_CYCLES, UINT64, AVERAGE),
 388         COUNTABLE(PERF_SP_WAVE_SHORT_SYNC_CYCLES, UINT64, AVERAGE),
 389         COUNTABLE(PERF_SP_WAVE_JOIN_CYCLES, UINT64, AVERAGE),
 390         COUNTABLE(PERF_SP_LM_LOAD_INSTRUCTIONS, UINT64, AVERAGE),
 391         COUNTABLE(PERF_SP_LM_STORE_INSTRUCTIONS, UINT64, AVERAGE),
 392         COUNTABLE(PERF_SP_LM_ATOMICS, UINT64, AVERAGE),
 393         COUNTABLE(PERF_SP_GM_LOAD_INSTRUCTIONS, UINT64, AVERAGE),
 394         COUNTABLE(PERF_SP_GM_STORE_INSTRUCTIONS, UINT64, AVERAGE),
 395         COUNTABLE(PERF_SP_GM_ATOMICS, UINT64, AVERAGE),
 396         COUNTABLE(PERF_SP_VS_STAGE_TEX_INSTRUCTIONS, UINT64, AVERAGE),
 397         COUNTABLE(PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS, UINT64, AVERAGE),
 398         COUNTABLE(PERF_SP_VS_STAGE_EFU_INSTRUCTIONS, UINT64, AVERAGE),
 399         COUNTABLE(PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS, UINT64, AVERAGE),
 400         COUNTABLE(PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS, UINT64, AVERAGE),
 401         COUNTABLE(PERF_SP_FS_STAGE_TEX_INSTRUCTIONS, UINT64, AVERAGE),
 402         COUNTABLE(PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS, UINT64, AVERAGE),
 403         COUNTABLE(PERF_SP_FS_STAGE_EFU_INSTRUCTIONS, UINT64, AVERAGE),
 404         COUNTABLE(PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS, UINT64, AVERAGE),
 405         COUNTABLE(PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS, UINT64, AVERAGE),
 406         COUNTABLE(PERF_SP_FS_STAGE_BARY_INSTRUCTIONS, UINT64, AVERAGE),
 407         COUNTABLE(PERF_SP_VS_INSTRUCTIONS, UINT64, AVERAGE),
 408         COUNTABLE(PERF_SP_FS_INSTRUCTIONS, UINT64, AVERAGE),
 409         COUNTABLE(PERF_SP_ADDR_LOCK_COUNT, UINT64, AVERAGE),
 410         COUNTABLE(PERF_SP_UCHE_READ_TRANS, UINT64, AVERAGE),
 411         COUNTABLE(PERF_SP_UCHE_WRITE_TRANS, UINT64, AVERAGE),
 412         COUNTABLE(PERF_SP_EXPORT_VPC_TRANS, UINT64, AVERAGE),
 413         COUNTABLE(PERF_SP_EXPORT_RB_TRANS, UINT64, AVERAGE),
 414         COUNTABLE(PERF_SP_PIXELS_KILLED, UINT64, AVERAGE),
 415         COUNTABLE(PERF_SP_ICL1_REQUESTS, UINT64, AVERAGE),
 416         COUNTABLE(PERF_SP_ICL1_MISSES, UINT64, AVERAGE),
 417         COUNTABLE(PERF_SP_ICL0_REQUESTS, UINT64, AVERAGE),
 418         COUNTABLE(PERF_SP_ICL0_MISSES, UINT64, AVERAGE),
 419         COUNTABLE(PERF_SP_HS_INSTRUCTIONS, UINT64, AVERAGE),
 420         COUNTABLE(PERF_SP_DS_INSTRUCTIONS, UINT64, AVERAGE),
 421         COUNTABLE(PERF_SP_GS_INSTRUCTIONS, UINT64, AVERAGE),
 422         COUNTABLE(PERF_SP_CS_INSTRUCTIONS, UINT64, AVERAGE),
 423         COUNTABLE(PERF_SP_GPR_READ, UINT64, AVERAGE),
 424         COUNTABLE(PERF_SP_GPR_WRITE, UINT64, AVERAGE),
 425         COUNTABLE(PERF_SP_LM_CH0_REQUESTS, UINT64, AVERAGE),
 426         COUNTABLE(PERF_SP_LM_CH1_REQUESTS, UINT64, AVERAGE),
 427         COUNTABLE(PERF_SP_LM_BANK_CONFLICTS, UINT64, AVERAGE),
 428 };
 429
 430 static const struct fd_perfcntr_counter tp_counters[] = {
 431         COUNTER(TPL1_PERFCTR_TP_SEL_0, RBBM_PERFCTR_TP_0_LO, RBBM_PERFCTR_TP_0_HI),
 432         COUNTER(TPL1_PERFCTR_TP_SEL_1, RBBM_PERFCTR_TP_1_LO, RBBM_PERFCTR_TP_1_HI),
 433         COUNTER(TPL1_PERFCTR_TP_SEL_2, RBBM_PERFCTR_TP_2_LO, RBBM_PERFCTR_TP_2_HI),
 434         COUNTER(TPL1_PERFCTR_TP_SEL_3, RBBM_PERFCTR_TP_3_LO, RBBM_PERFCTR_TP_3_HI),
 435         COUNTER(TPL1_PERFCTR_TP_SEL_4, RBBM_PERFCTR_TP_4_LO, RBBM_PERFCTR_TP_4_HI),
 436         COUNTER(TPL1_PERFCTR_TP_SEL_5, RBBM_PERFCTR_TP_5_LO, RBBM_PERFCTR_TP_5_HI),
 437         COUNTER(TPL1_PERFCTR_TP_SEL_6, RBBM_PERFCTR_TP_6_LO, RBBM_PERFCTR_TP_6_HI),
 438         COUNTER(TPL1_PERFCTR_TP_SEL_7, RBBM_PERFCTR_TP_7_LO, RBBM_PERFCTR_TP_7_HI),
 439 };
 440
 441 static const struct fd_perfcntr_countable tp_countables[] = {
 442         COUNTABLE(PERF_TP_BUSY_CYCLES, UINT64, AVERAGE),
 443         COUNTABLE(PERF_TP_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 444         COUNTABLE(PERF_TP_LATENCY_CYCLES, UINT64, AVERAGE),
 445         COUNTABLE(PERF_TP_LATENCY_TRANS, UINT64, AVERAGE),
 446         COUNTABLE(PERF_TP_FLAG_CACHE_REQUEST_SAMPLES, UINT64, AVERAGE),
 447         COUNTABLE(PERF_TP_FLAG_CACHE_REQUEST_LATENCY, UINT64, AVERAGE),
 448         COUNTABLE(PERF_TP_L1_CACHELINE_REQUESTS, UINT64, AVERAGE),
 449         COUNTABLE(PERF_TP_L1_CACHELINE_MISSES, UINT64, AVERAGE),
 450         COUNTABLE(PERF_TP_SP_TP_TRANS, UINT64, AVERAGE),
 451         COUNTABLE(PERF_TP_TP_SP_TRANS, UINT64, AVERAGE),
 452         COUNTABLE(PERF_TP_OUTPUT_PIXELS, UINT64, AVERAGE),
 453         COUNTABLE(PERF_TP_FILTER_WORKLOAD_16BIT, UINT64, AVERAGE),
 454         COUNTABLE(PERF_TP_FILTER_WORKLOAD_32BIT, UINT64, AVERAGE),
 455         COUNTABLE(PERF_TP_QUADS_RECEIVED, UINT64, AVERAGE),
 456         COUNTABLE(PERF_TP_QUADS_OFFSET, UINT64, AVERAGE),
 457         COUNTABLE(PERF_TP_QUADS_SHADOW, UINT64, AVERAGE),
 458         COUNTABLE(PERF_TP_QUADS_ARRAY, UINT64, AVERAGE),
 459         COUNTABLE(PERF_TP_QUADS_GRADIENT, UINT64, AVERAGE),
 460         COUNTABLE(PERF_TP_QUADS_1D, UINT64, AVERAGE),
 461         COUNTABLE(PERF_TP_QUADS_2D, UINT64, AVERAGE),
 462         COUNTABLE(PERF_TP_QUADS_BUFFER, UINT64, AVERAGE),
 463         COUNTABLE(PERF_TP_QUADS_3D, UINT64, AVERAGE),
 464         COUNTABLE(PERF_TP_QUADS_CUBE, UINT64, AVERAGE),
 465         COUNTABLE(PERF_TP_STATE_CACHE_REQUESTS, UINT64, AVERAGE),
 466         COUNTABLE(PERF_TP_STATE_CACHE_MISSES, UINT64, AVERAGE),
 467         COUNTABLE(PERF_TP_DIVERGENT_QUADS_RECEIVED, UINT64, AVERAGE),
 468         COUNTABLE(PERF_TP_BINDLESS_STATE_CACHE_REQUESTS, UINT64, AVERAGE),
 469         COUNTABLE(PERF_TP_BINDLESS_STATE_CACHE_MISSES, UINT64, AVERAGE),
 470         COUNTABLE(PERF_TP_PRT_NON_RESIDENT_EVENTS, UINT64, AVERAGE),
 471         COUNTABLE(PERF_TP_OUTPUT_PIXELS_POINT, UINT64, AVERAGE),
 472         COUNTABLE(PERF_TP_OUTPUT_PIXELS_BILINEAR, UINT64, AVERAGE),
 473         COUNTABLE(PERF_TP_OUTPUT_PIXELS_MIP, UINT64, AVERAGE),
 474         COUNTABLE(PERF_TP_OUTPUT_PIXELS_ANISO, UINT64, AVERAGE),
 475         COUNTABLE(PERF_TP_OUTPUT_PIXELS_ZERO_LOD, UINT64, AVERAGE),
 476         COUNTABLE(PERF_TP_FLAG_CACHE_REQUESTS, UINT64, AVERAGE),
 477         COUNTABLE(PERF_TP_FLAG_CACHE_MISSES, UINT64, AVERAGE),
 478         COUNTABLE(PERF_TP_L1_5_L2_REQUESTS, UINT64, AVERAGE),
 479         COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS, UINT64, AVERAGE),
 480         COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_POINT, UINT64, AVERAGE),
 481         COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_BILINEAR, UINT64, AVERAGE),
 482         COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_16BIT, UINT64, AVERAGE),
 483         COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_32BIT, UINT64, AVERAGE),
 484 };
 485
 486 static const struct fd_perfcntr_counter uche_counters[] = {
 487         COUNTER(UCHE_PERFCTR_UCHE_SEL_0, RBBM_PERFCTR_UCHE_0_LO, RBBM_PERFCTR_UCHE_0_HI),
 488         COUNTER(UCHE_PERFCTR_UCHE_SEL_1, RBBM_PERFCTR_UCHE_1_LO, RBBM_PERFCTR_UCHE_1_HI),
 489         COUNTER(UCHE_PERFCTR_UCHE_SEL_2, RBBM_PERFCTR_UCHE_2_LO, RBBM_PERFCTR_UCHE_2_HI),
 490         COUNTER(UCHE_PERFCTR_UCHE_SEL_3, RBBM_PERFCTR_UCHE_3_LO, RBBM_PERFCTR_UCHE_3_HI),
 491         COUNTER(UCHE_PERFCTR_UCHE_SEL_4, RBBM_PERFCTR_UCHE_4_LO, RBBM_PERFCTR_UCHE_4_HI),
 492         COUNTER(UCHE_PERFCTR_UCHE_SEL_5, RBBM_PERFCTR_UCHE_5_LO, RBBM_PERFCTR_UCHE_5_HI),
 493         COUNTER(UCHE_PERFCTR_UCHE_SEL_6, RBBM_PERFCTR_UCHE_6_LO, RBBM_PERFCTR_UCHE_6_HI),
 494         COUNTER(UCHE_PERFCTR_UCHE_SEL_7, RBBM_PERFCTR_UCHE_7_LO, RBBM_PERFCTR_UCHE_7_HI),
 495 };
 496
 497 static const struct fd_perfcntr_countable uche_countables[] = {
 498         COUNTABLE(PERF_UCHE_BUSY_CYCLES, UINT64, AVERAGE),
 499         COUNTABLE(PERF_UCHE_STALL_CYCLES_VBIF, UINT64, AVERAGE),
 500         COUNTABLE(PERF_UCHE_VBIF_LATENCY_CYCLES, UINT64, AVERAGE),
 501         COUNTABLE(PERF_UCHE_VBIF_LATENCY_SAMPLES, UINT64, AVERAGE),
 502         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_TP, UINT64, AVERAGE),
 503         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_VFD, UINT64, AVERAGE),
 504         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_HLSQ, UINT64, AVERAGE),
 505         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_LRZ, UINT64, AVERAGE),
 506         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_SP, UINT64, AVERAGE),
 507         COUNTABLE(PERF_UCHE_READ_REQUESTS_TP, UINT64, AVERAGE),
 508         COUNTABLE(PERF_UCHE_READ_REQUESTS_VFD, UINT64, AVERAGE),
 509         COUNTABLE(PERF_UCHE_READ_REQUESTS_HLSQ, UINT64, AVERAGE),
 510         COUNTABLE(PERF_UCHE_READ_REQUESTS_LRZ, UINT64, AVERAGE),
 511         COUNTABLE(PERF_UCHE_READ_REQUESTS_SP, UINT64, AVERAGE),
 512         COUNTABLE(PERF_UCHE_WRITE_REQUESTS_LRZ, UINT64, AVERAGE),
 513         COUNTABLE(PERF_UCHE_WRITE_REQUESTS_SP, UINT64, AVERAGE),
 514         COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VPC, UINT64, AVERAGE),
 515         COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VSC, UINT64, AVERAGE),
 516         COUNTABLE(PERF_UCHE_EVICTS, UINT64, AVERAGE),
 517         COUNTABLE(PERF_UCHE_BANK_REQ0, UINT64, AVERAGE),
 518         COUNTABLE(PERF_UCHE_BANK_REQ1, UINT64, AVERAGE),
 519         COUNTABLE(PERF_UCHE_BANK_REQ2, UINT64, AVERAGE),
 520         COUNTABLE(PERF_UCHE_BANK_REQ3, UINT64, AVERAGE),
 521         COUNTABLE(PERF_UCHE_BANK_REQ4, UINT64, AVERAGE),
 522         COUNTABLE(PERF_UCHE_BANK_REQ5, UINT64, AVERAGE),
 523         COUNTABLE(PERF_UCHE_BANK_REQ6, UINT64, AVERAGE),
 524         COUNTABLE(PERF_UCHE_BANK_REQ7, UINT64, AVERAGE),
 525         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH0, UINT64, AVERAGE),
 526         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH1, UINT64, AVERAGE),
 527         COUNTABLE(PERF_UCHE_GMEM_READ_BEATS, UINT64, AVERAGE),
 528         COUNTABLE(PERF_UCHE_FLAG_COUNT, UINT64, AVERAGE),
 529 };
 530
 531 static const struct fd_perfcntr_counter vfd_counters[] = {
 532         COUNTER(VFD_PERFCTR_VFD_SEL_0, RBBM_PERFCTR_VFD_0_LO, RBBM_PERFCTR_VFD_0_HI),
 533         COUNTER(VFD_PERFCTR_VFD_SEL_1, RBBM_PERFCTR_VFD_1_LO, RBBM_PERFCTR_VFD_1_HI),
 534         COUNTER(VFD_PERFCTR_VFD_SEL_2, RBBM_PERFCTR_VFD_2_LO, RBBM_PERFCTR_VFD_2_HI),
 535         COUNTER(VFD_PERFCTR_VFD_SEL_3, RBBM_PERFCTR_VFD_3_LO, RBBM_PERFCTR_VFD_3_HI),
 536         COUNTER(VFD_PERFCTR_VFD_SEL_4, RBBM_PERFCTR_VFD_4_LO, RBBM_PERFCTR_VFD_4_HI),
 537         COUNTER(VFD_PERFCTR_VFD_SEL_5, RBBM_PERFCTR_VFD_5_LO, RBBM_PERFCTR_VFD_5_HI),
 538         COUNTER(VFD_PERFCTR_VFD_SEL_6, RBBM_PERFCTR_VFD_6_LO, RBBM_PERFCTR_VFD_6_HI),
 539         COUNTER(VFD_PERFCTR_VFD_SEL_7, RBBM_PERFCTR_VFD_7_LO, RBBM_PERFCTR_VFD_7_HI),
 540 };
 541
 542 static const struct fd_perfcntr_countable vfd_countables[] = {
 543         COUNTABLE(PERF_VFD_BUSY_CYCLES, UINT64, AVERAGE),
 544         COUNTABLE(PERF_VFD_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 545         COUNTABLE(PERF_VFD_STALL_CYCLES_VPC_ALLOC, UINT64, AVERAGE),
 546         COUNTABLE(PERF_VFD_STALL_CYCLES_MISS_VB, UINT64, AVERAGE),
 547         COUNTABLE(PERF_VFD_STALL_CYCLES_MISS_Q, UINT64, AVERAGE),
 548         COUNTABLE(PERF_VFD_STALL_CYCLES_SP_INFO, UINT64, AVERAGE),
 549         COUNTABLE(PERF_VFD_STALL_CYCLES_SP_ATTR, UINT64, AVERAGE),
 550         COUNTABLE(PERF_VFD_STALL_CYCLES_VFDP_VB, UINT64, AVERAGE),
 551         COUNTABLE(PERF_VFD_STALL_CYCLES_VFDP_Q, UINT64, AVERAGE),
 552         COUNTABLE(PERF_VFD_DECODER_PACKER_STALL, UINT64, AVERAGE),
 553         COUNTABLE(PERF_VFD_STARVE_CYCLES_UCHE, UINT64, AVERAGE),
 554         COUNTABLE(PERF_VFD_RBUFFER_FULL, UINT64, AVERAGE),
 555         COUNTABLE(PERF_VFD_ATTR_INFO_FIFO_FULL, UINT64, AVERAGE),
 556         COUNTABLE(PERF_VFD_DECODED_ATTRIBUTE_BYTES, UINT64, AVERAGE),
 557         COUNTABLE(PERF_VFD_NUM_ATTRIBUTES, UINT64, AVERAGE),
 558         COUNTABLE(PERF_VFD_INSTRUCTIONS, UINT64, AVERAGE),
 559         COUNTABLE(PERF_VFD_UPPER_SHADER_FIBERS, UINT64, AVERAGE),
 560         COUNTABLE(PERF_VFD_LOWER_SHADER_FIBERS, UINT64, AVERAGE),
 561         COUNTABLE(PERF_VFD_MODE_0_FIBERS, UINT64, AVERAGE),
 562         COUNTABLE(PERF_VFD_MODE_1_FIBERS, UINT64, AVERAGE),
 563         COUNTABLE(PERF_VFD_MODE_2_FIBERS, UINT64, AVERAGE),
 564         COUNTABLE(PERF_VFD_MODE_3_FIBERS, UINT64, AVERAGE),
 565         COUNTABLE(PERF_VFD_MODE_4_FIBERS, UINT64, AVERAGE),
 566         COUNTABLE(PERF_VFD_TOTAL_VERTICES, UINT64, AVERAGE),
 567         COUNTABLE(PERF_VFD_NUM_ATTR_MISS, UINT64, AVERAGE),
 568         COUNTABLE(PERF_VFD_1_BURST_REQ, UINT64, AVERAGE),
 569         COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD, UINT64, AVERAGE),
 570         COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_INDEX, UINT64, AVERAGE),
 571         COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_PROG, UINT64, AVERAGE),
 572         COUNTABLE(PERF_VFDP_STARVE_CYCLES_PC, UINT64, AVERAGE),
 573         COUNTABLE(PERF_VFDP_VS_STAGE_32_WAVES, UINT64, AVERAGE),
 574 };
 575
 576 static const struct fd_perfcntr_counter vpc_counters[] = {
 577         COUNTER(VPC_PERFCTR_VPC_SEL_0, RBBM_PERFCTR_VPC_0_LO, RBBM_PERFCTR_VPC_0_HI),
 578         COUNTER(VPC_PERFCTR_VPC_SEL_1, RBBM_PERFCTR_VPC_1_LO, RBBM_PERFCTR_VPC_1_HI),
 579         COUNTER(VPC_PERFCTR_VPC_SEL_2, RBBM_PERFCTR_VPC_2_LO, RBBM_PERFCTR_VPC_2_HI),
 580         COUNTER(VPC_PERFCTR_VPC_SEL_3, RBBM_PERFCTR_VPC_3_LO, RBBM_PERFCTR_VPC_3_HI),
 581 };
 582
 583 static const struct fd_perfcntr_countable vpc_countables[] = {
 584         COUNTABLE(PERF_VPC_BUSY_CYCLES, UINT64, AVERAGE),
 585         COUNTABLE(PERF_VPC_WORKING_CYCLES, UINT64, AVERAGE),
 586         COUNTABLE(PERF_VPC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 587         COUNTABLE(PERF_VPC_STALL_CYCLES_VFD_WACK, UINT64, AVERAGE),
 588         COUNTABLE(PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC, UINT64, AVERAGE),
 589         COUNTABLE(PERF_VPC_STALL_CYCLES_PC, UINT64, AVERAGE),
 590         COUNTABLE(PERF_VPC_STALL_CYCLES_SP_LM, UINT64, AVERAGE),
 591         COUNTABLE(PERF_VPC_POS_EXPORT_STALL_CYCLES, UINT64, AVERAGE),
 592         COUNTABLE(PERF_VPC_STARVE_CYCLES_SP, UINT64, AVERAGE),
 593         COUNTABLE(PERF_VPC_STARVE_CYCLES_LRZ, UINT64, AVERAGE),
 594         COUNTABLE(PERF_VPC_PC_PRIMITIVES, UINT64, AVERAGE),
 595         COUNTABLE(PERF_VPC_SP_COMPONENTS, UINT64, AVERAGE),
 596         COUNTABLE(PERF_VPC_SP_LM_PRIMITIVES, UINT64, AVERAGE),
 597         COUNTABLE(PERF_VPC_SP_LM_COMPONENTS, UINT64, AVERAGE),
 598         COUNTABLE(PERF_VPC_SP_LM_DWORDS, UINT64, AVERAGE),
 599         COUNTABLE(PERF_VPC_STREAMOUT_COMPONENTS, UINT64, AVERAGE),
 600         COUNTABLE(PERF_VPC_GRANT_PHASES, UINT64, AVERAGE),
 601 };
 602
 603 static const struct fd_perfcntr_counter vsc_counters[] = {
 604         COUNTER(VSC_PERFCTR_VSC_SEL_0, RBBM_PERFCTR_VSC_0_LO, RBBM_PERFCTR_VSC_0_HI),
 605         COUNTER(VSC_PERFCTR_VSC_SEL_1, RBBM_PERFCTR_VSC_1_LO, RBBM_PERFCTR_VSC_1_HI),
 606 };
 607
 608 static const struct fd_perfcntr_countable vsc_countables[] = {
 609         COUNTABLE(PERF_VSC_BUSY_CYCLES, UINT64, AVERAGE),
 610         COUNTABLE(PERF_VSC_WORKING_CYCLES, UINT64, AVERAGE),
 611         COUNTABLE(PERF_VSC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 612         COUNTABLE(PERF_VSC_EOT_NUM, UINT64, AVERAGE),
 613 };
 614
 615 /* VBIF counters probably not too userful for userspace, and they make
 616  * frameretrace take many more passes to collect all the metrics, so
 617  * for now let's hide them.
 618  */
 619 #if 0
 620 /* VBIF counters break the pattern a bit, with enable and clear regs: */
 621 static const struct fd_perfcntr_counter vbif_counters[] = {
 622         COUNTER2(VBIF_PERF_CNT_SEL0, VBIF_PERF_CNT_LOW0, VBIF_PERF_CNT_HIGH0, VBIF_PERF_CNT_EN0, VBIF_PERF_CNT_CLR0),
 623         COUNTER2(VBIF_PERF_CNT_SEL1, VBIF_PERF_CNT_LOW1, VBIF_PERF_CNT_HIGH1, VBIF_PERF_CNT_EN1, VBIF_PERF_CNT_CLR1),
 624         COUNTER2(VBIF_PERF_CNT_SEL2, VBIF_PERF_CNT_LOW2, VBIF_PERF_CNT_HIGH2, VBIF_PERF_CNT_EN2, VBIF_PERF_CNT_CLR2),
 625         COUNTER2(VBIF_PERF_CNT_SEL3, VBIF_PERF_CNT_LOW3, VBIF_PERF_CNT_HIGH3, VBIF_PERF_CNT_EN3, VBIF_PERF_CNT_CLR3),
 626 };
 627
 628 static const struct fd_perfcntr_countable vbif_countables[] = {
 629         COUNTABLE(AXI_READ_REQUESTS_ID_0, UINT64, AVERAGE),
 630         COUNTABLE(AXI_READ_REQUESTS_ID_1, UINT64, AVERAGE),
 631         COUNTABLE(AXI_READ_REQUESTS_ID_2, UINT64, AVERAGE),
 632         COUNTABLE(AXI_READ_REQUESTS_ID_3, UINT64, AVERAGE),
 633         COUNTABLE(AXI_READ_REQUESTS_ID_4, UINT64, AVERAGE),
 634         COUNTABLE(AXI_READ_REQUESTS_ID_5, UINT64, AVERAGE),
 635         COUNTABLE(AXI_READ_REQUESTS_ID_6, UINT64, AVERAGE),
 636         COUNTABLE(AXI_READ_REQUESTS_ID_7, UINT64, AVERAGE),
 637         COUNTABLE(AXI_READ_REQUESTS_ID_8, UINT64, AVERAGE),
 638         COUNTABLE(AXI_READ_REQUESTS_ID_9, UINT64, AVERAGE),
 639         COUNTABLE(AXI_READ_REQUESTS_ID_10, UINT64, AVERAGE),
 640         COUNTABLE(AXI_READ_REQUESTS_ID_11, UINT64, AVERAGE),
 641         COUNTABLE(AXI_READ_REQUESTS_ID_12, UINT64, AVERAGE),
 642         COUNTABLE(AXI_READ_REQUESTS_ID_13, UINT64, AVERAGE),
 643         COUNTABLE(AXI_READ_REQUESTS_ID_14, UINT64, AVERAGE),
 644         COUNTABLE(AXI_READ_REQUESTS_ID_15, UINT64, AVERAGE),
 645         COUNTABLE(AXI0_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
 646         COUNTABLE(AXI1_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
 647         COUNTABLE(AXI2_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
 648         COUNTABLE(AXI3_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
 649         COUNTABLE(AXI_READ_REQUESTS_TOTAL, UINT64, AVERAGE),
 650         COUNTABLE(AXI_WRITE_REQUESTS_ID_0, UINT64, AVERAGE),
 651         COUNTABLE(AXI_WRITE_REQUESTS_ID_1, UINT64, AVERAGE),
 652         COUNTABLE(AXI_WRITE_REQUESTS_ID_2, UINT64, AVERAGE),
 653         COUNTABLE(AXI_WRITE_REQUESTS_ID_3, UINT64, AVERAGE),
 654         COUNTABLE(AXI_WRITE_REQUESTS_ID_4, UINT64, AVERAGE),
 655         COUNTABLE(AXI_WRITE_REQUESTS_ID_5, UINT64, AVERAGE),
 656         COUNTABLE(AXI_WRITE_REQUESTS_ID_6, UINT64, AVERAGE),
 657         COUNTABLE(AXI_WRITE_REQUESTS_ID_7, UINT64, AVERAGE),
 658         COUNTABLE(AXI_WRITE_REQUESTS_ID_8, UINT64, AVERAGE),
 659         COUNTABLE(AXI_WRITE_REQUESTS_ID_9, UINT64, AVERAGE),
 660         COUNTABLE(AXI_WRITE_REQUESTS_ID_10, UINT64, AVERAGE),
 661         COUNTABLE(AXI_WRITE_REQUESTS_ID_11, UINT64, AVERAGE),
 662         COUNTABLE(AXI_WRITE_REQUESTS_ID_12, UINT64, AVERAGE),
 663         COUNTABLE(AXI_WRITE_REQUESTS_ID_13, UINT64, AVERAGE),
 664         COUNTABLE(AXI_WRITE_REQUESTS_ID_14, UINT64, AVERAGE),
 665         COUNTABLE(AXI_WRITE_REQUESTS_ID_15, UINT64, AVERAGE),
 666         COUNTABLE(AXI0_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
 667         COUNTABLE(AXI1_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
 668         COUNTABLE(AXI2_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
 669         COUNTABLE(AXI3_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
 670         COUNTABLE(AXI_WRITE_REQUESTS_TOTAL, UINT64, AVERAGE),
 671         COUNTABLE(AXI_TOTAL_REQUESTS, UINT64, AVERAGE),
 672         COUNTABLE(AXI_READ_DATA_BEATS_ID_0, UINT64, AVERAGE),
 673         COUNTABLE(AXI_READ_DATA_BEATS_ID_1, UINT64, AVERAGE),
 674         COUNTABLE(AXI_READ_DATA_BEATS_ID_2, UINT64, AVERAGE),
 675         COUNTABLE(AXI_READ_DATA_BEATS_ID_3, UINT64, AVERAGE),
 676         COUNTABLE(AXI_READ_DATA_BEATS_ID_4, UINT64, AVERAGE),
 677         COUNTABLE(AXI_READ_DATA_BEATS_ID_5, UINT64, AVERAGE),
 678         COUNTABLE(AXI_READ_DATA_BEATS_ID_6, UINT64, AVERAGE),
 679         COUNTABLE(AXI_READ_DATA_BEATS_ID_7, UINT64, AVERAGE),
 680         COUNTABLE(AXI_READ_DATA_BEATS_ID_8, UINT64, AVERAGE),
 681         COUNTABLE(AXI_READ_DATA_BEATS_ID_9, UINT64, AVERAGE),
 682         COUNTABLE(AXI_READ_DATA_BEATS_ID_10, UINT64, AVERAGE),
 683         COUNTABLE(AXI_READ_DATA_BEATS_ID_11, UINT64, AVERAGE),
 684         COUNTABLE(AXI_READ_DATA_BEATS_ID_12, UINT64, AVERAGE),
 685         COUNTABLE(AXI_READ_DATA_BEATS_ID_13, UINT64, AVERAGE),
 686         COUNTABLE(AXI_READ_DATA_BEATS_ID_14, UINT64, AVERAGE),
 687         COUNTABLE(AXI_READ_DATA_BEATS_ID_15, UINT64, AVERAGE),
 688         COUNTABLE(AXI0_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
 689         COUNTABLE(AXI1_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
 690         COUNTABLE(AXI2_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
 691         COUNTABLE(AXI3_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
 692         COUNTABLE(AXI_READ_DATA_BEATS_TOTAL, UINT64, AVERAGE),
 693         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_0, UINT64, AVERAGE),
 694         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_1, UINT64, AVERAGE),
 695         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_2, UINT64, AVERAGE),
 696         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_3, UINT64, AVERAGE),
 697         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_4, UINT64, AVERAGE),
 698         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_5, UINT64, AVERAGE),
 699         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_6, UINT64, AVERAGE),
 700         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_7, UINT64, AVERAGE),
 701         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_8, UINT64, AVERAGE),
 702         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_9, UINT64, AVERAGE),
 703         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_10, UINT64, AVERAGE),
 704         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_11, UINT64, AVERAGE),
 705         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_12, UINT64, AVERAGE),
 706         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_13, UINT64, AVERAGE),
 707         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_14, UINT64, AVERAGE),
 708         COUNTABLE(AXI_WRITE_DATA_BEATS_ID_15, UINT64, AVERAGE),
 709         COUNTABLE(AXI0_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
 710         COUNTABLE(AXI1_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
 711         COUNTABLE(AXI2_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
 712         COUNTABLE(AXI3_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
 713         COUNTABLE(AXI_WRITE_DATA_BEATS_TOTAL, UINT64, AVERAGE),
 714         COUNTABLE(AXI_DATA_BEATS_TOTAL, UINT64, AVERAGE),
 715 };
 716 #endif
 717
 718 const struct fd_perfcntr_group a5xx_perfcntr_groups[] = {
 719         GROUP("CP", cp_counters, cp_countables),
 720         GROUP("CCU", ccu_counters, ccu_countables),
 721         GROUP("TSE", tse_counters, tse_countables),
 722         GROUP("RAS", ras_counters, ras_countables),
 723         GROUP("LRZ", lrz_counters, lrz_countables),
 724         GROUP("HLSQ", hlsq_counters, hlsq_countables),
 725         GROUP("PC", pc_counters, pc_countables),
 726         GROUP("RB", rb_counters, rb_countables),
 727         GROUP("RBBM", rbbm_counters, rbbm_countables),
 728         GROUP("SP", sp_counters, sp_countables),
 729         GROUP("TP", tp_counters, tp_countables),
 730         GROUP("UCHE", uche_counters, uche_countables),
 731         GROUP("VFD", vfd_counters, vfd_countables),
 732         GROUP("VPC", vpc_counters, vpc_countables),
 733         GROUP("VSC", vsc_counters, vsc_countables),
 734 //      GROUP("VBIF", vbif_counters, vbif_countables),
 735 };
 736
 737 const unsigned a5xx_num_perfcntr_groups = ARRAY_SIZE(a5xx_perfcntr_groups);
 738
 739 #endif /* FD5_PERFCNTR_H_ */