src/freedreno/registers/a6xx.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5 <import file="freedreno_copyright.xml"/>
   6 <import file="adreno/adreno_common.xml"/>
   7 <import file="adreno/adreno_pm4.xml"/>
   8
   9 <!-- these might be same as a5xx -->
  10 <enum name="a6xx_tile_mode">
  11         <value name="TILE6_LINEAR" value="0"/>
  12         <value name="TILE6_2" value="2"/>
  13         <value name="TILE6_3" value="3"/>
  14 </enum>
  15
  16 <enum name="a6xx_format">
  17         <value value="0x02" name="FMT6_A8_UNORM"/>
  18         <value value="0x03" name="FMT6_8_UNORM"/>
  19         <value value="0x04" name="FMT6_8_SNORM"/>
  20         <value value="0x05" name="FMT6_8_UINT"/>
  21         <value value="0x06" name="FMT6_8_SINT"/>
  22
  23         <value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
  24         <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
  25         <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
  26         <value value="0x0e" name="FMT6_5_6_5_UNORM"/>
  27
  28         <value value="0x0f" name="FMT6_8_8_UNORM"/>
  29         <value value="0x10" name="FMT6_8_8_SNORM"/>
  30         <value value="0x11" name="FMT6_8_8_UINT"/>
  31         <value value="0x12" name="FMT6_8_8_SINT"/>
  32         <value value="0x13" name="FMT6_L8_A8_UNORM"/>
  33
  34         <value value="0x15" name="FMT6_16_UNORM"/>
  35         <value value="0x16" name="FMT6_16_SNORM"/>
  36         <value value="0x17" name="FMT6_16_FLOAT"/>
  37         <value value="0x18" name="FMT6_16_UINT"/>
  38         <value value="0x19" name="FMT6_16_SINT"/>
  39
  40         <value value="0x21" name="FMT6_8_8_8_UNORM"/>
  41         <value value="0x22" name="FMT6_8_8_8_SNORM"/>
  42         <value value="0x23" name="FMT6_8_8_8_UINT"/>
  43         <value value="0x24" name="FMT6_8_8_8_SINT"/>
  44
  45         <value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
  46         <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
  47         <value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
  48         <value value="0x33" name="FMT6_8_8_8_8_UINT"/>
  49         <value value="0x34" name="FMT6_8_8_8_8_SINT"/>
  50
  51         <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
  52
  53         <value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
  54         <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
  55         <value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
  56         <value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
  57         <value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
  58
  59         <value value="0x42" name="FMT6_11_11_10_FLOAT"/>
  60
  61         <value value="0x43" name="FMT6_16_16_UNORM"/>
  62         <value value="0x44" name="FMT6_16_16_SNORM"/>
  63         <value value="0x45" name="FMT6_16_16_FLOAT"/>
  64         <value value="0x46" name="FMT6_16_16_UINT"/>
  65         <value value="0x47" name="FMT6_16_16_SINT"/>
  66
  67         <value value="0x48" name="FMT6_32_UNORM"/>
  68         <value value="0x49" name="FMT6_32_SNORM"/>
  69         <value value="0x4a" name="FMT6_32_FLOAT"/>
  70         <value value="0x4b" name="FMT6_32_UINT"/>
  71         <value value="0x4c" name="FMT6_32_SINT"/>
  72         <value value="0x4d" name="FMT6_32_FIXED"/>
  73
  74         <value value="0x58" name="FMT6_16_16_16_UNORM"/>
  75         <value value="0x59" name="FMT6_16_16_16_SNORM"/>
  76         <value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
  77         <value value="0x5b" name="FMT6_16_16_16_UINT"/>
  78         <value value="0x5c" name="FMT6_16_16_16_SINT"/>
  79
  80         <value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
  81         <value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
  82         <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
  83         <value value="0x63" name="FMT6_16_16_16_16_UINT"/>
  84         <value value="0x64" name="FMT6_16_16_16_16_SINT"/>
  85
  86         <value value="0x65" name="FMT6_32_32_UNORM"/>
  87         <value value="0x66" name="FMT6_32_32_SNORM"/>
  88         <value value="0x67" name="FMT6_32_32_FLOAT"/>
  89         <value value="0x68" name="FMT6_32_32_UINT"/>
  90         <value value="0x69" name="FMT6_32_32_SINT"/>
  91         <value value="0x6a" name="FMT6_32_32_FIXED"/>
  92
  93         <value value="0x70" name="FMT6_32_32_32_UNORM"/>
  94         <value value="0x71" name="FMT6_32_32_32_SNORM"/>
  95         <value value="0x72" name="FMT6_32_32_32_UINT"/>
  96         <value value="0x73" name="FMT6_32_32_32_SINT"/>
  97         <value value="0x74" name="FMT6_32_32_32_FLOAT"/>
  98         <value value="0x75" name="FMT6_32_32_32_FIXED"/>
  99
 100         <value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
 101         <value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
 102         <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
 103         <value value="0x83" name="FMT6_32_32_32_32_UINT"/>
 104         <value value="0x84" name="FMT6_32_32_32_32_SINT"/>
 105         <value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
 106
 107         <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
 108         <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
 109
 110         <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
 111         <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
 112         <value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
 113         <value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
 114         <value value="0xaf" name="FMT6_ETC1"/>
 115         <value value="0xb0" name="FMT6_ETC2_RGB8"/>
 116         <value value="0xb1" name="FMT6_ETC2_RGBA8"/>
 117         <value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
 118         <value value="0xb3" name="FMT6_DXT1"/>
 119         <value value="0xb4" name="FMT6_DXT3"/>
 120         <value value="0xb5" name="FMT6_DXT5"/>
 121         <value value="0xb7" name="FMT6_RGTC1_UNORM"/>
 122         <value value="0xb8" name="FMT6_RGTC1_SNORM"/>
 123         <value value="0xbb" name="FMT6_RGTC2_UNORM"/>
 124         <value value="0xbc" name="FMT6_RGTC2_SNORM"/>
 125         <value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
 126         <value value="0xbf" name="FMT6_BPTC_FLOAT"/>
 127         <value value="0xc0" name="FMT6_BPTC"/>
 128         <value value="0xc1" name="FMT6_ASTC_4x4"/>
 129         <value value="0xc2" name="FMT6_ASTC_5x4"/>
 130         <value value="0xc3" name="FMT6_ASTC_5x5"/>
 131         <value value="0xc4" name="FMT6_ASTC_6x5"/>
 132         <value value="0xc5" name="FMT6_ASTC_6x6"/>
 133         <value value="0xc6" name="FMT6_ASTC_8x5"/>
 134         <value value="0xc7" name="FMT6_ASTC_8x6"/>
 135         <value value="0xc8" name="FMT6_ASTC_8x8"/>
 136         <value value="0xc9" name="FMT6_ASTC_10x5"/>
 137         <value value="0xca" name="FMT6_ASTC_10x6"/>
 138         <value value="0xcb" name="FMT6_ASTC_10x8"/>
 139         <value value="0xcc" name="FMT6_ASTC_10x10"/>
 140         <value value="0xcd" name="FMT6_ASTC_12x10"/>
 141         <value value="0xce" name="FMT6_ASTC_12x12"/>
 142
 143         <!-- same as X8Z24_UNORM but for sampling stencil (integer, 2nd channel) -->
 144         <value value="0xea" name="FMT6_S8Z24_UINT"/>
 145 </enum>
 146
 147 <enum name="a6xx_tex_fetchsize">
 148         <value name="TFETCH6_1_BYTE"  value="0"/>
 149         <value name="TFETCH6_2_BYTE"  value="1"/>
 150         <value name="TFETCH6_4_BYTE"  value="2"/>
 151         <value name="TFETCH6_8_BYTE"  value="3"/>
 152         <value name="TFETCH6_16_BYTE" value="4"/>
 153 </enum>
 154
 155 <!-- probably same as a5xx -->
 156 <enum name="a6xx_depth_format">
 157         <value name="DEPTH6_NONE" value="0"/>
 158         <value name="DEPTH6_16" value="1"/>
 159         <value name="DEPTH6_24_8" value="2"/>
 160         <value name="DEPTH6_32" value="4"/>
 161 </enum>
 162
 163 <bitset name="a6x_cp_protect" inline="yes">
 164         <bitfield name="BASE_ADDR" low="0" high="17"/>
 165         <bitfield name="MASK_LEN" low="18" high="30"/>
 166         <bitfield name="READ" pos="31"/>
 167 </bitset>
 168
 169 <enum name="a6xx_shader_id">
 170         <value value="0x9" name="A6XX_TP0_TMO_DATA"/>
 171         <value value="0xa" name="A6XX_TP0_SMO_DATA"/>
 172         <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
 173         <value value="0x19" name="A6XX_TP1_TMO_DATA"/>
 174         <value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
 175         <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
 176         <value value="0x29" name="A6XX_SP_INST_DATA"/>
 177         <value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
 178         <value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
 179         <value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
 180         <value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
 181         <value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
 182         <value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
 183         <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
 184         <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
 185         <value value="0x32" name="A6XX_SP_UAV_DATA"/>
 186         <value value="0x33" name="A6XX_SP_INST_TAG"/>
 187         <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
 188         <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
 189         <value value="0x36" name="A6XX_SP_SMO_TAG"/>
 190         <value value="0x37" name="A6XX_SP_STATE_DATA"/>
 191         <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
 192         <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
 193         <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
 194         <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
 195         <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
 196         <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
 197         <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
 198         <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
 199         <value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
 200         <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
 201         <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
 202         <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
 203         <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
 204         <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
 205         <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
 206         <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
 207         <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
 208         <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
 209         <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
 210         <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
 211         <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
 212         <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
 213 </enum>
 214
 215 <enum name="a6xx_debugbus_id">
 216         <value value="0x1" name="A6XX_DBGBUS_CP"/>
 217         <value value="0x2" name="A6XX_DBGBUS_RBBM"/>
 218         <value value="0x3" name="A6XX_DBGBUS_VBIF"/>
 219         <value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
 220         <value value="0x5" name="A6XX_DBGBUS_UCHE"/>
 221         <value value="0x6" name="A6XX_DBGBUS_DPM"/>
 222         <value value="0x7" name="A6XX_DBGBUS_TESS"/>
 223         <value value="0x8" name="A6XX_DBGBUS_PC"/>
 224         <value value="0x9" name="A6XX_DBGBUS_VFDP"/>
 225         <value value="0xa" name="A6XX_DBGBUS_VPC"/>
 226         <value value="0xb" name="A6XX_DBGBUS_TSE"/>
 227         <value value="0xc" name="A6XX_DBGBUS_RAS"/>
 228         <value value="0xd" name="A6XX_DBGBUS_VSC"/>
 229         <value value="0xe" name="A6XX_DBGBUS_COM"/>
 230         <value value="0x10" name="A6XX_DBGBUS_LRZ"/>
 231         <value value="0x11" name="A6XX_DBGBUS_A2D"/>
 232         <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
 233         <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
 234         <value value="0x14" name="A6XX_DBGBUS_RBP"/>
 235         <value value="0x15" name="A6XX_DBGBUS_DCS"/>
 236         <value value="0x16" name="A6XX_DBGBUS_DBGC"/>
 237         <value value="0x17" name="A6XX_DBGBUS_CX"/>
 238         <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
 239         <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
 240         <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
 241         <value value="0x1d" name="A6XX_DBGBUS_GPC"/>
 242         <value value="0x1e" name="A6XX_DBGBUS_LARC"/>
 243         <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
 244         <value value="0x20" name="A6XX_DBGBUS_RB_0"/>
 245         <value value="0x21" name="A6XX_DBGBUS_RB_1"/>
 246         <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
 247         <value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
 248         <value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
 249         <value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
 250         <value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
 251         <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
 252         <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
 253         <value value="0x40" name="A6XX_DBGBUS_SP_0"/>
 254         <value value="0x41" name="A6XX_DBGBUS_SP_1"/>
 255         <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
 256         <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
 257         <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
 258         <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
 259 </enum>
 260
 261 <enum name="a6xx_cp_perfcounter_select">
 262         <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
 263         <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
 264         <value value="2" name="PERF_CP_BUSY_CYCLES"/>
 265         <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
 266         <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
 267         <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
 268         <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
 269         <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
 270         <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
 271         <value value="9" name="PERF_CP_MODE_SWITCH"/>
 272         <value value="10" name="PERF_CP_ZPASS_DONE"/>
 273         <value value="11" name="PERF_CP_CONTEXT_DONE"/>
 274         <value value="12" name="PERF_CP_CACHE_FLUSH"/>
 275         <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
 276         <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
 277         <value value="15" name="PERF_CP_SQE_IDLE"/>
 278         <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
 279         <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
 280         <value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
 281         <value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
 282         <value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
 283         <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
 284         <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
 285         <value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
 286         <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
 287         <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
 288         <value value="26" name="PERF_CP_SQE_T4_EXEC"/>
 289         <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
 290         <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
 291         <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
 292         <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
 293         <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
 294         <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
 295         <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
 296         <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
 297         <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
 298         <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
 299         <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
 300         <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
 301         <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
 302         <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
 303         <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
 304         <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
 305         <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
 306         <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
 307         <value value="45" name="PERF_CP_PM4_DATA"/>
 308         <value value="46" name="PERF_CP_PM4_HEADERS"/>
 309         <value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
 310         <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
 311         <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
 312 </enum>
 313
 314 <enum name="a6xx_rbbm_perfcounter_select">
 315         <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
 316         <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
 317         <value value="2" name="PERF_RBBM_TSE_BUSY"/>
 318         <value value="3" name="PERF_RBBM_RAS_BUSY"/>
 319         <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
 320         <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
 321         <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
 322         <value value="7" name="PERF_RBBM_COM_BUSY"/>
 323         <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
 324         <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
 325         <value value="10" name="PERF_RBBM_VSC_BUSY"/>
 326         <value value="11" name="PERF_RBBM_TESS_BUSY"/>
 327         <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
 328         <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
 329 </enum>
 330
 331 <enum name="a6xx_pc_perfcounter_select">
 332         <value value="0" name="PERF_PC_BUSY_CYCLES"/>
 333         <value value="1" name="PERF_PC_WORKING_CYCLES"/>
 334         <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
 335         <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
 336         <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
 337         <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
 338         <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
 339         <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
 340         <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
 341         <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
 342         <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
 343         <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
 344         <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
 345         <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
 346         <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
 347         <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
 348         <value value="16" name="PERF_PC_INSTANCES"/>
 349         <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
 350         <value value="18" name="PERF_PC_DEAD_PRIM"/>
 351         <value value="19" name="PERF_PC_LIVE_PRIM"/>
 352         <value value="20" name="PERF_PC_VERTEX_HITS"/>
 353         <value value="21" name="PERF_PC_IA_VERTICES"/>
 354         <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
 355         <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
 356         <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
 357         <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
 358         <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
 359         <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
 360         <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
 361         <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
 362         <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
 363         <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
 364         <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
 365         <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
 366         <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
 367         <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
 368         <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
 369         <value value="37" name="PERF_PC_TSE_TRANSACTION"/>
 370         <value value="38" name="PERF_PC_TSE_VERTEX"/>
 371         <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
 372         <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
 373         <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
 374 </enum>
 375
 376 <enum name="a6xx_vfd_perfcounter_select">
 377         <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
 378         <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
 379         <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
 380         <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
 381         <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
 382         <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
 383         <value value="6" name="PERF_VFD_RBUFFER_FULL"/>
 384         <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
 385         <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
 386         <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
 387         <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
 388         <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
 389         <value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
 390         <value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
 391         <value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
 392         <value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
 393         <value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
 394         <value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
 395         <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
 396         <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
 397         <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
 398         <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
 399         <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
 400 </enum>
 401
 402 <enum name="a6xx_hlsq_perfcounter_select">
 403         <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
 404         <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
 405         <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
 406         <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
 407         <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
 408         <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
 409         <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
 410         <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
 411         <value value="8" name="PERF_HLSQ_QUADS"/>
 412         <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
 413         <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
 414         <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
 415         <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
 416         <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
 417         <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
 418         <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
 419         <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
 420         <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
 421         <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
 422         <value value="19" name="PERF_HLSQ_PIXELS"/>
 423         <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
 424 </enum>
 425
 426 <enum name="a6xx_vpc_perfcounter_select">
 427         <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
 428         <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
 429         <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
 430         <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
 431         <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
 432         <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
 433         <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
 434         <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
 435         <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
 436         <value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
 437         <value value="10" name="PERF_VPC_SP_COMPONENTS"/>
 438         <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
 439         <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
 440         <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
 441         <value value="14" name="PERF_VPC_LM_TRANSACTION"/>
 442         <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
 443         <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
 444         <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
 445         <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
 446         <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
 447         <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
 448         <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
 449         <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
 450         <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
 451         <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
 452         <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
 453         <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
 454         <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
 455 </enum>
 456
 457 <enum name="a6xx_tse_perfcounter_select">
 458         <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
 459         <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
 460         <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
 461         <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
 462         <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
 463         <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
 464         <value value="6" name="PERF_TSE_INPUT_PRIM"/>
 465         <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
 466         <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
 467         <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
 468         <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
 469         <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
 470         <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
 471         <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
 472         <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
 473         <value value="15" name="PERF_TSE_CINVOCATION"/>
 474         <value value="16" name="PERF_TSE_CPRIMITIVES"/>
 475         <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
 476         <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
 477         <value value="19" name="PERF_TSE_CLIP_PLANES"/>
 478 </enum>
 479
 480 <enum name="a6xx_ras_perfcounter_select">
 481         <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
 482         <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
 483         <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
 484         <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
 485         <value value="4" name="PERF_RAS_SUPER_TILES"/>
 486         <value value="5" name="PERF_RAS_8X4_TILES"/>
 487         <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
 488         <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
 489         <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
 490         <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
 491         <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
 492         <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
 493         <value value="12" name="PERF_RAS_BLOCKS"/>
 494 </enum>
 495
 496 <enum name="a6xx_uche_perfcounter_select">
 497         <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
 498         <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
 499         <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
 500         <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
 501         <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
 502         <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
 503         <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
 504         <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
 505         <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
 506         <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
 507         <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
 508         <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
 509         <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
 510         <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
 511         <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
 512         <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
 513         <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
 514         <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
 515         <value value="18" name="PERF_UCHE_EVICTS"/>
 516         <value value="19" name="PERF_UCHE_BANK_REQ0"/>
 517         <value value="20" name="PERF_UCHE_BANK_REQ1"/>
 518         <value value="21" name="PERF_UCHE_BANK_REQ2"/>
 519         <value value="22" name="PERF_UCHE_BANK_REQ3"/>
 520         <value value="23" name="PERF_UCHE_BANK_REQ4"/>
 521         <value value="24" name="PERF_UCHE_BANK_REQ5"/>
 522         <value value="25" name="PERF_UCHE_BANK_REQ6"/>
 523         <value value="26" name="PERF_UCHE_BANK_REQ7"/>
 524         <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
 525         <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
 526         <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
 527         <value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
 528         <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
 529         <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
 530         <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
 531         <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
 532         <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
 533         <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
 534         <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
 535         <value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
 536         <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
 537 </enum>
 538
 539 <enum name="a6xx_tp_perfcounter_select">
 540         <value value="0" name="PERF_TP_BUSY_CYCLES"/>
 541         <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
 542         <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
 543         <value value="3" name="PERF_TP_LATENCY_TRANS"/>
 544         <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
 545         <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
 546         <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
 547         <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
 548         <value value="8" name="PERF_TP_SP_TP_TRANS"/>
 549         <value value="9" name="PERF_TP_TP_SP_TRANS"/>
 550         <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
 551         <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
 552         <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
 553         <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
 554         <value value="14" name="PERF_TP_QUADS_OFFSET"/>
 555         <value value="15" name="PERF_TP_QUADS_SHADOW"/>
 556         <value value="16" name="PERF_TP_QUADS_ARRAY"/>
 557         <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
 558         <value value="18" name="PERF_TP_QUADS_1D"/>
 559         <value value="19" name="PERF_TP_QUADS_2D"/>
 560         <value value="20" name="PERF_TP_QUADS_BUFFER"/>
 561         <value value="21" name="PERF_TP_QUADS_3D"/>
 562         <value value="22" name="PERF_TP_QUADS_CUBE"/>
 563         <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
 564         <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
 565         <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
 566         <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
 567         <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
 568         <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
 569         <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
 570         <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
 571         <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
 572         <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
 573         <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
 574         <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
 575         <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
 576         <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
 577         <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
 578         <value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
 579         <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
 580         <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
 581         <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
 582         <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
 583         <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
 584         <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
 585         <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
 586         <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
 587         <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
 588         <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
 589         <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
 590         <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
 591         <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
 592         <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
 593         <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
 594         <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
 595         <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
 596         <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
 597 </enum>
 598
 599 <enum name="a6xx_sp_perfcounter_select">
 600         <value value="0" name="PERF_SP_BUSY_CYCLES"/>
 601         <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
 602         <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
 603         <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
 604         <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
 605         <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
 606         <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
 607         <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
 608         <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
 609         <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
 610         <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
 611         <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
 612         <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
 613         <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
 614         <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
 615         <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
 616         <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
 617         <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
 618         <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
 619         <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
 620         <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
 621         <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
 622         <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
 623         <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
 624         <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
 625         <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
 626         <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
 627         <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
 628         <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
 629         <value value="29" name="PERF_SP_LM_ATOMICS"/>
 630         <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
 631         <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
 632         <value value="32" name="PERF_SP_GM_ATOMICS"/>
 633         <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
 634         <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
 635         <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 636         <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 637         <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
 638         <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
 639         <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
 640         <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 641         <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 642         <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
 643         <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
 644         <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
 645         <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
 646         <value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
 647         <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
 648         <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
 649         <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
 650         <value value="50" name="PERF_SP_PIXELS_KILLED"/>
 651         <value value="51" name="PERF_SP_ICL1_REQUESTS"/>
 652         <value value="52" name="PERF_SP_ICL1_MISSES"/>
 653         <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
 654         <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
 655         <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
 656         <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
 657         <value value="57" name="PERF_SP_GPR_READ"/>
 658         <value value="58" name="PERF_SP_GPR_WRITE"/>
 659         <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 660         <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 661         <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
 662         <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
 663         <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
 664         <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
 665         <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
 666         <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
 667         <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
 668         <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
 669         <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
 670         <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
 671         <value value="71" name="PERF_SP_WORKING_EU"/>
 672         <value value="72" name="PERF_SP_ANY_EU_WORKING"/>
 673         <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
 674         <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
 675         <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
 676         <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
 677         <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
 678         <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
 679         <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
 680         <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
 681         <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
 682         <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
 683         <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
 684         <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
 685 </enum>
 686
 687 <enum name="a6xx_rb_perfcounter_select">
 688         <value value="0" name="PERF_RB_BUSY_CYCLES"/>
 689         <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
 690         <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
 691         <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
 692         <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
 693         <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
 694         <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
 695         <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
 696         <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
 697         <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
 698         <value value="10" name="PERF_RB_Z_WORKLOAD"/>
 699         <value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
 700         <value value="12" name="PERF_RB_Z_READ"/>
 701         <value value="13" name="PERF_RB_Z_WRITE"/>
 702         <value value="14" name="PERF_RB_C_READ"/>
 703         <value value="15" name="PERF_RB_C_WRITE"/>
 704         <value value="16" name="PERF_RB_TOTAL_PASS"/>
 705         <value value="17" name="PERF_RB_Z_PASS"/>
 706         <value value="18" name="PERF_RB_Z_FAIL"/>
 707         <value value="19" name="PERF_RB_S_FAIL"/>
 708         <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
 709         <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
 710         <value value="22" name="PERF_RB_PS_INVOCATIONS"/>
 711         <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
 712         <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
 713         <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
 714         <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
 715         <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
 716         <value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
 717         <value value="29" name="PERF_RB_3D_PIXELS"/>
 718         <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
 719         <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
 720         <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
 721         <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
 722         <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
 723         <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
 724         <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
 725         <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
 726         <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
 727         <value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
 728         <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
 729         <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
 730         <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
 731         <value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
 732         <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
 733         <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
 734         <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
 735         <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
 736 </enum>
 737
 738 <enum name="a6xx_vsc_perfcounter_select">
 739         <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
 740         <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
 741         <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
 742         <value value="3" name="PERF_VSC_EOT_NUM"/>
 743         <value value="4" name="PERF_VSC_INPUT_TILES"/>
 744 </enum>
 745
 746 <enum name="a6xx_ccu_perfcounter_select">
 747         <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
 748         <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
 749         <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
 750         <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
 751         <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
 752         <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
 753         <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
 754         <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
 755         <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
 756         <value value="9" name="PERF_CCU_GMEM_READ"/>
 757         <value value="10" name="PERF_CCU_GMEM_WRITE"/>
 758         <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
 759         <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
 760         <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
 761         <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
 762         <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
 763         <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
 764         <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
 765         <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
 766         <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
 767         <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
 768         <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
 769         <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
 770         <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
 771         <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
 772         <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
 773         <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
 774         <value value="27" name="PERF_CCU_2D_RD_REQ"/>
 775         <value value="28" name="PERF_CCU_2D_WR_REQ"/>
 776 </enum>
 777
 778 <enum name="a6xx_lrz_perfcounter_select">
 779         <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
 780         <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
 781         <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
 782         <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
 783         <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
 784         <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
 785         <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
 786         <value value="7" name="PERF_LRZ_LRZ_READ"/>
 787         <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
 788         <value value="9" name="PERF_LRZ_READ_LATENCY"/>
 789         <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
 790         <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
 791         <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
 792         <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
 793         <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
 794         <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
 795         <value value="16" name="PERF_LRZ_TILE_KILLED"/>
 796         <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
 797         <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
 798         <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
 799         <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
 800         <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
 801         <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
 802         <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
 803         <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
 804         <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
 805         <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
 806         <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
 807 </enum>
 808
 809 <enum name="a6xx_cmp_perfcounter_select">
 810         <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
 811         <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
 812         <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
 813         <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
 814         <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
 815         <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
 816         <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
 817         <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
 818         <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
 819         <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
 820         <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
 821         <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
 822         <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
 823         <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
 824         <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
 825         <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
 826         <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
 827         <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
 828         <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
 829         <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
 830         <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
 831         <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
 832         <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
 833         <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
 834         <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
 835         <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
 836         <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
 837         <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
 838         <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
 839         <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
 840         <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
 841         <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
 842         <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
 843         <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
 844         <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
 845         <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
 846         <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
 847         <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
 848         <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
 849         <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
 850 </enum>
 851
 852 <!--
 853 Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
 854 component type/size, so I think it relates to internal format used for
 855 blending?  The one exception is that 16b unorm and 32b float use the
 856 same value... maybe 16b unorm is uncommon enough that it was just easier
 857 to upconvert to 32b float internally?
 858
 859  8b unorm:  10 (sometimes 0, is the high bit part of something else?)
 860 16b unorm:   4
 861
 862 32b int:     7
 863 16b int:     6
 864  8b int:     5
 865
 866 32b float:   4
 867 16b float:   3
 868  -->
 869 <enum name="a6xx_2d_ifmt">
 870         <value value="0x10" name="R2D_UNORM8"/>
 871         <value value="0x7"  name="R2D_INT32"/>
 872         <value value="0x6"  name="R2D_INT16"/>
 873         <value value="0x5"  name="R2D_INT8"/>
 874         <value value="0x4"  name="R2D_FLOAT32"/>
 875         <value value="0x3"  name="R2D_FLOAT16"/>
 876         <value value="0x1"  name="R2D_UNORM8_SRGB"/>
 877         <value value="0x0"  name="R2D_RAW"/>
 878 </enum>
 879
 880 <domain name="A6XX" width="32">
 881         <bitset name="A6XX_RBBM_INT_0_MASK" inline="yes">
 882                 <bitfield name="RBBM_GPU_IDLE" pos="0"/>
 883                 <bitfield name="CP_AHB_ERROR" pos="1"/>
 884                 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/>
 885                 <bitfield name="RBBM_GPC_ERROR" pos="7"/>
 886                 <bitfield name="CP_SW" pos="8"/>
 887                 <bitfield name="CP_HW_ERROR" pos="9"/>
 888                 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/>
 889                 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/>
 890                 <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/>
 891                 <bitfield name="CP_IB2" pos="13"/>
 892                 <bitfield name="CP_IB1" pos="14"/>
 893                 <bitfield name="CP_RB" pos="15"/>
 894                 <bitfield name="CP_RB_DONE_TS" pos="17"/>
 895                 <bitfield name="CP_WT_DONE_TS" pos="18"/>
 896                 <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/>
 897                 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/>
 898                 <bitfield name="RBBM_HANG_DETECT" pos="23"/>
 899                 <bitfield name="UCHE_OOB_ACCESS" pos="24"/>
 900                 <bitfield name="UCHE_TRAP_INTR" pos="25"/>
 901                 <bitfield name="DEBBUS_INTR_0" pos="26"/>
 902                 <bitfield name="DEBBUS_INTR_1" pos="27"/>
 903                 <bitfield name="ISDB_CPU_IRQ" pos="30"/>
 904                 <bitfield name="ISDB_UNDER_DEBUG" pos="31"/>
 905         </bitset>
 906
 907         <bitset name="A6XX_CP_INT">
 908                 <bitfield name="CP_OPCODE_ERROR" pos="0"/>
 909                 <bitfield name="CP_UCODE_ERROR" pos="1"/>
 910                 <bitfield name="CP_HW_FAULT_ERROR" pos="2"/>
 911                 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/>
 912                 <bitfield name="CP_AHB_ERROR" pos="5"/>
 913                 <bitfield name="CP_VSD_PARITY_ERROR" pos="6"/>
 914                 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7"/>
 915         </bitset>
 916
 917         <reg32 offset="0x0800" name="CP_RB_BASE"/>
 918         <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
 919         <reg32 offset="0x0802" name="CP_RB_CNTL"/>
 920         <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
 921         <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
 922         <reg32 offset="0x0806" name="CP_RB_RPTR"/>
 923         <reg32 offset="0x0807" name="CP_RB_WPTR"/>
 924         <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
 925         <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
 926                 <bitfield name="IFPC" pos="0" type="boolean"/>
 927         </reg32>
 928         <reg32 offset="0x0821" name="CP_HW_FAULT"/>
 929         <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
 930         <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
 931         <reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
 932         <reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
 933         <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
 934         <!-- all the threshold values seem to be in units of quad-dwords: -->
 935         <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
 936                 <doc>
 937                         b0..7 seems to contain the size of buffered by not yet processed
 938                         RB level cmdstream.. it's possible that it is a low threshold
 939                         and b8..15 is a high threshold?
 940
 941                         b16..23 identifies where IB1 data starts (and RB data ends?)
 942
 943                         b24..31 identifies where IB2 data starts (and IB1 data ends)
 944                 </doc>
 945                 <bitfield name="RB_LO" low="0" high="7" shr="2"/>
 946                 <bitfield name="RB_HI" low="8" high="15" shr="2"/>
 947                 <bitfield name="IB1_START" low="16" high="23" shr="2"/>
 948                 <bitfield name="IB2_START" low="24" high="31" shr="2"/>
 949         </reg32>
 950         <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
 951                 <doc>
 952                         low bits identify where CP_SET_DRAW_STATE stateobj
 953                         processing starts (and IB2 data ends). I'm guessing
 954                         b8 is part of this since (from downstream kgsl):
 955
 956                                 /* ROQ sizes are twice as big on a640/a680 than on a630 */
 957                                 if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
 958                                         kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
 959                                         kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
 960                                 } ...
 961                 </doc>
 962                 <bitfield name="SDS_START" low="0" high="8" shr="2"/>
 963                 <!-- total ROQ size: -->
 964                 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
 965         </reg32>
 966         <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
 967         <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
 968         <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL"/>
 969         <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
 970         <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
 971
 972         <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
 973                 <reg32 offset="0x0" name="REG" type="uint"/>
 974         </array>
 975         <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
 976                 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
 977         </array>
 978
 979         <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
 980         <reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
 981         <reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
 982         <reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
 983         <reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
 984         <reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
 985         <reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
 986         <reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
 987         <reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
 988         <reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
 989         <reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
 990         <reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
 991         <reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
 992         <reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
 993         <reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
 994         <reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
 995         <reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
 996         <reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
 997         <reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
 998         <reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
 999         <reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
1000         <reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
1001         <reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
1002         <reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
1003         <reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
1004         <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1005         <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1006         <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1007         <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1008         <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1009         <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1010         <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1011         <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1012         <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1013         <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1014         <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1015         <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1016         <reg32 offset="0x0928" name="CP_IB1_BASE"/>
1017         <reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
1018         <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1019         <reg32 offset="0x092B" name="CP_IB2_BASE"/>
1020         <reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
1021         <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1022         <!-- SDS == CP_SET_DRAW_STATE: -->
1023         <reg32 offset="0x092e" name="CP_SDS_BASE"/>
1024         <reg32 offset="0x092f" name="CP_SDS_BASE_HI"/>
1025         <reg32 offset="0x092e" name="CP_SDS_REM_SIZE"/>
1026         <reg32 offset="0x0931" name="CP_BIN_SIZE_ADDRESS"/>
1027         <reg32 offset="0x0932" name="CP_BIN_SIZE_ADDRESS_HI"/>
1028         <reg32 offset="0x0934" name="CP_BIN_DATA_ADDR"/>
1029         <reg32 offset="0x0935" name="CP_BIN_DATA_ADDR_HI"/>
1030         <!--
1031         There are probably similar registers for RB and SDS, teasing out SDS will
1032         take a slightly better test case..
1033          -->
1034         <reg32 offset="0x0949" name="CP_CSQ_IB1_STAT">
1035                 <doc>number of remaining dwords incl current dword being consumed?</doc>
1036                 <bitfield name="REM" low="16" high="31"/>
1037         </reg32>
1038         <reg32 offset="0x094a" name="CP_CSQ_IB2_STAT">
1039                 <doc>number of remaining dwords incl current dword being consumed?</doc>
1040                 <bitfield name="REM" low="16" high="31"/>
1041         </reg32>
1042         <reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
1043         <reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
1044         <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1045         <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
1046         <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
1047         <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL"/>
1048         <reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/>
1049         <reg32 offset="0x0210" name="RBBM_STATUS">
1050                 <bitfield high="23" low="23" name="GPU_BUSY_IGN_AHB" />
1051                 <bitfield high="22" low="22" name="GPU_BUSY_IGN_AHB_CP" />
1052                 <bitfield high="21" low="21" name="HLSQ_BUSY" />
1053                 <bitfield high="20" low="20" name="VSC_BUSY" />
1054                 <bitfield high="19" low="19" name="TPL1_BUSY" />
1055                 <bitfield high="18" low="18" name="SP_BUSY" />
1056                 <bitfield high="17" low="17" name="UCHE_BUSY" />
1057                 <bitfield high="16" low="16" name="VPC_BUSY" />
1058                 <bitfield high="15" low="15" name="VFD_BUSY" />
1059                 <bitfield high="14" low="14" name="TESS_BUSY" />
1060                 <bitfield high="13" low="13" name="PC_VSD_BUSY" />
1061                 <bitfield high="12" low="12" name="PC_DCALL_BUSY" />
1062                 <bitfield high="11" low="11" name="COM_DCOM_BUSY" />
1063                 <bitfield high="10" low="10" name="LRZ_BUSY" />
1064                 <bitfield high="9" low="9" name="A2D_BUSY" />
1065                 <bitfield high="8" low="8" name="CCU_BUSY" />
1066                 <bitfield high="7" low="7" name="RB_BUSY" />
1067                 <bitfield high="6" low="6" name="RAS_BUSY" />
1068                 <bitfield high="5" low="5" name="TSE_BUSY" />
1069                 <bitfield high="4" low="4" name="VBIF_BUSY" />
1070                 <bitfield high="3" low="3" name="GFX_DBGC_BUSY" />
1071                 <bitfield high="2" low="2" name="CP_BUSY" />
1072                 <bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" />
1073                 <bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/>
1074         </reg32>
1075         <reg32 offset="0x0213" name="RBBM_STATUS3">
1076                 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
1077         </reg32>
1078         <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1079         <reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
1080         <reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
1081         <reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
1082         <reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
1083         <reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
1084         <reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
1085         <reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
1086         <reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
1087         <reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
1088         <reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
1089         <reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
1090         <reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
1091         <reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
1092         <reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
1093         <reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
1094         <reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
1095         <reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
1096         <reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
1097         <reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
1098         <reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
1099         <reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
1100         <reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
1101         <reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
1102         <reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
1103         <reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
1104         <reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
1105         <reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
1106         <reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
1107         <reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
1108         <reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
1109         <reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
1110         <reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
1111         <reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
1112         <reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
1113         <reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
1114         <reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
1115         <reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
1116         <reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
1117         <reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
1118         <reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
1119         <reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
1120         <reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
1121         <reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
1122         <reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
1123         <reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
1124         <reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
1125         <reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
1126         <reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
1127         <reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
1128         <reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
1129         <reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
1130         <reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
1131         <reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
1132         <reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
1133         <reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
1134         <reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
1135         <reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
1136         <reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
1137         <reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
1138         <reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
1139         <reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
1140         <reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
1141         <reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
1142         <reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
1143         <reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
1144         <reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
1145         <reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
1146         <reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
1147         <reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1148         <reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1149         <reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1150         <reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1151         <reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1152         <reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1153         <reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1154         <reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1155         <reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1156         <reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1157         <reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1158         <reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1159         <reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
1160         <reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
1161         <reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
1162         <reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
1163         <reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
1164         <reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
1165         <reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
1166         <reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
1167         <reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
1168         <reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
1169         <reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
1170         <reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
1171         <reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
1172         <reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
1173         <reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
1174         <reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
1175         <reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
1176         <reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
1177         <reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
1178         <reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
1179         <reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
1180         <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
1181         <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
1182         <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
1183         <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
1184         <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
1185         <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
1186         <reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
1187         <reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
1188         <reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
1189         <reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
1190         <reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
1191         <reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
1192         <reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
1193         <reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
1194         <reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
1195         <reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
1196         <reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
1197         <reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
1198         <reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
1199         <reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
1200         <reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
1201         <reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
1202         <reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
1203         <reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
1204         <reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
1205         <reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
1206         <reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
1207         <reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
1208         <reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
1209         <reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
1210         <reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
1211         <reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
1212         <reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
1213         <reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
1214         <reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
1215         <reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
1216         <reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
1217         <reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
1218         <reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
1219         <reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
1220         <reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
1221         <reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
1222         <reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
1223         <reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
1224         <reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
1225         <reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
1226         <reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
1227         <reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
1228         <reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
1229         <reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
1230         <reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
1231         <reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
1232         <reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
1233         <reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
1234         <reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
1235         <reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
1236         <reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
1237         <reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
1238         <reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
1239         <reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
1240         <reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
1241         <reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
1242         <reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
1243         <reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
1244         <reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
1245         <reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
1246         <reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
1247         <reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
1248         <reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
1249         <reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
1250         <reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
1251         <reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
1252         <reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
1253         <reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
1254         <reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
1255         <reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
1256         <reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
1257         <reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
1258         <reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
1259         <reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
1260         <reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
1261         <reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
1262         <reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
1263         <reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
1264         <reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
1265         <reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
1266         <reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
1267         <reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
1268         <reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
1269         <reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
1270         <reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
1271         <reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
1272         <reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
1273         <reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
1274         <reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
1275         <reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
1276         <reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
1277         <reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
1278         <reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
1279         <reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
1280         <reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
1281         <reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
1282         <reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
1283         <reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
1284         <reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
1285         <reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
1286         <reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
1287         <reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
1288         <reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
1289         <reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
1290         <reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
1291         <reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
1292         <reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
1293         <reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
1294         <reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
1295         <reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
1296         <reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
1297         <reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
1298         <reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
1299         <reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
1300         <reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
1301         <reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
1302         <reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
1303         <reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
1304         <reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
1305         <reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
1306         <reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
1307         <reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
1308         <reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
1309         <reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
1310         <reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
1311         <reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
1312         <reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
1313         <reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
1314         <reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
1315         <reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
1316         <reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
1317         <reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
1318         <reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
1319         <reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
1320         <reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
1321         <reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
1322         <reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
1323         <reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
1324         <reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
1325         <reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
1326         <reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
1327         <reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
1328         <reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
1329         <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1330         <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1331         <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1332         <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1333         <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1334         <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1335         <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1336         <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
1337         <reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
1338         <reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
1339         <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
1340         <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1341         <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1342
1343         <!---
1344             This block of registers aren't tied to perf counters. They
1345             count various geometry stats, for example number of
1346             vertices in, number of primnitives assembled etc.
1347         -->
1348
1349         <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/>  <!-- vs vertices in -->
1350         <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
1351         <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/>  <!-- vs primitives out -->
1352         <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
1353         <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/>  <!-- hs vertices in -->
1354         <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
1355         <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/>  <!-- hs patches out -->
1356         <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
1357         <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/>  <!-- dss vertices in -->
1358         <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
1359         <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/>  <!-- ds primitives out -->
1360         <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
1361         <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/>  <!-- gs primitives in -->
1362         <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
1363         <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/>  <!-- gs primitives out -->
1364         <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
1365         <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/>  <!-- gs primitives out -->
1366         <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
1367         <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/>  <!-- raster primitives in -->
1368         <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
1369         <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
1370         <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
1371
1372         <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1373         <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1374         <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1375         <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1376         <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1377         <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/>
1378         <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1379         <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1380         <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD"/>
1381         <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
1382         <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1383         <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1384         <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1385         <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1386         <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1387         <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1388         <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1389         <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1390         <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1391         <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1392         <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1393         <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1394         <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1395         <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1396         <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1397         <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1398         <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1399         <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1400         <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1401         <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1402         <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1403         <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1404         <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1405         <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1406         <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1407         <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1408         <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1409         <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1410         <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1411         <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1412         <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1413         <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1414         <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1415         <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1416         <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1417         <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1418         <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1419         <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1420         <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1421         <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1422         <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1423         <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1424         <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1425         <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1426         <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1427         <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1428         <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1429         <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1430         <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1431         <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1432         <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1433         <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1434         <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1435         <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1436         <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1437         <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1438         <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1439         <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1440         <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1441         <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1442         <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1443         <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1444         <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1445         <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1446         <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1447         <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1448         <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1449         <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1450         <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1451         <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1452         <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1453         <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1454         <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1455         <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1456         <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1457         <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1458         <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1459         <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1460         <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1461         <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1462         <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1463         <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1464         <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1465         <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1466         <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1467         <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1468         <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1469         <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1470         <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1471         <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1472         <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1473         <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1474         <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1475         <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1476         <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1477         <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1478         <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1479         <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1480         <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1481         <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1482         <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1483         <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1484         <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1485         <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1486         <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1487         <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1488         <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1489         <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1490         <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1491         <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1492         <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1493         <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1494         <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1495         <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1496         <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1497                 <bitfield high="7" low="0" name="PING_INDEX"/>
1498                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
1499         </reg32>
1500         <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1501                 <bitfield high="5" low="0" name="TRACEEN"/>
1502                 <bitfield high="14" low="12" name="GRANU"/>
1503                 <bitfield high="31" low="28" name="SEGT"/>
1504         </reg32>
1505         <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1506                 <bitfield high="27" low="24" name="ENABLE"/>
1507         </reg32>
1508         <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1509         <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1510         <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1511         <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1512         <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1513         <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1514         <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1515         <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1516         <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1517                 <bitfield high="3" low="0" name="BYTEL0"/>
1518                 <bitfield high="7" low="4" name="BYTEL1"/>
1519                 <bitfield high="11" low="8" name="BYTEL2"/>
1520                 <bitfield high="15" low="12" name="BYTEL3"/>
1521                 <bitfield high="19" low="16" name="BYTEL4"/>
1522                 <bitfield high="23" low="20" name="BYTEL5"/>
1523                 <bitfield high="27" low="24" name="BYTEL6"/>
1524                 <bitfield high="31" low="28" name="BYTEL7"/>
1525         </reg32>
1526         <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1527                 <bitfield high="3" low="0" name="BYTEL8"/>
1528                 <bitfield high="7" low="4" name="BYTEL9"/>
1529                 <bitfield high="11" low="8" name="BYTEL10"/>
1530                 <bitfield high="15" low="12" name="BYTEL11"/>
1531                 <bitfield high="19" low="16" name="BYTEL12"/>
1532                 <bitfield high="23" low="20" name="BYTEL13"/>
1533                 <bitfield high="27" low="24" name="BYTEL14"/>
1534                 <bitfield high="31" low="28" name="BYTEL15"/>
1535         </reg32>
1536         <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1537         <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1538         <reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
1539         <reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
1540         <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL"/>
1541         <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
1542         <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
1543         <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
1544         <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
1545         <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
1546         <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
1547         <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
1548         <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
1549         <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
1550         <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
1551         <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
1552         <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
1553         <reg32 offset="0x8E05" name="RB_ADDR_MODE_CNTL"/>
1554         <reg32 offset="0x8E08" name="RB_NC_MODE_CNTL"/>
1555         <reg32 offset="0x8E10" name="RB_PERFCTR_RB_SEL_0"/>
1556         <reg32 offset="0x8E11" name="RB_PERFCTR_RB_SEL_1"/>
1557         <reg32 offset="0x8E12" name="RB_PERFCTR_RB_SEL_2"/>
1558         <reg32 offset="0x8E13" name="RB_PERFCTR_RB_SEL_3"/>
1559         <reg32 offset="0x8E14" name="RB_PERFCTR_RB_SEL_4"/>
1560         <reg32 offset="0x8E15" name="RB_PERFCTR_RB_SEL_5"/>
1561         <reg32 offset="0x8E16" name="RB_PERFCTR_RB_SEL_6"/>
1562         <reg32 offset="0x8E17" name="RB_PERFCTR_RB_SEL_7"/>
1563         <reg32 offset="0x8E18" name="RB_PERFCTR_CCU_SEL_0"/>
1564         <reg32 offset="0x8E19" name="RB_PERFCTR_CCU_SEL_1"/>
1565         <reg32 offset="0x8E1A" name="RB_PERFCTR_CCU_SEL_2"/>
1566         <reg32 offset="0x8E1B" name="RB_PERFCTR_CCU_SEL_3"/>
1567         <reg32 offset="0x8E1C" name="RB_PERFCTR_CCU_SEL_4"/>
1568         <reg32 offset="0x8E2C" name="RB_PERFCTR_CMP_SEL_0"/>
1569         <reg32 offset="0x8E2D" name="RB_PERFCTR_CMP_SEL_1"/>
1570         <reg32 offset="0x8E2E" name="RB_PERFCTR_CMP_SEL_2"/>
1571         <reg32 offset="0x8E2F" name="RB_PERFCTR_CMP_SEL_3"/>
1572         <reg32 offset="0x8E3D" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
1573         <reg32 offset="0x8E50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/>
1574         <reg32 offset="0x9E00" name="PC_DBG_ECO_CNTL"/>
1575         <reg32 offset="0x9E01" name="PC_ADDR_MODE_CNTL"/>
1576         <reg32 offset="0x9E34" name="PC_PERFCTR_PC_SEL_0"/>
1577         <reg32 offset="0x9E35" name="PC_PERFCTR_PC_SEL_1"/>
1578         <reg32 offset="0x9E36" name="PC_PERFCTR_PC_SEL_2"/>
1579         <reg32 offset="0x9E37" name="PC_PERFCTR_PC_SEL_3"/>
1580         <reg32 offset="0x9E38" name="PC_PERFCTR_PC_SEL_4"/>
1581         <reg32 offset="0x9E39" name="PC_PERFCTR_PC_SEL_5"/>
1582         <reg32 offset="0x9E3A" name="PC_PERFCTR_PC_SEL_6"/>
1583         <reg32 offset="0x9E3B" name="PC_PERFCTR_PC_SEL_7"/>
1584         <reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/>
1585         <reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
1586         <reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
1587         <reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
1588         <reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
1589         <reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
1590         <reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
1591         <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1592         <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1593         <reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL"/>
1594         <reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
1595         <reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
1596         <reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
1597         <reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
1598         <reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
1599         <reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
1600         <reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
1601         <reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
1602         <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL"/>
1603         <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
1604         <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
1605         <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
1606         <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
1607         <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
1608         <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
1609         <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL"/>
1610         <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1611         <reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
1612         <reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
1613         <reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
1614         <reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
1615         <reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
1616         <reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
1617         <reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
1618         <reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
1619         <reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
1620         <reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
1621         <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
1622         <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1623         <reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
1624                 <bitfield high="7" low="0" name="PERFSEL"/>
1625         </reg32>
1626         <reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
1627         <reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
1628         <reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
1629         <reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
1630         <reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
1631         <reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
1632         <reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
1633         <reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
1634         <reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
1635         <reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
1636         <reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
1637         <reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
1638         <reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL"/>
1639         <reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
1640         <reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
1641         <reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
1642         <reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
1643         <reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
1644         <reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
1645         <reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
1646         <reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
1647         <reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
1648         <reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
1649         <reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
1650         <reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
1651         <reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
1652         <reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
1653         <reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
1654         <reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
1655         <reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
1656         <reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
1657         <reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
1658         <reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
1659         <reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
1660         <reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
1661         <reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
1662         <reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
1663         <reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
1664         <reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL"/>
1665         <reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
1666         <reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
1667         <reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
1668         <reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
1669         <reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
1670         <reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
1671         <reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
1672         <reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
1673         <reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
1674         <reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
1675         <reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
1676         <reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
1677         <reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
1678         <reg32 offset="0x3000" name="VBIF_VERSION"/>
1679         <reg32 offset="0x3001" name="VBIF_CLKON">
1680                 <bitfield pos="1" name="FORCE_ON_TESTBUS"/>
1681         </reg32>
1682         <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1683         <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1684         <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1685         <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1686         <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1687         <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1688                 <bitfield low="0" high="3" name="DATA_SEL"/>
1689         </reg32>
1690         <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1691         <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1692                 <bitfield low="0" high="8" name="DATA_SEL"/>
1693         </reg32>
1694         <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1695         <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1696         <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1697         <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1698         <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1699         <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1700         <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1701         <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1702         <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1703         <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1704         <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1705         <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1706         <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1707         <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1708         <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1709         <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1710         <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1711         <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1712         <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1713         <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1714         <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1715         <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1716
1717         <!-- move/rename these.. -->
1718
1719         <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/>
1720         <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1721         <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1722
1723         <!-- same as RB_BIN_CONTROL -->
1724         <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
1725                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1726                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1727                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
1728                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
1729         </reg32>
1730
1731         <!--
1732                 from offset it seems it should be RB, but weird to duplicate
1733                 other regs from same block??
1734          -->
1735         <reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
1736                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1737                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1738         </reg32>
1739
1740         <reg32 offset="0x0c02" name="VSC_BIN_SIZE">
1741                 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1742                 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
1743         </reg32>
1744         <reg32 offset="0x0c03" name="VSC_SIZE_ADDRESS_LO"/>
1745         <reg32 offset="0x0c04" name="VSC_SIZE_ADDRESS_HI"/>
1746         <reg64 offset="0x0c03" name="VSC_SIZE_ADDRESS" type="waddress"/>
1747         <reg32 offset="0x0c06" name="VSC_BIN_COUNT">
1748                 <bitfield name="NX" low="1" high="10" type="uint"/>
1749                 <bitfield name="NY" low="11" high="20" type="uint"/>
1750         </reg32>
1751         <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
1752                 <reg32 offset="0x0" name="REG">
1753                         <doc>
1754                                 Configures the mapping between VSC_PIPE buffer and
1755                                 bin, X/Y specify the bin index in the horiz/vert
1756                                 direction (0,0 is upper left, 0,1 is leftmost bin
1757                                 on second row, and so on).  W/H specify the number
1758                                 of bins assigned to this VSC_PIPE in the horiz/vert
1759                                 dimension.
1760                         </doc>
1761                         <bitfield name="X" low="0" high="9" type="uint"/>
1762                         <bitfield name="Y" low="10" high="19" type="uint"/>
1763                         <bitfield name="W" low="20" high="25" type="uint"/>
1764                         <bitfield name="H" low="26" high="31" type="uint"/>
1765                 </reg32>
1766         </array>
1767         <!--
1768         compared to a5xx and earlier, we just program the address of the first
1769         visibility stream and hw adds (pipe_num * VSC_PIPE_DATA_PITCH)
1770
1771         TODO now there seem to be two buffers of VSC data (both referenced by
1772         CP_SET_BIN_DATA packet.  Not sure what this new DATA2 one is, but seems
1773         to have the larger pitch.
1774
1775         The "DATA2" buffer is probably actually the main visibility stream; it
1776         is at least the larger of the two.
1777
1778         For VSC_DATA_PITCH, 0x20 actually seems to be sufficient (although blob
1779         uses something somewhat larger) for many cases, although required value
1780         can ramp up somewhat higher.  Values less than 0x20 trigger GPU hangs
1781         even with small amount of geometry (so possibly 0x20 is minimum
1782         alignment or something like that).  So far I can't seem to find any-
1783         thing that needs values larger than 0x20
1784          -->
1785         <reg32 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS_LO"/>
1786         <reg32 offset="0x0c31" name="VSC_PIPE_DATA2_ADDRESS_HI"/>
1787         <reg64 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS" type="waddress"/>
1788         <reg32 offset="0x0c32" name="VSC_PIPE_DATA2_PITCH"/>
1789         <reg32 offset="0x0c33" name="VSC_PIPE_DATA2_ARRAY_PITCH" shr="4" type="uint"/>
1790         <reg32 offset="0x0c34" name="VSC_PIPE_DATA_ADDRESS_LO"/>
1791         <reg32 offset="0x0c35" name="VSC_PIPE_DATA_ADDRESS_HI"/>
1792         <reg64 offset="0x0c34" name="VSC_PIPE_DATA_ADDRESS" type="waddress"/>
1793         <reg32 offset="0x0c36" name="VSC_PIPE_DATA_PITCH"/>
1794         <reg32 offset="0x0c37" name="VSC_PIPE_DATA_ARRAY_PITCH" shr="4" type="uint"/>
1795
1796         <array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
1797                 <doc>
1798                         Seems to be a bitmap of which tiles mapped to the VSC
1799                         pipe contain geometry.
1800
1801                         I suppose we can connect a maximum of 32 tiles to a
1802                         single VSC pipe.
1803                 </doc>
1804                 <reg32 offset="0x0" name="REG"/>
1805         </array>
1806
1807         <array offset="0x0c58" name="VSC_SIZE2" stride="1" length="32">
1808                 <doc>
1809                         Has the size of data written to corresponding VSC_DATA2
1810                         buffer.
1811                 </doc>
1812                 <reg32 offset="0x0" name="REG"/>
1813         </array>
1814
1815         <array offset="0x0c78" name="VSC_SIZE" stride="1" length="32">
1816                 <doc>
1817                         Has the size of data written to corresponding VSC pipe, ie.
1818                         same thing that is written out to VSC_SIZE_ADDRESS_LO/HI
1819                 </doc>
1820                 <reg32 offset="0x0" name="REG"/>
1821         </array>
1822
1823         <!-- always 0x03200000 ? -->
1824         <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
1825
1826         <reg32 offset="0x8000" name="GRAS_CL_CNTL">
1827                 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
1828                 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
1829                 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
1830                 <!-- set with depthClampEnable, not clear what it does -->
1831                 <bitfield name="UNK5" pos="5" type="boolean"/>
1832                 <!-- controls near z clip behavior (set for vulkan) -->
1833                 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
1834                 <!-- guess based on a3xx and meaning of bits 8 and 9
1835                      if the guess is right then this is related to point sprite clipping -->
1836                 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
1837                 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
1838                 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
1839         </reg32>
1840         <reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/>
1841         <reg32 offset="0x8002" name="GRAS_UNKNOWN_8002"/>
1842         <reg32 offset="0x8003" name="GRAS_UNKNOWN_8003"/>
1843
1844         <enum name="a6xx_layer_type">
1845           <value value="0x0" name="LAYER_MULTISAMPLE_ARRAY"/>
1846           <value value="0x1" name="LAYER_3D"/>
1847           <value value="0x2" name="LAYER_CUBEMAP"/>
1848           <value value="0x3" name="LAYER_2D_ARRAY"/>
1849         </enum>
1850
1851         <!-- index of highest layer that can be written to via gl_Layer -->
1852         <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" type="uint"/>
1853
1854         <reg32 offset="0x8005" name="GRAS_CNTL">
1855                 <!-- see also RB_RENDER_CONTROL0 -->
1856                 <bitfield name="VARYING" pos="0" type="boolean"/>
1857                 <!-- b1 set for interpolateAtCentroid() -->
1858                 <bitfield name="CENTROID" pos="1" type="boolean"/>
1859                 <!-- b2 set instead of b0 when running in per-sample mode -->
1860                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
1861                 <!--
1862                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1863                 mode, and frag_face
1864                  -->
1865                 <bitfield name="SIZE" pos="3" type="boolean"/>
1866                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1867                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
1868                 <bitfield name="XCOORD" pos="6" type="boolean"/>
1869                 <bitfield name="YCOORD" pos="7" type="boolean"/>
1870                 <bitfield name="ZCOORD" pos="8" type="boolean"/>
1871                 <bitfield name="WCOORD" pos="9" type="boolean"/>
1872         </reg32>
1873         <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1874                 <bitfield name="HORZ" low="0" high="9" type="uint"/>
1875                 <bitfield name="VERT" low="10" high="19" type="uint"/>
1876         </reg32>
1877         <reg32 offset="0x8010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1878         <reg32 offset="0x8011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1879         <reg32 offset="0x8012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1880         <reg32 offset="0x8013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1881         <reg32 offset="0x8014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1882         <reg32 offset="0x8015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1883
1884         <!-- not clear what it does, mirrors RB_Z_CLAMP_MIN -->
1885         <reg32 offset="0x8070" name="GRAS_CL_Z_CLAMP_MIN" type="float"/>
1886         <reg32 offset="0x8071" name="GRAS_CL_Z_CLAMP_MAX" type="float"/>
1887
1888         <reg32 offset="0x8090" name="GRAS_SU_CNTL">
1889                 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1890                 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
1891                 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
1892                 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1893                 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1894                 <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1895                 <!-- probably LINEHALFWIDTH is the same as a4xx.. -->
1896         </reg32>
1897         <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
1898                 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1899                 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1900         </reg32>
1901         <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1902
1903         <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1904                 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
1905         </reg32>
1906         <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1907         <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1908         <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1909         <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1910         <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1911                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
1912         </reg32>
1913
1914         <!-- always 0x0 -->
1915         <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099"/>
1916
1917         <!-- always 0x0 ? -->
1918         <reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/>
1919
1920         <reg32 offset="0x809c" name="GRAS_UNKNOWN_809C">
1921                 <bitfield name="GS_WRITES_LAYER" pos="0" type="boolean"/>
1922         </reg32>
1923
1924         <reg32 offset="0x809d" name="GRAS_UNKNOWN_809D"/>
1925
1926         <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/>
1927
1928         <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
1929                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1930         </reg32>
1931         <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
1932                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1933                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1934         </reg32>
1935
1936         <bitset name="a6xx_sample_config" inline="yes">
1937                 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
1938         </bitset>
1939
1940         <bitset name="a6xx_sample_locations" inline="yes">
1941                 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
1942                 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
1943                 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
1944                 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
1945                 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
1946                 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
1947                 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
1948                 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
1949         </bitset>
1950
1951         <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config"/>
1952         <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
1953         <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
1954
1955         <!-- always 0x0 -->
1956         <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF"/>
1957
1958         <reg32 offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
1959         <reg32 offset="0x80b1" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
1960         <reg32 offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
1961         <reg32 offset="0x80d1" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
1962         <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1963         <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1964
1965         <reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
1966                 <!--
1967                 These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
1968                 look when we get around to enabling lrz
1969                  -->
1970                 <bitfield name="ENABLE" pos="0" type="boolean"/>
1971                 <doc>LRZ write also disabled for blend/etc.</doc>
1972                 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
1973                 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
1974                 <bitfield name="GREATER" pos="2" type="boolean"/>
1975                 <bitfield name="UNK3" pos="3" type="boolean"/>
1976                 <!-- set when depth-test + depth-write enabled -->
1977                 <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
1978         </reg32>
1979         <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101"/>
1980         <reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
1981                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
1982         </reg32>
1983         <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
1984         <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
1985         <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" type="waddress"/>
1986         <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
1987                 <bitfield name="PITCH" low="0" high="10" shr="5" type="uint"/>
1988                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="5" type="uint"/> <!-- ??? -->
1989         </reg32>
1990         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
1991         <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
1992         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" type="waddress"/>
1993
1994         <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
1995                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
1996         </reg32>
1997
1998         <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110"/>
1999
2000         <enum name="a6xx_rotation">
2001           <value value="0x0" name="ROTATE_0"/>
2002           <value value="0x1" name="ROTATE_90"/>
2003           <value value="0x2" name="ROTATE_180"/>
2004           <value value="0x3" name="ROTATE_270"/>
2005           <value value="0x4" name="ROTATE_HFLIP"/>
2006           <value value="0x5" name="ROTATE_VFLIP"/>
2007         </enum>
2008
2009         <bitset name="a6xx_2d_blit_cntl" inline="yes">
2010                 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
2011                 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
2012                 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
2013                 <bitfield name="SCISSOR" pos="16" type="boolean"/>
2014
2015                 <bitfield name="UNK" low="17" high="18" type="uint"/>
2016
2017                 <!-- required when blitting D24S8/D24X8 -->
2018                 <bitfield name="D24S8" pos="19" type="boolean"/>
2019                 <!-- some sort of channel mask, disabled channels are set to zero ? -->
2020                 <bitfield name="MASK" low="20" high="23"/>
2021                 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
2022         </bitset>
2023
2024         <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2025
2026         <!-- could be the src coords are fixed point? -->
2027         <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X">
2028                 <bitfield name="X" low="8" high="31" type="int"/>
2029         </reg32>
2030         <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X">
2031                 <bitfield name="X" low="8" high="31" type="int"/>
2032         </reg32>
2033         <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y">
2034                 <bitfield name="Y" low="8" high="31" type="int"/>
2035         </reg32>
2036         <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y">
2037                 <bitfield name="Y" low="8" high="31" type="int"/>
2038         </reg32>
2039
2040         <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="adreno_reg_xy"/>
2041         <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="adreno_reg_xy"/>
2042
2043         <reg32 offset="0x840a" name="GRAS_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
2044         <reg32 offset="0x840b" name="GRAS_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
2045
2046         <!-- always 0x880 ? -->
2047         <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600"/>
2048
2049         <!-- same as GRAS_BIN_CONTROL: -->
2050         <reg32 offset="0x8800" name="RB_BIN_CONTROL">
2051                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
2052                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
2053                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
2054                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
2055         </reg32>
2056         <reg32 offset="0x8801" name="RB_RENDER_CNTL">
2057                 <!-- always set: ?? -->
2058                 <bitfield name="UNK4" pos="4" type="boolean"/>
2059                 <!-- set during binning pass: -->
2060                 <bitfield name="BINNING" pos="7" type="boolean"/>
2061                 <!-- bit seems to be set whenever depth buffer enabled: -->
2062                 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
2063                 <!-- bitmask of MRTs using UBWC flag buffer: -->
2064                 <bitfield name="FLAG_MRTS" low="16" high="23"/>
2065         </reg32>
2066         <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
2067                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2068         </reg32>
2069         <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
2070                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2071                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2072         </reg32>
2073
2074         <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config"/>
2075         <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
2076         <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
2077
2078         <!--
2079         note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
2080         name comes from kernel and is probably right)
2081          -->
2082         <reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
2083                 <!-- see also GRAS_CNTL -->
2084                 <bitfield name="VARYING" pos="0" type="boolean"/>
2085                 <!-- b1 set for interpolateAtCentroid() -->
2086                 <bitfield name="CENTROID" pos="1" type="boolean"/>
2087                 <!-- b2 set instead of b0 when running in per-sample mode -->
2088                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
2089                 <!--
2090                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
2091                 mode, and frag_face
2092                  -->
2093                 <bitfield name="SIZE" pos="3" type="boolean"/>
2094                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
2095                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
2096                 <bitfield name="XCOORD" pos="6" type="boolean"/>
2097                 <bitfield name="YCOORD" pos="7" type="boolean"/>
2098                 <bitfield name="ZCOORD" pos="8" type="boolean"/>
2099                 <bitfield name="WCOORD" pos="9" type="boolean"/>
2100                 <bitfield name="UNK10" pos="10" type="boolean"/>
2101         </reg32>
2102         <reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
2103                 <!-- enable bits for various FS sysvalue regs: -->
2104                 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
2105                 <bitfield name="FACENESS" pos="2" type="boolean"/>
2106                 <bitfield name="SAMPLEID" pos="3" type="boolean"/>
2107                 <!-- b4 and b5 set in per-sample mode: -->
2108                 <bitfield name="UNK4" pos="4" type="boolean"/>
2109                 <bitfield name="UNK5" pos="5" type="boolean"/>
2110                 <bitfield name="SIZE" pos="6" type="boolean"/>
2111         </reg32>
2112
2113         <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
2114                 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
2115                 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
2116         </reg32>
2117         <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
2118                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2119         </reg32>
2120         <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
2121                 <bitfield name="RT0" low="0" high="3"/>
2122                 <bitfield name="RT1" low="4" high="7"/>
2123                 <bitfield name="RT2" low="8" high="11"/>
2124                 <bitfield name="RT3" low="12" high="15"/>
2125                 <bitfield name="RT4" low="16" high="19"/>
2126                 <bitfield name="RT5" low="20" high="23"/>
2127                 <bitfield name="RT6" low="24" high="27"/>
2128                 <bitfield name="RT7" low="28" high="31"/>
2129         </reg32>
2130         <reg32 offset="0x880e" name="RB_DITHER_CNTL">
2131                 <bitfield name="DITHER_MODE_MRT0" low="0"  high="1"  type="adreno_rb_dither_mode"/>
2132                 <bitfield name="DITHER_MODE_MRT1" low="2"  high="3"  type="adreno_rb_dither_mode"/>
2133                 <bitfield name="DITHER_MODE_MRT2" low="4"  high="5"  type="adreno_rb_dither_mode"/>
2134                 <bitfield name="DITHER_MODE_MRT3" low="6"  high="7"  type="adreno_rb_dither_mode"/>
2135                 <bitfield name="DITHER_MODE_MRT4" low="8"  high="9"  type="adreno_rb_dither_mode"/>
2136                 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
2137                 <bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/>
2138                 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
2139         </reg32>
2140         <reg32 offset="0x880f" name="RB_SRGB_CNTL">
2141                 <!-- Same as SP_SRGB_CNTL -->
2142                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2143                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2144                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2145                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2146                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2147                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2148                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2149                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2150         </reg32>
2151
2152         <reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
2153                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2154         </reg32>
2155         <reg32 offset="0x8811" name="RB_UNKNOWN_8811"/>
2156
2157         <!-- always 0x0 ? -->
2158         <reg32 offset="0x8818" name="RB_UNKNOWN_8818"/>
2159         <reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
2160         <reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
2161         <reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
2162         <reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
2163         <reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
2164         <reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
2165
2166         <array offset="0x8820" name="RB_MRT" stride="8" length="8">
2167                 <reg32 offset="0x0" name="CONTROL">
2168                         <bitfield name="BLEND" pos="0" type="boolean"/>
2169                         <bitfield name="BLEND2" pos="1" type="boolean"/>
2170                         <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2171                         <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2172                         <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2173                 </reg32>
2174                 <reg32 offset="0x1" name="BLEND_CONTROL">
2175                         <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2176                         <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2177                         <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2178                         <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2179                         <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2180                         <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2181                 </reg32>
2182                 <reg32 offset="0x2" name="BUF_INFO">
2183                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2184                         <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2185                         <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2186                 </reg32>
2187                 <!--
2188                 at least in gmem, things seem to be aligned to pitch of 64..
2189                 maybe an artifact of tiled format used in gmem?
2190                  -->
2191                 <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
2192                 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
2193                 <!--
2194                 Compared to a5xx and before, we configure both a GMEM base and
2195                 external base.  Not sure if this is to facilitate GMEM save/
2196                 restore for context switch, or just to simplify state setup to
2197                 not have to care about GMEM vs BYPASS mode.
2198                  -->
2199                 <reg32 offset="0x5" name="BASE_LO"/>
2200                 <reg32 offset="0x6" name="BASE_HI"/>
2201
2202                 <reg64 offset="0x5" name="BASE" type="waddress"/>
2203
2204                 <reg32 offset="0x7" name="BASE_GMEM"/>
2205         </array>
2206
2207         <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
2208         <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
2209         <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
2210         <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
2211         <reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
2212                 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2213                 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2214                 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2215         </reg32>
2216         <reg32 offset="0x8865" name="RB_BLEND_CNTL">
2217                 <!-- per-mrt enable bit -->
2218                 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
2219                 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2220                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2221                 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
2222         </reg32>
2223         <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
2224                 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
2225         </reg32>
2226
2227         <reg32 offset="0x8871" name="RB_DEPTH_CNTL">
2228                 <bitfield name="Z_ENABLE" pos="0" type="boolean"/>
2229                 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2230                 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2231                 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
2232                 <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
2233                 <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
2234         </reg32>
2235         <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2236         <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
2237                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2238         </reg32>
2239 <!-- probably: -->
2240         <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
2241                 <doc>stride of depth/stencil buffer</doc>
2242         </reg32>
2243         <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2244                 <doc>size of layer</doc>
2245         </reg32>
2246         <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
2247         <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
2248         <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress"/>
2249         <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/>
2250
2251         <!-- always 0x0 ? -->
2252         <reg32 offset="0x8878" name="RB_UNKNOWN_8878"/>
2253         <!-- always 0x0 ? -->
2254         <reg32 offset="0x8879" name="RB_UNKNOWN_8879"/>
2255
2256         <reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
2257                 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2258                 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2259                 <!--
2260                         set for stencil operations that require read from stencil
2261                         buffer, but not for example for stencil clear (which does
2262                         not require read).. so guessing this is analogous to
2263                         READ_DEST_ENABLE for color buffer..
2264                  -->
2265                 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2266                 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2267                 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2268                 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2269                 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2270                 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2271                 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2272                 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2273                 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2274         </reg32>
2275         <reg32 offset="0x8881" name="RB_STENCIL_INFO">
2276                 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2277         </reg32>
2278         <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" shr="6" type="uint">
2279                 <doc>stride of stencil buffer</doc>
2280         </reg32>
2281         <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2282                 <doc>size of layer</doc>
2283         </reg32>
2284         <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
2285         <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
2286         <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress"/>
2287         <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM"/>
2288         <reg32 offset="0x8887" name="RB_STENCILREF">
2289                 <bitfield name="REF" low="0" high="7"/>
2290                 <bitfield name="BFREF" low="8" high="15"/>
2291         </reg32>
2292         <reg32 offset="0x8888" name="RB_STENCILMASK">
2293                 <bitfield name="MASK" low="0" high="7"/>
2294                 <bitfield name="BFMASK" low="8" high="15"/>
2295         </reg32>
2296         <reg32 offset="0x8889" name="RB_STENCILWRMASK">
2297                 <bitfield name="WRMASK" low="0" high="7"/>
2298                 <bitfield name="BFWRMASK" low="8" high="15"/>
2299         </reg32>
2300         <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
2301         <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
2302                 <bitfield name="COPY" pos="1" type="boolean"/>
2303         </reg32>
2304
2305         <reg32 offset="0x8898" name="RB_LRZ_CNTL">
2306                 <bitfield name="ENABLE" pos="0" type="boolean"/>
2307         </reg32>
2308
2309         <!-- clamps depth value for depth test/write -->
2310         <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/>
2311         <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/>
2312
2313         <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"/>
2314         <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="adreno_reg_xy"/>
2315         <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="adreno_reg_xy"/>
2316
2317         <reg32 offset="0x88d5" name="RB_MSAA_CNTL">
2318                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2319         </reg32>
2320         <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM"/>
2321         <!-- s/DST_FORMAT/DST_INFO/ probably: -->
2322         <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
2323                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
2324                 <bitfield name="FLAGS" pos="2" type="boolean"/>
2325                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2326                 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
2327                 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
2328         </reg32>
2329         <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress"/>
2330         <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
2331         <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
2332         <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
2333         <!-- array-pitch is size of layer -->
2334         <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
2335         <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress"/>
2336         <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
2337         <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
2338         <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
2339                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2340                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2341         </reg32>
2342
2343         <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
2344         <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
2345         <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
2346         <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>
2347
2348         <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2349         <reg32 offset="0x88e3" name="RB_BLIT_INFO">
2350                 <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color restore? -->
2351                 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2352                 <bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably -->
2353                 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2354                 <doc>
2355                         For clearing depth/stencil
2356                                 1 - depth
2357                                 2 - stencil
2358                                 3 - depth+stencil
2359                         For clearing color buffer:
2360                                 then probably a component mask, I always see 0xf
2361                 </doc>
2362                 <bitfield name="CLEAR_MASK" low="4" high="7"/>
2363         </reg32>
2364
2365         <!-- always 0x0 ? -->
2366         <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0"/>
2367
2368         <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2369         <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2370         <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress"/>
2371         <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2372                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2373                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2374         </reg32>
2375         <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
2376                 <reg32 offset="0" name="ADDR_LO"/>
2377                 <reg32 offset="1" name="ADDR_HI"/>
2378                 <reg64 offset="0" name="ADDR" type="waddress"/>
2379                 <reg32 offset="2" name="PITCH">
2380                         <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2381                         <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> <!-- ??? -->
2382                 </reg32>
2383         </array>
2384         <reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2385         <reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2386
2387         <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2388         <reg32 offset="0x8c01" name="RB_UNKNOWN_8C01"/>
2389
2390         <bitset name="a6xx_2d_surf_info" inline="yes">
2391                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2392                 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2393                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2394                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2395                 <bitfield name="SRGB" pos="13" type="boolean"/>
2396                 <!-- the rest is only for src -->
2397                 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
2398                 <bitfield name="FILTER" pos="16" type="boolean"/>
2399                 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
2400                 <bitfield name="UNK20" pos="20" type="boolean"/>
2401                 <bitfield name="UNK22" pos="22" type="boolean"/>
2402         </bitset>
2403
2404         <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
2405         <reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
2406         <reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
2407         <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress"/>
2408         <reg32 offset="0x8c1a" name="RB_2D_DST_SIZE">
2409                 <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2410         </reg32>
2411
2412         <reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
2413         <reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
2414         <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress"/>
2415         <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH">
2416                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2417                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2418         </reg32>
2419
2420         <!-- unlike a5xx, these are per channel values rather than packed -->
2421         <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
2422         <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
2423         <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
2424         <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>
2425
2426         <!-- always 0x1 ? -->
2427         <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>
2428
2429         <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/>
2430
2431         <reg32 offset="0x8e07" name="RB_CCU_CNTL">
2432                 <!-- offset into GMEM for something.
2433                         important for sysmem path
2434                         BLIT_OP_SCALE also writes to GMEM at this offset for GMEM store
2435                         blob values for GMEM path (note: close to GMEM size):
2436                         a618: 0x7c000 a630/a640: 0xf8000 a650: 0x114000
2437                         SYSMEM path values:
2438                         a618: 0x10000 a630/a640: 0x20000 a650: 0x30000
2439                 -->
2440                 <bitfield name="OFFSET" low="23" high="31" shr="12" type="uint"/>
2441                 <bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
2442                 <bitfield name="UNK2" pos="2" type="boolean"/> <!-- sometimes set with GMEM? -->
2443         </reg32>
2444
2445         <reg32 offset="0x9100" name="VPC_UNKNOWN_9100"/>
2446
2447         <!-- always 0x00ffff00 ? */ -->
2448         <reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/>
2449         <reg32 offset="0x9102" name="VPC_UNKNOWN_9102"/>
2450         <reg32 offset="0x9103" name="VPC_UNKNOWN_9103"/>
2451
2452         <reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/>
2453
2454         <reg32 offset="0x9105" name="VPC_UNKNOWN_9105">
2455                 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
2456         </reg32>
2457
2458         <reg32 offset="0x9106" name="VPC_UNKNOWN_9106"/>
2459         <reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
2460         <reg32 offset="0x9108" name="VPC_UNKNOWN_9108"/>
2461
2462         <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
2463                 <reg32 offset="0x0" name="MODE"/>
2464         </array>
2465         <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2466                 <reg32 offset="0x0" name="MODE"/>
2467         </array>
2468
2469         <!-- always 0x0 -->
2470         <reg32 offset="0x9210" name="VPC_UNKNOWN_9210"/>
2471         <reg32 offset="0x9211" name="VPC_UNKNOWN_9211"/>
2472
2473         <array offset="0x9212" name="VPC_VAR" stride="1" length="4">
2474                 <!-- one bit per varying component: -->
2475                 <reg32 offset="0" name="DISABLE"/>
2476         </array>
2477
2478         <reg32 offset="0x9216" name="VPC_SO_CNTL">
2479                 <!-- always 0x10000 when SO enabled.. -->
2480                 <bitfield name="ENABLE" pos="16" type="boolean"/>
2481         </reg32>
2482         <reg32 offset="0x9217" name="VPC_SO_PROG">
2483                 <bitfield name="A_BUF" low="0" high="1" type="uint"/>
2484                 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
2485                 <bitfield name="A_EN" pos="11" type="boolean"/>
2486                 <bitfield name="B_BUF" low="12" high="13" type="uint"/>
2487                 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
2488                 <bitfield name="B_EN" pos="23" type="boolean"/>
2489         </reg32>
2490
2491         <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/>
2492         <reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
2493
2494         <array offset="0x921a" name="VPC_SO" stride="7" length="4">
2495                 <reg64 offset="0" name="BUFFER_BASE" type="waddress"/>
2496                 <reg32 offset="0" name="BUFFER_BASE_LO"/>
2497                 <reg32 offset="1" name="BUFFER_BASE_HI"/>
2498                 <reg32 offset="2" name="BUFFER_SIZE"/>
2499                 <reg32 offset="3" name="NCOMP"/>  <!-- component count -->
2500                 <reg32 offset="4" name="BUFFER_OFFSET"/>
2501                 <reg64 offset="5" name="FLUSH_BASE" type="waddress"/>
2502                 <reg32 offset="5" name="FLUSH_BASE_LO"/>
2503                 <reg32 offset="6" name="FLUSH_BASE_HI"/>
2504         </array>
2505
2506         <!-- always 0x0 ? -->
2507         <reg32 offset="0x9236" name="VPC_UNKNOWN_9236">
2508                 <bitfield name="POINT_COORD_INVERT" pos="0" type="uint"/>
2509         </reg32>
2510
2511         <!-- always 0x0 ? -->
2512         <reg32 offset="0x9300" name="VPC_UNKNOWN_9300"/>
2513
2514         <reg32 offset="0x9301" name="VPC_PACK">
2515                 <doc>
2516                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2517                         plus # of transform-feedback (streamout) varyings if using the
2518                         hw streamout (rather than stg instructions in shader)
2519                 </doc>
2520                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2521                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2522                 <!--
2523                 This seems to be the OUTLOC for the psize output.  It could possibly
2524                 be the max-OUTLOC position, but it is only set when VS writes psize
2525                 (and blob always puts psize at highest OUTLOC)
2526                  -->
2527                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2528         </reg32>
2529
2530         <reg32 offset="0x9302" name="VPC_PACK_GS">
2531                 <doc>
2532                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2533                         plus # of transform-feedback (streamout) varyings if using the
2534                         hw streamout (rather than stg instructions in shader)
2535                 </doc>
2536                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2537                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2538                 <!--
2539                 This seems to be the OUTLOC for the psize output.  It could possibly
2540                 be the max-OUTLOC position, but it is only set when VS writes psize
2541                 (and blob always puts psize at highest OUTLOC)
2542                  -->
2543                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2544         </reg32>
2545
2546         <reg32 offset="0x9303" name="VPC_PACK_3">
2547                 <doc>
2548                         domain shader version of VPC_PACK
2549                 </doc>
2550                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2551                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2552                 <!--
2553                 This seems to be the OUTLOC for the psize output.  It could possibly
2554                 be the max-OUTLOC position, but it is only set when VS writes psize
2555                 (and blob always puts psize at highest OUTLOC)
2556                  -->
2557                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2558         </reg32>
2559
2560         <reg32 offset="0x9304" name="VPC_CNTL_0">
2561                 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2562                 <bitfield name="VARYING" pos="16" type="boolean"/>
2563         </reg32>
2564
2565         <reg32 offset="0x9305" name="VPC_SO_BUF_CNTL">
2566                 <bitfield name="BUF0" pos="0" type="boolean"/>
2567                 <bitfield name="BUF1" pos="3" type="boolean"/>
2568                 <bitfield name="BUF2" pos="6" type="boolean"/>
2569                 <bitfield name="BUF3" pos="9" type="boolean"/>
2570                 <bitfield name="ENABLE" pos="15" type="boolean"/>
2571         </reg32>
2572         <reg32 offset="0x9306" name="VPC_SO_OVERRIDE">
2573                 <bitfield name="SO_DISABLE" pos="0" type="boolean"/>
2574         </reg32>
2575
2576         <!-- always 0x0 ? -->
2577         <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/>
2578         <!-- always 0x0 ? -->
2579         <reg32 offset="0x9602" name="VPC_UNKNOWN_9602"/>
2580
2581         <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX"/>
2582
2583         <!-- always 0x0 ? -->
2584         <reg32 offset="0x9801" name="PC_UNKNOWN_9801"/>
2585
2586         <enum name="a6xx_tess_spacing">
2587           <value value="0x0" name="TESS_EQUAL"/>
2588           <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
2589           <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
2590         </enum>
2591
2592         <enum name="a6xx_tess_output">
2593           <value value="0x0" name="TESS_POINTS"/>
2594           <value value="0x1" name="TESS_LINES"/>
2595           <value value="0x2" name="TESS_CW_TRIS"/>
2596           <value value="0x3" name="TESS_CCW_TRIS"/>
2597         </enum>
2598
2599         <reg32 offset="0x9802" name="PC_TESS_CNTL">
2600           <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
2601           <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
2602         </reg32>
2603
2604         <!-- probably: -->
2605         <reg32 offset="0x9803" name="PC_RESTART_INDEX"/>
2606         <reg32 offset="0x9804" name="PC_MODE_CNTL"/>
2607
2608         <!-- always 0x1 ? -->
2609         <reg32 offset="0x9805" name="PC_UNKNOWN_9805"/>
2610         <reg32 offset="0x9806" name="PC_UNKNOWN_9806"/>
2611
2612         <reg32 offset="0x9980" name="PC_UNKNOWN_9980"/>
2613         <reg32 offset="0x9981" name="PC_UNKNOWN_9981"/>
2614
2615         <reg32 offset="0x9990" name="PC_UNKNOWN_9990"/>
2616
2617         <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
2618                 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
2619                 <!-- maybe?  b1 seems always set, so just assume it is for now: -->
2620                 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
2621         </reg32>
2622         <reg32 offset="0x9b01" name="PC_PRIMITIVE_CNTL_1">
2623                 <doc>
2624                         vertex shader
2625
2626                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2627                         plus # of transform-feedback (streamout) varyings if using the
2628                         hw streamout (rather than stg instructions in shader)
2629                 </doc>
2630                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2631                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2632         </reg32>
2633
2634         <reg32 offset="0x9b02" name="PC_PRIMITIVE_CNTL_2">
2635                 <doc>
2636                   geometry shader
2637                 </doc>
2638                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2639                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2640                 <bitfield name="LAYER" pos="9" type="boolean"/>
2641                 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
2642         </reg32>
2643
2644         <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3">
2645                 <doc>
2646                         hull shader?
2647
2648                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2649                         plus # of transform-feedback (streamout) varyings if using the
2650                         hw streamout (rather than stg instructions in shader)
2651                 </doc>
2652                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2653                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2654         </reg32>
2655         <reg32 offset="0x9b04" name="PC_PRIMITIVE_CNTL_4">
2656                 <doc>
2657                         domain shader
2658                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2659                         plus # of transform-feedback (streamout) varyings if using the
2660                         hw streamout (rather than stg instructions in shader)
2661                 </doc>
2662                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2663                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2664         </reg32>
2665
2666         <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
2667                 <doc>
2668                   geometry shader
2669                 </doc>
2670                 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
2671                 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
2672                 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
2673         </reg32>
2674
2675         <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
2676                 <doc>
2677                   size in vec4s of per-primitive storage for gs
2678                 </doc>
2679                 <bitfield name="STRIDE_IN_VPC" low="0" high="8" type="uint"/>
2680         </reg32>
2681
2682         <reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/>
2683
2684         <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
2685         <reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
2686
2687         <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
2688         <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
2689                 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
2690                 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
2691         </reg32>
2692         <reg32 offset="0x9e12" name="PC_BIN_DATA_ADDR2_LO"/>
2693         <reg32 offset="0x9e13" name="PC_BIN_DATA_ADDR2_HI"/>
2694         <reg32 offset="0x9e14" name="PC_BIN_DATA_ADDR_LO"/>
2695         <reg32 offset="0x9e15" name="PC_BIN_DATA_ADDR_HI"/>
2696
2697         <!-- always 0x0 -->
2698         <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
2699
2700         <reg32 offset="0xa000" name="VFD_CONTROL_0">
2701                 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
2702                 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
2703         </reg32>
2704         <reg32 offset="0xa001" name="VFD_CONTROL_1">
2705                 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2706                 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
2707                 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
2708         </reg32>
2709         <reg32 offset="0xa002" name="VFD_CONTROL_2">
2710                 <bitfield name="REGID_HSPATCHID" low="0" high="7" type="a3xx_regid"/>
2711                 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
2712         </reg32>
2713         <reg32 offset="0xa003" name="VFD_CONTROL_3">
2714                 <bitfield name="REGID_DSPATCHID" low="8" high="15" type="a3xx_regid"/>
2715                 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
2716                 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
2717         </reg32>
2718         <reg32 offset="0xa004" name="VFD_CONTROL_4">
2719         </reg32>
2720         <reg32 offset="0xa005" name="VFD_CONTROL_5">
2721                 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
2722         </reg32>
2723         <reg32 offset="0xa006" name="VFD_CONTROL_6">
2724         </reg32>
2725
2726         <reg32 offset="0xa007" name="VFD_MODE_CNTL">
2727                 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
2728         </reg32>
2729
2730         <!-- always 0x0 ? -->
2731         <reg32 offset="0xa008" name="VFD_UNKNOWN_A008"/>
2732         <reg32 offset="0xa009" name="VFD_ADD_OFFSET">
2733                 <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
2734                 <bitfield name="VERTEX" pos="0" type="boolean"/>
2735                 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
2736                 <bitfield name="INSTANCE" pos="1" type="boolean"/>
2737         </reg32>
2738
2739         <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
2740         <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
2741         <array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
2742                 <reg64 offset="0x0" name="BASE" type="address"/>
2743                 <reg32 offset="0x0" name="BASE_LO"/>
2744                 <reg32 offset="0x1" name="BASE_HI"/>
2745                 <reg32 offset="0x2" name="SIZE" type="uint"/>
2746                 <reg32 offset="0x3" name="STRIDE" type="uint"/>
2747         </array>
2748         <array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
2749                 <reg32 offset="0x0" name="INSTR">
2750                         <!-- IDX and byte OFFSET into VFD_FETCH -->
2751                         <bitfield name="IDX" low="0" high="4" type="uint"/>
2752                         <bitfield name="OFFSET" low="5" high="16"/>
2753                         <bitfield name="INSTANCED" pos="17" type="boolean"/>
2754                         <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
2755                         <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
2756                         <bitfield name="UNK30" pos="30" type="boolean"/>
2757                         <bitfield name="FLOAT" pos="31" type="boolean"/>
2758                 </reg32>
2759                 <reg32 offset="0x1" name="STEP_RATE"/>
2760         </array>
2761         <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32">
2762                 <reg32 offset="0x0" name="INSTR">
2763                         <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2764                         <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
2765                 </reg32>
2766         </array>
2767
2768         <!-- always 0x1 ? -->
2769         <reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/>
2770
2771         <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
2772                 <!--
2773                 When b31 set we just see FULLREGFOOTPRINT set.  The pattern of
2774                 used registers is a bit odd too:
2775                         - used (half): 0-15 68-179 (cnt=128, max=179)
2776                         - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
2777                 whereas we usually see a (mostly) contiguous range of regs used.  But if
2778                 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
2779                 then:
2780                         - used (merged): 0-191 (cnt=192, max=191)
2781                 So I think if b31 is set, then the half precision registers overlap
2782                 the full precision registers.  (Which seems like a pretty sensible
2783                 feature, actually I'm not sure when you *wouldn't* want to use that,
2784                 since it gives register allocation more flexibility)
2785                  -->
2786                 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
2787                 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
2788                 <!-- seems to be nesting level for flow control:.. -->
2789                 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
2790                 <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
2791                 <bitfield name="VARYING" pos="22" type="boolean"/>
2792                 <!-- set when dFdxFine/dFdyFine is used -->
2793                 <bitfield name="DIFF_FINE" pos="23" type="boolean"/>
2794                 <bitfield name="PIXLODENABLE" pos="26" type="boolean"/>
2795                 <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
2796         </bitset>
2797
2798         <bitset name="a6xx_sp_xs_config" inline="yes">
2799                 <!--
2800                 Each of these are set if the given resource type is used
2801                 with the Vulkan/bindless binding model.
2802                 -->
2803                 <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
2804                 <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
2805                 <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
2806                 <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
2807
2808                 <bitfield name="ENABLED" pos="8" type="boolean"/>
2809                 <!--
2810                 number of textures and samplers.. these might be swapped, with GL I
2811                 always see the same value for both.
2812                  -->
2813                 <bitfield name="NTEX" low="9" high="16" type="uint"/>
2814                 <bitfield name="NSAMP" low="17" high="21" type="uint"/>
2815                 <bitfield name="NIBO" low="22" high="29" type="uint"/>
2816         </bitset>
2817
2818         <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2819         <reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL">
2820                 <!-- # of VS outputs including pos/psize -->
2821                 <bitfield name="VSOUT" low="0" high="5" type="uint"/>
2822         </reg32>
2823         <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
2824                 <reg32 offset="0x0" name="REG">
2825                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2826                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2827                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2828                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2829                 </reg32>
2830         </array>
2831         <!--
2832         Starting with a5xx, position/psize outputs from shader end up in the
2833         SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
2834         the last entries too, except when gl_PointCoord is used, blob inserts
2835         an extra varying after, but with a lower OUTLOC position.  If present,
2836         psize is last, preceded by position.
2837          -->
2838         <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
2839                 <reg32 offset="0x0" name="REG">
2840                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2841                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2842                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2843                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2844                 </reg32>
2845         </array>
2846
2847         <reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/>
2848         <reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
2849         <reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
2850         <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" type="uint"/>
2851         <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/>
2852         <reg32 offset="0xa824" name="SP_VS_INSTRLEN" type="uint"/>
2853
2854         <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2855         <reg32 offset="0xa831" name="SP_HS_UNKNOWN_A831"/>
2856         <reg32 offset="0xa833" name="SP_HS_UNKNOWN_A833"/>
2857         <reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/>
2858         <reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/>
2859         <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" type="uint"/>
2860         <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/>
2861         <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" type="uint"/>
2862
2863         <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2864         <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL">
2865                 <!-- # of DS outputs including pos/psize -->
2866                 <bitfield name="DSOUT" low="0" high="4" type="uint"/>
2867         </reg32>
2868         <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
2869                 <reg32 offset="0x0" name="REG">
2870                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2871                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2872                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2873                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2874                 </reg32>
2875         </array>
2876         <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8">
2877                 <reg32 offset="0x0" name="REG">
2878                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2879                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2880                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2881                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2882                 </reg32>
2883         </array>
2884
2885         <reg32 offset="0xa85b" name="SP_DS_UNKNOWN_A85B"/>
2886         <reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/>
2887         <reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/>
2888         <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" type="uint"/>
2889         <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/>
2890         <reg32 offset="0xa864" name="SP_DS_INSTRLEN" type="uint"/>
2891
2892         <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2893         <reg32 offset="0xa871" name="SP_GS_UNKNOWN_A871"/>
2894
2895         <reg32 offset="0xa873" name="SP_PRIMITIVE_CNTL_GS">
2896                 <!-- # of VS outputs including pos/psize -->
2897                 <bitfield name="GSOUT" low="0" high="5" type="uint"/>
2898                 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
2899         </reg32>
2900
2901         <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16">
2902                 <reg32 offset="0x0" name="REG">
2903                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2904                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2905                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2906                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2907                 </reg32>
2908         </array>
2909
2910         <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8">
2911                 <reg32 offset="0x0" name="REG">
2912                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2913                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2914                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2915                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2916                 </reg32>
2917         </array>
2918
2919         <reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
2920         <reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
2921         <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/>
2922         <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/>
2923         <reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/>
2924
2925         <reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/>
2926         <reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/>
2927         <reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/>
2928         <reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/>
2929         <reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/>
2930         <reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/>
2931         <reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/>
2932         <reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/>
2933         <reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/>
2934         <reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/>
2935         <reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/>
2936         <reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/>
2937         <reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/>
2938         <reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/>
2939         <reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/>
2940         <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
2941
2942         <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2943         <reg32 offset="0xa981" name="SP_UNKNOWN_A981">
2944                 <bitfield name="FACE0" pos="0" type="boolean"/>
2945                 <bitfield name="FACE1" pos="1" type="boolean"/>
2946                 <bitfield name="FACE2" pos="2" type="boolean"/>
2947                 <bitfield name="FACE3" pos="3" type="boolean"/>
2948                 <bitfield name="FACE4" pos="4" type="boolean"/>
2949                 <bitfield name="FACE5" pos="5" type="boolean"/>
2950         </reg32>
2951         <reg32 offset="0xa982" name="SP_UNKNOWN_A982"/>
2952         <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
2953         <reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
2954
2955         <reg32 offset="0xa989" name="SP_BLEND_CNTL">
2956                 <bitfield name="ENABLED" pos="0" type="boolean"/>
2957                 <bitfield name="UNK8" pos="8" type="boolean"/>
2958                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2959         </reg32>
2960         <reg32 offset="0xa98a" name="SP_SRGB_CNTL">
2961                 <!-- Same as RB_SRGB_CNTL -->
2962                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2963                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2964                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2965                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2966                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2967                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2968                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2969                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2970         </reg32>
2971         <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS">
2972                 <bitfield name="RT0" low="0" high="3"/>
2973                 <bitfield name="RT1" low="4" high="7"/>
2974                 <bitfield name="RT2" low="8" high="11"/>
2975                 <bitfield name="RT3" low="12" high="15"/>
2976                 <bitfield name="RT4" low="16" high="19"/>
2977                 <bitfield name="RT5" low="20" high="23"/>
2978                 <bitfield name="RT6" low="24" high="27"/>
2979                 <bitfield name="RT7" low="28" high="31"/>
2980         </reg32>
2981         <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
2982                 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
2983                 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
2984         </reg32>
2985         <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
2986                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2987         </reg32>
2988
2989         <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8">
2990                 <reg32 offset="0" name="REG">
2991                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2992                         <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
2993                         <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
2994                 </reg32>
2995         </array>
2996
2997         <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL">
2998                 <!-- unknown bits 0x7fc0 always set -->
2999                 <bitfield name="COUNT" low="0" high="2" type="uint"/>
3000                 <!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? -->
3001                 <bitfield name="UNK3" pos="3" type="boolean"/>
3002                 <bitfield name="UNK4" low="4" high="11" type="a3xx_regid"/>
3003         </reg32>
3004         <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4">
3005                 <reg32 offset="0" name="CMD">
3006                         <bitfield name="SRC" low="0" high="6" type="uint"/>
3007                         <bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
3008                         <bitfield name="TEX_ID" low="11" high="15" type="uint"/>
3009                         <bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
3010                         <bitfield name="WRMASK" low="22" high="25" type="hex"/>
3011                         <bitfield name="HALF" pos="26" type="boolean"/>
3012                         <!--
3013                         CMD seems always 0x4??  3d, textureProj, textureLod seem to
3014                         skip pre-fetch.. TODO test texelFetch
3015                         CMD is 0x6 when the Vulkan mode is enabled, and
3016                         TEX_ID/SAMP_ID refer to the descriptor sets while the
3017                         indices come from SP_FS_BINDLESS_PREFETCH[n]
3018                          -->
3019                         <bitfield name="CMD" low="27" high="31"/>
3020                 </reg32>
3021         </array>
3022
3023         <!-- TODO confirm that this is actually an array -->
3024         <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4">
3025                 <reg32 offset="0" name="CMD">
3026                         <bitfield name="SAMP_ID" low="0" high="7" type="uint"/>
3027                         <bitfield name="TEX_ID" low="16" high="23" type="uint"/>
3028                 </reg32>
3029         </array>
3030
3031         <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
3032
3033         <!-- always 0x0 ? -->
3034         <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8"/>
3035
3036         <!-- set for compute shaders, always 0x41 -->
3037         <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint"/>
3038
3039         <!-- set for compute shaders, always 0x0 -->
3040         <reg32 offset="0xa9b3" name="SP_CS_UNKNOWN_A9B3" type="uint"/>
3041
3042         <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/>
3043
3044         <reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/>
3045         <reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/>
3046         <reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/>
3047         <reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/>
3048         <reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/>
3049         <reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/>
3050         <reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
3051         <reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
3052
3053         <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
3054                 <reg64 offset="0" name="ADDR" type="waddress"/>
3055         </array>
3056
3057         <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
3058                 <doc>per MRT</doc>
3059                 <reg32 offset="0x0" name="REG">
3060                         <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
3061                         <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
3062                 </reg32>
3063         </array>
3064
3065         <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3066         <reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/>
3067         <reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/>
3068         <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/>
3069         <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" type="uint"/>
3070
3071         <!--
3072         IBO state for compute shader:
3073          -->
3074         <reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/>
3075         <reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/>
3076         <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
3077
3078         <!-- always 0x5 ? -->
3079         <reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/>
3080
3081         <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
3082         <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>
3083
3084         <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5">
3085                 <reg64 offset="0" name="ADDR" type="waddress"/>
3086         </array>
3087
3088         <!--
3089         Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
3090         instructions VS/HS/DS/GS/FS.  See SP_CS_IBO_* for compute shaders.
3091          -->
3092         <reg32 offset="0xab1a" name="SP_IBO_LO"/>
3093         <reg32 offset="0xab1b" name="SP_IBO_HI"/>
3094         <reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
3095
3096         <!--
3097         not really src, COLOR_FORMAT/SRGB seem to be related to ifmt which is for dst
3098          -->
3099         <reg32 offset="0xacc0" name="SP_2D_SRC_FORMAT">
3100                 <bitfield name="NORM" pos="0" type="boolean"/>
3101                 <bitfield name="SINT" pos="1" type="boolean"/>
3102                 <bitfield name="UINT" pos="2" type="boolean"/>
3103                 <!-- looks like HW only cares about the base type of this format,
3104                      which matches the ifmt? -->
3105                 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
3106                 <!-- set when ifmt is R2D_UNORM8_SRGB -->
3107                 <bitfield name="SRGB" pos="11" type="boolean"/>
3108                 <!-- some sort of channel mask, not sure what it is for -->
3109                 <bitfield name="MASK" low="12" high="15"/>
3110         </reg32>
3111
3112         <!-- always 0x0 -->
3113         <reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/>
3114
3115         <reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
3116         <reg32 offset="0xae04" name="SP_UNKNOWN_AE04"/>
3117
3118         <!-- always 0x3f ? -->
3119         <reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/>
3120
3121         <!--
3122         The downstream kernel calls the debug cluster of registers
3123         "a6xx_sp_ps_tp_cluster" but this actually specifies the border
3124         color base for compute shaders.
3125         -->
3126         <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3127         <!-- always 0x0 ? -->
3128         <reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
3129         <reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>
3130
3131         <!-- could be all the stuff below here is actually TPL1?? -->
3132
3133         <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL">
3134                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3135         </reg32>
3136         <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL">
3137                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3138                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
3139         </reg32>
3140
3141         <!-- looks to work in the same way as a5xx: -->
3142         <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3143         <reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
3144         <reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
3145         <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config"/>
3146         <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
3147         <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
3148
3149         <reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309"/>
3150
3151         <!--
3152         Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
3153         badly named or the functionality moved in a6xx.  But downstream kernel
3154         calls this "a6xx_sp_ps_tp_2d_cluster"
3155          -->
3156         <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/>
3157         <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
3158                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3159                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3160         </reg32>
3161         <reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
3162         <reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
3163         <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="waddress"/>
3164         <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
3165            <bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/>
3166         </reg32>
3167
3168         <reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
3169         <reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
3170         <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="waddress"/>
3171         <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
3172                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3173                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
3174         </reg32>
3175
3176         <!-- always 0x00100000 ? -->
3177         <reg32 offset="0xb600" name="SP_UNKNOWN_B600"/>
3178
3179         <!-- always 0x44 ? -->
3180         <reg32 offset="0xb605" name="SP_UNKNOWN_B605"/>
3181
3182         <bitset name="a6xx_hlsq_xs_cntl" inline="yes">
3183                 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
3184                 <bitfield name="ENABLED" pos="8" type="boolean"/>
3185         </bitset>
3186
3187         <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3188         <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3189         <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3190         <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3191
3192         <reg32 offset="0xb980" name="HLSQ_UNKNOWN_B980"/>
3193
3194         <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG">
3195                 <!-- always 0x7 ? -->
3196         </reg32>
3197         <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
3198                 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
3199                 <!-- SAMPLEID is loaded into a half-precision register: -->
3200                 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
3201                 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
3202                 <!--
3203                 SIZE is the "size" of the primitive, ie. what the i/j coords need
3204                 to be divided by to scale to a single fragment.  It is probably
3205                 the longer of the two lines that form the tri (ie v0v1 and v0v2)?
3206                  -->
3207                 <bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
3208         </reg32>
3209         <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
3210                 <!-- register loaded with position (bary.f) -->
3211                 <bitfield name="BARY_IJ_PIXEL" low="0" high="7" type="a3xx_regid"/>
3212                 <bitfield name="BARY_IJ_CENTROID" low="16" high="23" type="a3xx_regid"/>
3213         </reg32>
3214         <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
3215                 <bitfield name="BARY_IJ_PIXEL_PERSAMP" low="0" high="7" type="a3xx_regid"/>
3216                 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
3217                 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
3218         </reg32>
3219         <reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
3220                 <!-- unknown regid in low 8b -->
3221         </reg32>
3222         <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3223
3224         <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0">
3225                 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
3226                 <!-- localsize is value minus one: -->
3227                 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
3228                 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
3229                 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
3230         </reg32>
3231         <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1">
3232                 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
3233         </reg32>
3234         <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2">
3235                 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
3236         </reg32>
3237         <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3">
3238                 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
3239         </reg32>
3240         <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4">
3241                 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
3242         </reg32>
3243         <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5">
3244                 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
3245         </reg32>
3246         <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6">
3247                 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
3248         </reg32>
3249         <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0">
3250                 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
3251                 <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
3252                 <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
3253                 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
3254         </reg32>
3255         <reg32 offset="0xb998" name="HLSQ_CS_UNKNOWN_B998"/> <!-- always 0x2fc -->
3256         <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/>
3257         <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
3258         <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
3259
3260         <!-- mirror of SP_CS_BINDLESS_BASE -->
3261         <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5">
3262                 <reg64 offset="0" name="ADDR" type="waddress"/>
3263         </array>
3264
3265         <!-- probably: -->
3266         <reg32 offset="0xbb08" name="HLSQ_UPDATE_CNTL"/>
3267
3268         <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3269
3270         <!-- always 0x0 ? -->
3271         <reg32 offset="0xbb11" name="HLSQ_UNKNOWN_BB11"/>
3272
3273         <!-- mirror of SP_BINDLESS_BASE -->
3274         <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5">
3275                 <reg64 offset="0" name="ADDR" type="waddress"/>
3276         </array>
3277
3278         <!-- always 0x80 ? -->
3279         <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/>
3280         <!-- always 0x0 ? -->
3281         <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01"/>
3282         <!-- always 0x0 ? -->
3283         <reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>
3284
3285 </domain>
3286
3287 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
3288 <domain name="A6XX_TEX_SAMP" width="32">
3289         <doc>Texture sampler dwords</doc>
3290         <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
3291                 <value name="A6XX_TEX_NEAREST" value="0"/>
3292                 <value name="A6XX_TEX_LINEAR" value="1"/>
3293                 <value name="A6XX_TEX_ANISO" value="2"/>
3294                 <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
3295         </enum>
3296         <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
3297                 <value name="A6XX_TEX_REPEAT" value="0"/>
3298                 <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
3299                 <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
3300                 <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
3301                 <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
3302         </enum>
3303         <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
3304                 <value name="A6XX_TEX_ANISO_1" value="0"/>
3305                 <value name="A6XX_TEX_ANISO_2" value="1"/>
3306                 <value name="A6XX_TEX_ANISO_4" value="2"/>
3307                 <value name="A6XX_TEX_ANISO_8" value="3"/>
3308                 <value name="A6XX_TEX_ANISO_16" value="4"/>
3309         </enum>
3310         <enum name="a6xx_reduction_mode">
3311                 <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
3312                 <value name="A6XX_REDUCTION_MODE_MIN" value="1"/>
3313                 <value name="A6XX_REDUCTION_MODE_MAX" value="2"/>
3314         </enum>
3315
3316         <reg32 offset="0" name="0">
3317                 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
3318                 <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
3319                 <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
3320                 <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
3321                 <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
3322                 <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
3323                 <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
3324                 <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
3325         </reg32>
3326         <reg32 offset="1" name="1">
3327                 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
3328                 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
3329                 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
3330                 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
3331                 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
3332                 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
3333         </reg32>
3334         <reg32 offset="2" name="2">
3335                 <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
3336                 <bitfield name="BCOLOR_OFFSET" low="7" high="31" shr="7"/>
3337         </reg32>
3338         <reg32 offset="3" name="3"/>
3339 </domain>
3340
3341 <domain name="A6XX_TEX_CONST" width="32">
3342         <doc>Texture constant dwords</doc>
3343         <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
3344                 <value name="A6XX_TEX_X" value="0"/>
3345                 <value name="A6XX_TEX_Y" value="1"/>
3346                 <value name="A6XX_TEX_Z" value="2"/>
3347                 <value name="A6XX_TEX_W" value="3"/>
3348                 <value name="A6XX_TEX_ZERO" value="4"/>
3349                 <value name="A6XX_TEX_ONE" value="5"/>
3350         </enum>
3351         <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
3352                 <value name="A6XX_TEX_1D" value="0"/>
3353                 <value name="A6XX_TEX_2D" value="1"/>
3354                 <value name="A6XX_TEX_CUBE" value="2"/>
3355                 <value name="A6XX_TEX_3D" value="3"/>
3356         </enum>
3357         <reg32 offset="0" name="0">
3358                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3359                 <bitfield name="SRGB" pos="2" type="boolean"/>
3360                 <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
3361                 <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
3362                 <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
3363                 <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
3364                 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
3365                 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
3366                 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3367                 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
3368         </reg32>
3369         <reg32 offset="1" name="1">
3370                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3371                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3372         </reg32>
3373         <reg32 offset="2" name="2">
3374                 <!--
3375                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3376                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3377
3378                 b31 is probably the 'BUFFER' bit.. it is the one that changes
3379                 behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
3380                  -->
3381                 <bitfield name="UNK4" pos="4" type="boolean"/>
3382                 <bitfield name="FETCHSIZE" low="0" high="3" type="a6xx_tex_fetchsize"/>
3383                 <doc>Pitch in bytes (so actually stride)</doc>
3384                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3385                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3386                 <bitfield name="UNK31" pos="31" type="boolean"/>
3387         </reg32>
3388         <reg32 offset="3" name="3">
3389                 <!--
3390                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3391                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3392                 layer size at the point that it stops being reduced moving to
3393                 higher (smaller) mipmap levels
3394                  -->
3395                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3396                 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
3397                 <!--
3398                 by default levels with w < 16 are linear
3399                 TILE_ALL makes all levels have tiling
3400                 seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
3401                  -->
3402                 <bitfield name="TILE_ALL" pos="27" type="boolean"/>
3403                 <bitfield name="FLAG" pos="28" type="boolean"/>
3404         </reg32>
3405         <reg32 offset="4" name="4">
3406                 <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
3407         </reg32>
3408         <reg32 offset="5" name="5">
3409                 <bitfield name="BASE_HI" low="0" high="16"/>
3410                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3411         </reg32>
3412         <reg32 offset="6" name="6"/>
3413         <reg32 offset="7" name="7">
3414                 <bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
3415         </reg32>
3416         <reg32 offset="8" name="8">
3417                 <bitfield name="FLAG_HI" low="0" high="16"/>
3418         </reg32>
3419         <reg32 offset="9" name="9">
3420                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3421         </reg32>
3422         <reg32 offset="10" name="10">
3423                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3424                 <!-- log2 size of the first level, required for mipmapping -->
3425                 <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
3426                 <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
3427         </reg32>
3428         <reg32 offset="11" name="11"/>
3429         <reg32 offset="12" name="12"/>
3430         <reg32 offset="13" name="13"/>
3431         <reg32 offset="14" name="14"/>
3432         <reg32 offset="15" name="15"/>
3433 </domain>
3434
3435 <!--
3436 Note the "SSBO" state blocks are actually used for both images and SSBOs,
3437 naming is just because I r/e'd SSBOs first.  I should probably come up
3438 with a better name.
3439 -->
3440 <domain name="A6XX_IBO" width="32">
3441         <reg32 offset="0" name="0">
3442                 <!--
3443                 NOTE: same position as in TEX_CONST state.. I don't see other bits
3444                 used but if they are good chance position is same as TEX_CONST
3445                  -->
3446                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3447                 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3448         </reg32>
3449         <reg32 offset="1" name="1">
3450                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3451                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3452         </reg32>
3453         <reg32 offset="2" name="2">
3454                 <!--
3455                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3456                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3457                  -->
3458                 <bitfield name="UNK4" pos="4" type="boolean"/>
3459                 <doc>Pitch in bytes (so actually stride)</doc>
3460                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3461                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3462                 <bitfield name="UNK31" pos="31" type="boolean"/>
3463         </reg32>
3464         <reg32 offset="3" name="3">
3465                 <!--
3466                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3467                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3468                 layer size at the point that it stops being reduced moving to
3469                 higher (smaller) mipmap levels
3470                  -->
3471                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3472                 <bitfield name="UNK27" pos="27" type="boolean"/>
3473                 <bitfield name="FLAG" pos="28" type="boolean"/>
3474         </reg32>
3475         <reg32 offset="4" name="4">
3476                 <bitfield name="BASE_LO" low="0" high="31"/>
3477         </reg32>
3478         <reg32 offset="5" name="5">
3479                 <bitfield name="BASE_HI" low="0" high="16"/>
3480                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3481         </reg32>
3482         <reg32 offset="6" name="6">
3483         </reg32>
3484         <reg32 offset="7" name="7">
3485         </reg32>
3486         <reg32 offset="8" name="8">
3487         </reg32>
3488         <reg32 offset="9" name="9">
3489                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3490         </reg32>
3491         <reg32 offset="10" name="10">
3492                 <!--
3493                 I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
3494                 don't seem to be particularly sensible... or needed for UBWC to work
3495                  -->
3496                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3497         </reg32>
3498 </domain>
3499
3500 <domain name="A6XX_UBO" width="32">
3501         <reg32 offset="0" name="0">
3502                 <bitfield name="BASE_LO" low="0" high="31"/>
3503         </reg32>
3504         <reg32 offset="1" name="1">
3505                 <bitfield name="BASE_HI" low="0" high="16"/>
3506                 <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
3507         </reg32>
3508 </domain>
3509
3510 <domain name="A6XX_PDC" width="32">
3511         <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
3512         <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
3513         <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
3514         <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
3515         <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
3516         <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
3517         <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
3518         <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
3519         <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
3520         <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
3521         <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
3522         <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
3523         <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
3524         <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
3525         <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
3526         <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
3527         <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
3528         <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
3529         <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
3530         <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
3531         <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
3532         <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
3533         <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
3534         <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
3535         <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
3536         <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
3537 </domain>
3538
3539 <domain name="A6XX_PDC_GPU_SEQ" width="32">
3540         <reg32 offset="0x0" name="MEM_0"/>
3541 </domain>
3542
3543 <domain name="A6XX_CX_DBGC" width="32">
3544         <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
3545                 <bitfield high="7" low="0" name="PING_INDEX"/>
3546                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
3547         </reg32>
3548         <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
3549         <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
3550         <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
3551         <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
3552                 <bitfield high="5" low="0" name="TRACEEN"/>
3553                 <bitfield high="14" low="12" name="GRANU"/>
3554                 <bitfield high="31" low="28" name="SEGT"/>
3555         </reg32>
3556         <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
3557                 <bitfield high="27" low="24" name="ENABLE"/>
3558         </reg32>
3559         <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
3560         <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
3561         <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
3562         <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
3563         <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
3564         <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
3565         <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
3566         <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
3567         <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
3568                 <bitfield high="3" low="0" name="BYTEL0"/>
3569                 <bitfield high="7" low="4" name="BYTEL1"/>
3570                 <bitfield high="11" low="8" name="BYTEL2"/>
3571                 <bitfield high="15" low="12" name="BYTEL3"/>
3572                 <bitfield high="19" low="16" name="BYTEL4"/>
3573                 <bitfield high="23" low="20" name="BYTEL5"/>
3574                 <bitfield high="27" low="24" name="BYTEL6"/>
3575                 <bitfield high="31" low="28" name="BYTEL7"/>
3576         </reg32>
3577         <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
3578                 <bitfield high="3" low="0" name="BYTEL8"/>
3579                 <bitfield high="7" low="4" name="BYTEL9"/>
3580                 <bitfield high="11" low="8" name="BYTEL10"/>
3581                 <bitfield high="15" low="12" name="BYTEL11"/>
3582                 <bitfield high="19" low="16" name="BYTEL12"/>
3583                 <bitfield high="23" low="20" name="BYTEL13"/>
3584                 <bitfield high="27" low="24" name="BYTEL14"/>
3585                 <bitfield high="31" low="28" name="BYTEL15"/>
3586         </reg32>
3587
3588         <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
3589         <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
3590 </domain>
3591
3592 <domain name="A6XX_CX_MISC" width="32">
3593         <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
3594         <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
3595 </domain>
3596
3597 </database>