src/freedreno/registers/adreno_pm4.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5
   6 <enum name="vgt_event_type">
   7         <value name="VS_DEALLOC" value="0"/>
   8         <value name="PS_DEALLOC" value="1"/>
   9         <value name="VS_DONE_TS" value="2"/>
  10         <value name="PS_DONE_TS" value="3"/>
  11         <value name="CACHE_FLUSH_TS" value="4"/>
  12         <value name="CONTEXT_DONE" value="5"/>
  13         <value name="CACHE_FLUSH" value="6"/>
  14         <value name="HLSQ_FLUSH" value="7"/> <!-- on a3xx -->
  15         <value name="VIZQUERY_START" value="7"/> <!-- on a2xx (??) -->
  16         <value name="VIZQUERY_END" value="8"/>
  17         <value name="SC_WAIT_WC" value="9"/>
  18         <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
  19         <value name="RST_PIX_CNT" value="13"/>
  20         <value name="RST_VTX_CNT" value="14"/>
  21         <value name="TILE_FLUSH" value="15"/>
  22         <value name="STAT_EVENT" value="16"/>
  23         <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX,A3XX,A4XX"/>
  24         <value name="ZPASS_DONE" value="21"/>
  25         <value name="CACHE_FLUSH_AND_INV_EVENT" value="22"/>
  26         <value name="PERFCOUNTER_START" value="23" variants="A2XX,A3XX,A4XX"/>
  27         <value name="PERFCOUNTER_STOP" value="24" variants="A2XX,A3XX,A4XX"/>
  28         <value name="VS_FETCH_DONE" value="27"/>
  29         <value name="FACENESS_FLUSH" value="28" variants="A2XX,A3XX,A4XX"/>
  30
  31         <!-- a5xx events -->
  32         <value name="FLUSH_SO_0" value="17" variants="A5XX,A6XX"/>
  33         <value name="FLUSH_SO_1" value="18" variants="A5XX,A6XX"/>
  34         <value name="FLUSH_SO_2" value="19" variants="A5XX,A6XX"/>
  35         <value name="FLUSH_SO_3" value="20" variants="A5XX,A6XX"/>
  36         <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX,A6XX"/>
  37         <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX,A6XX"/>
  38         <value name="UNK_1C" value="28" variants="A5XX,A6XX"/>
  39         <value name="UNK_1D" value="29" variants="A5XX,A6XX"/>
  40         <value name="BLIT" value="30" variants="A5XX,A6XX"/>
  41         <value name="UNK_25" value="37" variants="A5XX"/>
  42         <value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
  43         <value name="UNK_2C" value="44" variants="A5XX"/>
  44         <value name="UNK_2D" value="45" variants="A5XX"/>
  45
  46         <!-- a6xx events -->
  47         <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
  48 </enum>
  49
  50 <enum name="pc_di_primtype">
  51         <value name="DI_PT_NONE" value="0"/>
  52         <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
  53         <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
  54         <value name="DI_PT_LINELIST" value="2"/>
  55         <value name="DI_PT_LINESTRIP" value="3"/>
  56         <value name="DI_PT_TRILIST" value="4"/>
  57         <value name="DI_PT_TRIFAN" value="5"/>
  58         <value name="DI_PT_TRISTRIP" value="6"/>
  59         <value name="DI_PT_LINELOOP" value="7"/>  <!-- a22x, a3xx -->
  60         <value name="DI_PT_RECTLIST" value="8"/>
  61         <value name="DI_PT_POINTLIST" value="9"/>
  62         <value name="DI_PT_LINE_ADJ" value="0xa"/>
  63         <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
  64         <value name="DI_PT_TRI_ADJ" value="0xc"/>
  65         <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
  66
  67         <value name="DI_PT_PATCHES0" value="0x1f"/>
  68         <value name="DI_PT_PATCHES1" value="0x20"/>
  69         <value name="DI_PT_PATCHES2" value="0x21"/>
  70         <value name="DI_PT_PATCHES3" value="0x22"/>
  71         <value name="DI_PT_PATCHES4" value="0x23"/>
  72         <value name="DI_PT_PATCHES5" value="0x24"/>
  73         <value name="DI_PT_PATCHES6" value="0x25"/>
  74         <value name="DI_PT_PATCHES7" value="0x26"/>
  75         <value name="DI_PT_PATCHES8" value="0x27"/>
  76         <value name="DI_PT_PATCHES9" value="0x28"/>
  77         <value name="DI_PT_PATCHES10" value="0x29"/>
  78         <value name="DI_PT_PATCHES11" value="0x2a"/>
  79         <value name="DI_PT_PATCHES12" value="0x2b"/>
  80         <value name="DI_PT_PATCHES13" value="0x2c"/>
  81         <value name="DI_PT_PATCHES14" value="0x2d"/>
  82         <value name="DI_PT_PATCHES15" value="0x2e"/>
  83         <value name="DI_PT_PATCHES16" value="0x2f"/>
  84         <value name="DI_PT_PATCHES17" value="0x30"/>
  85         <value name="DI_PT_PATCHES18" value="0x31"/>
  86         <value name="DI_PT_PATCHES19" value="0x32"/>
  87         <value name="DI_PT_PATCHES20" value="0x33"/>
  88         <value name="DI_PT_PATCHES21" value="0x34"/>
  89         <value name="DI_PT_PATCHES22" value="0x35"/>
  90         <value name="DI_PT_PATCHES23" value="0x36"/>
  91         <value name="DI_PT_PATCHES24" value="0x37"/>
  92         <value name="DI_PT_PATCHES25" value="0x38"/>
  93         <value name="DI_PT_PATCHES26" value="0x39"/>
  94         <value name="DI_PT_PATCHES27" value="0x3a"/>
  95         <value name="DI_PT_PATCHES28" value="0x3b"/>
  96         <value name="DI_PT_PATCHES29" value="0x3c"/>
  97         <value name="DI_PT_PATCHES30" value="0x3d"/>
  98         <value name="DI_PT_PATCHES31" value="0x3e"/>
  99 </enum>
 100
 101 <enum name="pc_di_src_sel">
 102         <value name="DI_SRC_SEL_DMA" value="0"/>
 103         <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
 104         <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
 105         <value name="DI_SRC_SEL_RESERVED" value="3"/>
 106 </enum>
 107
 108 <enum name="pc_di_face_cull_sel">
 109         <value name="DI_FACE_CULL_NONE" value="0"/>
 110         <value name="DI_FACE_CULL_FETCH" value="1"/>
 111         <value name="DI_FACE_BACKFACE_CULL" value="2"/>
 112         <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
 113 </enum>
 114
 115 <enum name="pc_di_index_size">
 116         <value name="INDEX_SIZE_IGN" value="0"/>
 117         <value name="INDEX_SIZE_16_BIT" value="0"/>
 118         <value name="INDEX_SIZE_32_BIT" value="1"/>
 119         <value name="INDEX_SIZE_8_BIT" value="2"/>
 120         <value name="INDEX_SIZE_INVALID"/>
 121 </enum>
 122
 123 <enum name="pc_di_vis_cull_mode">
 124         <value name="IGNORE_VISIBILITY" value="0"/>
 125         <value name="USE_VISIBILITY" value="1"/>
 126 </enum>
 127
 128 <enum name="adreno_pm4_packet_type">
 129         <value name="CP_TYPE0_PKT" value="0x00000000"/>
 130         <value name="CP_TYPE1_PKT" value="0x40000000"/>
 131         <value name="CP_TYPE2_PKT" value="0x80000000"/>
 132         <value name="CP_TYPE3_PKT" value="0xc0000000"/>
 133         <value name="CP_TYPE4_PKT" value="0x40000000"/>
 134         <value name="CP_TYPE7_PKT" value="0x70000000"/>
 135 </enum>
 136
 137 <!--
 138    Note that in some cases, the same packet id is recycled on a later
 139    generation, so variants attribute is used to distinguish.   They
 140    may not be completely accurate, we would probably have to analyze
 141    the pfp and me/pm4 firmware to verify the packet is actually
 142    handled on a particular generation.  But it is at least enough to
 143    disambiguate the packet-id's that were re-used for different
 144    packets starting with a5xx.
 145  -->
 146 <enum name="adreno_pm4_type3_packets">
 147         <doc>initialize CP's micro-engine</doc>
 148         <value name="CP_ME_INIT" value="0x48"/>
 149         <doc>skip N 32-bit words to get to the next packet</doc>
 150         <value name="CP_NOP" value="0x10"/>
 151         <doc>
 152                 indirect buffer dispatch.  prefetch parser uses this packet
 153                 type to determine whether to pre-fetch the IB
 154         </doc>
 155         <value name="CP_PREEMPT_ENABLE" value="0x1c"/>
 156         <value name="CP_PREEMPT_TOKEN" value="0x1e"/>
 157         <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
 158         <doc>indirect buffer dispatch.  same as IB, but init is pipelined</doc>
 159         <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
 160         <doc>wait for the IDLE state of the engine</doc>
 161         <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
 162         <doc>wait until a register or memory location is a specific value</doc>
 163         <value name="CP_WAIT_REG_MEM" value="0x3c"/>
 164         <doc>wait until a register location is equal to a specific value</doc>
 165         <value name="CP_WAIT_REG_EQ" value="0x52"/>
 166         <doc>wait until a register location is >= a specific value</doc>
 167         <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX,A3XX,A4XX"/>
 168         <doc>wait until a read completes</doc>
 169         <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX,A3XX,A4XX"/>
 170         <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
 171         <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
 172         <doc>register read/modify/write</doc>
 173         <value name="CP_REG_RMW" value="0x21"/>
 174         <doc>Set binning configuration registers</doc>
 175         <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX,A3XX,A4XX"/>
 176         <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX,A6XX"/>
 177         <doc>reads register in chip and writes to memory</doc>
 178         <value name="CP_REG_TO_MEM" value="0x3e"/>
 179         <doc>write N 32-bit words to memory</doc>
 180         <value name="CP_MEM_WRITE" value="0x3d"/>
 181         <doc>write CP_PROG_COUNTER value to memory</doc>
 182         <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
 183         <doc>conditional execution of a sequence of packets</doc>
 184         <value name="CP_COND_EXEC" value="0x44"/>
 185         <doc>conditional write to memory or register</doc>
 186         <value name="CP_COND_WRITE" value="0x45" variants="A2XX,A3XX,A4XX"/>
 187         <value name="CP_COND_WRITE5" value="0x45" variants="A5XX,A6XX"/>
 188         <doc>generate an event that creates a write to memory when completed</doc>
 189         <value name="CP_EVENT_WRITE" value="0x46"/>
 190         <doc>generate a VS|PS_done event</doc>
 191         <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
 192         <doc>generate a cache flush done event</doc>
 193         <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
 194         <doc>generate a z_pass done event</doc>
 195         <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
 196         <doc>
 197                 not sure the real name, but this seems to be what is used for
 198                 opencl, instead of CP_DRAW_INDX..
 199         </doc>
 200         <value name="CP_RUN_OPENCL" value="0x31"/>
 201         <doc>initiate fetch of index buffer and draw</doc>
 202         <value name="CP_DRAW_INDX" value="0x22"/>
 203         <doc>draw using supplied indices in packet</doc>
 204         <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX,A3XX,A4XX"/>  <!-- this is something different on a6xx and unused on a5xx -->
 205         <doc>initiate fetch of index buffer and binIDs and draw</doc>
 206         <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX,A3XX,A4XX"/>
 207         <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
 208         <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX,A3XX,A4XX"/>
 209         <doc>begin/end initiator for viz query extent processing</doc>
 210         <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX,A3XX,A4XX"/>
 211         <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
 212         <value name="CP_SET_STATE" value="0x25"/>
 213         <doc>load constant into chip and to memory</doc>
 214         <value name="CP_SET_CONSTANT" value="0x2d"/>
 215         <doc>load sequencer instruction memory (pointer-based)</doc>
 216         <value name="CP_IM_LOAD" value="0x27"/>
 217         <doc>load sequencer instruction memory (code embedded in packet)</doc>
 218         <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
 219         <doc>load constants from a location in memory</doc>
 220         <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e"/>
 221         <doc>selective invalidation of state pointers</doc>
 222         <value name="CP_INVALIDATE_STATE" value="0x3b"/>
 223         <doc>dynamically changes shader instruction memory partition</doc>
 224         <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX,A3XX,A4XX"/>
 225         <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
 226         <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX,A3XX,A4XX"/>
 227         <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
 228         <value name="CP_SET_BIN_SELECT" value="0x51"/>
 229         <doc>updates the current context, if needed</doc>
 230         <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
 231         <doc>generate interrupt from the command stream</doc>
 232         <value name="CP_INTERRUPT" value="0x40"/>
 233         <doc>copy sequencer instruction memory to system memory</doc>
 234         <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
 235
 236         <!-- For a20x -->
 237 <!-- TODO handle variants..
 238         <doc>
 239                 Program an offset that will added to the BIN_BASE value of
 240                 the 3D_DRAW_INDX_BIN packet
 241         </doc>
 242         <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
 243  -->
 244
 245         <!-- for a22x -->
 246         <doc>
 247                 sets draw initiator flags register in PFP, gets bitwise-ORed into
 248                 every draw initiator
 249         </doc>
 250         <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
 251         <doc>sets the register protection mode</doc>
 252         <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
 253
 254         <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
 255
 256         <!-- for a3xx -->
 257         <doc>load high level sequencer command</doc>
 258         <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
 259         <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX,A5XX"/>
 260         <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
 261         <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
 262         <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
 263         <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
 264         <doc>Load a buffer with pre-fetch enabled</doc>
 265         <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
 266         <doc>Set bin (?)</doc>
 267         <value name="CP_SET_BIN" value="0x4c"/>
 268
 269         <doc>test 2 memory locations to dword values specified</doc>
 270         <value name="CP_TEST_TWO_MEMS" value="0x71"/>
 271
 272         <doc>Write register, ignoring context state for context sensitive registers</doc>
 273         <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
 274
 275         <doc>Record the real-time when this packet is processed by PFP</doc>
 276         <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
 277
 278         <!-- Used to switch GPU between secure and non-secure modes -->
 279         <value name="CP_SET_SECURE_MODE" value="0x66"/>
 280
 281         <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
 282         <value name="CP_WAIT_FOR_ME" value="0x13"/>
 283
 284         <!-- for a4xx -->
 285         <doc>
 286                 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
 287                 groups of registers.  Looks like it can be used to create state
 288                 objects in GPU memory, and on state change only emit pointer
 289                 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
 290                 overhead:
 291
 292                 (A4x) save PM4 stream pointers to execute upon a visible draw
 293         </doc>
 294         <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX,A5XX,A6XX"/>
 295         <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
 296         <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX,A5XX,A6XX"/>
 297         <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX,A5XX,A6XX"/>
 298         <value name="CP_DRAW_AUTO" value="0x24"/>
 299
 300         <value name="CP_UNKNOWN_19" value="0x19"/>
 301
 302         <doc>set to 1 for fastclear..:</doc>
 303         <value name="CP_UNKNOWN_1A" value="0x1a"/>
 304
 305         <value name="CP_UNKNOWN_4E" value="0x4e"/>
 306
 307         <doc>
 308                 for A4xx
 309                 Write to register with address that does not fit into type-0 pkt
 310         </doc>
 311         <value name="CP_WIDE_REG_WRITE" value="0x74"/>
 312
 313         <doc>copy from ME scratch RAM to a register</doc>
 314         <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
 315
 316         <doc>Copy from REG to ME scratch RAM</doc>
 317         <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
 318
 319         <doc>Wait for memory writes to complete</doc>
 320         <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
 321
 322         <doc>Conditional execution based on register comparison</doc>
 323         <value name="CP_COND_REG_EXEC" value="0x47"/>
 324
 325         <doc>Memory to REG copy</doc>
 326         <value name="CP_MEM_TO_REG" value="0x42"/>
 327
 328         <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX,A5XX,A6XX"/>
 329         <value name="CP_EXEC_CS" value="0x33"/>
 330
 331         <doc>
 332                 for a5xx
 333         </doc>
 334         <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
 335         <!-- switches SMMU pagetable, used on a5xx only -->
 336         <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX,A6XX"/>
 337         <!-- for a6xx -->
 338         <doc>Tells CP the current mode of GPU operation</doc>
 339         <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
 340         <doc>Instruct CP to set a few internal CP registers</doc>
 341         <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
 342         <!--
 343         pairs of regid and value.. seems to be used to program some TF
 344         related regs:
 345          -->
 346         <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX,A6XX"/>
 347         <!-- A5XX Enable yield in RB only -->
 348         <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
 349         <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX,A6XX"/>
 350         <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX,A6XX"/>
 351         <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX,A6XX"/>
 352         <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX,A6XX"/>
 353         <!-- Enable/Disable/Defer A5x global preemption model -->
 354         <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
 355         <!-- Enable/Disable A5x local preemption model -->
 356         <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
 357         <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
 358         <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX"/>
 359         <!-- Inform CP about current render mode (needed for a5xx preemption) -->
 360         <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
 361         <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
 362         <!-- check if this works on earlier.. -->
 363         <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX,A6XX"/>
 364         <value name="CP_BLIT" value="0x2c" variants="A5XX,A6XX"/>
 365
 366         <!-- Test specified bit in specified register and set predicate -->
 367         <value name="CP_REG_TEST" value="0x39" variants="A5XX,A6XX"/>
 368
 369         <!--
 370         Seems to set the mode flags which control which CP_SET_DRAW_STATE
 371         packets are executed, based on their ENABLE_MASK values
 372
 373         CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
 374         packets w/ ENABLE_MASK & 0x6 to execute immediately
 375          -->
 376         <value name="CP_SET_MODE" value="0x63" variants="A6XX"/>
 377
 378         <!--
 379         Seems like there are now separate blocks of state for VS vs FS/CS
 380         (probably these amounts to geometry vs fragments so that geometry
 381         stage of the pipeline for next draw can start while fragment stage
 382         of current draw is still running.  The format of the payload of the
 383         packets is the same, the only difference is the offsets of the regs
 384         the firmware code that handles the packet writes.
 385
 386         Note that for CL, starting with a6xx, the preferred # of local
 387         threads is no longer the same as the max, implying that the shader
 388         core can now run warps from unrelated shaders (ie.
 389         CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
 390         CL_KERNEL_WORK_GROUP_SIZE)
 391          -->
 392         <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/>
 393         <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/>
 394         <!--
 395         Note: For IBO state (Image/SSBOs) which have shared state across
 396         shader stages, for 3d pipeline CP_LOAD_STATE6 is used.  But for
 397         compute shaders, CP_LOAD_STATE6_FRAG is used.  Possibly they are
 398         interchangable.
 399          -->
 400         <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/>
 401
 402         <!-- internal packets: -->
 403         <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
 404         <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
 405         <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
 406         <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
 407         <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
 408         <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
 409         <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
 410         <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
 411
 412         <!-- jmptable entry used to handle type4 packet on a5xx+: -->
 413         <value name="PKT4" value="0x04" variants="A5XX,A6XX"/>
 414 <!--
 415 unknown a6xx opcodes:
 416
 417 opcode: (null) (14) (5 dwords)
 418 opcode: (null) (55) (4 dwords)
 419 opcode: (null) (6d) (4 dwords)
 420  -->
 421         <value name="CP_UNK_A6XX_14" value="0x14" variants="A6XX"/>
 422         <value name="CP_UNK_A6XX_55" value="0x55" variants="A6XX"/>
 423
 424         <!--
 425         Seems to always have the payload:
 426           00000002 00008801 00004010
 427         or:
 428           00000002 00008801 00004090
 429         or:
 430           00000002 00008801 00000010
 431           00000002 00008801 00010010
 432           00000002 00008801 00d64010
 433           ...
 434         Note set for compute shaders..
 435         Is 0x8801 a register offset?
 436         This appears to be a special sort of register write packet
 437         more or less, but the firmware has some special handling..
 438         Seems like it intercepts/modifies certain register offsets,
 439         but others are treated like a normal PKT4 reg write.  I
 440         guess there are some registers that the fw controls certain
 441         bits.
 442          -->
 443         <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
 444
 445 </enum>
 446
 447
 448 <domain name="CP_LOAD_STATE" width="32">
 449         <doc>Load state, a3xx (and later?)</doc>
 450         <enum name="adreno_state_block">
 451                 <value name="SB_VERT_TEX" value="0"/>
 452                 <value name="SB_VERT_MIPADDR" value="1"/>
 453                 <value name="SB_FRAG_TEX" value="2"/>
 454                 <value name="SB_FRAG_MIPADDR" value="3"/>
 455                 <value name="SB_VERT_SHADER" value="4"/>
 456                 <value name="SB_GEOM_SHADER" value="5"/>
 457                 <value name="SB_FRAG_SHADER" value="6"/>
 458                 <value name="SB_COMPUTE_SHADER" value="7"/>
 459         </enum>
 460         <enum name="adreno_state_type">
 461                 <value name="ST_SHADER" value="0"/>
 462                 <value name="ST_CONSTANTS" value="1"/>
 463         </enum>
 464         <enum name="adreno_state_src">
 465                 <value name="SS_DIRECT" value="0">
 466                         <doc>inline with the CP_LOAD_STATE packet</doc>
 467                 </value>
 468                 <value name="SS_INVALID_ALL_IC" value="2"/>
 469                 <value name="SS_INVALID_PART_IC" value="3"/>
 470                 <value name="SS_INDIRECT" value="4">
 471                         <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
 472                 </value>
 473                 <value name="SS_INDIRECT_TCM" value="5"/>
 474                 <value name="SS_INDIRECT_STM" value="6"/>
 475         </enum>
 476         <reg32 offset="0" name="0">
 477                 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
 478                 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
 479                 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
 480                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 481         </reg32>
 482         <reg32 offset="1" name="1">
 483                 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
 484                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 485         </reg32>
 486 </domain>
 487
 488 <domain name="CP_LOAD_STATE4" width="32" varset="chip">
 489         <doc>Load state, a4xx+</doc>
 490         <enum name="a4xx_state_block">
 491                 <!--
 492                 unknown: 0x7 and 0xf <- seen in compute shader
 493
 494                 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
 495                 Seen in some GL shaders.  Payload is NUM_UNIT dwords, and it contains
 496                 the gpuaddr of the following shader constants block.  DST_OFF seems
 497                 to specify which shader stage:
 498
 499                     16 -> vert
 500                     36 -> tcs
 501                     56 -> tes
 502                     76 -> geom
 503                     96 -> frag
 504
 505                 Example:
 506
 507 opcode: CP_LOAD_STATE4 (30) (12 dwords)
 508         { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
 509         { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
 510         { EXT_SRC_ADDR_HI = 0 }
 511                         0000: c0264100 00000000 00000000 00000000
 512                 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
 513
 514 opcode: CP_LOAD_STATE4 (30) (4 dwords)
 515         { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 516         { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
 517         { EXT_SRC_ADDR_HI = 0 }
 518                         0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
 519                         0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
 520                         0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
 521
 522                 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader.  NUM_UNITS * 2 dwords.
 523
 524                  -->
 525                 <value name="SB4_VS_TEX"    value="0x0"/>
 526                 <value name="SB4_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
 527                 <value name="SB4_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
 528                 <value name="SB4_GS_TEX"    value="0x3"/>
 529                 <value name="SB4_FS_TEX"    value="0x4"/>
 530                 <value name="SB4_CS_TEX"    value="0x5"/>
 531                 <value name="SB4_VS_SHADER" value="0x8"/>
 532                 <value name="SB4_HS_SHADER" value="0x9"/>
 533                 <value name="SB4_DS_SHADER" value="0xa"/>
 534                 <value name="SB4_GS_SHADER" value="0xb"/>
 535                 <value name="SB4_FS_SHADER" value="0xc"/>
 536                 <value name="SB4_CS_SHADER" value="0xd"/>
 537                 <!--
 538                 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
 539                 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
 540
 541                 Compute has it's own dedicated SSBO state, it seems, but the rest
 542                 of the stages share state
 543                  -->
 544                 <value name="SB4_SSBO"   value="0xe"/>
 545                 <value name="SB4_CS_SSBO"   value="0xf"/>
 546         </enum>
 547         <enum name="a4xx_state_type">
 548                 <value name="ST4_SHADER" value="0"/>
 549                 <value name="ST4_CONSTANTS" value="1"/>
 550                 <value name="ST4_UBO" value="2"/>
 551         </enum>
 552         <enum name="a4xx_state_src">
 553                 <value name="SS4_DIRECT" value="0"/>
 554                 <value name="SS4_INDIRECT" value="2"/>
 555         </enum>
 556         <reg32 offset="0" name="0">
 557                 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
 558                 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
 559                 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
 560                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 561         </reg32>
 562         <reg32 offset="1" name="1">
 563                 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
 564                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 565         </reg32>
 566         <reg32 offset="2" name="2" variants="A5XX-">
 567                 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
 568         </reg32>
 569 </domain>
 570
 571 <!-- looks basically same CP_LOAD_STATE4 -->
 572 <domain name="CP_LOAD_STATE6" width="32" varset="chip">
 573         <doc>Load state, a6xx+</doc>
 574         <enum name="a6xx_state_block">
 575                 <value name="SB6_VS_TEX"    value="0x0"/>
 576                 <value name="SB6_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
 577                 <value name="SB6_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
 578                 <value name="SB6_GS_TEX"    value="0x3"/>
 579                 <value name="SB6_FS_TEX"    value="0x4"/>
 580                 <value name="SB6_CS_TEX"    value="0x5"/>
 581                 <value name="SB6_VS_SHADER" value="0x8"/>
 582                 <value name="SB6_HS_SHADER" value="0x9"/>
 583                 <value name="SB6_DS_SHADER" value="0xa"/>
 584                 <value name="SB6_GS_SHADER" value="0xb"/>
 585                 <value name="SB6_FS_SHADER" value="0xc"/>
 586                 <value name="SB6_CS_SHADER" value="0xd"/>
 587                 <value name="SB6_IBO"       value="0xe"/>
 588                 <value name="SB6_CS_IBO"    value="0xf"/>
 589         </enum>
 590         <enum name="a6xx_state_type">
 591                 <value name="ST6_SHADER" value="0"/>
 592                 <value name="ST6_CONSTANTS" value="1"/>
 593                 <value name="ST6_UBO" value="2"/>
 594                 <value name="ST6_IBO" value="3"/>
 595         </enum>
 596         <enum name="a6xx_state_src">
 597                 <value name="SS6_DIRECT" value="0"/>
 598                 <value name="SS6_INDIRECT" value="2"/>
 599         </enum>
 600         <reg32 offset="0" name="0">
 601                 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
 602                 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
 603                 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
 604                 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
 605                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 606         </reg32>
 607         <reg32 offset="1" name="1">
 608                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 609         </reg32>
 610         <reg32 offset="2" name="2">
 611                 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
 612         </reg32>
 613 </domain>
 614
 615 <bitset name="vgt_draw_initiator" inline="yes">
 616         <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
 617         <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
 618         <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
 619         <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
 620         <bitfield name="NOT_EOP" pos="12" type="boolean"/>
 621         <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
 622         <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
 623         <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
 624 </bitset>
 625
 626 <!-- changed on a4xx: -->
 627 <enum name="a4xx_index_size">
 628         <value name="INDEX4_SIZE_8_BIT" value="0"/>
 629         <value name="INDEX4_SIZE_16_BIT" value="1"/>
 630         <value name="INDEX4_SIZE_32_BIT" value="2"/>
 631 </enum>
 632
 633 <enum name="a6xx_patch_type">
 634   <value name="TESS_QUADS" value="0"/>
 635   <value name="TESS_TRIANGLES" value="1"/>
 636   <value name="TESS_ISOLINES" value="2"/>
 637 </enum>
 638
 639 <bitset name="vgt_draw_initiator_a4xx" inline="yes">
 640         <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
 641         <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
 642         <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
 643         <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
 644         <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
 645         <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
 646         <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
 647 </bitset>
 648
 649 <domain name="CP_DRAW_INDX" width="32">
 650         <reg32 offset="0" name="0">
 651                 <bitfield name="VIZ_QUERY" low="0" high="31"/>
 652         </reg32>
 653         <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
 654         <reg32 offset="2" name="2">
 655                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 656         </reg32>
 657         <reg32 offset="3" name="3">
 658                 <bitfield name="INDX_BASE" low="0" high="31"/>
 659         </reg32>
 660         <reg32 offset="4" name="4">
 661                 <bitfield name="INDX_SIZE" low="0" high="31"/>
 662         </reg32>
 663 </domain>
 664
 665 <domain name="CP_DRAW_INDX_2" width="32">
 666         <reg32 offset="0" name="0">
 667                 <bitfield name="VIZ_QUERY" low="0" high="31"/>
 668         </reg32>
 669         <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
 670         <reg32 offset="2" name="2">
 671                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 672         </reg32>
 673         <!-- followed by NUM_INDICES indices.. -->
 674 </domain>
 675
 676 <domain name="CP_DRAW_INDX_OFFSET" width="32">
 677         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 678         <reg32 offset="1" name="1">
 679                 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
 680         </reg32>
 681         <reg32 offset="2" name="2">
 682                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 683         </reg32>
 684         <reg32 offset="3" name="3">
 685         </reg32>
 686
 687         <stripe variants="A5XX-">
 688                 <reg32 offset="4" name="4">
 689                         <bitfield name="INDX_BASE_LO" low="0" high="31"/>
 690                 </reg32>
 691                 <reg32 offset="5" name="5">
 692                         <bitfield name="INDX_BASE_HI" low="0" high="31"/>
 693                 </reg32>
 694                 <reg32 offset="6" name="6">
 695                         <bitfield name="INDX_SIZE" low="0" high="31"/>
 696                 </reg32>
 697         </stripe>
 698
 699         <reg32 offset="4" name="4">
 700                 <bitfield name="INDX_BASE" low="0" high="31"/>
 701         </reg32>
 702
 703         <reg32 offset="5" name="5">
 704                 <bitfield name="INDX_SIZE" low="0" high="31"/>
 705         </reg32>
 706 </domain>
 707
 708 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
 709         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 710         <reg32 offset="1" name="1">
 711                 <bitfield name="INDIRECT" low="0" high="31"/>
 712         </reg32>
 713         <stripe variants="A5XX-">
 714                 <reg32 offset="2" name="2">
 715                         <bitfield name="INDIRECT_HI" low="0" high="31"/>
 716                 </reg32>
 717         </stripe>
 718 </domain>
 719
 720 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
 721         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 722         <stripe variants="A4XX">
 723                 <reg32 offset="1" name="1">
 724                         <bitfield name="INDX_BASE" low="0" high="31"/>
 725                 </reg32>
 726                 <reg32 offset="2" name="2">
 727                         <!-- max # of bytes in index buffer -->
 728                         <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
 729                 </reg32>
 730                 <reg32 offset="3" name="3">
 731                         <bitfield name="INDIRECT" low="0" high="31"/>
 732                 </reg32>
 733         </stripe>
 734         <stripe variants="A5XX-">
 735                 <reg32 offset="1" name="1">
 736                         <bitfield name="INDX_BASE_LO" low="0" high="31"/>
 737                 </reg32>
 738                 <reg32 offset="2" name="2">
 739                         <bitfield name="INDX_BASE_HI" low="0" high="31"/>
 740                 </reg32>
 741                 <reg32 offset="3" name="3">
 742                         <!-- max # of elements in index buffer -->
 743                         <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
 744                 </reg32>
 745                 <reg32 offset="4" name="4">
 746                         <bitfield name="INDIRECT_LO" low="0" high="31"/>
 747                 </reg32>
 748                 <reg32 offset="5" name="5">
 749                         <bitfield name="INDIRECT_HI" low="0" high="31"/>
 750                 </reg32>
 751         </stripe>
 752 </domain>
 753
 754 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
 755         <array offset="0" name="" stride="3" length="100">
 756                 <reg32 offset="0" name="0">
 757                         <bitfield name="COUNT" low="0" high="15" type="uint"/>
 758                         <bitfield name="DIRTY" pos="16" type="boolean"/>
 759                         <bitfield name="DISABLE" pos="17" type="boolean"/>
 760                         <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
 761                         <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
 762                         <!--
 763                         I think this is a bitmask of states that this group applies to
 764                         (ie. binning/bypass/gmem)?  At least starting w/ a6xx blob
 765                         emits different VS state at the same time, with ENABLE_MASK=0x1
 766                         for binning pass VS state, and ENABLE_MASK=0x6 for full VS.
 767                         -->
 768                         <bitfield name="ENABLE_MASK" low="20" high="23" variants="A6XX-"/>
 769                         <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
 770                 </reg32>
 771                 <reg32 offset="1" name="1">
 772                         <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
 773                 </reg32>
 774                 <reg32 offset="2" name="2" variants="A5XX-">
 775                         <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
 776                 </reg32>
 777         </array>
 778 </domain>
 779
 780 <domain name="CP_SET_BIN" width="32">
 781         <doc>value at offset 0 always seems to be 0x00000000..</doc>
 782         <reg32 offset="0" name="0"/>
 783         <reg32 offset="1" name="1">
 784                 <bitfield name="X1" low="0" high="15" type="uint"/>
 785                 <bitfield name="Y1" low="16" high="31" type="uint"/>
 786         </reg32>
 787         <reg32 offset="2" name="2">
 788                 <bitfield name="X2" low="0" high="15" type="uint"/>
 789                 <bitfield name="Y2" low="16" high="31" type="uint"/>
 790         </reg32>
 791 </domain>
 792
 793 <domain name="CP_SET_BIN_DATA" width="32">
 794         <reg32 offset="0" name="0">
 795                 <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
 796                 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
 797         </reg32>
 798         <reg32 offset="1" name="1">
 799                 <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
 800                 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
 801         </reg32>
 802 </domain>
 803
 804 <domain name="CP_SET_BIN_DATA5" width="32">
 805         <reg32 offset="0" name="0">
 806                 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
 807                 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
 808                 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
 809                 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
 810         </reg32>
 811         <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
 812         <reg32 offset="1" name="1">
 813                 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
 814         </reg32>
 815         <reg32 offset="2" name="2">
 816                 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
 817         </reg32>
 818         <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
 819         <reg32 offset="3" name="3">
 820                 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
 821         </reg32>
 822         <reg32 offset="4" name="4">
 823                 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
 824         </reg32>
 825         <!-- what is this new address? -->
 826         <reg32 offset="5" name="5">
 827                 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
 828         </reg32>
 829         <reg32 offset="6" name="6">
 830                 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
 831         </reg32>
 832 </domain>
 833
 834 <domain name="CP_REG_TO_MEM" width="32">
 835         <reg32 offset="0" name="0">
 836                 <bitfield name="REG" low="0" high="15" type="hex"/>
 837                 <!--
 838                 number of regsiters/dwords copied is CNT+1.. unsure
 839                 about # of bits
 840                  -->
 841                 <bitfield name="CNT" low="19" high="29" type="uint"/>
 842                 <bitfield name="64B" pos="30" type="boolean"/>
 843                 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 844         </reg32>
 845         <reg32 offset="1" name="1">
 846                 <bitfield name="DEST" low="0" high="31"/>
 847         </reg32>
 848         <reg32 offset="2" name="2" variants="A5XX-">
 849                 <bitfield name="DEST_HI" low="0" high="31"/>
 850         </reg32>
 851 </domain>
 852
 853 <domain name="CP_MEM_TO_REG" width="32">
 854         <reg32 offset="0" name="0">
 855                 <bitfield name="REG" low="0" high="15" type="hex"/>
 856                 <!--
 857                 number of regsiters/dwords copied is CNT+1.. unsure
 858                 about # of bits
 859                  -->
 860                 <bitfield name="CNT" low="19" high="29" type="uint"/>
 861                 <bitfield name="64B" pos="30" type="boolean"/>
 862                 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 863         </reg32>
 864         <reg32 offset="1" name="1">
 865                 <bitfield name="SRC" low="0" high="31"/>
 866         </reg32>
 867         <reg32 offset="2" name="2" variants="A5XX-">
 868                 <bitfield name="SRC_HI" low="0" high="31"/>
 869         </reg32>
 870 </domain>
 871
 872 <domain name="CP_MEM_TO_MEM" width="32">
 873         <reg32 offset="0" name="0">
 874                 <!--
 875                 not sure how many src operands we have, but the low
 876                 bits negate the n'th src argument.
 877                  -->
 878                 <bitfield name="NEG_A" pos="0" type="boolean"/>
 879                 <bitfield name="NEG_B" pos="1" type="boolean"/>
 880                 <bitfield name="NEG_C" pos="2" type="boolean"/>
 881
 882                 <!-- if set treat src/dst as 64bit values -->
 883                 <bitfield name="DOUBLE" pos="29" type="boolean"/>
 884         </reg32>
 885         <!--
 886         followed by sequence of addresses.. the first is the
 887         destination and the rest are N src addresses which are
 888         summed (after being negated if NEG_x bit set) allowing
 889         to do things like 'result += end - start' (which turns
 890         out to be useful for queries and accumulating results
 891         across multiple tiles)
 892          -->
 893 </domain>
 894
 895 <enum name="cp_cond_function">
 896         <value value="0" name="WRITE_ALWAYS"/>
 897         <value value="1" name="WRITE_LT"/>
 898         <value value="2" name="WRITE_LE"/>
 899         <value value="3" name="WRITE_EQ"/>
 900         <value value="4" name="WRITE_NE"/>
 901         <value value="5" name="WRITE_GE"/>
 902         <value value="6" name="WRITE_GT"/>
 903 </enum>
 904
 905 <domain name="CP_COND_WRITE" width="32">
 906         <reg32 offset="0" name="0">
 907                 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
 908                 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
 909                 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
 910         </reg32>
 911         <reg32 offset="1" name="1">
 912                 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
 913         </reg32>
 914         <reg32 offset="2" name="2">
 915                 <bitfield name="REF" low="0" high="31"/>
 916         </reg32>
 917         <reg32 offset="3" name="3">
 918                 <bitfield name="MASK" low="0" high="31"/>
 919         </reg32>
 920         <reg32 offset="4" name="4">
 921                 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
 922         </reg32>
 923         <reg32 offset="5" name="5">
 924                 <bitfield name="WRITE_DATA" low="0" high="31"/>
 925         </reg32>
 926 </domain>
 927
 928 <domain name="CP_COND_WRITE5" width="32">
 929         <reg32 offset="0" name="0">
 930                 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
 931                 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
 932                 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
 933         </reg32>
 934         <reg32 offset="1" name="1">
 935                 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
 936         </reg32>
 937         <reg32 offset="2" name="2">
 938                 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
 939         </reg32>
 940         <reg32 offset="3" name="3">
 941                 <bitfield name="REF" low="0" high="31"/>
 942         </reg32>
 943         <reg32 offset="4" name="4">
 944                 <bitfield name="MASK" low="0" high="31"/>
 945         </reg32>
 946         <reg32 offset="5" name="5">
 947                 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
 948         </reg32>
 949         <reg32 offset="6" name="6">
 950                 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
 951         </reg32>
 952         <reg32 offset="7" name="7">
 953                 <bitfield name="WRITE_DATA" low="0" high="31"/>
 954         </reg32>
 955 </domain>
 956
 957 <domain name="CP_DISPATCH_COMPUTE" width="32">
 958         <reg32 offset="0" name="0"/>
 959         <reg32 offset="1" name="1">
 960                 <bitfield name="X" low="0" high="31"/>
 961         </reg32>
 962         <reg32 offset="2" name="2">
 963                 <bitfield name="Y" low="0" high="31"/>
 964         </reg32>
 965         <reg32 offset="3" name="3">
 966                 <bitfield name="Z" low="0" high="31"/>
 967         </reg32>
 968 </domain>
 969
 970 <domain name="CP_SET_RENDER_MODE" width="32">
 971         <enum name="render_mode_cmd">
 972                 <value value="1" name="BYPASS"/>
 973                 <value value="2" name="BINNING"/>
 974                 <value value="3" name="GMEM"/>
 975                 <value value="5" name="BLIT2D"/>
 976                 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
 977                 <value value="7" name="BLIT2DSCALE"/>
 978                 <!-- 8 set before going back to BYPASS exiting 2D -->
 979                 <value value="8" name="END2D"/>
 980         </enum>
 981         <reg32 offset="0" name="0">
 982                 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
 983                 <!--
 984                 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
 985                 0x21xx range.. possibly (at least some) a5xx variants have a
 986                 2d core?
 987                  -->
 988         </reg32>
 989         <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
 990         <reg32 offset="1" name="1">
 991                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
 992         </reg32>
 993         <reg32 offset="2" name="2">
 994                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
 995         </reg32>
 996         <reg32 offset="3" name="3">
 997                 <!--
 998                 set when in GMEM.. maybe indicates GMEM contents need to be
 999                 preserved on ctx switch?
1000                  -->
1001                 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
1002                 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
1003         </reg32>
1004         <reg32 offset="4" name="4"/>
1005         <!-- second buffer looks like some cmdstream.. length in dwords: -->
1006         <reg32 offset="5" name="5">
1007                 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1008         </reg32>
1009         <reg32 offset="6" name="6">
1010                 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1011         </reg32>
1012         <reg32 offset="7" name="7">
1013                 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
1014         </reg32>
1015 </domain>
1016
1017 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
1018 <domain name="CP_COMPUTE_CHECKPOINT" width="32">
1019         <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1020         <reg32 offset="0" name="0">
1021                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1022         </reg32>
1023         <reg32 offset="1" name="1">
1024                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1025         </reg32>
1026         <reg32 offset="2" name="2">
1027         </reg32>
1028         <!-- second buffer looks like some cmdstream.. length in dwords: -->
1029         <reg32 offset="3" name="3">
1030                 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1031         </reg32>
1032         <reg32 offset="4" name="4"/>
1033         <reg32 offset="5" name="5">
1034                 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1035         </reg32>
1036         <reg32 offset="6" name="6">
1037                 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
1038         </reg32>
1039         <reg32 offset="7" name="7"/>
1040 </domain>
1041
1042 <domain name="CP_PERFCOUNTER_ACTION" width="32">
1043         <reg32 offset="0" name="0">
1044         </reg32>
1045         <reg32 offset="1" name="1">
1046                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1047         </reg32>
1048         <reg32 offset="2" name="2">
1049                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1050         </reg32>
1051 </domain>
1052
1053 <domain name="CP_EVENT_WRITE" width="32">
1054         <reg32 offset="0" name="0">
1055                 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1056                 <!-- when set, write back timestamp instead of value from packet: -->
1057                 <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1058         </reg32>
1059         <!--
1060         TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
1061         context switch?
1062          -->
1063         <reg32 offset="1" name="1">
1064                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1065         </reg32>
1066         <reg32 offset="2" name="2">
1067                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1068         </reg32>
1069         <reg32 offset="3" name="3">
1070                 <!-- ??? -->
1071         </reg32>
1072 </domain>
1073
1074 <domain name="CP_BLIT" width="32">
1075         <enum name="cp_blit_cmd">
1076                 <value value="0" name="BLIT_OP_FILL"/>
1077                 <value value="1" name="BLIT_OP_COPY"/>
1078                 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1079         </enum>
1080         <reg32 offset="0" name="0">
1081                 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1082         </reg32>
1083         <reg32 offset="1" name="1">
1084                 <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1085                 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1086         </reg32>
1087         <reg32 offset="2" name="2">
1088                 <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1089                 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1090         </reg32>
1091         <reg32 offset="3" name="3">
1092                 <bitfield name="DST_X1" low="0" high="13" type="uint"/>
1093                 <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1094         </reg32>
1095         <reg32 offset="4" name="4">
1096                 <bitfield name="DST_X2" low="0" high="13" type="uint"/>
1097                 <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1098         </reg32>
1099 </domain>
1100
1101 <domain name="CP_EXEC_CS" width="32">
1102         <reg32 offset="0" name="0">
1103         </reg32>
1104         <reg32 offset="1" name="1">
1105                 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1106         </reg32>
1107         <reg32 offset="2" name="2">
1108                 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1109         </reg32>
1110         <reg32 offset="3" name="3">
1111                 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1112         </reg32>
1113 </domain>
1114
1115 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1116         <reg32 offset="0" name="0">
1117         </reg32>
1118         <stripe variants="A4XX">
1119                 <reg32 offset="1" name="1">
1120                         <bitfield name="ADDR" low="0" high="31"/>
1121                 </reg32>
1122                 <reg32 offset="2" name="2">
1123                         <!-- localsize is value minus one: -->
1124                         <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1125                         <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1126                         <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1127                 </reg32>
1128         </stripe>
1129         <stripe variants="A5XX-">
1130                 <reg32 offset="1" name="1">
1131                         <bitfield name="ADDR_LO" low="0" high="31"/>
1132                 </reg32>
1133                 <reg32 offset="2" name="2">
1134                         <bitfield name="ADDR_HI" low="0" high="31"/>
1135                 </reg32>
1136                 <reg32 offset="3" name="3">
1137                         <!-- localsize is value minus one: -->
1138                         <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1139                         <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1140                         <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1141                 </reg32>
1142         </stripe>
1143 </domain>
1144
1145 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1146         <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
1147         <enum name="a6xx_render_mode">
1148                 <value value="1" name="RM6_BYPASS"/>
1149                 <value value="2" name="RM6_BINNING"/>
1150                 <value value="4" name="RM6_GMEM"/>
1151                 <value value="5" name="RM6_BLIT2D"/>
1152                 <value value="6" name="RM6_RESOLVE"/>
1153                 <value value="0xc" name="RM6_BLIT2DSCALE"/>
1154         </enum>
1155         <reg32 offset="0" name="0">
1156                 <bitfield name="MARKER" low="0" high="3"/>
1157                 <bitfield name="MODE" low="0" high="3" type="a6xx_render_mode"/>
1158                 <!-- IFPC - inter-frame power collapse -->
1159                 <bitfield name="IFPC" pos="8" type="boolean"/>
1160         </reg32>
1161 </domain>
1162
1163 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1164         <doc>Set internal CP registers, used to indicate context save data addresses</doc>
1165         <enum name="pseudo_reg">
1166                 <value value="0" name="SMMU_INFO"/>
1167                 <value value="1" name="NON_SECURE_SAVE_ADDR"/>
1168                 <value value="2" name="SECURE_SAVE_ADDR"/>
1169                 <value value="3" name="NON_PRIV_SAVE_ADDR"/>
1170                 <value value="4" name="COUNTER"/>
1171         </enum>
1172         <array offset="0" name="" stride="3" length="100">
1173                 <reg32 offset="0" name="0">
1174                         <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/>
1175                 </reg32>
1176                 <reg32 offset="1" name="1">
1177                         <bitfield name="LO" low="0" high="31"/>
1178                 </reg32>
1179                 <reg32 offset="2" name="2">
1180                         <bitfield name="HI" low="0" high="31"/>
1181                 </reg32>
1182         </array>
1183 </domain>
1184
1185 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1186         <doc>
1187                 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
1188                 So:
1189
1190                         opcode: CP_REG_TEST (39) (2 dwords)
1191                                 { REG = 0xc10 | BIT = 0 }
1192                                        0000: 70b90001 00000c10
1193                         opcode: CP_COND_REG_EXEC (47) (3 dwords)
1194                                        0000: 70c70002 10000000 00000004
1195                         opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1196
1197                 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
1198                 offset 0x0c10 is 1
1199         </doc>
1200         <reg32 offset="0" name="0">
1201                 <!-- the register to test -->
1202                 <bitfield name="REG" low="0" high="11"/>
1203                 <!-- the bit to test -->
1204                 <bitfield name="BIT" low="20" high="24" type="uint"/>
1205                 <bitfield name="UNK25" pos="25" type="boolean"/>
1206         </reg32>
1207 </domain>
1208
1209 <!-- I *think* this existed at least as far back as a4xx -->
1210 <domain name="CP_COND_REG_EXEC" width="32">
1211         <reg32 offset="0" name="0">
1212                 <bitfield name="UNK28" pos="28" type="boolean"/>
1213         </reg32>
1214         <reg32 offset="1" name="1">
1215                 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1216         </reg32>
1217 </domain>
1218
1219 </database>
1220