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516133def5612fc19cb6c98be780abfc0d4a89f2
[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
33
34 #include "vk_format.h"
35
36 #include "tu_cs.h"
37 #include "tu_blit.h"
38
39 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
40
41 void
42 tu_bo_list_init(struct tu_bo_list *list)
43 {
44 list->count = list->capacity = 0;
45 list->bo_infos = NULL;
46 }
47
48 void
49 tu_bo_list_destroy(struct tu_bo_list *list)
50 {
51 free(list->bo_infos);
52 }
53
54 void
55 tu_bo_list_reset(struct tu_bo_list *list)
56 {
57 list->count = 0;
58 }
59
60 /**
61 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
62 */
63 static uint32_t
64 tu_bo_list_add_info(struct tu_bo_list *list,
65 const struct drm_msm_gem_submit_bo *bo_info)
66 {
67 assert(bo_info->handle != 0);
68
69 for (uint32_t i = 0; i < list->count; ++i) {
70 if (list->bo_infos[i].handle == bo_info->handle) {
71 assert(list->bo_infos[i].presumed == bo_info->presumed);
72 list->bo_infos[i].flags |= bo_info->flags;
73 return i;
74 }
75 }
76
77 /* grow list->bo_infos if needed */
78 if (list->count == list->capacity) {
79 uint32_t new_capacity = MAX2(2 * list->count, 16);
80 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
81 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
82 if (!new_bo_infos)
83 return TU_BO_LIST_FAILED;
84 list->bo_infos = new_bo_infos;
85 list->capacity = new_capacity;
86 }
87
88 list->bo_infos[list->count] = *bo_info;
89 return list->count++;
90 }
91
92 uint32_t
93 tu_bo_list_add(struct tu_bo_list *list,
94 const struct tu_bo *bo,
95 uint32_t flags)
96 {
97 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
98 .flags = flags,
99 .handle = bo->gem_handle,
100 .presumed = bo->iova,
101 });
102 }
103
104 VkResult
105 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
106 {
107 for (uint32_t i = 0; i < other->count; i++) {
108 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
109 return VK_ERROR_OUT_OF_HOST_MEMORY;
110 }
111
112 return VK_SUCCESS;
113 }
114
115 static void
116 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
117 const struct tu_device *dev,
118 uint32_t pixels)
119 {
120 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
121 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
122 const uint32_t max_tile_width = 1024; /* A6xx */
123
124 tiling->tile0.offset = (VkOffset2D) {
125 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
126 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
127 };
128
129 const uint32_t ra_width =
130 tiling->render_area.extent.width +
131 (tiling->render_area.offset.x - tiling->tile0.offset.x);
132 const uint32_t ra_height =
133 tiling->render_area.extent.height +
134 (tiling->render_area.offset.y - tiling->tile0.offset.y);
135
136 /* start from 1 tile */
137 tiling->tile_count = (VkExtent2D) {
138 .width = 1,
139 .height = 1,
140 };
141 tiling->tile0.extent = (VkExtent2D) {
142 .width = align(ra_width, tile_align_w),
143 .height = align(ra_height, tile_align_h),
144 };
145
146 /* do not exceed max tile width */
147 while (tiling->tile0.extent.width > max_tile_width) {
148 tiling->tile_count.width++;
149 tiling->tile0.extent.width =
150 align(ra_width / tiling->tile_count.width, tile_align_w);
151 }
152
153 /* do not exceed gmem size */
154 while (tiling->tile0.extent.width * tiling->tile0.extent.height > pixels) {
155 if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
156 tiling->tile_count.width++;
157 tiling->tile0.extent.width =
158 align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
159 } else {
160 /* if this assert fails then layout is impossible.. */
161 assert(tiling->tile0.extent.height > tile_align_h);
162 tiling->tile_count.height++;
163 tiling->tile0.extent.height =
164 align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
165 }
166 }
167 }
168
169 static void
170 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
171 const struct tu_device *dev)
172 {
173 const uint32_t max_pipe_count = 32; /* A6xx */
174
175 /* start from 1 tile per pipe */
176 tiling->pipe0 = (VkExtent2D) {
177 .width = 1,
178 .height = 1,
179 };
180 tiling->pipe_count = tiling->tile_count;
181
182 /* do not exceed max pipe count vertically */
183 while (tiling->pipe_count.height > max_pipe_count) {
184 tiling->pipe0.height += 2;
185 tiling->pipe_count.height =
186 (tiling->tile_count.height + tiling->pipe0.height - 1) /
187 tiling->pipe0.height;
188 }
189
190 /* do not exceed max pipe count */
191 while (tiling->pipe_count.width * tiling->pipe_count.height >
192 max_pipe_count) {
193 tiling->pipe0.width += 1;
194 tiling->pipe_count.width =
195 (tiling->tile_count.width + tiling->pipe0.width - 1) /
196 tiling->pipe0.width;
197 }
198 }
199
200 static void
201 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
202 const struct tu_device *dev)
203 {
204 const uint32_t max_pipe_count = 32; /* A6xx */
205 const uint32_t used_pipe_count =
206 tiling->pipe_count.width * tiling->pipe_count.height;
207 const VkExtent2D last_pipe = {
208 .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
209 .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
210 };
211
212 assert(used_pipe_count <= max_pipe_count);
213 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
214
215 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
216 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
217 const uint32_t pipe_x = tiling->pipe0.width * x;
218 const uint32_t pipe_y = tiling->pipe0.height * y;
219 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
220 ? last_pipe.width
221 : tiling->pipe0.width;
222 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
223 ? last_pipe.height
224 : tiling->pipe0.height;
225 const uint32_t n = tiling->pipe_count.width * y + x;
226
227 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
228 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
229 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
230 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
231 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
232 }
233 }
234
235 memset(tiling->pipe_config + used_pipe_count, 0,
236 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
237 }
238
239 static void
240 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
241 const struct tu_device *dev,
242 uint32_t tx,
243 uint32_t ty,
244 struct tu_tile *tile)
245 {
246 /* find the pipe and the slot for tile (tx, ty) */
247 const uint32_t px = tx / tiling->pipe0.width;
248 const uint32_t py = ty / tiling->pipe0.height;
249 const uint32_t sx = tx - tiling->pipe0.width * px;
250 const uint32_t sy = ty - tiling->pipe0.height * py;
251
252 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
253 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
254 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
255
256 /* convert to 1D indices */
257 tile->pipe = tiling->pipe_count.width * py + px;
258 tile->slot = tiling->pipe0.width * sy + sx;
259
260 /* get the blit area for the tile */
261 tile->begin = (VkOffset2D) {
262 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
263 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
264 };
265 tile->end.x =
266 (tx == tiling->tile_count.width - 1)
267 ? tiling->render_area.offset.x + tiling->render_area.extent.width
268 : tile->begin.x + tiling->tile0.extent.width;
269 tile->end.y =
270 (ty == tiling->tile_count.height - 1)
271 ? tiling->render_area.offset.y + tiling->render_area.extent.height
272 : tile->begin.y + tiling->tile0.extent.height;
273 }
274
275 enum a3xx_msaa_samples
276 tu_msaa_samples(uint32_t samples)
277 {
278 switch (samples) {
279 case 1:
280 return MSAA_ONE;
281 case 2:
282 return MSAA_TWO;
283 case 4:
284 return MSAA_FOUR;
285 case 8:
286 return MSAA_EIGHT;
287 default:
288 assert(!"invalid sample count");
289 return MSAA_ONE;
290 }
291 }
292
293 static enum a4xx_index_size
294 tu6_index_size(VkIndexType type)
295 {
296 switch (type) {
297 case VK_INDEX_TYPE_UINT16:
298 return INDEX4_SIZE_16_BIT;
299 case VK_INDEX_TYPE_UINT32:
300 return INDEX4_SIZE_32_BIT;
301 default:
302 unreachable("invalid VkIndexType");
303 return INDEX4_SIZE_8_BIT;
304 }
305 }
306
307 static void
308 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
309 {
310 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
311 }
312
313 unsigned
314 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
315 struct tu_cs *cs,
316 enum vgt_event_type event,
317 bool need_seqno)
318 {
319 unsigned seqno = 0;
320
321 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
322 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
323 if (need_seqno) {
324 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
325 seqno = ++cmd->scratch_seqno;
326 tu_cs_emit(cs, seqno);
327 }
328
329 return seqno;
330 }
331
332 static void
333 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
334 {
335 tu6_emit_event_write(cmd, cs, 0x31, false);
336 }
337
338 static void
339 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
340 {
341 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
342 }
343
344 static void
345 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
346 {
347 if (cmd->wait_for_idle) {
348 tu_cs_emit_wfi(cs);
349 cmd->wait_for_idle = false;
350 }
351 }
352
353 static void
354 tu6_emit_flag_buffer(struct tu_cs *cs, const struct tu_image_view *iview)
355 {
356 uint64_t va = tu_image_ubwc_base(iview->image, iview->base_mip, iview->base_layer);
357 uint32_t pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip);
358 uint32_t size = tu_image_ubwc_size(iview->image, iview->base_mip);
359 if (iview->image->layout.ubwc_size) {
360 tu_cs_emit_qw(cs, va);
361 tu_cs_emit(cs, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(pitch) |
362 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(size >> 2));
363 } else {
364 tu_cs_emit_qw(cs, 0);
365 tu_cs_emit(cs, 0);
366 }
367 }
368
369 static void
370 tu6_emit_zs(struct tu_cmd_buffer *cmd,
371 const struct tu_subpass *subpass,
372 struct tu_cs *cs)
373 {
374 const struct tu_framebuffer *fb = cmd->state.framebuffer;
375
376 const uint32_t a = subpass->depth_stencil_attachment.attachment;
377 if (a == VK_ATTACHMENT_UNUSED) {
378 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
379 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
380 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
381 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
382 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
383 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
384 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
385
386 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
387 tu_cs_emit(cs,
388 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
389
390 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
391 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
392 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
393 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
394 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
395 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
396
397 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
398 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
399
400 return;
401 }
402
403 const struct tu_image_view *iview = fb->attachments[a].attachment;
404 enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
405
406 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
407 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
408 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)));
409 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layout.layer_size));
410 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
411 tu_cs_emit(cs, cmd->state.pass->attachments[a].gmem_offset);
412
413 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
414 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
415
416 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
417 tu6_emit_flag_buffer(cs, iview);
418
419 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
420 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
421 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
422 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
423 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
424 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
425
426 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
427 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
428
429 /* enable zs? */
430 }
431
432 static void
433 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
434 const struct tu_subpass *subpass,
435 struct tu_cs *cs)
436 {
437 const struct tu_framebuffer *fb = cmd->state.framebuffer;
438 unsigned char mrt_comp[MAX_RTS] = { 0 };
439 unsigned srgb_cntl = 0;
440
441 for (uint32_t i = 0; i < subpass->color_count; ++i) {
442 uint32_t a = subpass->color_attachments[i].attachment;
443 if (a == VK_ATTACHMENT_UNUSED)
444 continue;
445
446 const struct tu_image_view *iview = fb->attachments[a].attachment;
447 const enum a6xx_tile_mode tile_mode =
448 tu6_get_image_tile_mode(iview->image, iview->base_mip);
449
450 mrt_comp[i] = 0xf;
451
452 if (vk_format_is_srgb(iview->vk_format))
453 srgb_cntl |= (1 << i);
454
455 const struct tu_native_format *format =
456 tu6_get_native_format(iview->vk_format);
457 assert(format && format->rb >= 0);
458
459 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
460 tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
461 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
462 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
463 tu_cs_emit(cs, A6XX_RB_MRT_PITCH(tu_image_stride(iview->image, iview->base_mip)));
464 tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(iview->image->layout.layer_size));
465 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
466 tu_cs_emit(cs, cmd->state.pass->attachments[a].gmem_offset);
467
468 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
469 tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb) |
470 COND(vk_format_is_sint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_SINT) |
471 COND(vk_format_is_uint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_UINT));
472
473 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
474 tu6_emit_flag_buffer(cs, iview);
475 }
476
477 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
478 tu_cs_emit(cs, srgb_cntl);
479
480 tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
481 tu_cs_emit(cs, srgb_cntl);
482
483 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
484 tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
485 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
486 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
487 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
488 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
489 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
490 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
491 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
492
493 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
494 tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
495 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
496 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
497 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
498 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
499 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
500 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
501 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
502 }
503
504 static void
505 tu6_emit_msaa(struct tu_cmd_buffer *cmd,
506 const struct tu_subpass *subpass,
507 struct tu_cs *cs)
508 {
509 const enum a3xx_msaa_samples samples = tu_msaa_samples(subpass->samples);
510
511 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
512 tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
513 tu_cs_emit(cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
514 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
515
516 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
517 tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
518 tu_cs_emit(cs, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
519 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
520
521 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
522 tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
523 tu_cs_emit(cs, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
524 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
525
526 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
527 tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
528 }
529
530 static void
531 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
532 {
533 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
534 const uint32_t bin_w = tiling->tile0.extent.width;
535 const uint32_t bin_h = tiling->tile0.extent.height;
536
537 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
538 tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
539 A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
540
541 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
542 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
543 A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
544
545 /* no flag for RB_BIN_CONTROL2... */
546 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
547 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
548 A6XX_RB_BIN_CONTROL2_BINH(bin_h));
549 }
550
551 static void
552 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
553 struct tu_cs *cs,
554 bool binning)
555 {
556 uint32_t cntl = 0;
557 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
558 if (binning)
559 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
560
561 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
562 tu_cs_emit(cs, 0x2);
563 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
564 tu_cs_emit(cs, cntl);
565 }
566
567 static void
568 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
569 {
570 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
571 uint32_t x1 = render_area->offset.x;
572 uint32_t y1 = render_area->offset.y;
573 uint32_t x2 = x1 + render_area->extent.width - 1;
574 uint32_t y2 = y1 + render_area->extent.height - 1;
575
576 /* TODO: alignment requirement seems to be less than tile_align_w/h */
577 if (align) {
578 x1 = x1 & ~cmd->device->physical_device->tile_align_w;
579 y1 = y1 & ~cmd->device->physical_device->tile_align_h;
580 x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
581 y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
582 }
583
584 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
585 tu_cs_emit(cs,
586 A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
587 tu_cs_emit(cs,
588 A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
589 }
590
591 static void
592 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
593 struct tu_cs *cs,
594 const struct tu_image_view *iview,
595 uint32_t gmem_offset,
596 bool resolve)
597 {
598 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
599 tu_cs_emit(cs, resolve ? 0 : (A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM));
600
601 const struct tu_native_format *format =
602 tu6_get_native_format(iview->vk_format);
603 assert(format && format->rb >= 0);
604
605 enum a6xx_tile_mode tile_mode =
606 tu6_get_image_tile_mode(iview->image, iview->base_mip);
607 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
608 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
609 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
610 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
611 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap) |
612 COND(iview->image->layout.ubwc_size,
613 A6XX_RB_BLIT_DST_INFO_FLAGS));
614 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
615 tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)));
616 tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layout.layer_size));
617
618 if (iview->image->layout.ubwc_size) {
619 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
620 tu6_emit_flag_buffer(cs, iview);
621 }
622
623 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
624 tu_cs_emit(cs, gmem_offset);
625 }
626
627 static void
628 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
629 {
630 tu6_emit_marker(cmd, cs);
631 tu6_emit_event_write(cmd, cs, BLIT, false);
632 tu6_emit_marker(cmd, cs);
633 }
634
635 static void
636 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
637 struct tu_cs *cs,
638 uint32_t x1,
639 uint32_t y1,
640 uint32_t x2,
641 uint32_t y2)
642 {
643 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
644 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
645 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
646 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
647 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
648
649 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
650 tu_cs_emit(
651 cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
652 tu_cs_emit(
653 cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
654 }
655
656 static void
657 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
658 struct tu_cs *cs,
659 uint32_t x1,
660 uint32_t y1)
661 {
662 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
663 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
664
665 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
666 tu_cs_emit(cs,
667 A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
668
669 tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
670 tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
671
672 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
673 tu_cs_emit(
674 cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
675 }
676
677 static bool
678 use_hw_binning(struct tu_cmd_buffer *cmd)
679 {
680 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
681
682 if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
683 return false;
684
685 return (tiling->tile_count.width * tiling->tile_count.height) > 2;
686 }
687
688 static void
689 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
690 struct tu_cs *cs,
691 const struct tu_tile *tile)
692 {
693 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
694 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
695
696 tu6_emit_marker(cmd, cs);
697 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
698 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
699 tu6_emit_marker(cmd, cs);
700
701 const uint32_t x1 = tile->begin.x;
702 const uint32_t y1 = tile->begin.y;
703 const uint32_t x2 = tile->end.x - 1;
704 const uint32_t y2 = tile->end.y - 1;
705 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
706 tu6_emit_window_offset(cmd, cs, x1, y1);
707
708 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
709 tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
710
711 if (use_hw_binning(cmd)) {
712 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
713
714 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
715 tu_cs_emit(cs, 0x0);
716
717 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
718 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
719 A6XX_CP_REG_TEST_0_BIT(0) |
720 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
721
722 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
723 tu_cs_emit(cs, 0x10000000);
724 tu_cs_emit(cs, 11); /* conditionally execute next 11 dwords */
725
726 /* if (no overflow) */ {
727 tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
728 tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
729 CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
730 tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
731 tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
732 tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
733
734 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
735 tu_cs_emit(cs, 0x0);
736
737 /* use a NOP packet to skip over the 'else' side: */
738 tu_cs_emit_pkt7(cs, CP_NOP, 2);
739 } /* else */ {
740 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
741 tu_cs_emit(cs, 0x1);
742 }
743
744 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
745 tu_cs_emit(cs, 0x0);
746
747 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_8804, 1);
748 tu_cs_emit(cs, 0x0);
749
750 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 1);
751 tu_cs_emit(cs, 0x0);
752
753 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 1);
754 tu_cs_emit(cs, 0x0);
755 } else {
756 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
757 tu_cs_emit(cs, 0x1);
758
759 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
760 tu_cs_emit(cs, 0x0);
761 }
762 }
763
764 static void
765 tu6_emit_load_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a)
766 {
767 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
768 const struct tu_framebuffer *fb = cmd->state.framebuffer;
769 const struct tu_image_view *iview = fb->attachments[a].attachment;
770 const struct tu_render_pass_attachment *attachment =
771 &cmd->state.pass->attachments[a];
772
773 if (attachment->gmem_offset < 0)
774 return;
775
776 const uint32_t x1 = tiling->render_area.offset.x;
777 const uint32_t y1 = tiling->render_area.offset.y;
778 const uint32_t x2 = x1 + tiling->render_area.extent.width;
779 const uint32_t y2 = y1 + tiling->render_area.extent.height;
780 const uint32_t tile_x2 =
781 tiling->tile0.offset.x + tiling->tile0.extent.width * tiling->tile_count.width;
782 const uint32_t tile_y2 =
783 tiling->tile0.offset.y + tiling->tile0.extent.height * tiling->tile_count.height;
784 bool need_load =
785 x1 != tiling->tile0.offset.x || x2 != MIN2(fb->width, tile_x2) ||
786 y1 != tiling->tile0.offset.y || y2 != MIN2(fb->height, tile_y2);
787
788 if (need_load)
789 tu_finishme("improve handling of unaligned render area");
790
791 if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
792 need_load = true;
793
794 if (vk_format_has_stencil(iview->vk_format) &&
795 attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
796 need_load = true;
797
798 if (need_load) {
799 tu6_emit_blit_info(cmd, cs, iview, attachment->gmem_offset, false);
800 tu6_emit_blit(cmd, cs);
801 }
802 }
803
804 static void
805 tu6_emit_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
806 uint32_t a,
807 const VkRenderPassBeginInfo *info)
808 {
809 const struct tu_framebuffer *fb = cmd->state.framebuffer;
810 const struct tu_image_view *iview = fb->attachments[a].attachment;
811 const struct tu_render_pass_attachment *attachment =
812 &cmd->state.pass->attachments[a];
813 unsigned clear_mask = 0;
814
815 /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
816 if (attachment->gmem_offset < 0)
817 return;
818
819 if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
820 clear_mask = 0xf;
821
822 if (vk_format_has_stencil(iview->vk_format)) {
823 clear_mask &= 0x1;
824 if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
825 clear_mask |= 0x2;
826 }
827 if (!clear_mask)
828 return;
829
830 const struct tu_native_format *format =
831 tu6_get_native_format(iview->vk_format);
832 assert(format && format->rb >= 0);
833
834 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
835 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb));
836
837 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
838 tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(clear_mask));
839
840 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
841 tu_cs_emit(cs, attachment->gmem_offset);
842
843 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
844 tu_cs_emit(cs, 0);
845
846 uint32_t clear_vals[4] = { 0 };
847 tu_pack_clear_value(&info->pClearValues[a], iview->vk_format, clear_vals);
848
849 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
850 tu_cs_emit(cs, clear_vals[0]);
851 tu_cs_emit(cs, clear_vals[1]);
852 tu_cs_emit(cs, clear_vals[2]);
853 tu_cs_emit(cs, clear_vals[3]);
854
855 tu6_emit_blit(cmd, cs);
856 }
857
858 static void
859 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
860 struct tu_cs *cs,
861 uint32_t a,
862 uint32_t gmem_a)
863 {
864 if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
865 return;
866
867 tu6_emit_blit_info(cmd, cs,
868 cmd->state.framebuffer->attachments[a].attachment,
869 cmd->state.pass->attachments[gmem_a].gmem_offset, true);
870 tu6_emit_blit(cmd, cs);
871 }
872
873 static void
874 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
875 {
876 const struct tu_render_pass *pass = cmd->state.pass;
877 const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
878
879 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
880 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
881 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
882 CP_SET_DRAW_STATE__0_GROUP_ID(0));
883 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
884 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
885
886 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
887 tu_cs_emit(cs, 0x0);
888
889 tu6_emit_marker(cmd, cs);
890 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
891 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
892 tu6_emit_marker(cmd, cs);
893
894 tu6_emit_blit_scissor(cmd, cs, true);
895
896 for (uint32_t a = 0; a < pass->attachment_count; ++a) {
897 if (pass->attachments[a].gmem_offset >= 0)
898 tu6_emit_store_attachment(cmd, cs, a, a);
899 }
900
901 if (subpass->resolve_attachments) {
902 for (unsigned i = 0; i < subpass->color_count; i++) {
903 uint32_t a = subpass->resolve_attachments[i].attachment;
904 if (a != VK_ATTACHMENT_UNUSED)
905 tu6_emit_store_attachment(cmd, cs, a,
906 subpass->color_attachments[i].attachment);
907 }
908 }
909 }
910
911 static void
912 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
913 {
914 tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
915 tu_cs_emit(cs, restart_index);
916 }
917
918 static void
919 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
920 {
921 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
922 if (result != VK_SUCCESS) {
923 cmd->record_result = result;
924 return;
925 }
926
927 tu6_emit_cache_flush(cmd, cs);
928
929 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
930
931 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
932 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
933 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
934 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
935 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
936 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
937 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
938 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
939 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
940
941 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
942 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
943 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
944 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
945 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
946 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
947 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
948 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
949 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
950 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
951 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
952 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
953 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
954 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
955
956 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
957
958 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
959 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
960 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
961
962 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
963 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
964 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
965 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
966 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
967 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
968 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
969 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
970 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
971 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
972 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
973 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
974
975 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
976 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
977
978 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
979 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
980
981 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
982 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
983
984 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
985 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
986 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
987
988 tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
989 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
990
991 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
992
993 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
994
995 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
996 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
997 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
998 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
999 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
1000 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
1001 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
1002 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
1003 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
1004 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1005 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1006 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1007 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
1008 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1009 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1010 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1011 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
1012 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
1013 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
1014 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
1015 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1016
1017 tu6_emit_marker(cmd, cs);
1018
1019 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
1020
1021 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
1022
1023 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
1024
1025 /* we don't use this yet.. probably best to disable.. */
1026 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1027 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1028 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1029 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1030 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1031 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1032
1033 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1034 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1035 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1036 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1037
1038 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1039 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1040 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1041
1042 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1043 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
1044
1045 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1046 tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
1047
1048 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1049 tu_cs_emit(cs, 0x00000000);
1050 tu_cs_emit(cs, 0x00000000);
1051 tu_cs_emit(cs, 0x00000000);
1052
1053 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1054 tu_cs_emit(cs, 0x00000000);
1055 tu_cs_emit(cs, 0x00000000);
1056 tu_cs_emit(cs, 0x00000000);
1057 tu_cs_emit(cs, 0x00000000);
1058 tu_cs_emit(cs, 0x00000000);
1059 tu_cs_emit(cs, 0x00000000);
1060
1061 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1062 tu_cs_emit(cs, 0x00000000);
1063 tu_cs_emit(cs, 0x00000000);
1064 tu_cs_emit(cs, 0x00000000);
1065 tu_cs_emit(cs, 0x00000000);
1066 tu_cs_emit(cs, 0x00000000);
1067 tu_cs_emit(cs, 0x00000000);
1068
1069 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1070 tu_cs_emit(cs, 0x00000000);
1071 tu_cs_emit(cs, 0x00000000);
1072 tu_cs_emit(cs, 0x00000000);
1073
1074 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
1075 tu_cs_emit(cs, 0x00000000);
1076
1077 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1078 tu_cs_emit(cs, 0x00000000);
1079
1080 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1081 tu_cs_emit(cs, 0x00000000);
1082
1083 tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1084 tu_cs_emit(cs, 0x00000000);
1085
1086 tu_cs_sanity_check(cs);
1087 }
1088
1089 static void
1090 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1091 {
1092 unsigned seqno;
1093
1094 seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_AND_INV_EVENT, true);
1095
1096 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
1097 tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1098 CP_WAIT_REG_MEM_0_POLL_MEMORY);
1099 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1100 tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
1101 tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
1102 tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1103
1104 seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1105
1106 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
1107 tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
1108 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1109 tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
1110 }
1111
1112 static void
1113 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1114 {
1115 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1116
1117 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_BIN_SIZE, 3);
1118 tu_cs_emit(cs, A6XX_VSC_BIN_SIZE_WIDTH(tiling->tile0.extent.width) |
1119 A6XX_VSC_BIN_SIZE_HEIGHT(tiling->tile0.extent.height));
1120 tu_cs_emit_qw(cs, cmd->vsc_data.iova + 32 * cmd->vsc_data_pitch); /* VSC_SIZE_ADDRESS_LO/HI */
1121
1122 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_BIN_COUNT, 1);
1123 tu_cs_emit(cs, A6XX_VSC_BIN_COUNT_NX(tiling->tile_count.width) |
1124 A6XX_VSC_BIN_COUNT_NY(tiling->tile_count.height));
1125
1126 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1127 for (unsigned i = 0; i < 32; i++)
1128 tu_cs_emit(cs, tiling->pipe_config[i]);
1129
1130 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO, 4);
1131 tu_cs_emit_qw(cs, cmd->vsc_data2.iova);
1132 tu_cs_emit(cs, cmd->vsc_data2_pitch);
1133 tu_cs_emit(cs, cmd->vsc_data2.size);
1134
1135 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO, 4);
1136 tu_cs_emit_qw(cs, cmd->vsc_data.iova);
1137 tu_cs_emit(cs, cmd->vsc_data_pitch);
1138 tu_cs_emit(cs, cmd->vsc_data.size);
1139 }
1140
1141 static void
1142 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1143 {
1144 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1145 const uint32_t used_pipe_count =
1146 tiling->pipe_count.width * tiling->pipe_count.height;
1147
1148 /* Clear vsc_scratch: */
1149 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
1150 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1151 tu_cs_emit(cs, 0x0);
1152
1153 /* Check for overflow, write vsc_scratch if detected: */
1154 for (int i = 0; i < used_pipe_count; i++) {
1155 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1156 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1157 CP_COND_WRITE5_0_WRITE_MEMORY);
1158 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
1159 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1160 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
1161 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1162 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1163 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
1164
1165 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1166 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1167 CP_COND_WRITE5_0_WRITE_MEMORY);
1168 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
1169 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1170 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
1171 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1172 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1173 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
1174 }
1175
1176 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1177
1178 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1179
1180 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
1181 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
1182 CP_MEM_TO_REG_0_CNT(1 - 1));
1183 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1184
1185 /*
1186 * This is a bit awkward, we really want a way to invert the
1187 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1188 * execute cmds to use hwbinning when a bit is *not* set. This
1189 * dance is to invert OVERFLOW_FLAG_REG
1190 *
1191 * A CP_NOP packet is used to skip executing the 'else' clause
1192 * if (b0 set)..
1193 */
1194
1195 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1196 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1197 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1198 A6XX_CP_REG_TEST_0_BIT(0) |
1199 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1200
1201 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1202 tu_cs_emit(cs, 0x10000000);
1203 tu_cs_emit(cs, 7); /* conditionally execute next 7 dwords */
1204
1205 /* if (b0 set) */ {
1206 /*
1207 * On overflow, mirror the value to control->vsc_overflow
1208 * which CPU is checking to detect overflow (see
1209 * check_vsc_overflow())
1210 */
1211 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1212 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1213 CP_REG_TO_MEM_0_CNT(0));
1214 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_OVERFLOW);
1215
1216 tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1217 tu_cs_emit(cs, 0x0);
1218
1219 tu_cs_emit_pkt7(cs, CP_NOP, 2); /* skip 'else' when 'if' is taken */
1220 } /* else */ {
1221 tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1222 tu_cs_emit(cs, 0x1);
1223 }
1224 }
1225
1226 static void
1227 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1228 {
1229 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1230
1231 uint32_t x1 = tiling->tile0.offset.x;
1232 uint32_t y1 = tiling->tile0.offset.y;
1233 uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1234 uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1235
1236 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
1237
1238 tu6_emit_marker(cmd, cs);
1239 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1240 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1241 tu6_emit_marker(cmd, cs);
1242
1243 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1244 tu_cs_emit(cs, 0x1);
1245
1246 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1247 tu_cs_emit(cs, 0x1);
1248
1249 tu_cs_emit_wfi(cs);
1250
1251 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_MODE_CNTL, 1);
1252 tu_cs_emit(cs, A6XX_VFD_MODE_CNTL_BINNING_PASS);
1253
1254 update_vsc_pipe(cmd, cs);
1255
1256 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9805, 1);
1257 tu_cs_emit(cs, 0x1);
1258
1259 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A0F8, 1);
1260 tu_cs_emit(cs, 0x1);
1261
1262 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1263 tu_cs_emit(cs, UNK_2C);
1264
1265 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
1266 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(0) |
1267 A6XX_RB_WINDOW_OFFSET_Y(0));
1268
1269 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
1270 tu_cs_emit(cs, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
1271 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
1272
1273 /* emit IB to binning drawcmds: */
1274 tu_cs_emit_call(cs, &cmd->draw_cs);
1275
1276 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1277 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1278 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1279 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1280 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1281 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1282
1283 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1284 tu_cs_emit(cs, UNK_2D);
1285
1286 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1287 tu6_cache_flush(cmd, cs);
1288
1289 tu_cs_emit_wfi(cs);
1290
1291 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1292
1293 emit_vsc_overflow_test(cmd, cs);
1294
1295 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1296 tu_cs_emit(cs, 0x0);
1297
1298 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1299 tu_cs_emit(cs, 0x0);
1300
1301 tu_cs_emit_wfi(cs);
1302
1303 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1304 tu_cs_emit(cs, 0x7c400004);
1305
1306 cmd->wait_for_idle = false;
1307 }
1308
1309 static void
1310 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1311 {
1312 VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
1313 if (result != VK_SUCCESS) {
1314 cmd->record_result = result;
1315 return;
1316 }
1317
1318 tu6_emit_lrz_flush(cmd, cs);
1319
1320 /* lrz clear? */
1321
1322 tu6_emit_cache_flush(cmd, cs);
1323
1324 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1325 tu_cs_emit(cs, 0x0);
1326
1327 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1328 tu6_emit_wfi(cmd, cs);
1329 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1330 tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1331
1332 if (use_hw_binning(cmd)) {
1333 tu6_emit_bin_size(cmd, cs, A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1334
1335 tu6_emit_render_cntl(cmd, cs, true);
1336
1337 tu6_emit_binning_pass(cmd, cs);
1338
1339 tu6_emit_bin_size(cmd, cs, A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1340
1341 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_MODE_CNTL, 1);
1342 tu_cs_emit(cs, 0x0);
1343
1344 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9805, 1);
1345 tu_cs_emit(cs, 0x1);
1346
1347 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A0F8, 1);
1348 tu_cs_emit(cs, 0x1);
1349
1350 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1351 tu_cs_emit(cs, 0x1);
1352 } else {
1353 tu6_emit_bin_size(cmd, cs, 0x6000000);
1354 }
1355
1356 tu6_emit_render_cntl(cmd, cs, false);
1357
1358 tu_cs_sanity_check(cs);
1359 }
1360
1361 static void
1362 tu6_render_tile(struct tu_cmd_buffer *cmd,
1363 struct tu_cs *cs,
1364 const struct tu_tile *tile)
1365 {
1366 const uint32_t render_tile_space = 256 + tu_cs_get_call_size(&cmd->draw_cs);
1367 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1368 if (result != VK_SUCCESS) {
1369 cmd->record_result = result;
1370 return;
1371 }
1372
1373 tu6_emit_tile_select(cmd, cs, tile);
1374 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1375
1376 tu_cs_emit_call(cs, &cmd->draw_cs);
1377 cmd->wait_for_idle = true;
1378
1379 if (use_hw_binning(cmd)) {
1380 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1381 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1382 A6XX_CP_REG_TEST_0_BIT(0) |
1383 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1384
1385 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1386 tu_cs_emit(cs, 0x10000000);
1387 tu_cs_emit(cs, 2); /* conditionally execute next 2 dwords */
1388
1389 /* if (no overflow) */ {
1390 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1391 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1392 }
1393 }
1394
1395 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1396
1397 tu_cs_sanity_check(cs);
1398 }
1399
1400 static void
1401 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1402 {
1403 VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1404 if (result != VK_SUCCESS) {
1405 cmd->record_result = result;
1406 return;
1407 }
1408
1409 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1410 tu_cs_emit(cs, 0);
1411
1412 tu6_emit_lrz_flush(cmd, cs);
1413
1414 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1415
1416 tu_cs_sanity_check(cs);
1417 }
1418
1419 static void
1420 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1421 {
1422 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1423
1424 tu6_render_begin(cmd, &cmd->cs);
1425
1426 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1427 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1428 struct tu_tile tile;
1429 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1430 tu6_render_tile(cmd, &cmd->cs, &tile);
1431 }
1432 }
1433
1434 tu6_render_end(cmd, &cmd->cs);
1435 }
1436
1437 static void
1438 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd,
1439 const VkRenderPassBeginInfo *info)
1440 {
1441 const uint32_t tile_load_space =
1442 8 + (23+19) * cmd->state.pass->attachment_count +
1443 21 + (13 * cmd->state.subpass->color_count + 8) + 11;
1444
1445 struct tu_cs sub_cs;
1446
1447 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs,
1448 tile_load_space, &sub_cs);
1449 if (result != VK_SUCCESS) {
1450 cmd->record_result = result;
1451 return;
1452 }
1453
1454 tu6_emit_blit_scissor(cmd, &sub_cs, true);
1455
1456 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1457 tu6_emit_load_attachment(cmd, &sub_cs, i);
1458
1459 tu6_emit_blit_scissor(cmd, &sub_cs, false);
1460
1461 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1462 tu6_emit_clear_attachment(cmd, &sub_cs, i, info);
1463
1464 /* invalidate because reading input attachments will cache GMEM and
1465 * the cache isn''t updated when GMEM is written
1466 * TODO: is there a no-cache bit for textures?
1467 */
1468 if (cmd->state.subpass->input_count)
1469 tu6_emit_event_write(cmd, &sub_cs, CACHE_INVALIDATE, false);
1470
1471 tu6_emit_zs(cmd, cmd->state.subpass, &sub_cs);
1472 tu6_emit_mrt(cmd, cmd->state.subpass, &sub_cs);
1473 tu6_emit_msaa(cmd, cmd->state.subpass, &sub_cs);
1474
1475 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1476 }
1477
1478 static void
1479 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1480 {
1481 const uint32_t tile_store_space = 32 + 23 * cmd->state.pass->attachment_count;
1482 struct tu_cs sub_cs;
1483
1484 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs,
1485 tile_store_space, &sub_cs);
1486 if (result != VK_SUCCESS) {
1487 cmd->record_result = result;
1488 return;
1489 }
1490
1491 /* emit to tile-store sub_cs */
1492 tu6_emit_tile_store(cmd, &sub_cs);
1493
1494 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1495 }
1496
1497 static void
1498 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1499 const VkRect2D *render_area)
1500 {
1501 const struct tu_device *dev = cmd->device;
1502 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1503
1504 tiling->render_area = *render_area;
1505
1506 tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass->gmem_pixels);
1507 tu_tiling_config_update_pipe_layout(tiling, dev);
1508 tu_tiling_config_update_pipes(tiling, dev);
1509 }
1510
1511 const struct tu_dynamic_state default_dynamic_state = {
1512 .viewport =
1513 {
1514 .count = 0,
1515 },
1516 .scissor =
1517 {
1518 .count = 0,
1519 },
1520 .line_width = 1.0f,
1521 .depth_bias =
1522 {
1523 .bias = 0.0f,
1524 .clamp = 0.0f,
1525 .slope = 0.0f,
1526 },
1527 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1528 .depth_bounds =
1529 {
1530 .min = 0.0f,
1531 .max = 1.0f,
1532 },
1533 .stencil_compare_mask =
1534 {
1535 .front = ~0u,
1536 .back = ~0u,
1537 },
1538 .stencil_write_mask =
1539 {
1540 .front = ~0u,
1541 .back = ~0u,
1542 },
1543 .stencil_reference =
1544 {
1545 .front = 0u,
1546 .back = 0u,
1547 },
1548 };
1549
1550 static void UNUSED /* FINISHME */
1551 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1552 const struct tu_dynamic_state *src)
1553 {
1554 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1555 uint32_t copy_mask = src->mask;
1556 uint32_t dest_mask = 0;
1557
1558 tu_use_args(cmd_buffer); /* FINISHME */
1559
1560 /* Make sure to copy the number of viewports/scissors because they can
1561 * only be specified at pipeline creation time.
1562 */
1563 dest->viewport.count = src->viewport.count;
1564 dest->scissor.count = src->scissor.count;
1565 dest->discard_rectangle.count = src->discard_rectangle.count;
1566
1567 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1568 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1569 src->viewport.count * sizeof(VkViewport))) {
1570 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1571 src->viewport.count);
1572 dest_mask |= TU_DYNAMIC_VIEWPORT;
1573 }
1574 }
1575
1576 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1577 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1578 src->scissor.count * sizeof(VkRect2D))) {
1579 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1580 src->scissor.count);
1581 dest_mask |= TU_DYNAMIC_SCISSOR;
1582 }
1583 }
1584
1585 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1586 if (dest->line_width != src->line_width) {
1587 dest->line_width = src->line_width;
1588 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1589 }
1590 }
1591
1592 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1593 if (memcmp(&dest->depth_bias, &src->depth_bias,
1594 sizeof(src->depth_bias))) {
1595 dest->depth_bias = src->depth_bias;
1596 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1597 }
1598 }
1599
1600 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1601 if (memcmp(&dest->blend_constants, &src->blend_constants,
1602 sizeof(src->blend_constants))) {
1603 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1604 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1605 }
1606 }
1607
1608 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1609 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1610 sizeof(src->depth_bounds))) {
1611 dest->depth_bounds = src->depth_bounds;
1612 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1613 }
1614 }
1615
1616 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1617 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1618 sizeof(src->stencil_compare_mask))) {
1619 dest->stencil_compare_mask = src->stencil_compare_mask;
1620 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1621 }
1622 }
1623
1624 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1625 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1626 sizeof(src->stencil_write_mask))) {
1627 dest->stencil_write_mask = src->stencil_write_mask;
1628 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1629 }
1630 }
1631
1632 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1633 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1634 sizeof(src->stencil_reference))) {
1635 dest->stencil_reference = src->stencil_reference;
1636 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1637 }
1638 }
1639
1640 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1641 if (memcmp(&dest->discard_rectangle.rectangles,
1642 &src->discard_rectangle.rectangles,
1643 src->discard_rectangle.count * sizeof(VkRect2D))) {
1644 typed_memcpy(dest->discard_rectangle.rectangles,
1645 src->discard_rectangle.rectangles,
1646 src->discard_rectangle.count);
1647 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1648 }
1649 }
1650 }
1651
1652 static VkResult
1653 tu_create_cmd_buffer(struct tu_device *device,
1654 struct tu_cmd_pool *pool,
1655 VkCommandBufferLevel level,
1656 VkCommandBuffer *pCommandBuffer)
1657 {
1658 struct tu_cmd_buffer *cmd_buffer;
1659 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1660 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1661 if (cmd_buffer == NULL)
1662 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1663
1664 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1665 cmd_buffer->device = device;
1666 cmd_buffer->pool = pool;
1667 cmd_buffer->level = level;
1668
1669 if (pool) {
1670 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1671 cmd_buffer->queue_family_index = pool->queue_family_index;
1672
1673 } else {
1674 /* Init the pool_link so we can safely call list_del when we destroy
1675 * the command buffer
1676 */
1677 list_inithead(&cmd_buffer->pool_link);
1678 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1679 }
1680
1681 tu_bo_list_init(&cmd_buffer->bo_list);
1682 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1683 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1684 tu_cs_init(&cmd_buffer->sub_cs, TU_CS_MODE_SUB_STREAM, 2048);
1685
1686 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1687
1688 list_inithead(&cmd_buffer->upload.list);
1689
1690 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1691 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1692
1693 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1694 if (result != VK_SUCCESS)
1695 return result;
1696
1697 #define VSC_DATA_SIZE(pitch) ((pitch) * 32 + 0x100) /* extra size to store VSC_SIZE */
1698 #define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
1699
1700 /* TODO: resize on overflow or compute a max size from # of vertices in renderpass?? */
1701 cmd_buffer->vsc_data_pitch = 0x440 * 4;
1702 cmd_buffer->vsc_data2_pitch = 0x1040 * 4;
1703
1704 result = tu_bo_init_new(device, &cmd_buffer->vsc_data, VSC_DATA_SIZE(cmd_buffer->vsc_data_pitch));
1705 if (result != VK_SUCCESS)
1706 goto fail_vsc_data;
1707
1708 result = tu_bo_init_new(device, &cmd_buffer->vsc_data2, VSC_DATA2_SIZE(cmd_buffer->vsc_data2_pitch));
1709 if (result != VK_SUCCESS)
1710 goto fail_vsc_data2;
1711
1712 return VK_SUCCESS;
1713
1714 fail_vsc_data2:
1715 tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data);
1716 fail_vsc_data:
1717 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1718 return result;
1719 }
1720
1721 static void
1722 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1723 {
1724 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1725 tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data);
1726 tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data2);
1727
1728 list_del(&cmd_buffer->pool_link);
1729
1730 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1731 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1732
1733 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1734 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1735 tu_cs_finish(cmd_buffer->device, &cmd_buffer->sub_cs);
1736
1737 tu_bo_list_destroy(&cmd_buffer->bo_list);
1738 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1739 }
1740
1741 static VkResult
1742 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1743 {
1744 cmd_buffer->wait_for_idle = true;
1745
1746 cmd_buffer->record_result = VK_SUCCESS;
1747
1748 tu_bo_list_reset(&cmd_buffer->bo_list);
1749 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1750 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1751 tu_cs_reset(cmd_buffer->device, &cmd_buffer->sub_cs);
1752
1753 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1754 cmd_buffer->descriptors[i].dirty = 0;
1755 cmd_buffer->descriptors[i].valid = 0;
1756 cmd_buffer->descriptors[i].push_dirty = false;
1757 }
1758
1759 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1760
1761 return cmd_buffer->record_result;
1762 }
1763
1764 VkResult
1765 tu_AllocateCommandBuffers(VkDevice _device,
1766 const VkCommandBufferAllocateInfo *pAllocateInfo,
1767 VkCommandBuffer *pCommandBuffers)
1768 {
1769 TU_FROM_HANDLE(tu_device, device, _device);
1770 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1771
1772 VkResult result = VK_SUCCESS;
1773 uint32_t i;
1774
1775 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1776
1777 if (!list_is_empty(&pool->free_cmd_buffers)) {
1778 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1779 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1780
1781 list_del(&cmd_buffer->pool_link);
1782 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1783
1784 result = tu_reset_cmd_buffer(cmd_buffer);
1785 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1786 cmd_buffer->level = pAllocateInfo->level;
1787
1788 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1789 } else {
1790 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1791 &pCommandBuffers[i]);
1792 }
1793 if (result != VK_SUCCESS)
1794 break;
1795 }
1796
1797 if (result != VK_SUCCESS) {
1798 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1799 pCommandBuffers);
1800
1801 /* From the Vulkan 1.0.66 spec:
1802 *
1803 * "vkAllocateCommandBuffers can be used to create multiple
1804 * command buffers. If the creation of any of those command
1805 * buffers fails, the implementation must destroy all
1806 * successfully created command buffer objects from this
1807 * command, set all entries of the pCommandBuffers array to
1808 * NULL and return the error."
1809 */
1810 memset(pCommandBuffers, 0,
1811 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1812 }
1813
1814 return result;
1815 }
1816
1817 void
1818 tu_FreeCommandBuffers(VkDevice device,
1819 VkCommandPool commandPool,
1820 uint32_t commandBufferCount,
1821 const VkCommandBuffer *pCommandBuffers)
1822 {
1823 for (uint32_t i = 0; i < commandBufferCount; i++) {
1824 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1825
1826 if (cmd_buffer) {
1827 if (cmd_buffer->pool) {
1828 list_del(&cmd_buffer->pool_link);
1829 list_addtail(&cmd_buffer->pool_link,
1830 &cmd_buffer->pool->free_cmd_buffers);
1831 } else
1832 tu_cmd_buffer_destroy(cmd_buffer);
1833 }
1834 }
1835 }
1836
1837 VkResult
1838 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1839 VkCommandBufferResetFlags flags)
1840 {
1841 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1842 return tu_reset_cmd_buffer(cmd_buffer);
1843 }
1844
1845 VkResult
1846 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1847 const VkCommandBufferBeginInfo *pBeginInfo)
1848 {
1849 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1850 VkResult result = VK_SUCCESS;
1851
1852 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1853 /* If the command buffer has already been resetted with
1854 * vkResetCommandBuffer, no need to do it again.
1855 */
1856 result = tu_reset_cmd_buffer(cmd_buffer);
1857 if (result != VK_SUCCESS)
1858 return result;
1859 }
1860
1861 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1862 cmd_buffer->usage_flags = pBeginInfo->flags;
1863
1864 tu_cs_begin(&cmd_buffer->cs);
1865 tu_cs_begin(&cmd_buffer->draw_cs);
1866
1867 cmd_buffer->marker_seqno = 0;
1868 cmd_buffer->scratch_seqno = 0;
1869
1870 /* setup initial configuration into command buffer */
1871 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1872 switch (cmd_buffer->queue_family_index) {
1873 case TU_QUEUE_GENERAL:
1874 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1875 break;
1876 default:
1877 break;
1878 }
1879 } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
1880 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
1881 assert(pBeginInfo->pInheritanceInfo);
1882 cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1883 cmd_buffer->state.subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1884 }
1885
1886 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1887
1888 return VK_SUCCESS;
1889 }
1890
1891 void
1892 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1893 uint32_t firstBinding,
1894 uint32_t bindingCount,
1895 const VkBuffer *pBuffers,
1896 const VkDeviceSize *pOffsets)
1897 {
1898 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1899
1900 assert(firstBinding + bindingCount <= MAX_VBS);
1901
1902 for (uint32_t i = 0; i < bindingCount; i++) {
1903 cmd->state.vb.buffers[firstBinding + i] =
1904 tu_buffer_from_handle(pBuffers[i]);
1905 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1906 }
1907
1908 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1909 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1910 }
1911
1912 void
1913 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1914 VkBuffer buffer,
1915 VkDeviceSize offset,
1916 VkIndexType indexType)
1917 {
1918 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1919 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1920
1921 /* initialize/update the restart index */
1922 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1923 struct tu_cs *draw_cs = &cmd->draw_cs;
1924 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1925 if (result != VK_SUCCESS) {
1926 cmd->record_result = result;
1927 return;
1928 }
1929
1930 tu6_emit_restart_index(
1931 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1932
1933 tu_cs_sanity_check(draw_cs);
1934 }
1935
1936 /* track the BO */
1937 if (cmd->state.index_buffer != buf)
1938 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1939
1940 cmd->state.index_buffer = buf;
1941 cmd->state.index_offset = offset;
1942 cmd->state.index_type = indexType;
1943 }
1944
1945 void
1946 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1947 VkPipelineBindPoint pipelineBindPoint,
1948 VkPipelineLayout _layout,
1949 uint32_t firstSet,
1950 uint32_t descriptorSetCount,
1951 const VkDescriptorSet *pDescriptorSets,
1952 uint32_t dynamicOffsetCount,
1953 const uint32_t *pDynamicOffsets)
1954 {
1955 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1956 TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1957 unsigned dyn_idx = 0;
1958
1959 struct tu_descriptor_state *descriptors_state =
1960 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1961
1962 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1963 unsigned idx = i + firstSet;
1964 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1965
1966 descriptors_state->sets[idx] = set;
1967 descriptors_state->valid |= (1u << idx);
1968
1969 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1970 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1971 assert(dyn_idx < dynamicOffsetCount);
1972
1973 descriptors_state->dynamic_buffers[idx] =
1974 set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
1975 }
1976 }
1977
1978 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1979 }
1980
1981 void
1982 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1983 VkPipelineLayout layout,
1984 VkShaderStageFlags stageFlags,
1985 uint32_t offset,
1986 uint32_t size,
1987 const void *pValues)
1988 {
1989 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1990 memcpy((void*) cmd->push_constants + offset, pValues, size);
1991 cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
1992 }
1993
1994 VkResult
1995 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1996 {
1997 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1998
1999 if (cmd_buffer->scratch_seqno) {
2000 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
2001 MSM_SUBMIT_BO_WRITE);
2002 }
2003
2004 if (cmd_buffer->use_vsc_data) {
2005 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
2006 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2007 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
2008 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2009 }
2010
2011 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
2012 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
2013 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2014 }
2015
2016 for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
2017 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
2018 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2019 }
2020
2021 tu_cs_end(&cmd_buffer->cs);
2022 tu_cs_end(&cmd_buffer->draw_cs);
2023
2024 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
2025
2026 return cmd_buffer->record_result;
2027 }
2028
2029 void
2030 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
2031 VkPipelineBindPoint pipelineBindPoint,
2032 VkPipeline _pipeline)
2033 {
2034 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2035 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2036
2037 switch (pipelineBindPoint) {
2038 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2039 cmd->state.pipeline = pipeline;
2040 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
2041 break;
2042 case VK_PIPELINE_BIND_POINT_COMPUTE:
2043 cmd->state.compute_pipeline = pipeline;
2044 cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2045 break;
2046 default:
2047 unreachable("unrecognized pipeline bind point");
2048 break;
2049 }
2050
2051 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2052 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2053 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2054 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2055 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2056 }
2057 }
2058
2059 void
2060 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2061 uint32_t firstViewport,
2062 uint32_t viewportCount,
2063 const VkViewport *pViewports)
2064 {
2065 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2066 struct tu_cs *draw_cs = &cmd->draw_cs;
2067
2068 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
2069 if (result != VK_SUCCESS) {
2070 cmd->record_result = result;
2071 return;
2072 }
2073
2074 assert(firstViewport == 0 && viewportCount == 1);
2075 tu6_emit_viewport(draw_cs, pViewports);
2076
2077 tu_cs_sanity_check(draw_cs);
2078 }
2079
2080 void
2081 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2082 uint32_t firstScissor,
2083 uint32_t scissorCount,
2084 const VkRect2D *pScissors)
2085 {
2086 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2087 struct tu_cs *draw_cs = &cmd->draw_cs;
2088
2089 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
2090 if (result != VK_SUCCESS) {
2091 cmd->record_result = result;
2092 return;
2093 }
2094
2095 assert(firstScissor == 0 && scissorCount == 1);
2096 tu6_emit_scissor(draw_cs, pScissors);
2097
2098 tu_cs_sanity_check(draw_cs);
2099 }
2100
2101 void
2102 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2103 {
2104 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2105
2106 cmd->state.dynamic.line_width = lineWidth;
2107
2108 /* line width depends on VkPipelineRasterizationStateCreateInfo */
2109 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2110 }
2111
2112 void
2113 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2114 float depthBiasConstantFactor,
2115 float depthBiasClamp,
2116 float depthBiasSlopeFactor)
2117 {
2118 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2119 struct tu_cs *draw_cs = &cmd->draw_cs;
2120
2121 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
2122 if (result != VK_SUCCESS) {
2123 cmd->record_result = result;
2124 return;
2125 }
2126
2127 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2128 depthBiasSlopeFactor);
2129
2130 tu_cs_sanity_check(draw_cs);
2131 }
2132
2133 void
2134 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2135 const float blendConstants[4])
2136 {
2137 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2138 struct tu_cs *draw_cs = &cmd->draw_cs;
2139
2140 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
2141 if (result != VK_SUCCESS) {
2142 cmd->record_result = result;
2143 return;
2144 }
2145
2146 tu6_emit_blend_constants(draw_cs, blendConstants);
2147
2148 tu_cs_sanity_check(draw_cs);
2149 }
2150
2151 void
2152 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2153 float minDepthBounds,
2154 float maxDepthBounds)
2155 {
2156 }
2157
2158 void
2159 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2160 VkStencilFaceFlags faceMask,
2161 uint32_t compareMask)
2162 {
2163 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2164
2165 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2166 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2167 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2168 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2169
2170 /* the front/back compare masks must be updated together */
2171 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2172 }
2173
2174 void
2175 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2176 VkStencilFaceFlags faceMask,
2177 uint32_t writeMask)
2178 {
2179 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2180
2181 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2182 cmd->state.dynamic.stencil_write_mask.front = writeMask;
2183 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2184 cmd->state.dynamic.stencil_write_mask.back = writeMask;
2185
2186 /* the front/back write masks must be updated together */
2187 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2188 }
2189
2190 void
2191 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2192 VkStencilFaceFlags faceMask,
2193 uint32_t reference)
2194 {
2195 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2196
2197 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2198 cmd->state.dynamic.stencil_reference.front = reference;
2199 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2200 cmd->state.dynamic.stencil_reference.back = reference;
2201
2202 /* the front/back references must be updated together */
2203 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2204 }
2205
2206 void
2207 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2208 uint32_t commandBufferCount,
2209 const VkCommandBuffer *pCmdBuffers)
2210 {
2211 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2212 VkResult result;
2213
2214 assert(commandBufferCount > 0);
2215
2216 for (uint32_t i = 0; i < commandBufferCount; i++) {
2217 TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
2218
2219 result = tu_bo_list_merge(&cmd->bo_list, &secondary->bo_list);
2220 if (result != VK_SUCCESS) {
2221 cmd->record_result = result;
2222 break;
2223 }
2224
2225 result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
2226 if (result != VK_SUCCESS) {
2227 cmd->record_result = result;
2228 break;
2229 }
2230 }
2231 cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
2232 }
2233
2234 VkResult
2235 tu_CreateCommandPool(VkDevice _device,
2236 const VkCommandPoolCreateInfo *pCreateInfo,
2237 const VkAllocationCallbacks *pAllocator,
2238 VkCommandPool *pCmdPool)
2239 {
2240 TU_FROM_HANDLE(tu_device, device, _device);
2241 struct tu_cmd_pool *pool;
2242
2243 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2244 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2245 if (pool == NULL)
2246 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2247
2248 if (pAllocator)
2249 pool->alloc = *pAllocator;
2250 else
2251 pool->alloc = device->alloc;
2252
2253 list_inithead(&pool->cmd_buffers);
2254 list_inithead(&pool->free_cmd_buffers);
2255
2256 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2257
2258 *pCmdPool = tu_cmd_pool_to_handle(pool);
2259
2260 return VK_SUCCESS;
2261 }
2262
2263 void
2264 tu_DestroyCommandPool(VkDevice _device,
2265 VkCommandPool commandPool,
2266 const VkAllocationCallbacks *pAllocator)
2267 {
2268 TU_FROM_HANDLE(tu_device, device, _device);
2269 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2270
2271 if (!pool)
2272 return;
2273
2274 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2275 &pool->cmd_buffers, pool_link)
2276 {
2277 tu_cmd_buffer_destroy(cmd_buffer);
2278 }
2279
2280 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2281 &pool->free_cmd_buffers, pool_link)
2282 {
2283 tu_cmd_buffer_destroy(cmd_buffer);
2284 }
2285
2286 vk_free2(&device->alloc, pAllocator, pool);
2287 }
2288
2289 VkResult
2290 tu_ResetCommandPool(VkDevice device,
2291 VkCommandPool commandPool,
2292 VkCommandPoolResetFlags flags)
2293 {
2294 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2295 VkResult result;
2296
2297 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2298 pool_link)
2299 {
2300 result = tu_reset_cmd_buffer(cmd_buffer);
2301 if (result != VK_SUCCESS)
2302 return result;
2303 }
2304
2305 return VK_SUCCESS;
2306 }
2307
2308 void
2309 tu_TrimCommandPool(VkDevice device,
2310 VkCommandPool commandPool,
2311 VkCommandPoolTrimFlags flags)
2312 {
2313 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2314
2315 if (!pool)
2316 return;
2317
2318 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2319 &pool->free_cmd_buffers, pool_link)
2320 {
2321 tu_cmd_buffer_destroy(cmd_buffer);
2322 }
2323 }
2324
2325 void
2326 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2327 const VkRenderPassBeginInfo *pRenderPassBegin,
2328 VkSubpassContents contents)
2329 {
2330 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2331 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2332 TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2333
2334 cmd->state.pass = pass;
2335 cmd->state.subpass = pass->subpasses;
2336 cmd->state.framebuffer = fb;
2337
2338 tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2339 tu_cmd_prepare_tile_load_ib(cmd, pRenderPassBegin);
2340 tu_cmd_prepare_tile_store_ib(cmd);
2341
2342 /* note: use_hw_binning only checks tiling config */
2343 if (use_hw_binning(cmd))
2344 cmd->use_vsc_data = true;
2345
2346 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2347 const struct tu_image_view *iview = fb->attachments[i].attachment;
2348 tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2349 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2350 }
2351 }
2352
2353 void
2354 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
2355 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2356 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2357 {
2358 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2359 pSubpassBeginInfo->contents);
2360 }
2361
2362 void
2363 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2364 {
2365 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2366 const struct tu_render_pass *pass = cmd->state.pass;
2367 struct tu_cs *cs = &cmd->draw_cs;
2368
2369 VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
2370 if (result != VK_SUCCESS) {
2371 cmd->record_result = result;
2372 return;
2373 }
2374
2375 const struct tu_subpass *subpass = cmd->state.subpass++;
2376 /* TODO:
2377 * if msaa samples change between subpasses,
2378 * attachment store is broken for some attachments
2379 */
2380 if (subpass->resolve_attachments) {
2381 tu6_emit_blit_scissor(cmd, cs, true);
2382 for (unsigned i = 0; i < subpass->color_count; i++) {
2383 uint32_t a = subpass->resolve_attachments[i].attachment;
2384 if (a != VK_ATTACHMENT_UNUSED) {
2385 tu6_emit_store_attachment(cmd, cs, a,
2386 subpass->color_attachments[i].attachment);
2387 }
2388 }
2389 }
2390
2391 /* invalidate because reading input attachments will cache GMEM and
2392 * the cache isn''t updated when GMEM is written
2393 * TODO: is there a no-cache bit for textures?
2394 */
2395 if (cmd->state.subpass->input_count)
2396 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2397
2398 /* emit mrt/zs/msaa state for the subpass that is starting */
2399 tu6_emit_zs(cmd, cmd->state.subpass, cs);
2400 tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2401 tu6_emit_msaa(cmd, cmd->state.subpass, cs);
2402
2403 /* TODO:
2404 * since we don't know how to do GMEM->GMEM resolve,
2405 * resolve attachments are resolved to memory then loaded to GMEM again if needed
2406 */
2407 if (subpass->resolve_attachments) {
2408 for (unsigned i = 0; i < subpass->color_count; i++) {
2409 uint32_t a = subpass->resolve_attachments[i].attachment;
2410 const struct tu_image_view *iview =
2411 cmd->state.framebuffer->attachments[a].attachment;
2412 if (a != VK_ATTACHMENT_UNUSED && pass->attachments[a].gmem_offset >= 0) {
2413 tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
2414 tu6_emit_blit_info(cmd, cs, iview, pass->attachments[a].gmem_offset, false);
2415 tu6_emit_blit(cmd, cs);
2416 }
2417 }
2418 }
2419 }
2420
2421 void
2422 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
2423 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2424 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2425 {
2426 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2427 }
2428
2429 struct tu_draw_info
2430 {
2431 /**
2432 * Number of vertices.
2433 */
2434 uint32_t count;
2435
2436 /**
2437 * Index of the first vertex.
2438 */
2439 int32_t vertex_offset;
2440
2441 /**
2442 * First instance id.
2443 */
2444 uint32_t first_instance;
2445
2446 /**
2447 * Number of instances.
2448 */
2449 uint32_t instance_count;
2450
2451 /**
2452 * First index (indexed draws only).
2453 */
2454 uint32_t first_index;
2455
2456 /**
2457 * Whether it's an indexed draw.
2458 */
2459 bool indexed;
2460
2461 /**
2462 * Indirect draw parameters resource.
2463 */
2464 struct tu_buffer *indirect;
2465 uint64_t indirect_offset;
2466 uint32_t stride;
2467
2468 /**
2469 * Draw count parameters resource.
2470 */
2471 struct tu_buffer *count_buffer;
2472 uint64_t count_buffer_offset;
2473 };
2474
2475 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2476 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2477
2478 enum tu_draw_state_group_id
2479 {
2480 TU_DRAW_STATE_PROGRAM,
2481 TU_DRAW_STATE_PROGRAM_BINNING,
2482 TU_DRAW_STATE_VI,
2483 TU_DRAW_STATE_VI_BINNING,
2484 TU_DRAW_STATE_VP,
2485 TU_DRAW_STATE_RAST,
2486 TU_DRAW_STATE_DS,
2487 TU_DRAW_STATE_BLEND,
2488 TU_DRAW_STATE_VS_CONST,
2489 TU_DRAW_STATE_FS_CONST,
2490 TU_DRAW_STATE_VS_TEX,
2491 TU_DRAW_STATE_FS_TEX,
2492 TU_DRAW_STATE_FS_IBO,
2493 TU_DRAW_STATE_VS_PARAMS,
2494
2495 TU_DRAW_STATE_COUNT,
2496 };
2497
2498 struct tu_draw_state_group
2499 {
2500 enum tu_draw_state_group_id id;
2501 uint32_t enable_mask;
2502 struct tu_cs_entry ib;
2503 };
2504
2505 const static struct tu_sampler*
2506 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2507 const struct tu_descriptor_map *map, unsigned i,
2508 unsigned array_index)
2509 {
2510 assert(descriptors_state->valid & (1 << map->set[i]));
2511
2512 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2513 assert(map->binding[i] < set->layout->binding_count);
2514
2515 const struct tu_descriptor_set_binding_layout *layout =
2516 &set->layout->binding[map->binding[i]];
2517
2518 if (layout->immutable_samplers_offset) {
2519 const struct tu_sampler *immutable_samplers =
2520 tu_immutable_samplers(set->layout, layout);
2521
2522 return &immutable_samplers[array_index];
2523 }
2524
2525 switch (layout->type) {
2526 case VK_DESCRIPTOR_TYPE_SAMPLER:
2527 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2528 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2529 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS +
2530 array_index *
2531 (A6XX_TEX_CONST_DWORDS +
2532 sizeof(struct tu_sampler) / 4)];
2533 default:
2534 unreachable("unimplemented descriptor type");
2535 break;
2536 }
2537 }
2538
2539 static void
2540 write_tex_const(struct tu_cmd_buffer *cmd,
2541 uint32_t *dst,
2542 struct tu_descriptor_state *descriptors_state,
2543 const struct tu_descriptor_map *map,
2544 unsigned i, unsigned array_index)
2545 {
2546 assert(descriptors_state->valid & (1 << map->set[i]));
2547
2548 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2549 assert(map->binding[i] < set->layout->binding_count);
2550
2551 const struct tu_descriptor_set_binding_layout *layout =
2552 &set->layout->binding[map->binding[i]];
2553
2554 switch (layout->type) {
2555 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2556 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2557 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2558 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2559 memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2560 array_index * A6XX_TEX_CONST_DWORDS],
2561 A6XX_TEX_CONST_DWORDS * 4);
2562 break;
2563 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2564 memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2565 array_index *
2566 (A6XX_TEX_CONST_DWORDS +
2567 sizeof(struct tu_sampler) / 4)],
2568 A6XX_TEX_CONST_DWORDS * 4);
2569 break;
2570 default:
2571 unreachable("unimplemented descriptor type");
2572 break;
2573 }
2574
2575 if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
2576 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2577 uint32_t a = cmd->state.subpass->input_attachments[map->value[i] +
2578 array_index].attachment;
2579 const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
2580
2581 assert(att->gmem_offset >= 0);
2582
2583 dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2584 dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2585 dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2586 dst[2] |=
2587 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2588 A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
2589 dst[3] = 0;
2590 dst[4] = 0x100000 + att->gmem_offset;
2591 dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2592 for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2593 dst[i] = 0;
2594
2595 if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
2596 tu_finishme("patch input attachment pitch for secondary cmd buffer");
2597 }
2598 }
2599
2600 static uint64_t
2601 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2602 const struct tu_descriptor_map *map,
2603 unsigned i, unsigned array_index)
2604 {
2605 assert(descriptors_state->valid & (1 << map->set[i]));
2606
2607 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2608 assert(map->binding[i] < set->layout->binding_count);
2609
2610 const struct tu_descriptor_set_binding_layout *layout =
2611 &set->layout->binding[map->binding[i]];
2612
2613 switch (layout->type) {
2614 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2615 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2616 return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset +
2617 array_index];
2618 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2619 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2620 return (uint64_t) set->mapped_ptr[layout->offset / 4 + array_index * 2 + 1] << 32 |
2621 set->mapped_ptr[layout->offset / 4 + array_index * 2];
2622 default:
2623 unreachable("unimplemented descriptor type");
2624 break;
2625 }
2626 }
2627
2628 static inline uint32_t
2629 tu6_stage2opcode(gl_shader_stage type)
2630 {
2631 switch (type) {
2632 case MESA_SHADER_VERTEX:
2633 case MESA_SHADER_TESS_CTRL:
2634 case MESA_SHADER_TESS_EVAL:
2635 case MESA_SHADER_GEOMETRY:
2636 return CP_LOAD_STATE6_GEOM;
2637 case MESA_SHADER_FRAGMENT:
2638 case MESA_SHADER_COMPUTE:
2639 case MESA_SHADER_KERNEL:
2640 return CP_LOAD_STATE6_FRAG;
2641 default:
2642 unreachable("bad shader type");
2643 }
2644 }
2645
2646 static inline enum a6xx_state_block
2647 tu6_stage2shadersb(gl_shader_stage type)
2648 {
2649 switch (type) {
2650 case MESA_SHADER_VERTEX:
2651 return SB6_VS_SHADER;
2652 case MESA_SHADER_FRAGMENT:
2653 return SB6_FS_SHADER;
2654 case MESA_SHADER_COMPUTE:
2655 case MESA_SHADER_KERNEL:
2656 return SB6_CS_SHADER;
2657 default:
2658 unreachable("bad shader type");
2659 return ~0;
2660 }
2661 }
2662
2663 static void
2664 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2665 struct tu_descriptor_state *descriptors_state,
2666 gl_shader_stage type,
2667 uint32_t *push_constants)
2668 {
2669 const struct tu_program_descriptor_linkage *link =
2670 &pipeline->program.link[type];
2671 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2672
2673 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2674 if (state->range[i].start < state->range[i].end) {
2675 uint32_t size = state->range[i].end - state->range[i].start;
2676 uint32_t offset = state->range[i].start;
2677
2678 /* and even if the start of the const buffer is before
2679 * first_immediate, the end may not be:
2680 */
2681 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2682
2683 if (size == 0)
2684 continue;
2685
2686 /* things should be aligned to vec4: */
2687 debug_assert((state->range[i].offset % 16) == 0);
2688 debug_assert((size % 16) == 0);
2689 debug_assert((offset % 16) == 0);
2690
2691 if (i == 0) {
2692 /* push constants */
2693 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2694 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2695 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2696 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2697 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2698 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2699 tu_cs_emit(cs, 0);
2700 tu_cs_emit(cs, 0);
2701 for (unsigned i = 0; i < size / 4; i++)
2702 tu_cs_emit(cs, push_constants[i + offset / 4]);
2703 continue;
2704 }
2705
2706 /* Look through the UBO map to find our UBO index, and get the VA for
2707 * that UBO.
2708 */
2709 uint64_t va = 0;
2710 uint32_t ubo_idx = i - 1;
2711 uint32_t ubo_map_base = 0;
2712 for (int j = 0; j < link->ubo_map.num; j++) {
2713 if (ubo_idx >= ubo_map_base &&
2714 ubo_idx < ubo_map_base + link->ubo_map.array_size[j]) {
2715 va = buffer_ptr(descriptors_state, &link->ubo_map, j,
2716 ubo_idx - ubo_map_base);
2717 break;
2718 }
2719 ubo_map_base += link->ubo_map.array_size[j];
2720 }
2721 assert(va);
2722
2723 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2724 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2725 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2726 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2727 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2728 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2729 tu_cs_emit_qw(cs, va + offset);
2730 }
2731 }
2732 }
2733
2734 static void
2735 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2736 struct tu_descriptor_state *descriptors_state,
2737 gl_shader_stage type)
2738 {
2739 const struct tu_program_descriptor_linkage *link =
2740 &pipeline->program.link[type];
2741
2742 uint32_t num = MIN2(link->ubo_map.num_desc, link->const_state.num_ubos);
2743 uint32_t anum = align(num, 2);
2744
2745 if (!num)
2746 return;
2747
2748 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2749 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2750 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2751 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2752 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2753 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2754 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2755 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2756
2757 unsigned emitted = 0;
2758 for (unsigned i = 0; emitted < num && i < link->ubo_map.num; i++) {
2759 for (unsigned j = 0; emitted < num && j < link->ubo_map.array_size[i]; j++) {
2760 tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i, j));
2761 emitted++;
2762 }
2763 }
2764
2765 for (; emitted < anum; emitted++) {
2766 tu_cs_emit(cs, 0xffffffff);
2767 tu_cs_emit(cs, 0xffffffff);
2768 }
2769 }
2770
2771 static struct tu_cs_entry
2772 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2773 const struct tu_pipeline *pipeline,
2774 struct tu_descriptor_state *descriptors_state,
2775 gl_shader_stage type)
2776 {
2777 struct tu_cs cs;
2778 tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
2779
2780 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2781 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2782
2783 return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2784 }
2785
2786 static VkResult
2787 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
2788 const struct tu_draw_info *draw,
2789 struct tu_cs_entry *entry)
2790 {
2791 /* TODO: fill out more than just base instance */
2792 const struct tu_program_descriptor_linkage *link =
2793 &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
2794 const struct ir3_const_state *const_state = &link->const_state;
2795 struct tu_cs cs;
2796
2797 if (const_state->offsets.driver_param >= link->constlen) {
2798 *entry = (struct tu_cs_entry) {};
2799 return VK_SUCCESS;
2800 }
2801
2802 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs, 8, &cs);
2803 if (result != VK_SUCCESS)
2804 return result;
2805
2806 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
2807 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
2808 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2809 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2810 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
2811 CP_LOAD_STATE6_0_NUM_UNIT(1));
2812 tu_cs_emit(&cs, 0);
2813 tu_cs_emit(&cs, 0);
2814
2815 STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
2816
2817 tu_cs_emit(&cs, 0);
2818 tu_cs_emit(&cs, 0);
2819 tu_cs_emit(&cs, draw->first_instance);
2820 tu_cs_emit(&cs, 0);
2821
2822 *entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2823 return VK_SUCCESS;
2824 }
2825
2826 static VkResult
2827 tu6_emit_textures(struct tu_cmd_buffer *cmd,
2828 const struct tu_pipeline *pipeline,
2829 struct tu_descriptor_state *descriptors_state,
2830 gl_shader_stage type,
2831 struct tu_cs_entry *entry,
2832 bool *needs_border)
2833 {
2834 struct tu_device *device = cmd->device;
2835 struct tu_cs *draw_state = &cmd->sub_cs;
2836 const struct tu_program_descriptor_linkage *link =
2837 &pipeline->program.link[type];
2838 VkResult result;
2839
2840 if (link->texture_map.num_desc == 0 && link->sampler_map.num_desc == 0) {
2841 *entry = (struct tu_cs_entry) {};
2842 return VK_SUCCESS;
2843 }
2844
2845 /* allocate and fill texture state */
2846 struct ts_cs_memory tex_const;
2847 result = tu_cs_alloc(device, draw_state, link->texture_map.num_desc,
2848 A6XX_TEX_CONST_DWORDS, &tex_const);
2849 if (result != VK_SUCCESS)
2850 return result;
2851
2852 int tex_index = 0;
2853 for (unsigned i = 0; i < link->texture_map.num; i++) {
2854 for (int j = 0; j < link->texture_map.array_size[i]; j++) {
2855 write_tex_const(cmd,
2856 &tex_const.map[A6XX_TEX_CONST_DWORDS * tex_index++],
2857 descriptors_state, &link->texture_map, i, j);
2858 }
2859 }
2860
2861 /* allocate and fill sampler state */
2862 struct ts_cs_memory tex_samp = { 0 };
2863 if (link->sampler_map.num_desc) {
2864 result = tu_cs_alloc(device, draw_state, link->sampler_map.num_desc,
2865 A6XX_TEX_SAMP_DWORDS, &tex_samp);
2866 if (result != VK_SUCCESS)
2867 return result;
2868
2869 int sampler_index = 0;
2870 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2871 for (int j = 0; j < link->sampler_map.array_size[i]; j++) {
2872 const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
2873 &link->sampler_map,
2874 i, j);
2875 memcpy(&tex_samp.map[A6XX_TEX_SAMP_DWORDS * sampler_index++],
2876 sampler->state, sizeof(sampler->state));
2877 *needs_border |= sampler->needs_border;
2878 }
2879 }
2880 }
2881
2882 unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
2883 enum a6xx_state_block sb;
2884
2885 switch (type) {
2886 case MESA_SHADER_VERTEX:
2887 sb = SB6_VS_TEX;
2888 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2889 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2890 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2891 break;
2892 case MESA_SHADER_FRAGMENT:
2893 sb = SB6_FS_TEX;
2894 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2895 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2896 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2897 break;
2898 case MESA_SHADER_COMPUTE:
2899 sb = SB6_CS_TEX;
2900 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2901 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2902 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2903 break;
2904 default:
2905 unreachable("bad state block");
2906 }
2907
2908 struct tu_cs cs;
2909 result = tu_cs_begin_sub_stream(device, draw_state, 16, &cs);
2910 if (result != VK_SUCCESS)
2911 return result;
2912
2913 if (link->sampler_map.num_desc) {
2914 /* output sampler state: */
2915 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2916 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2917 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2918 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2919 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2920 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num_desc));
2921 tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2922
2923 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2924 tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2925 }
2926
2927 /* emit texture state: */
2928 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2929 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2930 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2931 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2932 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2933 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num_desc));
2934 tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2935
2936 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2937 tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2938
2939 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2940 tu_cs_emit(&cs, link->texture_map.num_desc);
2941
2942 *entry = tu_cs_end_sub_stream(draw_state, &cs);
2943 return VK_SUCCESS;
2944 }
2945
2946 static VkResult
2947 tu6_emit_ibo(struct tu_cmd_buffer *cmd,
2948 const struct tu_pipeline *pipeline,
2949 struct tu_descriptor_state *descriptors_state,
2950 gl_shader_stage type,
2951 struct tu_cs_entry *entry)
2952 {
2953 struct tu_device *device = cmd->device;
2954 struct tu_cs *draw_state = &cmd->sub_cs;
2955 const struct tu_program_descriptor_linkage *link =
2956 &pipeline->program.link[type];
2957 VkResult result;
2958
2959 if (link->image_mapping.num_ibo == 0) {
2960 *entry = (struct tu_cs_entry) {};
2961 return VK_SUCCESS;
2962 }
2963
2964 struct ts_cs_memory ibo_const;
2965 result = tu_cs_alloc(device, draw_state, link->image_mapping.num_ibo,
2966 A6XX_TEX_CONST_DWORDS, &ibo_const);
2967 if (result != VK_SUCCESS)
2968 return result;
2969
2970 for (unsigned i = 0; i < link->image_mapping.num_ibo; i++) {
2971 unsigned idx = link->image_mapping.ibo_to_image[i];
2972 uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * i];
2973
2974 if (idx & IBO_SSBO) {
2975 idx &= ~IBO_SSBO;
2976
2977 uint64_t va = buffer_ptr(descriptors_state, &link->ssbo_map, idx,
2978 0 /* XXX */);
2979 /* We don't expose robustBufferAccess, so leave the size unlimited. */
2980 uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
2981
2982 dst[0] = A6XX_IBO_0_FMT(TFMT6_32_UINT);
2983 dst[1] = A6XX_IBO_1_WIDTH(sz & MASK(15)) |
2984 A6XX_IBO_1_HEIGHT(sz >> 15);
2985 dst[2] = A6XX_IBO_2_UNK4 |
2986 A6XX_IBO_2_UNK31 |
2987 A6XX_IBO_2_TYPE(A6XX_TEX_1D);
2988 dst[3] = 0;
2989 dst[4] = va;
2990 dst[5] = va >> 32;
2991 for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2992 dst[i] = 0;
2993 } else {
2994 tu_finishme("Emit images");
2995 }
2996 }
2997
2998 struct tu_cs cs;
2999 result = tu_cs_begin_sub_stream(device, draw_state, 7, &cs);
3000 if (result != VK_SUCCESS)
3001 return result;
3002
3003 uint32_t opcode, ibo_addr_reg;
3004 enum a6xx_state_block sb;
3005 enum a6xx_state_type st;
3006
3007 switch (type) {
3008 case MESA_SHADER_FRAGMENT:
3009 opcode = CP_LOAD_STATE6;
3010 st = ST6_SHADER;
3011 sb = SB6_IBO;
3012 ibo_addr_reg = REG_A6XX_SP_IBO_LO;
3013 break;
3014 case MESA_SHADER_COMPUTE:
3015 opcode = CP_LOAD_STATE6_FRAG;
3016 st = ST6_IBO;
3017 sb = SB6_CS_SHADER;
3018 ibo_addr_reg = REG_A6XX_SP_CS_IBO_LO;
3019 break;
3020 default:
3021 unreachable("unsupported stage for ibos");
3022 }
3023
3024 /* emit texture state: */
3025 tu_cs_emit_pkt7(&cs, opcode, 3);
3026 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3027 CP_LOAD_STATE6_0_STATE_TYPE(st) |
3028 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3029 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3030 CP_LOAD_STATE6_0_NUM_UNIT(link->image_mapping.num_ibo));
3031 tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3032
3033 tu_cs_emit_pkt4(&cs, ibo_addr_reg, 2);
3034 tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3035
3036 *entry = tu_cs_end_sub_stream(draw_state, &cs);
3037 return VK_SUCCESS;
3038 }
3039
3040 struct PACKED bcolor_entry {
3041 uint32_t fp32[4];
3042 uint16_t ui16[4];
3043 int16_t si16[4];
3044 uint16_t fp16[4];
3045 uint16_t rgb565;
3046 uint16_t rgb5a1;
3047 uint16_t rgba4;
3048 uint8_t __pad0[2];
3049 uint8_t ui8[4];
3050 int8_t si8[4];
3051 uint32_t rgb10a2;
3052 uint32_t z24; /* also s8? */
3053 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
3054 uint8_t __pad1[56];
3055 } border_color[] = {
3056 [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = {},
3057 [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK] = {},
3058 [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = {
3059 .fp32[3] = 0x3f800000,
3060 .ui16[3] = 0xffff,
3061 .si16[3] = 0x7fff,
3062 .fp16[3] = 0x3c00,
3063 .rgb5a1 = 0x8000,
3064 .rgba4 = 0xf000,
3065 .ui8[3] = 0xff,
3066 .si8[3] = 0x7f,
3067 .rgb10a2 = 0xc0000000,
3068 .srgb[3] = 0x3c00,
3069 },
3070 [VK_BORDER_COLOR_INT_OPAQUE_BLACK] = {
3071 .fp32[3] = 1,
3072 .fp16[3] = 1,
3073 },
3074 [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] = {
3075 .fp32[0 ... 3] = 0x3f800000,
3076 .ui16[0 ... 3] = 0xffff,
3077 .si16[0 ... 3] = 0x7fff,
3078 .fp16[0 ... 3] = 0x3c00,
3079 .rgb565 = 0xffff,
3080 .rgb5a1 = 0xffff,
3081 .rgba4 = 0xffff,
3082 .ui8[0 ... 3] = 0xff,
3083 .si8[0 ... 3] = 0x7f,
3084 .rgb10a2 = 0xffffffff,
3085 .z24 = 0xffffff,
3086 .srgb[0 ... 3] = 0x3c00,
3087 },
3088 [VK_BORDER_COLOR_INT_OPAQUE_WHITE] = {
3089 .fp32[0 ... 3] = 1,
3090 .fp16[0 ... 3] = 1,
3091 },
3092 };
3093
3094 static VkResult
3095 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
3096 struct tu_cs *cs)
3097 {
3098 STATIC_ASSERT(sizeof(struct bcolor_entry) == 128);
3099
3100 const struct tu_pipeline *pipeline = cmd->state.pipeline;
3101 struct tu_descriptor_state *descriptors_state =
3102 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3103 const struct tu_descriptor_map *vs_sampler =
3104 &pipeline->program.link[MESA_SHADER_VERTEX].sampler_map;
3105 const struct tu_descriptor_map *fs_sampler =
3106 &pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map;
3107 struct ts_cs_memory ptr;
3108
3109 VkResult result = tu_cs_alloc(cmd->device, &cmd->sub_cs,
3110 vs_sampler->num_desc + fs_sampler->num_desc,
3111 128 / 4,
3112 &ptr);
3113 if (result != VK_SUCCESS)
3114 return result;
3115
3116 for (unsigned i = 0; i < vs_sampler->num; i++) {
3117 for (unsigned j = 0; j < vs_sampler->array_size[i]; j++) {
3118 const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3119 vs_sampler, i, j);
3120 memcpy(ptr.map, &border_color[sampler->border], 128);
3121 ptr.map += 128 / 4;
3122 }
3123 }
3124
3125 for (unsigned i = 0; i < fs_sampler->num; i++) {
3126 for (unsigned j = 0; j < fs_sampler->array_size[i]; j++) {
3127 const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3128 fs_sampler, i, j);
3129 memcpy(ptr.map, &border_color[sampler->border], 128);
3130 ptr.map += 128 / 4;
3131 }
3132 }
3133
3134 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
3135 tu_cs_emit_qw(cs, ptr.iova);
3136 return VK_SUCCESS;
3137 }
3138
3139 static VkResult
3140 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
3141 struct tu_cs *cs,
3142 const struct tu_draw_info *draw)
3143 {
3144 const struct tu_pipeline *pipeline = cmd->state.pipeline;
3145 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
3146 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
3147 uint32_t draw_state_group_count = 0;
3148
3149 struct tu_descriptor_state *descriptors_state =
3150 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3151
3152 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3153 if (result != VK_SUCCESS)
3154 return result;
3155
3156 /* TODO lrz */
3157
3158 uint32_t pc_primitive_cntl = 0;
3159 if (pipeline->ia.primitive_restart && draw->indexed)
3160 pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
3161
3162 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
3163 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
3164 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
3165
3166 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
3167 tu_cs_emit(cs, pc_primitive_cntl);
3168
3169 if (cmd->state.dirty &
3170 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
3171 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
3172 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
3173 dynamic->line_width);
3174 }
3175
3176 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
3177 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
3178 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
3179 dynamic->stencil_compare_mask.back);
3180 }
3181
3182 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
3183 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
3184 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
3185 dynamic->stencil_write_mask.back);
3186 }
3187
3188 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
3189 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
3190 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
3191 dynamic->stencil_reference.back);
3192 }
3193
3194 if (cmd->state.dirty &
3195 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
3196 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
3197 const uint32_t binding = pipeline->vi.bindings[i];
3198 const uint32_t stride = pipeline->vi.strides[i];
3199 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
3200 const VkDeviceSize offset = buf->bo_offset +
3201 cmd->state.vb.offsets[binding] +
3202 pipeline->vi.offsets[i];
3203 const VkDeviceSize size =
3204 offset < buf->bo->size ? buf->bo->size - offset : 0;
3205
3206 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
3207 tu_cs_emit_qw(cs, buf->bo->iova + offset);
3208 tu_cs_emit(cs, size);
3209 tu_cs_emit(cs, stride);
3210 }
3211 }
3212
3213 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
3214 draw_state_groups[draw_state_group_count++] =
3215 (struct tu_draw_state_group) {
3216 .id = TU_DRAW_STATE_PROGRAM,
3217 .enable_mask = ENABLE_DRAW,
3218 .ib = pipeline->program.state_ib,
3219 };
3220 draw_state_groups[draw_state_group_count++] =
3221 (struct tu_draw_state_group) {
3222 .id = TU_DRAW_STATE_PROGRAM_BINNING,
3223 .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3224 .ib = pipeline->program.binning_state_ib,
3225 };
3226 draw_state_groups[draw_state_group_count++] =
3227 (struct tu_draw_state_group) {
3228 .id = TU_DRAW_STATE_VI,
3229 .enable_mask = ENABLE_DRAW,
3230 .ib = pipeline->vi.state_ib,
3231 };
3232 draw_state_groups[draw_state_group_count++] =
3233 (struct tu_draw_state_group) {
3234 .id = TU_DRAW_STATE_VI_BINNING,
3235 .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3236 .ib = pipeline->vi.binning_state_ib,
3237 };
3238 draw_state_groups[draw_state_group_count++] =
3239 (struct tu_draw_state_group) {
3240 .id = TU_DRAW_STATE_VP,
3241 .enable_mask = ENABLE_ALL,
3242 .ib = pipeline->vp.state_ib,
3243 };
3244 draw_state_groups[draw_state_group_count++] =
3245 (struct tu_draw_state_group) {
3246 .id = TU_DRAW_STATE_RAST,
3247 .enable_mask = ENABLE_ALL,
3248 .ib = pipeline->rast.state_ib,
3249 };
3250 draw_state_groups[draw_state_group_count++] =
3251 (struct tu_draw_state_group) {
3252 .id = TU_DRAW_STATE_DS,
3253 .enable_mask = ENABLE_ALL,
3254 .ib = pipeline->ds.state_ib,
3255 };
3256 draw_state_groups[draw_state_group_count++] =
3257 (struct tu_draw_state_group) {
3258 .id = TU_DRAW_STATE_BLEND,
3259 .enable_mask = ENABLE_ALL,
3260 .ib = pipeline->blend.state_ib,
3261 };
3262 }
3263
3264 if (cmd->state.dirty &
3265 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
3266 draw_state_groups[draw_state_group_count++] =
3267 (struct tu_draw_state_group) {
3268 .id = TU_DRAW_STATE_VS_CONST,
3269 .enable_mask = ENABLE_ALL,
3270 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
3271 };
3272 draw_state_groups[draw_state_group_count++] =
3273 (struct tu_draw_state_group) {
3274 .id = TU_DRAW_STATE_FS_CONST,
3275 .enable_mask = ENABLE_DRAW,
3276 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
3277 };
3278 }
3279
3280 if (cmd->state.dirty &
3281 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
3282 bool needs_border = false;
3283 struct tu_cs_entry vs_tex, fs_tex, fs_ibo;
3284
3285 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3286 MESA_SHADER_VERTEX, &vs_tex, &needs_border);
3287 if (result != VK_SUCCESS)
3288 return result;
3289
3290 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3291 MESA_SHADER_FRAGMENT, &fs_tex, &needs_border);
3292 if (result != VK_SUCCESS)
3293 return result;
3294
3295 result = tu6_emit_ibo(cmd, pipeline, descriptors_state,
3296 MESA_SHADER_FRAGMENT, &fs_ibo);
3297 if (result != VK_SUCCESS)
3298 return result;
3299
3300 draw_state_groups[draw_state_group_count++] =
3301 (struct tu_draw_state_group) {
3302 .id = TU_DRAW_STATE_VS_TEX,
3303 .enable_mask = ENABLE_ALL,
3304 .ib = vs_tex,
3305 };
3306 draw_state_groups[draw_state_group_count++] =
3307 (struct tu_draw_state_group) {
3308 .id = TU_DRAW_STATE_FS_TEX,
3309 .enable_mask = ENABLE_DRAW,
3310 .ib = fs_tex,
3311 };
3312 draw_state_groups[draw_state_group_count++] =
3313 (struct tu_draw_state_group) {
3314 .id = TU_DRAW_STATE_FS_IBO,
3315 .enable_mask = ENABLE_DRAW,
3316 .ib = fs_ibo,
3317 };
3318
3319 if (needs_border) {
3320 result = tu6_emit_border_color(cmd, cs);
3321 if (result != VK_SUCCESS)
3322 return result;
3323 }
3324 }
3325
3326 struct tu_cs_entry vs_params;
3327 result = tu6_emit_vs_params(cmd, draw, &vs_params);
3328 if (result != VK_SUCCESS)
3329 return result;
3330
3331 draw_state_groups[draw_state_group_count++] =
3332 (struct tu_draw_state_group) {
3333 .id = TU_DRAW_STATE_VS_PARAMS,
3334 .enable_mask = ENABLE_ALL,
3335 .ib = vs_params,
3336 };
3337
3338 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3339 for (uint32_t i = 0; i < draw_state_group_count; i++) {
3340 const struct tu_draw_state_group *group = &draw_state_groups[i];
3341 debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
3342 uint32_t cp_set_draw_state =
3343 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3344 group->enable_mask |
3345 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3346 uint64_t iova;
3347 if (group->ib.size) {
3348 iova = group->ib.bo->iova + group->ib.offset;
3349 } else {
3350 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3351 iova = 0;
3352 }
3353
3354 tu_cs_emit(cs, cp_set_draw_state);
3355 tu_cs_emit_qw(cs, iova);
3356 }
3357
3358 tu_cs_sanity_check(cs);
3359
3360 /* track BOs */
3361 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3362 for (uint32_t i = 0; i < MAX_VBS; i++) {
3363 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3364 if (buf)
3365 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3366 }
3367 }
3368 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3369 unsigned i;
3370 for_each_bit(i, descriptors_state->valid) {
3371 struct tu_descriptor_set *set = descriptors_state->sets[i];
3372 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3373 if (set->descriptors[j]) {
3374 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3375 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3376 }
3377 }
3378 }
3379
3380 /* Fragment shader state overwrites compute shader state, so flag the
3381 * compute pipeline for re-emit.
3382 */
3383 cmd->state.dirty = TU_CMD_DIRTY_COMPUTE_PIPELINE;
3384 return VK_SUCCESS;
3385 }
3386
3387 static void
3388 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3389 struct tu_cs *cs,
3390 const struct tu_draw_info *draw)
3391 {
3392
3393 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3394
3395 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
3396 tu_cs_emit(cs, draw->vertex_offset);
3397 tu_cs_emit(cs, draw->first_instance);
3398
3399 /* TODO hw binning */
3400 if (draw->indexed) {
3401 const enum a4xx_index_size index_size =
3402 tu6_index_size(cmd->state.index_type);
3403 const uint32_t index_bytes =
3404 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3405 const struct tu_buffer *buf = cmd->state.index_buffer;
3406 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3407 index_bytes * draw->first_index;
3408 const uint32_t size = index_bytes * draw->count;
3409
3410 const uint32_t cp_draw_indx =
3411 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3412 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3413 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3414 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3415
3416 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3417 tu_cs_emit(cs, cp_draw_indx);
3418 tu_cs_emit(cs, draw->instance_count);
3419 tu_cs_emit(cs, draw->count);
3420 tu_cs_emit(cs, 0x0); /* XXX */
3421 tu_cs_emit_qw(cs, buf->bo->iova + offset);
3422 tu_cs_emit(cs, size);
3423 } else {
3424 const uint32_t cp_draw_indx =
3425 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3426 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3427 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3428
3429 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3430 tu_cs_emit(cs, cp_draw_indx);
3431 tu_cs_emit(cs, draw->instance_count);
3432 tu_cs_emit(cs, draw->count);
3433 }
3434 }
3435
3436 static void
3437 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3438 {
3439 struct tu_cs *cs = &cmd->draw_cs;
3440 VkResult result;
3441
3442 result = tu6_bind_draw_states(cmd, cs, draw);
3443 if (result != VK_SUCCESS) {
3444 cmd->record_result = result;
3445 return;
3446 }
3447
3448 result = tu_cs_reserve_space(cmd->device, cs, 32);
3449 if (result != VK_SUCCESS) {
3450 cmd->record_result = result;
3451 return;
3452 }
3453
3454 if (draw->indirect) {
3455 tu_finishme("indirect draw");
3456 return;
3457 }
3458
3459 /* TODO tu6_emit_marker should pick different regs depending on cs */
3460
3461 tu6_emit_marker(cmd, cs);
3462 tu6_emit_draw_direct(cmd, cs, draw);
3463 tu6_emit_marker(cmd, cs);
3464
3465 cmd->wait_for_idle = true;
3466
3467 tu_cs_sanity_check(cs);
3468 }
3469
3470 void
3471 tu_CmdDraw(VkCommandBuffer commandBuffer,
3472 uint32_t vertexCount,
3473 uint32_t instanceCount,
3474 uint32_t firstVertex,
3475 uint32_t firstInstance)
3476 {
3477 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3478 struct tu_draw_info info = {};
3479
3480 info.count = vertexCount;
3481 info.instance_count = instanceCount;
3482 info.first_instance = firstInstance;
3483 info.vertex_offset = firstVertex;
3484
3485 tu_draw(cmd_buffer, &info);
3486 }
3487
3488 void
3489 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3490 uint32_t indexCount,
3491 uint32_t instanceCount,
3492 uint32_t firstIndex,
3493 int32_t vertexOffset,
3494 uint32_t firstInstance)
3495 {
3496 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3497 struct tu_draw_info info = {};
3498
3499 info.indexed = true;
3500 info.count = indexCount;
3501 info.instance_count = instanceCount;
3502 info.first_index = firstIndex;
3503 info.vertex_offset = vertexOffset;
3504 info.first_instance = firstInstance;
3505
3506 tu_draw(cmd_buffer, &info);
3507 }
3508
3509 void
3510 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3511 VkBuffer _buffer,
3512 VkDeviceSize offset,
3513 uint32_t drawCount,
3514 uint32_t stride)
3515 {
3516 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3517 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3518 struct tu_draw_info info = {};
3519
3520 info.count = drawCount;
3521 info.indirect = buffer;
3522 info.indirect_offset = offset;
3523 info.stride = stride;
3524
3525 tu_draw(cmd_buffer, &info);
3526 }
3527
3528 void
3529 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3530 VkBuffer _buffer,
3531 VkDeviceSize offset,
3532 uint32_t drawCount,
3533 uint32_t stride)
3534 {
3535 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3536 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3537 struct tu_draw_info info = {};
3538
3539 info.indexed = true;
3540 info.count = drawCount;
3541 info.indirect = buffer;
3542 info.indirect_offset = offset;
3543 info.stride = stride;
3544
3545 tu_draw(cmd_buffer, &info);
3546 }
3547
3548 struct tu_dispatch_info
3549 {
3550 /**
3551 * Determine the layout of the grid (in block units) to be used.
3552 */
3553 uint32_t blocks[3];
3554
3555 /**
3556 * A starting offset for the grid. If unaligned is set, the offset
3557 * must still be aligned.
3558 */
3559 uint32_t offsets[3];
3560 /**
3561 * Whether it's an unaligned compute dispatch.
3562 */
3563 bool unaligned;
3564
3565 /**
3566 * Indirect compute parameters resource.
3567 */
3568 struct tu_buffer *indirect;
3569 uint64_t indirect_offset;
3570 };
3571
3572 static void
3573 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3574 const struct tu_dispatch_info *info)
3575 {
3576 gl_shader_stage type = MESA_SHADER_COMPUTE;
3577 const struct tu_program_descriptor_linkage *link =
3578 &pipeline->program.link[type];
3579 const struct ir3_const_state *const_state = &link->const_state;
3580 uint32_t offset = const_state->offsets.driver_param;
3581
3582 if (link->constlen <= offset)
3583 return;
3584
3585 if (!info->indirect) {
3586 uint32_t driver_params[IR3_DP_CS_COUNT] = {
3587 [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
3588 [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
3589 [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
3590 [IR3_DP_LOCAL_GROUP_SIZE_X] = pipeline->compute.local_size[0],
3591 [IR3_DP_LOCAL_GROUP_SIZE_Y] = pipeline->compute.local_size[1],
3592 [IR3_DP_LOCAL_GROUP_SIZE_Z] = pipeline->compute.local_size[2],
3593 };
3594
3595 uint32_t num_consts = MIN2(const_state->num_driver_params,
3596 (link->constlen - offset) * 4);
3597 /* push constants */
3598 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
3599 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
3600 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3601 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3602 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3603 CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
3604 tu_cs_emit(cs, 0);
3605 tu_cs_emit(cs, 0);
3606 uint32_t i;
3607 for (i = 0; i < num_consts; i++)
3608 tu_cs_emit(cs, driver_params[i]);
3609 } else {
3610 tu_finishme("Indirect driver params");
3611 }
3612 }
3613
3614 static void
3615 tu_dispatch(struct tu_cmd_buffer *cmd,
3616 const struct tu_dispatch_info *info)
3617 {
3618 struct tu_cs *cs = &cmd->cs;
3619 struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3620 struct tu_descriptor_state *descriptors_state =
3621 &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3622
3623 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3624 if (result != VK_SUCCESS) {
3625 cmd->record_result = result;
3626 return;
3627 }
3628
3629 if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3630 tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3631
3632 struct tu_cs_entry ib;
3633
3634 ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3635 if (ib.size)
3636 tu_cs_emit_ib(cs, &ib);
3637
3638 tu_emit_compute_driver_params(cs, pipeline, info);
3639
3640 bool needs_border;
3641 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3642 MESA_SHADER_COMPUTE, &ib, &needs_border);
3643 if (result != VK_SUCCESS) {
3644 cmd->record_result = result;
3645 return;
3646 }
3647
3648 if (ib.size)
3649 tu_cs_emit_ib(cs, &ib);
3650
3651 if (needs_border)
3652 tu_finishme("compute border color");
3653
3654 result = tu6_emit_ibo(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE, &ib);
3655 if (result != VK_SUCCESS) {
3656 cmd->record_result = result;
3657 return;
3658 }
3659
3660 if (ib.size)
3661 tu_cs_emit_ib(cs, &ib);
3662
3663 /* track BOs */
3664 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3665 unsigned i;
3666 for_each_bit(i, descriptors_state->valid) {
3667 struct tu_descriptor_set *set = descriptors_state->sets[i];
3668 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3669 if (set->descriptors[j]) {
3670 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3671 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3672 }
3673 }
3674 }
3675
3676 /* Compute shader state overwrites fragment shader state, so we flag the
3677 * graphics pipeline for re-emit.
3678 */
3679 cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
3680
3681 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3682 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x8));
3683
3684 const uint32_t *local_size = pipeline->compute.local_size;
3685 const uint32_t *num_groups = info->blocks;
3686 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_NDRANGE_0, 7);
3687 tu_cs_emit(cs,
3688 A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(3) |
3689 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
3690 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
3691 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
3692 tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size[0] * num_groups[0]));
3693 tu_cs_emit(cs, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
3694 tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size[1] * num_groups[1]));
3695 tu_cs_emit(cs, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
3696 tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size[2] * num_groups[2]));
3697 tu_cs_emit(cs, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
3698
3699 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X, 3);
3700 tu_cs_emit(cs, 1); /* HLSQ_CS_KERNEL_GROUP_X */
3701 tu_cs_emit(cs, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
3702 tu_cs_emit(cs, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
3703
3704 if (info->indirect) {
3705 uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3706
3707 tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3708 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3709
3710 tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3711 tu_cs_emit(cs, 0x00000000);
3712 tu_cs_emit_qw(cs, iova);
3713 tu_cs_emit(cs,
3714 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3715 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3716 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3717 } else {
3718 tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3719 tu_cs_emit(cs, 0x00000000);
3720 tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3721 tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3722 tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3723 }
3724
3725 tu_cs_emit_wfi(cs);
3726
3727 tu6_emit_cache_flush(cmd, cs);
3728 }
3729
3730 void
3731 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
3732 uint32_t base_x,
3733 uint32_t base_y,
3734 uint32_t base_z,
3735 uint32_t x,
3736 uint32_t y,
3737 uint32_t z)
3738 {
3739 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3740 struct tu_dispatch_info info = {};
3741
3742 info.blocks[0] = x;
3743 info.blocks[1] = y;
3744 info.blocks[2] = z;
3745
3746 info.offsets[0] = base_x;
3747 info.offsets[1] = base_y;
3748 info.offsets[2] = base_z;
3749 tu_dispatch(cmd_buffer, &info);
3750 }
3751
3752 void
3753 tu_CmdDispatch(VkCommandBuffer commandBuffer,
3754 uint32_t x,
3755 uint32_t y,
3756 uint32_t z)
3757 {
3758 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3759 }
3760
3761 void
3762 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
3763 VkBuffer _buffer,
3764 VkDeviceSize offset)
3765 {
3766 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3767 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3768 struct tu_dispatch_info info = {};
3769
3770 info.indirect = buffer;
3771 info.indirect_offset = offset;
3772
3773 tu_dispatch(cmd_buffer, &info);
3774 }
3775
3776 void
3777 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3778 {
3779 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3780
3781 tu_cs_end(&cmd_buffer->draw_cs);
3782
3783 tu_cmd_render_tiles(cmd_buffer);
3784
3785 /* discard draw_cs entries now that the tiles are rendered */
3786 tu_cs_discard_entries(&cmd_buffer->draw_cs);
3787 tu_cs_begin(&cmd_buffer->draw_cs);
3788
3789 cmd_buffer->state.pass = NULL;
3790 cmd_buffer->state.subpass = NULL;
3791 cmd_buffer->state.framebuffer = NULL;
3792 }
3793
3794 void
3795 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
3796 const VkSubpassEndInfoKHR *pSubpassEndInfo)
3797 {
3798 tu_CmdEndRenderPass(commandBuffer);
3799 }
3800
3801 struct tu_barrier_info
3802 {
3803 uint32_t eventCount;
3804 const VkEvent *pEvents;
3805 VkPipelineStageFlags srcStageMask;
3806 };
3807
3808 static void
3809 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
3810 uint32_t memoryBarrierCount,
3811 const VkMemoryBarrier *pMemoryBarriers,
3812 uint32_t bufferMemoryBarrierCount,
3813 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3814 uint32_t imageMemoryBarrierCount,
3815 const VkImageMemoryBarrier *pImageMemoryBarriers,
3816 const struct tu_barrier_info *info)
3817 {
3818 }
3819
3820 void
3821 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3822 VkPipelineStageFlags srcStageMask,
3823 VkPipelineStageFlags destStageMask,
3824 VkBool32 byRegion,
3825 uint32_t memoryBarrierCount,
3826 const VkMemoryBarrier *pMemoryBarriers,
3827 uint32_t bufferMemoryBarrierCount,
3828 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3829 uint32_t imageMemoryBarrierCount,
3830 const VkImageMemoryBarrier *pImageMemoryBarriers)
3831 {
3832 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3833 struct tu_barrier_info info;
3834
3835 info.eventCount = 0;
3836 info.pEvents = NULL;
3837 info.srcStageMask = srcStageMask;
3838
3839 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3840 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3841 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3842 }
3843
3844 static void
3845 write_event(struct tu_cmd_buffer *cmd_buffer,
3846 struct tu_event *event,
3847 VkPipelineStageFlags stageMask,
3848 unsigned value)
3849 {
3850 }
3851
3852 void
3853 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3854 VkEvent _event,
3855 VkPipelineStageFlags stageMask)
3856 {
3857 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3858 TU_FROM_HANDLE(tu_event, event, _event);
3859
3860 write_event(cmd_buffer, event, stageMask, 1);
3861 }
3862
3863 void
3864 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3865 VkEvent _event,
3866 VkPipelineStageFlags stageMask)
3867 {
3868 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3869 TU_FROM_HANDLE(tu_event, event, _event);
3870
3871 write_event(cmd_buffer, event, stageMask, 0);
3872 }
3873
3874 void
3875 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3876 uint32_t eventCount,
3877 const VkEvent *pEvents,
3878 VkPipelineStageFlags srcStageMask,
3879 VkPipelineStageFlags dstStageMask,
3880 uint32_t memoryBarrierCount,
3881 const VkMemoryBarrier *pMemoryBarriers,
3882 uint32_t bufferMemoryBarrierCount,
3883 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3884 uint32_t imageMemoryBarrierCount,
3885 const VkImageMemoryBarrier *pImageMemoryBarriers)
3886 {
3887 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3888 struct tu_barrier_info info;
3889
3890 info.eventCount = eventCount;
3891 info.pEvents = pEvents;
3892 info.srcStageMask = 0;
3893
3894 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3895 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3896 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3897 }
3898
3899 void
3900 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3901 {
3902 /* No-op */
3903 }