2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "adreno_pm4.xml.h"
31 #include "adreno_common.xml.h"
33 #include "vk_format.h"
38 tu_bo_list_init(struct tu_bo_list
*list
)
40 list
->count
= list
->capacity
= 0;
41 list
->bo_infos
= NULL
;
45 tu_bo_list_destroy(struct tu_bo_list
*list
)
51 tu_bo_list_reset(struct tu_bo_list
*list
)
57 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 tu_bo_list_add_info(struct tu_bo_list
*list
,
61 const struct drm_msm_gem_submit_bo
*bo_info
)
63 assert(bo_info
->handle
!= 0);
65 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
66 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
67 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
68 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
73 /* grow list->bo_infos if needed */
74 if (list
->count
== list
->capacity
) {
75 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
76 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
77 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
79 return TU_BO_LIST_FAILED
;
80 list
->bo_infos
= new_bo_infos
;
81 list
->capacity
= new_capacity
;
84 list
->bo_infos
[list
->count
] = *bo_info
;
89 tu_bo_list_add(struct tu_bo_list
*list
,
90 const struct tu_bo
*bo
,
93 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
95 .handle
= bo
->gem_handle
,
101 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
103 for (uint32_t i
= 0; i
< other
->count
; i
++) {
104 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
105 return VK_ERROR_OUT_OF_HOST_MEMORY
;
112 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
114 enum vgt_event_type event
)
116 bool need_seqno
= false;
121 case PC_CCU_FLUSH_DEPTH_TS
:
122 case PC_CCU_FLUSH_COLOR_TS
:
123 case PC_CCU_RESOLVE_TS
:
130 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
131 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
133 tu_cs_emit_qw(cs
, global_iova(cmd
, seqno_dummy
));
139 tu6_emit_flushes(struct tu_cmd_buffer
*cmd_buffer
,
141 enum tu_cmd_flush_bits flushes
)
143 /* Experiments show that invalidating CCU while it still has data in it
144 * doesn't work, so make sure to always flush before invalidating in case
145 * any data remains that hasn't yet been made available through a barrier.
146 * However it does seem to work for UCHE.
148 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_COLOR
|
149 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
))
150 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_COLOR_TS
);
151 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
152 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
))
153 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_DEPTH_TS
);
154 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_COLOR
)
155 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_COLOR
);
156 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
)
157 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_DEPTH
);
158 if (flushes
& TU_CMD_FLAG_CACHE_FLUSH
)
159 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_FLUSH_TS
);
160 if (flushes
& TU_CMD_FLAG_CACHE_INVALIDATE
)
161 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_INVALIDATE
);
162 if (flushes
& TU_CMD_FLAG_WAIT_MEM_WRITES
)
163 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
164 if (flushes
& TU_CMD_FLAG_WAIT_FOR_IDLE
)
166 if (flushes
& TU_CMD_FLAG_WAIT_FOR_ME
)
167 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
170 /* "Normal" cache flushes, that don't require any special handling */
173 tu_emit_cache_flush(struct tu_cmd_buffer
*cmd_buffer
,
176 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.cache
.flush_bits
);
177 cmd_buffer
->state
.cache
.flush_bits
= 0;
180 /* Renderpass cache flushes */
183 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
186 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.renderpass_cache
.flush_bits
);
187 cmd_buffer
->state
.renderpass_cache
.flush_bits
= 0;
190 /* Cache flushes for things that use the color/depth read/write path (i.e.
191 * blits and draws). This deals with changing CCU state as well as the usual
196 tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
198 enum tu_cmd_ccu_state ccu_state
)
200 enum tu_cmd_flush_bits flushes
= cmd_buffer
->state
.cache
.flush_bits
;
202 assert(ccu_state
!= TU_CMD_CCU_UNKNOWN
);
204 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
205 * the CCU may also contain data that we haven't flushed out yet, so we
206 * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
207 * emit a WFI as it isn't pipelined.
209 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
210 if (cmd_buffer
->state
.ccu_state
!= TU_CMD_CCU_GMEM
) {
212 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
213 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
214 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
215 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
216 TU_CMD_FLAG_CCU_FLUSH_DEPTH
);
219 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
220 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
221 TU_CMD_FLAG_WAIT_FOR_IDLE
;
222 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
223 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
224 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
225 TU_CMD_FLAG_WAIT_FOR_IDLE
);
228 tu6_emit_flushes(cmd_buffer
, cs
, flushes
);
229 cmd_buffer
->state
.cache
.flush_bits
= 0;
231 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
232 struct tu_physical_device
*phys_dev
= cmd_buffer
->device
->physical_device
;
234 A6XX_RB_CCU_CNTL(.offset
=
235 ccu_state
== TU_CMD_CCU_GMEM
?
236 phys_dev
->ccu_offset_gmem
:
237 phys_dev
->ccu_offset_bypass
,
238 .gmem
= ccu_state
== TU_CMD_CCU_GMEM
));
239 cmd_buffer
->state
.ccu_state
= ccu_state
;
244 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
245 const struct tu_subpass
*subpass
,
248 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
250 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
251 if (a
== VK_ATTACHMENT_UNUSED
) {
253 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
254 A6XX_RB_DEPTH_BUFFER_PITCH(0),
255 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
256 A6XX_RB_DEPTH_BUFFER_BASE(0),
257 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
260 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
263 A6XX_GRAS_LRZ_BUFFER_BASE(0),
264 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
265 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
267 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
272 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
273 const struct tu_render_pass_attachment
*attachment
=
274 &cmd
->state
.pass
->attachments
[a
];
275 enum a6xx_depth_format fmt
= tu6_pipe2depth(attachment
->format
);
277 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
278 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
).value
);
279 tu_cs_image_ref(cs
, iview
, 0);
280 tu_cs_emit(cs
, attachment
->gmem_offset
);
283 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
285 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
286 tu_cs_image_flag_ref(cs
, iview
, 0);
289 A6XX_GRAS_LRZ_BUFFER_BASE(0),
290 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
291 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
293 if (attachment
->format
== VK_FORMAT_S8_UINT
) {
294 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 6);
295 tu_cs_emit(cs
, A6XX_RB_STENCIL_INFO(.separate_stencil
= true).value
);
296 tu_cs_image_ref(cs
, iview
, 0);
297 tu_cs_emit(cs
, attachment
->gmem_offset
);
300 A6XX_RB_STENCIL_INFO(0));
305 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
306 const struct tu_subpass
*subpass
,
309 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
311 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
312 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
313 if (a
== VK_ATTACHMENT_UNUSED
)
316 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
318 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
319 tu_cs_emit(cs
, iview
->RB_MRT_BUF_INFO
);
320 tu_cs_image_ref(cs
, iview
, 0);
321 tu_cs_emit(cs
, cmd
->state
.pass
->attachments
[a
].gmem_offset
);
324 A6XX_SP_FS_MRT_REG(i
, .dword
= iview
->SP_FS_MRT_REG
));
326 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i
), 3);
327 tu_cs_image_flag_ref(cs
, iview
, 0);
331 A6XX_RB_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
333 A6XX_SP_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
335 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
339 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
341 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
342 bool msaa_disable
= samples
== MSAA_ONE
;
345 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
346 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
347 .msaa_disable
= msaa_disable
));
350 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
351 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
352 .msaa_disable
= msaa_disable
));
355 A6XX_RB_RAS_MSAA_CNTL(samples
),
356 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
357 .msaa_disable
= msaa_disable
));
360 A6XX_RB_MSAA_CNTL(samples
));
364 tu6_emit_bin_size(struct tu_cs
*cs
,
365 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
368 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
373 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
377 /* no flag for RB_BIN_CONTROL2... */
379 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
384 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
385 const struct tu_subpass
*subpass
,
389 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
391 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
393 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
395 uint32_t mrts_ubwc_enable
= 0;
396 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
397 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
398 if (a
== VK_ATTACHMENT_UNUSED
)
401 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
402 if (iview
->ubwc_enabled
)
403 mrts_ubwc_enable
|= 1 << i
;
406 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
408 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
409 if (a
!= VK_ATTACHMENT_UNUSED
) {
410 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
411 if (iview
->ubwc_enabled
)
412 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
415 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
416 * in order to set it correctly for the different subpasses. However,
417 * that means the packets we're emitting also happen during binning. So
418 * we need to guard the write on !BINNING at CP execution time.
420 tu_cs_reserve(cs
, 3 + 4);
421 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
422 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
423 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
424 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
427 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
428 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
429 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
430 tu_cs_emit(cs
, cntl
);
434 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
437 const VkRect2D
*render_area
= &cmd
->state
.render_area
;
439 /* Avoid assertion fails with an empty render area at (0, 0) where the
440 * subtraction below wraps around. Empty render areas should be forced to
441 * the sysmem path by use_sysmem_rendering(). It's not even clear whether
442 * an empty scissor here works, and the blob seems to force sysmem too as
443 * it sets something wrong (non-empty) for the scissor.
445 if (render_area
->extent
.width
== 0 ||
446 render_area
->extent
.height
== 0)
449 uint32_t x1
= render_area
->offset
.x
;
450 uint32_t y1
= render_area
->offset
.y
;
451 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
452 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
455 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
456 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
457 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
458 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
462 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
463 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
467 tu6_emit_window_scissor(struct tu_cs
*cs
,
474 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
475 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
478 A6XX_GRAS_2D_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
479 A6XX_GRAS_2D_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
483 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
486 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
489 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
492 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
495 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
499 tu_cs_emit_draw_state(struct tu_cs
*cs
, uint32_t id
, struct tu_draw_state state
)
501 uint32_t enable_mask
;
503 case TU_DRAW_STATE_PROGRAM
:
504 case TU_DRAW_STATE_VI
:
505 case TU_DRAW_STATE_FS_CONST
:
506 /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
507 * when resources would actually be used in the binning shader.
508 * Presumably the overhead of prefetching the resources isn't
511 case TU_DRAW_STATE_DESC_SETS_LOAD
:
512 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
513 CP_SET_DRAW_STATE__0_SYSMEM
;
515 case TU_DRAW_STATE_PROGRAM_BINNING
:
516 case TU_DRAW_STATE_VI_BINNING
:
517 enable_mask
= CP_SET_DRAW_STATE__0_BINNING
;
519 case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
:
520 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
;
522 case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
:
523 enable_mask
= CP_SET_DRAW_STATE__0_SYSMEM
;
526 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
527 CP_SET_DRAW_STATE__0_SYSMEM
|
528 CP_SET_DRAW_STATE__0_BINNING
;
532 /* We need to reload the descriptors every time the descriptor sets
533 * change. However, the commands we send only depend on the pipeline
534 * because the whole point is to cache descriptors which are used by the
535 * pipeline. There's a problem here, in that the firmware has an
536 * "optimization" which skips executing groups that are set to the same
537 * value as the last draw. This means that if the descriptor sets change
538 * but not the pipeline, we'd try to re-execute the same buffer which
539 * the firmware would ignore and we wouldn't pre-load the new
540 * descriptors. Set the DIRTY bit to avoid this optimization
542 if (id
== TU_DRAW_STATE_DESC_SETS_LOAD
)
543 enable_mask
|= CP_SET_DRAW_STATE__0_DIRTY
;
545 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(state
.size
) |
547 CP_SET_DRAW_STATE__0_GROUP_ID(id
) |
548 COND(!state
.size
, CP_SET_DRAW_STATE__0_DISABLE
));
549 tu_cs_emit_qw(cs
, state
.iova
);
553 use_hw_binning(struct tu_cmd_buffer
*cmd
)
555 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
557 /* XFB commands are emitted for BINNING || SYSMEM, which makes it incompatible
558 * with non-hw binning GMEM rendering. this is required because some of the
559 * XFB commands need to only be executed once
561 if (cmd
->state
.xfb_used
)
564 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
567 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
570 return (fb
->tile_count
.width
* fb
->tile_count
.height
) > 2;
574 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
576 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
579 /* can't fit attachments into gmem */
580 if (!cmd
->state
.pass
->gmem_pixels
)
583 if (cmd
->state
.framebuffer
->layers
> 1)
586 /* Use sysmem for empty render areas */
587 if (cmd
->state
.render_area
.extent
.width
== 0 ||
588 cmd
->state
.render_area
.extent
.height
== 0)
598 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
600 uint32_t tx
, uint32_t ty
, uint32_t pipe
, uint32_t slot
)
602 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
604 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
605 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
607 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
608 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
610 const uint32_t x1
= fb
->tile0
.width
* tx
;
611 const uint32_t y1
= fb
->tile0
.height
* ty
;
612 const uint32_t x2
= x1
+ fb
->tile0
.width
- 1;
613 const uint32_t y2
= y1
+ fb
->tile0
.height
- 1;
614 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
615 tu6_emit_window_offset(cs
, x1
, y1
);
617 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
619 if (use_hw_binning(cmd
)) {
620 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
622 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
625 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5_OFFSET
, 4);
626 tu_cs_emit(cs
, fb
->pipe_sizes
[pipe
] |
627 CP_SET_BIN_DATA5_0_VSC_N(slot
));
628 tu_cs_emit(cs
, pipe
* cmd
->vsc_draw_strm_pitch
);
629 tu_cs_emit(cs
, pipe
* 4);
630 tu_cs_emit(cs
, pipe
* cmd
->vsc_prim_strm_pitch
);
632 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
635 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
638 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
641 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
647 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
652 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
653 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
654 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
656 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.render_area
);
660 tu6_emit_sysmem_resolves(struct tu_cmd_buffer
*cmd
,
662 const struct tu_subpass
*subpass
)
664 if (subpass
->resolve_attachments
) {
665 /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
668 * End-of-subpass multisample resolves are treated as color
669 * attachment writes for the purposes of synchronization. That is,
670 * they are considered to execute in the
671 * VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage and
672 * their writes are synchronized with
673 * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
674 * rendering within a subpass and any resolve operations at the end
675 * of the subpass occurs automatically, without need for explicit
676 * dependencies or pipeline barriers. However, if the resolve
677 * attachment is also used in a different subpass, an explicit
678 * dependency is needed.
680 * We use the CP_BLIT path for sysmem resolves, which is really a
681 * transfer command, so we have to manually flush similar to the gmem
682 * resolve case. However, a flush afterwards isn't needed because of the
683 * last sentence and the fact that we're in sysmem mode.
685 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
686 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
688 /* Wait for the flushes to land before using the 2D engine */
691 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
692 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
693 if (a
== VK_ATTACHMENT_UNUSED
)
696 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
697 subpass
->color_attachments
[i
].attachment
);
703 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
705 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
706 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
708 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
709 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
710 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
711 CP_SET_DRAW_STATE__0_GROUP_ID(0));
712 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
713 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
715 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
718 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
719 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
721 tu6_emit_blit_scissor(cmd
, cs
, true);
723 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
724 if (pass
->attachments
[a
].gmem_offset
>= 0)
725 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
728 if (subpass
->resolve_attachments
) {
729 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
730 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
731 if (a
!= VK_ATTACHMENT_UNUSED
)
732 tu_store_gmem_attachment(cmd
, cs
, a
,
733 subpass
->color_attachments
[i
].attachment
);
739 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
741 struct tu_device
*dev
= cmd
->device
;
742 const struct tu_physical_device
*phys_dev
= dev
->physical_device
;
744 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
746 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(
755 .gfx_shared_const
= true,
756 .cs_shared_const
= true,
757 .gfx_bindless
= 0x1f,
758 .cs_bindless
= 0x1f));
762 cmd
->state
.cache
.pending_flush_bits
&=
763 ~(TU_CMD_FLAG_WAIT_FOR_IDLE
| TU_CMD_FLAG_CACHE_INVALIDATE
);
766 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
767 cmd
->state
.ccu_state
= TU_CMD_CCU_SYSMEM
;
768 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
769 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
770 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
771 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
772 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
773 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
774 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
775 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
777 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
778 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
779 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
780 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
781 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
782 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
783 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_SHARED_CONSTS
, 0);
784 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
785 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
786 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
787 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
788 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
789 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
791 /* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
792 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
793 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
794 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
796 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
798 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
800 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
801 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
802 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
803 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
804 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
805 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
806 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
807 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
808 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
809 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
810 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
812 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
814 tu_cs_emit_regs(cs
, A6XX_VPC_POINT_COORD_INVERT(false));
815 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
817 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(true));
819 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
821 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
822 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
824 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
826 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
828 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
829 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
830 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
831 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
832 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
833 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
834 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
835 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
836 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
838 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
840 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
842 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
844 /* we don't use this yet.. probably best to disable.. */
845 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
846 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
847 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
848 CP_SET_DRAW_STATE__0_GROUP_ID(0));
849 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
850 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
853 A6XX_SP_HS_CTRL_REG0(0));
856 A6XX_SP_GS_CTRL_REG0(0));
859 A6XX_GRAS_LRZ_CNTL(0));
862 A6XX_RB_LRZ_CNTL(0));
865 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &dev
->global_bo
,
866 .bo_offset
= gb_offset(border_color
)));
868 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &dev
->global_bo
,
869 .bo_offset
= gb_offset(border_color
)));
872 * use vsc pitches from the largest values used so far with this device
873 * if there hasn't been overflow, there will already be a scratch bo
874 * allocated for these sizes
876 * if overflow is detected, the stream size is increased by 2x
878 mtx_lock(&dev
->vsc_pitch_mtx
);
880 struct tu6_global
*global
= dev
->global_bo
.map
;
882 uint32_t vsc_draw_overflow
= global
->vsc_draw_overflow
;
883 uint32_t vsc_prim_overflow
= global
->vsc_prim_overflow
;
885 if (vsc_draw_overflow
>= dev
->vsc_draw_strm_pitch
)
886 dev
->vsc_draw_strm_pitch
= (dev
->vsc_draw_strm_pitch
- VSC_PAD
) * 2 + VSC_PAD
;
888 if (vsc_prim_overflow
>= dev
->vsc_prim_strm_pitch
)
889 dev
->vsc_prim_strm_pitch
= (dev
->vsc_prim_strm_pitch
- VSC_PAD
) * 2 + VSC_PAD
;
891 cmd
->vsc_prim_strm_pitch
= dev
->vsc_prim_strm_pitch
;
892 cmd
->vsc_draw_strm_pitch
= dev
->vsc_draw_strm_pitch
;
894 mtx_unlock(&dev
->vsc_pitch_mtx
);
896 struct tu_bo
*vsc_bo
;
897 uint32_t size0
= cmd
->vsc_prim_strm_pitch
* MAX_VSC_PIPES
+
898 cmd
->vsc_draw_strm_pitch
* MAX_VSC_PIPES
;
900 tu_get_scratch_bo(dev
, size0
+ MAX_VSC_PIPES
* 4, &vsc_bo
);
903 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo
= vsc_bo
, .bo_offset
= size0
));
905 A6XX_VSC_PRIM_STRM_ADDRESS(.bo
= vsc_bo
));
907 A6XX_VSC_DRAW_STRM_ADDRESS(.bo
= vsc_bo
,
908 .bo_offset
= cmd
->vsc_prim_strm_pitch
* MAX_VSC_PIPES
));
910 tu_bo_list_add(&cmd
->bo_list
, vsc_bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
912 tu_cs_sanity_check(cs
);
916 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
918 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
921 A6XX_VSC_BIN_SIZE(.width
= fb
->tile0
.width
,
922 .height
= fb
->tile0
.height
));
925 A6XX_VSC_BIN_COUNT(.nx
= fb
->tile_count
.width
,
926 .ny
= fb
->tile_count
.height
));
928 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
929 tu_cs_emit_array(cs
, fb
->pipe_config
, 32);
932 A6XX_VSC_PRIM_STRM_PITCH(cmd
->vsc_prim_strm_pitch
),
933 A6XX_VSC_PRIM_STRM_LIMIT(cmd
->vsc_prim_strm_pitch
- VSC_PAD
));
936 A6XX_VSC_DRAW_STRM_PITCH(cmd
->vsc_draw_strm_pitch
),
937 A6XX_VSC_DRAW_STRM_LIMIT(cmd
->vsc_draw_strm_pitch
- VSC_PAD
));
941 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
943 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
944 const uint32_t used_pipe_count
=
945 fb
->pipe_count
.width
* fb
->pipe_count
.height
;
947 for (int i
= 0; i
< used_pipe_count
; i
++) {
948 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
949 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
950 CP_COND_WRITE5_0_WRITE_MEMORY
);
951 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i
)));
952 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
953 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_draw_strm_pitch
- VSC_PAD
));
954 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
955 tu_cs_emit_qw(cs
, global_iova(cmd
, vsc_draw_overflow
));
956 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(cmd
->vsc_draw_strm_pitch
));
958 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
959 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
960 CP_COND_WRITE5_0_WRITE_MEMORY
);
961 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i
)));
962 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
963 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_prim_strm_pitch
- VSC_PAD
));
964 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
965 tu_cs_emit_qw(cs
, global_iova(cmd
, vsc_prim_overflow
));
966 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(cmd
->vsc_prim_strm_pitch
));
969 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
973 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
975 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
976 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
978 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
980 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
981 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
983 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
986 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
992 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
994 update_vsc_pipe(cmd
, cs
);
997 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1000 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1002 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1003 tu_cs_emit(cs
, UNK_2C
);
1006 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1009 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1011 /* emit IB to binning drawcmds: */
1012 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1014 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1015 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1016 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1017 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1018 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1019 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1021 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1022 tu_cs_emit(cs
, UNK_2D
);
1024 /* This flush is probably required because the VSC, which produces the
1025 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1026 * visibility stream (without caching) to do draw skipping. The
1027 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1028 * submitted are finished before reading the VSC regs (in
1029 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1032 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
);
1036 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1038 emit_vsc_overflow_test(cmd
, cs
);
1040 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1041 tu_cs_emit(cs
, 0x0);
1043 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1044 tu_cs_emit(cs
, 0x0);
1047 static struct tu_draw_state
1048 tu_emit_input_attachments(struct tu_cmd_buffer
*cmd
,
1049 const struct tu_subpass
*subpass
,
1052 /* note: we can probably emit input attachments just once for the whole
1053 * renderpass, this would avoid emitting both sysmem/gmem versions
1055 * emit two texture descriptors for each input, as a workaround for
1056 * d24s8, which can be sampled as both float (depth) and integer (stencil)
1057 * tu_shader lowers uint input attachment loads to use the 2nd descriptor
1059 * TODO: a smarter workaround
1062 if (!subpass
->input_count
)
1063 return (struct tu_draw_state
) {};
1065 struct tu_cs_memory texture
;
1066 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, subpass
->input_count
* 2,
1067 A6XX_TEX_CONST_DWORDS
, &texture
);
1068 assert(result
== VK_SUCCESS
);
1070 for (unsigned i
= 0; i
< subpass
->input_count
* 2; i
++) {
1071 uint32_t a
= subpass
->input_attachments
[i
/ 2].attachment
;
1072 if (a
== VK_ATTACHMENT_UNUSED
)
1075 struct tu_image_view
*iview
=
1076 cmd
->state
.framebuffer
->attachments
[a
].attachment
;
1077 const struct tu_render_pass_attachment
*att
=
1078 &cmd
->state
.pass
->attachments
[a
];
1079 uint32_t *dst
= &texture
.map
[A6XX_TEX_CONST_DWORDS
* i
];
1081 memcpy(dst
, iview
->descriptor
, A6XX_TEX_CONST_DWORDS
* 4);
1083 if (i
% 2 == 1 && att
->format
== VK_FORMAT_D24_UNORM_S8_UINT
) {
1084 /* note this works because spec says fb and input attachments
1085 * must use identity swizzle
1087 dst
[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK
|
1088 A6XX_TEX_CONST_0_SWIZ_X__MASK
| A6XX_TEX_CONST_0_SWIZ_Y__MASK
|
1089 A6XX_TEX_CONST_0_SWIZ_Z__MASK
| A6XX_TEX_CONST_0_SWIZ_W__MASK
);
1090 if (cmd
->device
->physical_device
->limited_z24s8
) {
1091 dst
[0] |= A6XX_TEX_CONST_0_FMT(FMT6_8_8_8_8_UINT
) |
1092 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_W
) |
1093 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO
) |
1094 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO
) |
1095 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE
);
1097 dst
[0] |= A6XX_TEX_CONST_0_FMT(FMT6_Z24_UINT_S8_UINT
) |
1098 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y
) |
1099 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO
) |
1100 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO
) |
1101 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE
);
1108 /* patched for gmem */
1109 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
1110 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
1112 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
1113 A6XX_TEX_CONST_2_PITCH(cmd
->state
.framebuffer
->tile0
.width
* att
->cpp
);
1115 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
1116 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
1117 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
1122 struct tu_draw_state ds
= tu_cs_draw_state(&cmd
->sub_cs
, &cs
, 9);
1124 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_FRAG
, 3);
1125 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1126 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1127 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1128 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX
) |
1129 CP_LOAD_STATE6_0_NUM_UNIT(subpass
->input_count
* 2));
1130 tu_cs_emit_qw(&cs
, texture
.iova
);
1132 tu_cs_emit_pkt4(&cs
, REG_A6XX_SP_FS_TEX_CONST_LO
, 2);
1133 tu_cs_emit_qw(&cs
, texture
.iova
);
1135 tu_cs_emit_regs(&cs
, A6XX_SP_FS_TEX_COUNT(subpass
->input_count
* 2));
1137 assert(cs
.cur
== cs
.end
); /* validate draw state size */
1143 tu_set_input_attachments(struct tu_cmd_buffer
*cmd
, const struct tu_subpass
*subpass
)
1145 struct tu_cs
*cs
= &cmd
->draw_cs
;
1147 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 6);
1148 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
,
1149 tu_emit_input_attachments(cmd
, subpass
, true));
1150 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
,
1151 tu_emit_input_attachments(cmd
, subpass
, false));
1155 tu_emit_renderpass_begin(struct tu_cmd_buffer
*cmd
,
1156 const VkRenderPassBeginInfo
*info
)
1158 struct tu_cs
*cs
= &cmd
->draw_cs
;
1160 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1162 tu6_emit_blit_scissor(cmd
, cs
, true);
1164 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1165 tu_load_gmem_attachment(cmd
, cs
, i
, false);
1167 tu6_emit_blit_scissor(cmd
, cs
, false);
1169 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1170 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1172 tu_cond_exec_end(cs
);
1174 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1176 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1177 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1179 tu_cond_exec_end(cs
);
1183 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1185 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1187 assert(fb
->width
> 0 && fb
->height
> 0);
1188 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1189 tu6_emit_window_offset(cs
, 0, 0);
1191 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1193 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1195 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1196 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1198 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1199 tu_cs_emit(cs
, 0x0);
1201 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_SYSMEM
);
1203 /* enable stream-out, with sysmem there is only one pass: */
1204 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1206 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1207 tu_cs_emit(cs
, 0x1);
1209 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1210 tu_cs_emit(cs
, 0x0);
1212 tu_cs_sanity_check(cs
);
1216 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1218 /* Do any resolves of the last subpass. These are handled in the
1219 * tile_store_ib in the gmem path.
1221 tu6_emit_sysmem_resolves(cmd
, cs
, cmd
->state
.subpass
);
1223 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1225 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1226 tu_cs_emit(cs
, 0x0);
1228 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1230 tu_cs_sanity_check(cs
);
1234 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1236 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1238 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1242 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1243 tu_cs_emit(cs
, 0x0);
1245 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_GMEM
);
1247 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1248 if (use_hw_binning(cmd
)) {
1249 /* enable stream-out during binning pass: */
1250 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1252 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
,
1253 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1255 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1257 tu6_emit_binning_pass(cmd
, cs
);
1259 /* and disable stream-out for draw pass: */
1260 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(true));
1262 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
,
1263 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1266 A6XX_VFD_MODE_CNTL(0));
1268 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1270 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1272 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1273 tu_cs_emit(cs
, 0x1);
1275 /* no binning pass, so enable stream-out for draw pass:: */
1276 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1278 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
, 0x6000000);
1281 tu_cs_sanity_check(cs
);
1285 tu6_render_tile(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1287 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1289 if (use_hw_binning(cmd
)) {
1290 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1291 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1294 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1296 tu_cs_sanity_check(cs
);
1300 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1302 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1305 A6XX_GRAS_LRZ_CNTL(0));
1307 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1309 tu6_emit_event_write(cmd
, cs
, PC_CCU_RESOLVE_TS
);
1311 tu_cs_sanity_check(cs
);
1315 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1317 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1319 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1322 for (uint32_t py
= 0; py
< fb
->pipe_count
.height
; py
++) {
1323 for (uint32_t px
= 0; px
< fb
->pipe_count
.width
; px
++, pipe
++) {
1324 uint32_t tx1
= px
* fb
->pipe0
.width
;
1325 uint32_t ty1
= py
* fb
->pipe0
.height
;
1326 uint32_t tx2
= MIN2(tx1
+ fb
->pipe0
.width
, fb
->tile_count
.width
);
1327 uint32_t ty2
= MIN2(ty1
+ fb
->pipe0
.height
, fb
->tile_count
.height
);
1329 for (uint32_t ty
= ty1
; ty
< ty2
; ty
++) {
1330 for (uint32_t tx
= tx1
; tx
< tx2
; tx
++, slot
++) {
1331 tu6_emit_tile_select(cmd
, &cmd
->cs
, tx
, ty
, pipe
, slot
);
1332 tu6_render_tile(cmd
, &cmd
->cs
);
1338 tu6_tile_render_end(cmd
, &cmd
->cs
);
1342 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1344 tu6_sysmem_render_begin(cmd
, &cmd
->cs
);
1346 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1348 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1352 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1354 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1355 struct tu_cs sub_cs
;
1358 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1359 if (result
!= VK_SUCCESS
) {
1360 cmd
->record_result
= result
;
1364 /* emit to tile-store sub_cs */
1365 tu6_emit_tile_store(cmd
, &sub_cs
);
1367 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1371 tu_create_cmd_buffer(struct tu_device
*device
,
1372 struct tu_cmd_pool
*pool
,
1373 VkCommandBufferLevel level
,
1374 VkCommandBuffer
*pCommandBuffer
)
1376 struct tu_cmd_buffer
*cmd_buffer
;
1378 cmd_buffer
= vk_object_zalloc(&device
->vk
, NULL
, sizeof(*cmd_buffer
),
1379 VK_OBJECT_TYPE_COMMAND_BUFFER
);
1380 if (cmd_buffer
== NULL
)
1381 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1383 cmd_buffer
->device
= device
;
1384 cmd_buffer
->pool
= pool
;
1385 cmd_buffer
->level
= level
;
1388 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1389 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1392 /* Init the pool_link so we can safely call list_del when we destroy
1393 * the command buffer
1395 list_inithead(&cmd_buffer
->pool_link
);
1396 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1399 tu_bo_list_init(&cmd_buffer
->bo_list
);
1400 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1401 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1402 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1403 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1405 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1407 list_inithead(&cmd_buffer
->upload
.list
);
1413 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1415 list_del(&cmd_buffer
->pool_link
);
1417 tu_cs_finish(&cmd_buffer
->cs
);
1418 tu_cs_finish(&cmd_buffer
->draw_cs
);
1419 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1420 tu_cs_finish(&cmd_buffer
->sub_cs
);
1422 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1423 vk_object_free(&cmd_buffer
->device
->vk
, &cmd_buffer
->pool
->alloc
, cmd_buffer
);
1427 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1429 cmd_buffer
->record_result
= VK_SUCCESS
;
1431 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1432 tu_cs_reset(&cmd_buffer
->cs
);
1433 tu_cs_reset(&cmd_buffer
->draw_cs
);
1434 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1435 tu_cs_reset(&cmd_buffer
->sub_cs
);
1437 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++)
1438 memset(&cmd_buffer
->descriptors
[i
].sets
, 0, sizeof(cmd_buffer
->descriptors
[i
].sets
));
1440 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1442 return cmd_buffer
->record_result
;
1446 tu_AllocateCommandBuffers(VkDevice _device
,
1447 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1448 VkCommandBuffer
*pCommandBuffers
)
1450 TU_FROM_HANDLE(tu_device
, device
, _device
);
1451 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1453 VkResult result
= VK_SUCCESS
;
1456 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1458 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1459 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1460 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1462 list_del(&cmd_buffer
->pool_link
);
1463 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1465 result
= tu_reset_cmd_buffer(cmd_buffer
);
1466 cmd_buffer
->level
= pAllocateInfo
->level
;
1468 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1470 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1471 &pCommandBuffers
[i
]);
1473 if (result
!= VK_SUCCESS
)
1477 if (result
!= VK_SUCCESS
) {
1478 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1481 /* From the Vulkan 1.0.66 spec:
1483 * "vkAllocateCommandBuffers can be used to create multiple
1484 * command buffers. If the creation of any of those command
1485 * buffers fails, the implementation must destroy all
1486 * successfully created command buffer objects from this
1487 * command, set all entries of the pCommandBuffers array to
1488 * NULL and return the error."
1490 memset(pCommandBuffers
, 0,
1491 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1498 tu_FreeCommandBuffers(VkDevice device
,
1499 VkCommandPool commandPool
,
1500 uint32_t commandBufferCount
,
1501 const VkCommandBuffer
*pCommandBuffers
)
1503 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1504 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1507 if (cmd_buffer
->pool
) {
1508 list_del(&cmd_buffer
->pool_link
);
1509 list_addtail(&cmd_buffer
->pool_link
,
1510 &cmd_buffer
->pool
->free_cmd_buffers
);
1512 tu_cmd_buffer_destroy(cmd_buffer
);
1518 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1519 VkCommandBufferResetFlags flags
)
1521 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1522 return tu_reset_cmd_buffer(cmd_buffer
);
1525 /* Initialize the cache, assuming all necessary flushes have happened but *not*
1529 tu_cache_init(struct tu_cache_state
*cache
)
1531 cache
->flush_bits
= 0;
1532 cache
->pending_flush_bits
= TU_CMD_FLAG_ALL_INVALIDATE
;
1536 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1537 const VkCommandBufferBeginInfo
*pBeginInfo
)
1539 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1540 VkResult result
= VK_SUCCESS
;
1542 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1543 /* If the command buffer has already been resetted with
1544 * vkResetCommandBuffer, no need to do it again.
1546 result
= tu_reset_cmd_buffer(cmd_buffer
);
1547 if (result
!= VK_SUCCESS
)
1551 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1552 cmd_buffer
->state
.index_size
= 0xff; /* dirty restart index */
1554 tu_cache_init(&cmd_buffer
->state
.cache
);
1555 tu_cache_init(&cmd_buffer
->state
.renderpass_cache
);
1556 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1558 tu_cs_begin(&cmd_buffer
->cs
);
1559 tu_cs_begin(&cmd_buffer
->draw_cs
);
1560 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1562 /* setup initial configuration into command buffer */
1563 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1564 switch (cmd_buffer
->queue_family_index
) {
1565 case TU_QUEUE_GENERAL
:
1566 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1571 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1572 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1573 assert(pBeginInfo
->pInheritanceInfo
);
1574 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1575 cmd_buffer
->state
.subpass
=
1576 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1578 /* When executing in the middle of another command buffer, the CCU
1581 cmd_buffer
->state
.ccu_state
= TU_CMD_CCU_UNKNOWN
;
1585 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1590 /* Sets vertex buffers to HW binding points. We emit VBs in SDS (so that bin
1591 * rendering can skip over unused state), so we need to collect all the
1592 * bindings together into a single state emit at draw time.
1595 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1596 uint32_t firstBinding
,
1597 uint32_t bindingCount
,
1598 const VkBuffer
*pBuffers
,
1599 const VkDeviceSize
*pOffsets
)
1601 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1603 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1605 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1606 struct tu_buffer
*buf
= tu_buffer_from_handle(pBuffers
[i
]);
1608 cmd
->state
.vb
.buffers
[firstBinding
+ i
] = buf
;
1609 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1611 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1614 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1618 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1620 VkDeviceSize offset
,
1621 VkIndexType indexType
)
1623 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1624 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1628 uint32_t index_size
, index_shift
, restart_index
;
1630 switch (indexType
) {
1631 case VK_INDEX_TYPE_UINT16
:
1632 index_size
= INDEX4_SIZE_16_BIT
;
1634 restart_index
= 0xffff;
1636 case VK_INDEX_TYPE_UINT32
:
1637 index_size
= INDEX4_SIZE_32_BIT
;
1639 restart_index
= 0xffffffff;
1641 case VK_INDEX_TYPE_UINT8_EXT
:
1642 index_size
= INDEX4_SIZE_8_BIT
;
1644 restart_index
= 0xff;
1647 unreachable("invalid VkIndexType");
1650 /* initialize/update the restart index */
1651 if (cmd
->state
.index_size
!= index_size
)
1652 tu_cs_emit_regs(&cmd
->draw_cs
, A6XX_PC_RESTART_INDEX(restart_index
));
1654 assert(buf
->size
>= offset
);
1656 cmd
->state
.index_va
= buf
->bo
->iova
+ buf
->bo_offset
+ offset
;
1657 cmd
->state
.max_index_count
= (buf
->size
- offset
) >> index_shift
;
1658 cmd
->state
.index_size
= index_size
;
1660 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1664 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1665 VkPipelineBindPoint pipelineBindPoint
,
1666 VkPipelineLayout _layout
,
1668 uint32_t descriptorSetCount
,
1669 const VkDescriptorSet
*pDescriptorSets
,
1670 uint32_t dynamicOffsetCount
,
1671 const uint32_t *pDynamicOffsets
)
1673 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1674 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1675 unsigned dyn_idx
= 0;
1677 struct tu_descriptor_state
*descriptors_state
=
1678 tu_get_descriptors_state(cmd
, pipelineBindPoint
);
1680 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1681 unsigned idx
= i
+ firstSet
;
1682 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1684 descriptors_state
->sets
[idx
] = set
;
1686 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1687 /* update the contents of the dynamic descriptor set */
1688 unsigned src_idx
= j
;
1689 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1690 assert(dyn_idx
< dynamicOffsetCount
);
1693 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1695 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1696 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1698 /* Patch the storage/uniform descriptors right away. */
1699 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1700 /* Note: we can assume here that the addition won't roll over and
1701 * change the SIZE field.
1703 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1708 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1709 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1710 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1717 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
1718 if (set
->buffers
[j
]) {
1719 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
1720 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1724 if (set
->size
> 0) {
1725 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
1726 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1729 assert(dyn_idx
== dynamicOffsetCount
);
1731 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
, hlsq_invalidate_value
;
1732 uint64_t addr
[MAX_SETS
+ 1] = {};
1733 struct tu_cs
*cs
, state_cs
;
1735 for (uint32_t i
= 0; i
< MAX_SETS
; i
++) {
1736 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
1738 addr
[i
] = set
->va
| 3;
1741 if (layout
->dynamic_offset_count
) {
1742 /* allocate and fill out dynamic descriptor set */
1743 struct tu_cs_memory dynamic_desc_set
;
1744 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, layout
->dynamic_offset_count
,
1745 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
1746 assert(result
== VK_SUCCESS
);
1748 memcpy(dynamic_desc_set
.map
, descriptors_state
->dynamic_descriptors
,
1749 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
1750 addr
[MAX_SETS
] = dynamic_desc_set
.iova
| 3;
1753 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1754 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
1755 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
1756 hlsq_invalidate_value
= A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(0x1f);
1758 cmd
->state
.desc_sets
= tu_cs_draw_state(&cmd
->sub_cs
, &state_cs
, 24);
1759 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESC_SETS_LOAD
| TU_CMD_DIRTY_SHADER_CONSTS
;
1762 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1764 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
1765 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
1766 hlsq_invalidate_value
= A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(0x1f);
1768 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
1772 tu_cs_emit_pkt4(cs
, sp_bindless_base_reg
, 10);
1773 tu_cs_emit_array(cs
, (const uint32_t*) addr
, 10);
1774 tu_cs_emit_pkt4(cs
, hlsq_bindless_base_reg
, 10);
1775 tu_cs_emit_array(cs
, (const uint32_t*) addr
, 10);
1776 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(.dword
= hlsq_invalidate_value
));
1778 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1779 assert(cs
->cur
== cs
->end
); /* validate draw state size */
1780 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
1781 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets
);
1785 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1786 uint32_t firstBinding
,
1787 uint32_t bindingCount
,
1788 const VkBuffer
*pBuffers
,
1789 const VkDeviceSize
*pOffsets
,
1790 const VkDeviceSize
*pSizes
)
1792 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1793 struct tu_cs
*cs
= &cmd
->draw_cs
;
1795 /* using COND_REG_EXEC for xfb commands matches the blob behavior
1796 * presumably there isn't any benefit using a draw state when the
1797 * condition is (SYSMEM | BINNING)
1799 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1800 CP_COND_REG_EXEC_0_SYSMEM
|
1801 CP_COND_REG_EXEC_0_BINNING
);
1803 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1804 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1805 uint64_t iova
= buf
->bo
->iova
+ pOffsets
[i
];
1806 uint32_t size
= buf
->bo
->size
- pOffsets
[i
];
1807 uint32_t idx
= i
+ firstBinding
;
1809 if (pSizes
&& pSizes
[i
] != VK_WHOLE_SIZE
)
1812 /* BUFFER_BASE is 32-byte aligned, add remaining offset to BUFFER_OFFSET */
1813 uint32_t offset
= iova
& 0x1f;
1814 iova
&= ~(uint64_t) 0x1f;
1816 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_BASE(idx
), 3);
1817 tu_cs_emit_qw(cs
, iova
);
1818 tu_cs_emit(cs
, size
+ offset
);
1820 cmd
->state
.streamout_offset
[idx
] = offset
;
1822 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_WRITE
);
1825 tu_cond_exec_end(cs
);
1829 tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1830 uint32_t firstCounterBuffer
,
1831 uint32_t counterBufferCount
,
1832 const VkBuffer
*pCounterBuffers
,
1833 const VkDeviceSize
*pCounterBufferOffsets
)
1835 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1836 struct tu_cs
*cs
= &cmd
->draw_cs
;
1838 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1839 CP_COND_REG_EXEC_0_SYSMEM
|
1840 CP_COND_REG_EXEC_0_BINNING
);
1842 /* TODO: only update offset for active buffers */
1843 for (uint32_t i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
1844 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, cmd
->state
.streamout_offset
[i
]));
1846 for (uint32_t i
= 0; i
< counterBufferCount
; i
++) {
1847 uint32_t idx
= firstCounterBuffer
+ i
;
1848 uint32_t offset
= cmd
->state
.streamout_offset
[idx
];
1850 if (!pCounterBuffers
[i
])
1853 TU_FROM_HANDLE(tu_buffer
, buf
, pCounterBuffers
[i
]);
1855 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1857 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1858 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx
)) |
1859 CP_MEM_TO_REG_0_UNK31
|
1860 CP_MEM_TO_REG_0_CNT(1));
1861 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ pCounterBufferOffsets
[i
]);
1864 tu_cs_emit_pkt7(cs
, CP_REG_RMW
, 3);
1865 tu_cs_emit(cs
, CP_REG_RMW_0_DST_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx
)) |
1866 CP_REG_RMW_0_SRC1_ADD
);
1867 tu_cs_emit_qw(cs
, 0xffffffff);
1868 tu_cs_emit_qw(cs
, offset
);
1872 tu_cond_exec_end(cs
);
1875 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1876 uint32_t firstCounterBuffer
,
1877 uint32_t counterBufferCount
,
1878 const VkBuffer
*pCounterBuffers
,
1879 const VkDeviceSize
*pCounterBufferOffsets
)
1881 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1882 struct tu_cs
*cs
= &cmd
->draw_cs
;
1884 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1885 CP_COND_REG_EXEC_0_SYSMEM
|
1886 CP_COND_REG_EXEC_0_BINNING
);
1888 /* TODO: only flush buffers that need to be flushed */
1889 for (uint32_t i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
1890 /* note: FLUSH_BASE is always the same, so it could go in init_hw()? */
1891 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_FLUSH_BASE(i
), 2);
1892 tu_cs_emit_qw(cs
, global_iova(cmd
, flush_base
[i
]));
1893 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
);
1896 for (uint32_t i
= 0; i
< counterBufferCount
; i
++) {
1897 uint32_t idx
= firstCounterBuffer
+ i
;
1898 uint32_t offset
= cmd
->state
.streamout_offset
[idx
];
1900 if (!pCounterBuffers
[i
])
1903 TU_FROM_HANDLE(tu_buffer
, buf
, pCounterBuffers
[i
]);
1905 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_WRITE
);
1907 /* VPC_SO_FLUSH_BASE has dwords counter, but counter should be in bytes */
1908 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1909 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1910 CP_MEM_TO_REG_0_SHIFT_BY_2
|
1912 CP_MEM_TO_REG_0_UNK31
|
1913 CP_MEM_TO_REG_0_CNT(1));
1914 tu_cs_emit_qw(cs
, global_iova(cmd
, flush_base
[idx
]));
1917 tu_cs_emit_pkt7(cs
, CP_REG_RMW
, 3);
1918 tu_cs_emit(cs
, CP_REG_RMW_0_DST_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1919 CP_REG_RMW_0_SRC1_ADD
);
1920 tu_cs_emit_qw(cs
, 0xffffffff);
1921 tu_cs_emit_qw(cs
, -offset
);
1924 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1925 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1926 CP_REG_TO_MEM_0_CNT(1));
1927 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ pCounterBufferOffsets
[i
]);
1930 tu_cond_exec_end(cs
);
1932 cmd
->state
.xfb_used
= true;
1936 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1937 VkPipelineLayout layout
,
1938 VkShaderStageFlags stageFlags
,
1941 const void *pValues
)
1943 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1944 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1945 cmd
->state
.dirty
|= TU_CMD_DIRTY_SHADER_CONSTS
;
1948 /* Flush everything which has been made available but we haven't actually
1952 tu_flush_all_pending(struct tu_cache_state
*cache
)
1954 cache
->flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
1955 cache
->pending_flush_bits
&= ~TU_CMD_FLAG_ALL_FLUSH
;
1959 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1961 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1963 /* We currently flush CCU at the end of the command buffer, like
1964 * what the blob does. There's implicit synchronization around every
1965 * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
1966 * know yet if this command buffer will be the last in the submit so we
1967 * have to defensively flush everything else.
1969 * TODO: We could definitely do better than this, since these flushes
1970 * aren't required by Vulkan, but we'd need kernel support to do that.
1971 * Ideally, we'd like the kernel to flush everything afterwards, so that we
1972 * wouldn't have to do any flushes here, and when submitting multiple
1973 * command buffers there wouldn't be any unnecessary flushes in between.
1975 if (cmd_buffer
->state
.pass
) {
1976 tu_flush_all_pending(&cmd_buffer
->state
.renderpass_cache
);
1977 tu_emit_cache_flush_renderpass(cmd_buffer
, &cmd_buffer
->draw_cs
);
1979 tu_flush_all_pending(&cmd_buffer
->state
.cache
);
1980 cmd_buffer
->state
.cache
.flush_bits
|=
1981 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
1982 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
1983 tu_emit_cache_flush(cmd_buffer
, &cmd_buffer
->cs
);
1986 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->global_bo
,
1987 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1989 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
1990 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
1991 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1994 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
1995 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
1996 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1999 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
2000 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
2001 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2004 tu_cs_end(&cmd_buffer
->cs
);
2005 tu_cs_end(&cmd_buffer
->draw_cs
);
2006 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
2008 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
2010 return cmd_buffer
->record_result
;
2014 tu_cmd_dynamic_state(struct tu_cmd_buffer
*cmd
, uint32_t id
, uint32_t size
)
2018 assert(id
< ARRAY_SIZE(cmd
->state
.dynamic_state
));
2019 cmd
->state
.dynamic_state
[id
] = tu_cs_draw_state(&cmd
->sub_cs
, &cs
, size
);
2021 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
2022 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DYNAMIC
+ id
, cmd
->state
.dynamic_state
[id
]);
2028 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
2029 VkPipelineBindPoint pipelineBindPoint
,
2030 VkPipeline _pipeline
)
2032 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2033 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2035 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2036 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2037 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2040 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
) {
2041 cmd
->state
.compute_pipeline
= pipeline
;
2042 tu_cs_emit_state_ib(&cmd
->cs
, pipeline
->program
.state
);
2046 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
);
2048 cmd
->state
.pipeline
= pipeline
;
2049 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESC_SETS_LOAD
| TU_CMD_DIRTY_SHADER_CONSTS
;
2051 struct tu_cs
*cs
= &cmd
->draw_cs
;
2052 uint32_t mask
= ~pipeline
->dynamic_state_mask
& BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT
);
2055 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (7 + util_bitcount(mask
)));
2056 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state
);
2057 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state
);
2058 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state
);
2059 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state
);
2060 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast_state
);
2061 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS
, pipeline
->ds_state
);
2062 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend_state
);
2063 for_each_bit(i
, mask
)
2064 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
, pipeline
->dynamic_state
[i
]);
2066 /* If the new pipeline requires more VBs than we had previously set up, we
2067 * need to re-emit them in SDS. If it requires the same set or fewer, we
2068 * can just re-use the old SDS.
2070 if (pipeline
->vi
.bindings_used
& ~cmd
->vertex_bindings_set
)
2071 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
2073 /* dynamic linewidth state depends pipeline state's gras_su_cntl
2074 * so the dynamic state ib must be updated when pipeline changes
2076 if (pipeline
->dynamic_state_mask
& BIT(VK_DYNAMIC_STATE_LINE_WIDTH
)) {
2077 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2079 cmd
->state
.dynamic_gras_su_cntl
&= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2080 cmd
->state
.dynamic_gras_su_cntl
|= pipeline
->gras_su_cntl
;
2082 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2087 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2088 uint32_t firstViewport
,
2089 uint32_t viewportCount
,
2090 const VkViewport
*pViewports
)
2092 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2093 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_VIEWPORT
, 18);
2095 assert(firstViewport
== 0 && viewportCount
== 1);
2097 tu6_emit_viewport(&cs
, pViewports
);
2101 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2102 uint32_t firstScissor
,
2103 uint32_t scissorCount
,
2104 const VkRect2D
*pScissors
)
2106 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2107 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_SCISSOR
, 3);
2109 assert(firstScissor
== 0 && scissorCount
== 1);
2111 tu6_emit_scissor(&cs
, pScissors
);
2115 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2117 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2118 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2120 cmd
->state
.dynamic_gras_su_cntl
&= ~A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2121 cmd
->state
.dynamic_gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(lineWidth
/ 2.0f
);
2123 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2127 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2128 float depthBiasConstantFactor
,
2129 float depthBiasClamp
,
2130 float depthBiasSlopeFactor
)
2132 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2133 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4);
2135 tu6_emit_depth_bias(&cs
, depthBiasConstantFactor
, depthBiasClamp
, depthBiasSlopeFactor
);
2139 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2140 const float blendConstants
[4])
2142 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2143 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5);
2145 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2146 tu_cs_emit_array(&cs
, (const uint32_t *) blendConstants
, 4);
2150 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2151 float minDepthBounds
,
2152 float maxDepthBounds
)
2154 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2155 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BOUNDS
, 3);
2157 tu_cs_emit_regs(&cs
,
2158 A6XX_RB_Z_BOUNDS_MIN(minDepthBounds
),
2159 A6XX_RB_Z_BOUNDS_MAX(maxDepthBounds
));
2163 update_stencil_mask(uint32_t *value
, VkStencilFaceFlags face
, uint32_t mask
)
2165 if (face
& VK_STENCIL_FACE_FRONT_BIT
)
2166 *value
= (*value
& 0xff00) | (mask
& 0xff);
2167 if (face
& VK_STENCIL_FACE_BACK_BIT
)
2168 *value
= (*value
& 0xff) | (mask
& 0xff) << 8;
2172 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2173 VkStencilFaceFlags faceMask
,
2174 uint32_t compareMask
)
2176 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2177 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2);
2179 update_stencil_mask(&cmd
->state
.dynamic_stencil_mask
, faceMask
, compareMask
);
2181 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.dword
= cmd
->state
.dynamic_stencil_mask
));
2185 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2186 VkStencilFaceFlags faceMask
,
2189 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2190 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2);
2192 update_stencil_mask(&cmd
->state
.dynamic_stencil_wrmask
, faceMask
, writeMask
);
2194 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.dword
= cmd
->state
.dynamic_stencil_wrmask
));
2198 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2199 VkStencilFaceFlags faceMask
,
2202 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2203 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2);
2205 update_stencil_mask(&cmd
->state
.dynamic_stencil_ref
, faceMask
, reference
);
2207 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.dword
= cmd
->state
.dynamic_stencil_ref
));
2211 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer
,
2212 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
2214 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2215 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
, 9);
2217 assert(pSampleLocationsInfo
);
2219 tu6_emit_sample_locations(&cs
, pSampleLocationsInfo
);
2223 tu_flush_for_access(struct tu_cache_state
*cache
,
2224 enum tu_cmd_access_mask src_mask
,
2225 enum tu_cmd_access_mask dst_mask
)
2227 enum tu_cmd_flush_bits flush_bits
= 0;
2229 if (src_mask
& TU_ACCESS_HOST_WRITE
) {
2230 /* Host writes are always visible to CP, so only invalidate GPU caches */
2231 cache
->pending_flush_bits
|= TU_CMD_FLAG_GPU_INVALIDATE
;
2234 if (src_mask
& TU_ACCESS_SYSMEM_WRITE
) {
2235 /* Invalidate CP and 2D engine (make it do WFI + WFM if necessary) as
2238 cache
->pending_flush_bits
|= TU_CMD_FLAG_ALL_INVALIDATE
;
2241 if (src_mask
& TU_ACCESS_CP_WRITE
) {
2242 /* Flush the CP write queue. However a WFI shouldn't be necessary as
2243 * WAIT_MEM_WRITES should cover it.
2245 cache
->pending_flush_bits
|=
2246 TU_CMD_FLAG_WAIT_MEM_WRITES
|
2247 TU_CMD_FLAG_GPU_INVALIDATE
|
2248 TU_CMD_FLAG_WAIT_FOR_ME
;
2251 #define SRC_FLUSH(domain, flush, invalidate) \
2252 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
2253 cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
2254 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2257 SRC_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2258 SRC_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2259 SRC_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2263 #define SRC_INCOHERENT_FLUSH(domain, flush, invalidate) \
2264 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
2265 flush_bits |= TU_CMD_FLAG_##flush; \
2266 cache->pending_flush_bits |= \
2267 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2270 SRC_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2271 SRC_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2273 #undef SRC_INCOHERENT_FLUSH
2275 /* Treat host & sysmem write accesses the same, since the kernel implicitly
2276 * drains the queue before signalling completion to the host.
2278 if (dst_mask
& (TU_ACCESS_SYSMEM_READ
| TU_ACCESS_SYSMEM_WRITE
|
2279 TU_ACCESS_HOST_READ
| TU_ACCESS_HOST_WRITE
)) {
2280 flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
2283 #define DST_FLUSH(domain, flush, invalidate) \
2284 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2285 TU_ACCESS_##domain##_WRITE)) { \
2286 flush_bits |= cache->pending_flush_bits & \
2287 (TU_CMD_FLAG_##invalidate | \
2288 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2291 DST_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2292 DST_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2293 DST_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2297 #define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
2298 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2299 TU_ACCESS_##domain##_WRITE)) { \
2300 flush_bits |= TU_CMD_FLAG_##invalidate | \
2301 (cache->pending_flush_bits & \
2302 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2305 DST_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2306 DST_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2308 #undef DST_INCOHERENT_FLUSH
2310 if (dst_mask
& TU_ACCESS_WFI_READ
) {
2311 flush_bits
|= cache
->pending_flush_bits
&
2312 (TU_CMD_FLAG_ALL_FLUSH
| TU_CMD_FLAG_WAIT_FOR_IDLE
);
2315 if (dst_mask
& TU_ACCESS_WFM_READ
) {
2316 flush_bits
|= cache
->pending_flush_bits
&
2317 (TU_CMD_FLAG_ALL_FLUSH
| TU_CMD_FLAG_WAIT_FOR_ME
);
2320 cache
->flush_bits
|= flush_bits
;
2321 cache
->pending_flush_bits
&= ~flush_bits
;
2324 static enum tu_cmd_access_mask
2325 vk2tu_access(VkAccessFlags flags
, bool gmem
)
2327 enum tu_cmd_access_mask mask
= 0;
2329 /* If the GPU writes a buffer that is then read by an indirect draw
2330 * command, we theoretically need to emit a WFI to wait for any cache
2331 * flushes, and then a WAIT_FOR_ME to wait on the CP for the WFI to
2332 * complete. Waiting for the WFI to complete is performed as part of the
2333 * draw by the firmware, so we just need to execute the WFI.
2335 * Transform feedback counters are read via CP_MEM_TO_REG, which implicitly
2336 * does CP_WAIT_FOR_ME, but we still need a WFI if the GPU writes it.
2339 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
|
2340 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
|
2341 VK_ACCESS_MEMORY_READ_BIT
)) {
2342 mask
|= TU_ACCESS_WFI_READ
;
2346 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
| /* Read performed by CP */
2347 VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
| /* Read performed by CP */
2348 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
| /* Read performed by CP */
2349 VK_ACCESS_MEMORY_READ_BIT
)) {
2350 mask
|= TU_ACCESS_SYSMEM_READ
;
2354 (VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
|
2355 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2356 mask
|= TU_ACCESS_CP_WRITE
;
2360 (VK_ACCESS_HOST_READ_BIT
|
2361 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2362 mask
|= TU_ACCESS_HOST_READ
;
2366 (VK_ACCESS_HOST_WRITE_BIT
|
2367 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2368 mask
|= TU_ACCESS_HOST_WRITE
;
2372 (VK_ACCESS_INDEX_READ_BIT
| /* Read performed by PC, I think */
2373 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
| /* Read performed by VFD */
2374 VK_ACCESS_UNIFORM_READ_BIT
| /* Read performed by SP */
2375 /* TODO: Is there a no-cache bit for textures so that we can ignore
2378 VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
| /* Read performed by TP */
2379 VK_ACCESS_SHADER_READ_BIT
| /* Read perfomed by SP/TP */
2380 VK_ACCESS_MEMORY_READ_BIT
)) {
2381 mask
|= TU_ACCESS_UCHE_READ
;
2385 (VK_ACCESS_SHADER_WRITE_BIT
| /* Write performed by SP */
2386 VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
| /* Write performed by VPC */
2387 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2388 mask
|= TU_ACCESS_UCHE_WRITE
;
2391 /* When using GMEM, the CCU is always flushed automatically to GMEM, and
2392 * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
2393 * previous writes in sysmem mode when transitioning to GMEM. Therefore we
2394 * can ignore CCU and pretend that color attachments and transfers use
2399 (VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
|
2400 VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT
|
2401 VK_ACCESS_MEMORY_READ_BIT
)) {
2403 mask
|= TU_ACCESS_SYSMEM_READ
;
2405 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_READ
;
2409 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
|
2410 VK_ACCESS_MEMORY_READ_BIT
)) {
2412 mask
|= TU_ACCESS_SYSMEM_READ
;
2414 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
;
2418 (VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
|
2419 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2421 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2423 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2428 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
|
2429 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2431 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2433 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2437 /* When the dst access is a transfer read/write, it seems we sometimes need
2438 * to insert a WFI after any flushes, to guarantee that the flushes finish
2439 * before the 2D engine starts. However the opposite (i.e. a WFI after
2440 * CP_BLIT and before any subsequent flush) does not seem to be needed, and
2441 * the blob doesn't emit such a WFI.
2445 (VK_ACCESS_TRANSFER_WRITE_BIT
|
2446 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2448 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2450 mask
|= TU_ACCESS_CCU_COLOR_WRITE
;
2452 mask
|= TU_ACCESS_WFI_READ
;
2456 (VK_ACCESS_TRANSFER_READ_BIT
| /* Access performed by TP */
2457 VK_ACCESS_MEMORY_READ_BIT
)) {
2458 mask
|= TU_ACCESS_UCHE_READ
| TU_ACCESS_WFI_READ
;
2466 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2467 uint32_t commandBufferCount
,
2468 const VkCommandBuffer
*pCmdBuffers
)
2470 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2473 assert(commandBufferCount
> 0);
2475 /* Emit any pending flushes. */
2476 if (cmd
->state
.pass
) {
2477 tu_flush_all_pending(&cmd
->state
.renderpass_cache
);
2478 tu_emit_cache_flush_renderpass(cmd
, &cmd
->draw_cs
);
2480 tu_flush_all_pending(&cmd
->state
.cache
);
2481 tu_emit_cache_flush(cmd
, &cmd
->cs
);
2484 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2485 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2487 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2488 if (result
!= VK_SUCCESS
) {
2489 cmd
->record_result
= result
;
2493 if (secondary
->usage_flags
&
2494 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2495 assert(tu_cs_is_empty(&secondary
->cs
));
2497 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2498 if (result
!= VK_SUCCESS
) {
2499 cmd
->record_result
= result
;
2503 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2504 &secondary
->draw_epilogue_cs
);
2505 if (result
!= VK_SUCCESS
) {
2506 cmd
->record_result
= result
;
2510 if (secondary
->has_tess
)
2511 cmd
->has_tess
= true;
2513 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2514 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2516 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2517 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2518 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2521 tu_cs_add_entries(&cmd
->cs
, &secondary
->cs
);
2524 cmd
->state
.index_size
= secondary
->state
.index_size
; /* for restart index update */
2526 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2528 /* After executing secondary command buffers, there may have been arbitrary
2529 * flushes executed, so when we encounter a pipeline barrier with a
2530 * srcMask, we have to assume that we need to invalidate. Therefore we need
2531 * to re-initialize the cache with all pending invalidate bits set.
2533 if (cmd
->state
.pass
) {
2534 tu_cache_init(&cmd
->state
.renderpass_cache
);
2536 tu_cache_init(&cmd
->state
.cache
);
2541 tu_CreateCommandPool(VkDevice _device
,
2542 const VkCommandPoolCreateInfo
*pCreateInfo
,
2543 const VkAllocationCallbacks
*pAllocator
,
2544 VkCommandPool
*pCmdPool
)
2546 TU_FROM_HANDLE(tu_device
, device
, _device
);
2547 struct tu_cmd_pool
*pool
;
2549 pool
= vk_object_alloc(&device
->vk
, pAllocator
, sizeof(*pool
),
2550 VK_OBJECT_TYPE_COMMAND_POOL
);
2552 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2555 pool
->alloc
= *pAllocator
;
2557 pool
->alloc
= device
->vk
.alloc
;
2559 list_inithead(&pool
->cmd_buffers
);
2560 list_inithead(&pool
->free_cmd_buffers
);
2562 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2564 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2570 tu_DestroyCommandPool(VkDevice _device
,
2571 VkCommandPool commandPool
,
2572 const VkAllocationCallbacks
*pAllocator
)
2574 TU_FROM_HANDLE(tu_device
, device
, _device
);
2575 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2580 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2581 &pool
->cmd_buffers
, pool_link
)
2583 tu_cmd_buffer_destroy(cmd_buffer
);
2586 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2587 &pool
->free_cmd_buffers
, pool_link
)
2589 tu_cmd_buffer_destroy(cmd_buffer
);
2592 vk_object_free(&device
->vk
, pAllocator
, pool
);
2596 tu_ResetCommandPool(VkDevice device
,
2597 VkCommandPool commandPool
,
2598 VkCommandPoolResetFlags flags
)
2600 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2603 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2606 result
= tu_reset_cmd_buffer(cmd_buffer
);
2607 if (result
!= VK_SUCCESS
)
2615 tu_TrimCommandPool(VkDevice device
,
2616 VkCommandPool commandPool
,
2617 VkCommandPoolTrimFlags flags
)
2619 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2624 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2625 &pool
->free_cmd_buffers
, pool_link
)
2627 tu_cmd_buffer_destroy(cmd_buffer
);
2632 tu_subpass_barrier(struct tu_cmd_buffer
*cmd_buffer
,
2633 const struct tu_subpass_barrier
*barrier
,
2636 /* Note: we don't know until the end of the subpass whether we'll use
2637 * sysmem, so assume sysmem here to be safe.
2639 struct tu_cache_state
*cache
=
2640 external
? &cmd_buffer
->state
.cache
: &cmd_buffer
->state
.renderpass_cache
;
2641 enum tu_cmd_access_mask src_flags
=
2642 vk2tu_access(barrier
->src_access_mask
, false);
2643 enum tu_cmd_access_mask dst_flags
=
2644 vk2tu_access(barrier
->dst_access_mask
, false);
2646 if (barrier
->incoherent_ccu_color
)
2647 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2648 if (barrier
->incoherent_ccu_depth
)
2649 src_flags
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2651 tu_flush_for_access(cache
, src_flags
, dst_flags
);
2655 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2656 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2657 VkSubpassContents contents
)
2659 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2660 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2661 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2663 cmd
->state
.pass
= pass
;
2664 cmd
->state
.subpass
= pass
->subpasses
;
2665 cmd
->state
.framebuffer
= fb
;
2666 cmd
->state
.render_area
= pRenderPassBegin
->renderArea
;
2668 tu_cmd_prepare_tile_store_ib(cmd
);
2670 /* Note: because this is external, any flushes will happen before draw_cs
2671 * gets called. However deferred flushes could have to happen later as part
2674 tu_subpass_barrier(cmd
, &pass
->subpasses
[0].start_barrier
, true);
2675 cmd
->state
.renderpass_cache
.pending_flush_bits
=
2676 cmd
->state
.cache
.pending_flush_bits
;
2677 cmd
->state
.renderpass_cache
.flush_bits
= 0;
2679 tu_emit_renderpass_begin(cmd
, pRenderPassBegin
);
2681 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2682 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2683 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2684 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2686 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2688 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2689 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2690 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2691 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2694 cmd
->state
.dirty
|= TU_CMD_DIRTY_DRAW_STATE
;
2698 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2699 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2700 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2702 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2703 pSubpassBeginInfo
->contents
);
2707 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2709 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2710 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2711 struct tu_cs
*cs
= &cmd
->draw_cs
;
2713 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2715 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2717 if (subpass
->resolve_attachments
) {
2718 tu6_emit_blit_scissor(cmd
, cs
, true);
2720 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2721 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2722 if (a
== VK_ATTACHMENT_UNUSED
)
2725 tu_store_gmem_attachment(cmd
, cs
, a
,
2726 subpass
->color_attachments
[i
].attachment
);
2728 if (pass
->attachments
[a
].gmem_offset
< 0)
2732 * check if the resolved attachment is needed by later subpasses,
2733 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2735 tu_finishme("missing GMEM->GMEM resolve path\n");
2736 tu_load_gmem_attachment(cmd
, cs
, a
, true);
2740 tu_cond_exec_end(cs
);
2742 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2744 tu6_emit_sysmem_resolves(cmd
, cs
, subpass
);
2746 tu_cond_exec_end(cs
);
2748 /* Handle dependencies for the next subpass */
2749 tu_subpass_barrier(cmd
, &cmd
->state
.subpass
->start_barrier
, false);
2751 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2752 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2753 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2754 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2755 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2757 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2761 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2762 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2763 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2765 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2769 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2770 struct tu_descriptor_state
*descriptors_state
,
2771 gl_shader_stage type
,
2772 uint32_t *push_constants
)
2774 const struct tu_program_descriptor_linkage
*link
=
2775 &pipeline
->program
.link
[type
];
2776 const struct ir3_ubo_analysis_state
*state
= &link
->const_state
.ubo_state
;
2778 if (link
->push_consts
.count
> 0) {
2779 unsigned num_units
= link
->push_consts
.count
;
2780 unsigned offset
= link
->push_consts
.lo
;
2781 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2782 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2783 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2784 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2785 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2786 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2789 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2790 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2793 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2794 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2795 uint32_t offset
= state
->range
[i
].start
;
2797 /* and even if the start of the const buffer is before
2798 * first_immediate, the end may not be:
2800 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2805 /* things should be aligned to vec4: */
2806 debug_assert((state
->range
[i
].offset
% 16) == 0);
2807 debug_assert((size
% 16) == 0);
2808 debug_assert((offset
% 16) == 0);
2810 /* Dig out the descriptor from the descriptor state and read the VA from
2813 assert(state
->range
[i
].ubo
.bindless
);
2814 uint32_t *base
= state
->range
[i
].ubo
.bindless_base
== MAX_SETS
?
2815 descriptors_state
->dynamic_descriptors
:
2816 descriptors_state
->sets
[state
->range
[i
].ubo
.bindless_base
]->mapped_ptr
;
2817 unsigned block
= state
->range
[i
].ubo
.block
;
2818 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2819 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2822 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2823 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2824 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2825 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2826 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2827 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2828 tu_cs_emit_qw(cs
, va
+ offset
);
2832 static struct tu_draw_state
2833 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2834 const struct tu_pipeline
*pipeline
,
2835 struct tu_descriptor_state
*descriptors_state
,
2836 gl_shader_stage type
)
2839 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2841 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2843 return tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2846 static struct tu_draw_state
2847 tu6_emit_vertex_buffers(struct tu_cmd_buffer
*cmd
,
2848 const struct tu_pipeline
*pipeline
)
2851 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 4 * MAX_VBS
, &cs
);
2854 for_each_bit(binding
, pipeline
->vi
.bindings_used
) {
2855 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2856 const VkDeviceSize offset
= buf
->bo_offset
+
2857 cmd
->state
.vb
.offsets
[binding
];
2859 tu_cs_emit_regs(&cs
,
2860 A6XX_VFD_FETCH_BASE(binding
, .bo
= buf
->bo
, .bo_offset
= offset
),
2861 A6XX_VFD_FETCH_SIZE(binding
, buf
->size
- offset
));
2865 cmd
->vertex_bindings_set
= pipeline
->vi
.bindings_used
;
2867 return tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2871 get_tess_param_bo_size(const struct tu_pipeline
*pipeline
,
2872 uint32_t draw_count
)
2874 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
2875 * Still not sure what to do here, so just allocate a reasonably large
2876 * BO and hope for the best for now. */
2880 /* the tess param BO is pipeline->tess.param_stride bytes per patch,
2881 * which includes both the per-vertex outputs and per-patch outputs
2882 * build_primitive_map in ir3 calculates this stride
2884 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
2885 uint32_t num_patches
= draw_count
/ verts_per_patch
;
2886 return num_patches
* pipeline
->tess
.param_stride
;
2890 get_tess_factor_bo_size(const struct tu_pipeline
*pipeline
,
2891 uint32_t draw_count
)
2893 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
2894 * Still not sure what to do here, so just allocate a reasonably large
2895 * BO and hope for the best for now. */
2899 /* Each distinct patch gets its own tess factor output. */
2900 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
2901 uint32_t num_patches
= draw_count
/ verts_per_patch
;
2902 uint32_t factor_stride
;
2903 switch (pipeline
->tess
.patch_type
) {
2904 case IR3_TESS_ISOLINES
:
2907 case IR3_TESS_TRIANGLES
:
2910 case IR3_TESS_QUADS
:
2914 unreachable("bad tessmode");
2916 return factor_stride
* num_patches
;
2920 tu6_emit_tess_consts(struct tu_cmd_buffer
*cmd
,
2921 uint32_t draw_count
,
2922 const struct tu_pipeline
*pipeline
,
2923 struct tu_draw_state
*state
,
2924 uint64_t *factor_iova
)
2927 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 16, &cs
);
2928 if (result
!= VK_SUCCESS
)
2931 uint64_t tess_factor_size
= get_tess_factor_bo_size(pipeline
, draw_count
);
2932 uint64_t tess_param_size
= get_tess_param_bo_size(pipeline
, draw_count
);
2933 uint64_t tess_bo_size
= tess_factor_size
+ tess_param_size
;
2934 if (tess_bo_size
> 0) {
2935 struct tu_bo
*tess_bo
;
2936 result
= tu_get_scratch_bo(cmd
->device
, tess_bo_size
, &tess_bo
);
2937 if (result
!= VK_SUCCESS
)
2940 tu_bo_list_add(&cmd
->bo_list
, tess_bo
,
2941 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2942 uint64_t tess_factor_iova
= tess_bo
->iova
;
2943 uint64_t tess_param_iova
= tess_factor_iova
+ tess_factor_size
;
2945 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2946 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.hs_bo_regid
) |
2947 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2948 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2949 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_HS_SHADER
) |
2950 CP_LOAD_STATE6_0_NUM_UNIT(1));
2951 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2952 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2953 tu_cs_emit_qw(&cs
, tess_param_iova
);
2954 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2956 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2957 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.ds_bo_regid
) |
2958 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2959 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2960 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_DS_SHADER
) |
2961 CP_LOAD_STATE6_0_NUM_UNIT(1));
2962 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2963 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2964 tu_cs_emit_qw(&cs
, tess_param_iova
);
2965 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2967 *factor_iova
= tess_factor_iova
;
2969 *state
= tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2974 tu6_draw_common(struct tu_cmd_buffer
*cmd
,
2977 /* note: draw_count is 0 for indirect */
2978 uint32_t draw_count
)
2980 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
2983 struct tu_descriptor_state
*descriptors_state
=
2984 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
2986 tu_emit_cache_flush_renderpass(cmd
, cs
);
2990 tu_cs_emit_regs(cs
, A6XX_PC_PRIMITIVE_CNTL_0(
2991 .primitive_restart
=
2992 pipeline
->ia
.primitive_restart
&& indexed
,
2993 .tess_upper_left_domain_origin
=
2994 pipeline
->tess
.upper_left_domain_origin
));
2996 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
2997 cmd
->state
.shader_const
[MESA_SHADER_VERTEX
] =
2998 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
);
2999 cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
] =
3000 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_CTRL
);
3001 cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
] =
3002 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_EVAL
);
3003 cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
] =
3004 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
);
3005 cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
] =
3006 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
);
3009 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3010 cmd
->state
.vertex_buffers
= tu6_emit_vertex_buffers(cmd
, pipeline
);
3013 pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
3014 struct tu_draw_state tess_consts
= {};
3016 uint64_t tess_factor_iova
= 0;
3018 cmd
->has_tess
= true;
3019 result
= tu6_emit_tess_consts(cmd
, draw_count
, pipeline
, &tess_consts
, &tess_factor_iova
);
3020 if (result
!= VK_SUCCESS
)
3023 /* this sequence matches what the blob does before every tess draw
3024 * PC_TESSFACTOR_ADDR_LO is a non-context register and needs a wfi
3025 * before writing to it
3029 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_TESSFACTOR_ADDR_LO
, 2);
3030 tu_cs_emit_qw(cs
, tess_factor_iova
);
3032 tu_cs_emit_pkt7(cs
, CP_SET_SUBDRAW_SIZE
, 1);
3033 tu_cs_emit(cs
, draw_count
);
3036 /* for the first draw in a renderpass, re-emit all the draw states
3038 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
3039 * used, then draw states must be re-emitted. note however this only happens
3040 * in the sysmem path, so this can be skipped this for the gmem path (TODO)
3042 * the two input attachment states are excluded because secondary command
3043 * buffer doesn't have a state ib to restore it, and not re-emitting them
3044 * is OK since CmdClearAttachments won't disable/overwrite them
3046 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DRAW_STATE
) {
3047 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (TU_DRAW_STATE_COUNT
- 2));
3049 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state
);
3050 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state
);
3051 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3052 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state
);
3053 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state
);
3054 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast_state
);
3055 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS
, pipeline
->ds_state
);
3056 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend_state
);
3057 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_VERTEX
]);
3058 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
]);
3059 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
]);
3060 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
]);
3061 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
]);
3062 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets
);
3063 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, pipeline
->load_state
);
3064 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers
);
3065 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_PARAMS
, cmd
->state
.vs_params
);
3067 for (uint32_t i
= 0; i
< ARRAY_SIZE(cmd
->state
.dynamic_state
); i
++) {
3068 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
,
3069 ((pipeline
->dynamic_state_mask
& BIT(i
)) ?
3070 cmd
->state
.dynamic_state
[i
] :
3071 pipeline
->dynamic_state
[i
]));
3075 /* emit draw states that were just updated
3076 * note we eventually don't want to have to emit anything here
3078 uint32_t draw_state_count
=
3080 ((cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) ? 5 : 0) +
3081 ((cmd
->state
.dirty
& TU_CMD_DIRTY_DESC_SETS_LOAD
) ? 1 : 0) +
3082 ((cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) ? 1 : 0) +
3085 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_count
);
3087 /* We may need to re-emit tess consts if the current draw call is
3088 * sufficiently larger than the last draw call. */
3090 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3091 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3092 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_VERTEX
]);
3093 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
]);
3094 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
]);
3095 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
]);
3096 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
]);
3098 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESC_SETS_LOAD
)
3099 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, pipeline
->load_state
);
3100 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3101 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers
);
3102 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_PARAMS
, cmd
->state
.vs_params
);
3105 tu_cs_sanity_check(cs
);
3107 /* There are too many graphics dirty bits to list here, so just list the
3108 * bits to preserve instead. The only things not emitted here are
3109 * compute-related state.
3111 cmd
->state
.dirty
&= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
3116 tu_draw_initiator(struct tu_cmd_buffer
*cmd
, enum pc_di_src_sel src_sel
)
3118 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3119 uint32_t initiator
=
3120 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(pipeline
->ia
.primtype
) |
3121 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(src_sel
) |
3122 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(cmd
->state
.index_size
) |
3123 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
);
3125 if (pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
)
3126 initiator
|= CP_DRAW_INDX_OFFSET_0_GS_ENABLE
;
3128 switch (pipeline
->tess
.patch_type
) {
3129 case IR3_TESS_TRIANGLES
:
3130 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_TRIANGLES
) |
3131 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3133 case IR3_TESS_ISOLINES
:
3134 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_ISOLINES
) |
3135 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3138 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
);
3140 case IR3_TESS_QUADS
:
3141 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
) |
3142 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3150 vs_params_offset(struct tu_cmd_buffer
*cmd
)
3152 const struct tu_program_descriptor_linkage
*link
=
3153 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
3154 const struct ir3_const_state
*const_state
= &link
->const_state
;
3156 if (const_state
->offsets
.driver_param
>= link
->constlen
)
3159 /* this layout is required by CP_DRAW_INDIRECT_MULTI */
3160 STATIC_ASSERT(IR3_DP_DRAWID
== 0);
3161 STATIC_ASSERT(IR3_DP_VTXID_BASE
== 1);
3162 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
3164 /* 0 means disabled for CP_DRAW_INDIRECT_MULTI */
3165 assert(const_state
->offsets
.driver_param
!= 0);
3167 return const_state
->offsets
.driver_param
;
3170 static struct tu_draw_state
3171 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
3172 uint32_t vertex_offset
,
3173 uint32_t first_instance
)
3175 uint32_t offset
= vs_params_offset(cmd
);
3178 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 3 + (offset
? 8 : 0), &cs
);
3179 if (result
!= VK_SUCCESS
) {
3180 cmd
->record_result
= result
;
3181 return (struct tu_draw_state
) {};
3184 /* TODO: don't make a new draw state when it doesn't change */
3186 tu_cs_emit_regs(&cs
,
3187 A6XX_VFD_INDEX_OFFSET(vertex_offset
),
3188 A6XX_VFD_INSTANCE_START_OFFSET(first_instance
));
3191 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
3192 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3193 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3194 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3195 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
3196 CP_LOAD_STATE6_0_NUM_UNIT(1));
3201 tu_cs_emit(&cs
, vertex_offset
);
3202 tu_cs_emit(&cs
, first_instance
);
3206 struct tu_cs_entry entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
3207 return (struct tu_draw_state
) {entry
.bo
->iova
+ entry
.offset
, entry
.size
/ 4};
3211 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3212 uint32_t vertexCount
,
3213 uint32_t instanceCount
,
3214 uint32_t firstVertex
,
3215 uint32_t firstInstance
)
3217 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3218 struct tu_cs
*cs
= &cmd
->draw_cs
;
3220 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, firstVertex
, firstInstance
);
3222 tu6_draw_common(cmd
, cs
, false, vertexCount
);
3224 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3225 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3226 tu_cs_emit(cs
, instanceCount
);
3227 tu_cs_emit(cs
, vertexCount
);
3231 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3232 uint32_t indexCount
,
3233 uint32_t instanceCount
,
3234 uint32_t firstIndex
,
3235 int32_t vertexOffset
,
3236 uint32_t firstInstance
)
3238 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3239 struct tu_cs
*cs
= &cmd
->draw_cs
;
3241 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, vertexOffset
, firstInstance
);
3243 tu6_draw_common(cmd
, cs
, true, indexCount
);
3245 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3246 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3247 tu_cs_emit(cs
, instanceCount
);
3248 tu_cs_emit(cs
, indexCount
);
3249 tu_cs_emit(cs
, firstIndex
);
3250 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3251 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3254 /* Various firmware bugs/inconsistencies mean that some indirect draw opcodes
3255 * do not wait for WFI's to complete before executing. Add a WAIT_FOR_ME if
3256 * pending for these opcodes. This may result in a few extra WAIT_FOR_ME's
3257 * with these opcodes, but the alternative would add unnecessary WAIT_FOR_ME's
3258 * before draw opcodes that don't need it.
3261 draw_wfm(struct tu_cmd_buffer
*cmd
)
3263 cmd
->state
.renderpass_cache
.flush_bits
|=
3264 cmd
->state
.renderpass_cache
.pending_flush_bits
& TU_CMD_FLAG_WAIT_FOR_ME
;
3265 cmd
->state
.renderpass_cache
.pending_flush_bits
&= ~TU_CMD_FLAG_WAIT_FOR_ME
;
3269 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3271 VkDeviceSize offset
,
3275 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3276 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3277 struct tu_cs
*cs
= &cmd
->draw_cs
;
3279 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3281 /* The latest known a630_sqe.fw fails to wait for WFI before reading the
3282 * indirect buffer when using CP_DRAW_INDIRECT_MULTI, so we have to fall
3283 * back to CP_WAIT_FOR_ME except for a650 which has a fixed firmware.
3285 * TODO: There may be newer a630_sqe.fw released in the future which fixes
3286 * this, if so we should detect it and avoid this workaround.
3288 if (cmd
->device
->physical_device
->gpu_id
!= 650)
3291 tu6_draw_common(cmd
, cs
, false, 0);
3293 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 6);
3294 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3295 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL
) |
3296 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3297 tu_cs_emit(cs
, drawCount
);
3298 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3299 tu_cs_emit(cs
, stride
);
3301 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3305 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3307 VkDeviceSize offset
,
3311 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3312 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3313 struct tu_cs
*cs
= &cmd
->draw_cs
;
3315 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3317 if (cmd
->device
->physical_device
->gpu_id
!= 650)
3320 tu6_draw_common(cmd
, cs
, true, 0);
3322 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 9);
3323 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3324 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED
) |
3325 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3326 tu_cs_emit(cs
, drawCount
);
3327 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3328 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3329 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3330 tu_cs_emit(cs
, stride
);
3332 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3336 tu_CmdDrawIndirectCount(VkCommandBuffer commandBuffer
,
3338 VkDeviceSize offset
,
3339 VkBuffer countBuffer
,
3340 VkDeviceSize countBufferOffset
,
3344 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3345 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3346 TU_FROM_HANDLE(tu_buffer
, count_buf
, countBuffer
);
3347 struct tu_cs
*cs
= &cmd
->draw_cs
;
3349 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3351 /* It turns out that the firmware we have for a650 only partially fixed the
3352 * problem with CP_DRAW_INDIRECT_MULTI not waiting for WFI's to complete
3353 * before reading indirect parameters. It waits for WFI's before reading
3354 * the draw parameters, but after reading the indirect count :(.
3358 tu6_draw_common(cmd
, cs
, false, 0);
3360 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 8);
3361 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3362 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT
) |
3363 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3364 tu_cs_emit(cs
, drawCount
);
3365 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3366 tu_cs_emit_qw(cs
, count_buf
->bo
->iova
+ count_buf
->bo_offset
+ countBufferOffset
);
3367 tu_cs_emit(cs
, stride
);
3369 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3370 tu_bo_list_add(&cmd
->bo_list
, count_buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3374 tu_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer
,
3376 VkDeviceSize offset
,
3377 VkBuffer countBuffer
,
3378 VkDeviceSize countBufferOffset
,
3382 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3383 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3384 TU_FROM_HANDLE(tu_buffer
, count_buf
, countBuffer
);
3385 struct tu_cs
*cs
= &cmd
->draw_cs
;
3387 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3391 tu6_draw_common(cmd
, cs
, true, 0);
3393 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 11);
3394 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3395 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT_INDEXED
) |
3396 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3397 tu_cs_emit(cs
, drawCount
);
3398 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3399 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3400 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3401 tu_cs_emit_qw(cs
, count_buf
->bo
->iova
+ count_buf
->bo_offset
+ countBufferOffset
);
3402 tu_cs_emit(cs
, stride
);
3404 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3405 tu_bo_list_add(&cmd
->bo_list
, count_buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3408 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3409 uint32_t instanceCount
,
3410 uint32_t firstInstance
,
3411 VkBuffer _counterBuffer
,
3412 VkDeviceSize counterBufferOffset
,
3413 uint32_t counterOffset
,
3414 uint32_t vertexStride
)
3416 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3417 TU_FROM_HANDLE(tu_buffer
, buf
, _counterBuffer
);
3418 struct tu_cs
*cs
= &cmd
->draw_cs
;
3420 /* All known firmware versions do not wait for WFI's with CP_DRAW_AUTO.
3421 * Plus, for the common case where the counter buffer is written by
3422 * vkCmdEndTransformFeedback, we need to wait for the CP_WAIT_MEM_WRITES to
3423 * complete which means we need a WAIT_FOR_ME anyway.
3427 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, 0, firstInstance
);
3429 tu6_draw_common(cmd
, cs
, false, 0);
3431 tu_cs_emit_pkt7(cs
, CP_DRAW_AUTO
, 6);
3432 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_XFB
));
3433 tu_cs_emit(cs
, instanceCount
);
3434 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ counterBufferOffset
);
3435 tu_cs_emit(cs
, counterOffset
);
3436 tu_cs_emit(cs
, vertexStride
);
3438 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3441 struct tu_dispatch_info
3444 * Determine the layout of the grid (in block units) to be used.
3449 * A starting offset for the grid. If unaligned is set, the offset
3450 * must still be aligned.
3452 uint32_t offsets
[3];
3454 * Whether it's an unaligned compute dispatch.
3459 * Indirect compute parameters resource.
3461 struct tu_buffer
*indirect
;
3462 uint64_t indirect_offset
;
3466 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3467 const struct tu_dispatch_info
*info
)
3469 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3470 const struct tu_program_descriptor_linkage
*link
=
3471 &pipeline
->program
.link
[type
];
3472 const struct ir3_const_state
*const_state
= &link
->const_state
;
3473 uint32_t offset
= const_state
->offsets
.driver_param
;
3475 if (link
->constlen
<= offset
)
3478 if (!info
->indirect
) {
3479 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3480 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3481 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3482 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3483 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3484 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3485 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3488 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3489 (link
->constlen
- offset
) * 4);
3490 /* push constants */
3491 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3492 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3493 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3494 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3495 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3496 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3500 for (i
= 0; i
< num_consts
; i
++)
3501 tu_cs_emit(cs
, driver_params
[i
]);
3503 tu_finishme("Indirect driver params");
3508 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3509 const struct tu_dispatch_info
*info
)
3511 struct tu_cs
*cs
= &cmd
->cs
;
3512 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3513 struct tu_descriptor_state
*descriptors_state
=
3514 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3516 /* TODO: We could probably flush less if we add a compute_flush_bits
3519 tu_emit_cache_flush(cmd
, cs
);
3521 /* note: no reason to have this in a separate IB */
3522 tu_cs_emit_state_ib(cs
,
3523 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
));
3525 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3527 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
)
3528 tu_cs_emit_state_ib(cs
, pipeline
->load_state
);
3530 cmd
->state
.dirty
&= ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
3532 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3533 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3535 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3536 const uint32_t *num_groups
= info
->blocks
;
3538 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3539 .localsizex
= local_size
[0] - 1,
3540 .localsizey
= local_size
[1] - 1,
3541 .localsizez
= local_size
[2] - 1),
3542 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3543 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3544 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3545 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3546 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3547 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3550 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3551 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3552 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3554 if (info
->indirect
) {
3555 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3557 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3558 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3560 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3561 tu_cs_emit(cs
, 0x00000000);
3562 tu_cs_emit_qw(cs
, iova
);
3564 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3565 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3566 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3568 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3569 tu_cs_emit(cs
, 0x00000000);
3570 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3571 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3572 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3579 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3587 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3588 struct tu_dispatch_info info
= {};
3594 info
.offsets
[0] = base_x
;
3595 info
.offsets
[1] = base_y
;
3596 info
.offsets
[2] = base_z
;
3597 tu_dispatch(cmd_buffer
, &info
);
3601 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3606 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3610 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3612 VkDeviceSize offset
)
3614 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3615 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3616 struct tu_dispatch_info info
= {};
3618 info
.indirect
= buffer
;
3619 info
.indirect_offset
= offset
;
3621 tu_dispatch(cmd_buffer
, &info
);
3625 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3627 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3629 tu_cs_end(&cmd_buffer
->draw_cs
);
3630 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3632 if (use_sysmem_rendering(cmd_buffer
))
3633 tu_cmd_render_sysmem(cmd_buffer
);
3635 tu_cmd_render_tiles(cmd_buffer
);
3637 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3639 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3640 tu_cs_begin(&cmd_buffer
->draw_cs
);
3641 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3642 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3644 cmd_buffer
->state
.cache
.pending_flush_bits
|=
3645 cmd_buffer
->state
.renderpass_cache
.pending_flush_bits
;
3646 tu_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
, true);
3648 cmd_buffer
->state
.pass
= NULL
;
3649 cmd_buffer
->state
.subpass
= NULL
;
3650 cmd_buffer
->state
.framebuffer
= NULL
;
3654 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3655 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3657 tu_CmdEndRenderPass(commandBuffer
);
3660 struct tu_barrier_info
3662 uint32_t eventCount
;
3663 const VkEvent
*pEvents
;
3664 VkPipelineStageFlags srcStageMask
;
3668 tu_barrier(struct tu_cmd_buffer
*cmd
,
3669 uint32_t memoryBarrierCount
,
3670 const VkMemoryBarrier
*pMemoryBarriers
,
3671 uint32_t bufferMemoryBarrierCount
,
3672 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3673 uint32_t imageMemoryBarrierCount
,
3674 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3675 const struct tu_barrier_info
*info
)
3677 struct tu_cs
*cs
= cmd
->state
.pass
? &cmd
->draw_cs
: &cmd
->cs
;
3678 VkAccessFlags srcAccessMask
= 0;
3679 VkAccessFlags dstAccessMask
= 0;
3681 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3682 srcAccessMask
|= pMemoryBarriers
[i
].srcAccessMask
;
3683 dstAccessMask
|= pMemoryBarriers
[i
].dstAccessMask
;
3686 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3687 srcAccessMask
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
3688 dstAccessMask
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
3691 enum tu_cmd_access_mask src_flags
= 0;
3692 enum tu_cmd_access_mask dst_flags
= 0;
3694 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3695 TU_FROM_HANDLE(tu_image
, image
, pImageMemoryBarriers
[i
].image
);
3696 VkImageLayout old_layout
= pImageMemoryBarriers
[i
].oldLayout
;
3697 /* For non-linear images, PREINITIALIZED is the same as UNDEFINED */
3698 if (old_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
3699 (image
->tiling
!= VK_IMAGE_TILING_LINEAR
&&
3700 old_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
)) {
3701 /* The underlying memory for this image may have been used earlier
3702 * within the same queue submission for a different image, which
3703 * means that there may be old, stale cache entries which are in the
3704 * "wrong" location, which could cause problems later after writing
3705 * to the image. We don't want these entries being flushed later and
3706 * overwriting the actual image, so we need to flush the CCU.
3708 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
3710 srcAccessMask
|= pImageMemoryBarriers
[i
].srcAccessMask
;
3711 dstAccessMask
|= pImageMemoryBarriers
[i
].dstAccessMask
;
3714 /* Inside a renderpass, we don't know yet whether we'll be using sysmem
3715 * so we have to use the sysmem flushes.
3717 bool gmem
= cmd
->state
.ccu_state
== TU_CMD_CCU_GMEM
&&
3719 src_flags
|= vk2tu_access(srcAccessMask
, gmem
);
3720 dst_flags
|= vk2tu_access(dstAccessMask
, gmem
);
3722 struct tu_cache_state
*cache
=
3723 cmd
->state
.pass
? &cmd
->state
.renderpass_cache
: &cmd
->state
.cache
;
3724 tu_flush_for_access(cache
, src_flags
, dst_flags
);
3726 for (uint32_t i
= 0; i
< info
->eventCount
; i
++) {
3727 TU_FROM_HANDLE(tu_event
, event
, info
->pEvents
[i
]);
3729 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3731 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3732 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3733 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3734 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3735 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3736 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3737 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3742 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3743 VkPipelineStageFlags srcStageMask
,
3744 VkPipelineStageFlags dstStageMask
,
3745 VkDependencyFlags dependencyFlags
,
3746 uint32_t memoryBarrierCount
,
3747 const VkMemoryBarrier
*pMemoryBarriers
,
3748 uint32_t bufferMemoryBarrierCount
,
3749 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3750 uint32_t imageMemoryBarrierCount
,
3751 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3753 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3754 struct tu_barrier_info info
;
3756 info
.eventCount
= 0;
3757 info
.pEvents
= NULL
;
3758 info
.srcStageMask
= srcStageMask
;
3760 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3761 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3762 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3766 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
,
3767 VkPipelineStageFlags stageMask
, unsigned value
)
3769 struct tu_cs
*cs
= &cmd
->cs
;
3771 /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
3772 assert(!cmd
->state
.pass
);
3774 tu_emit_cache_flush(cmd
, cs
);
3776 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3778 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
3779 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
3781 VkPipelineStageFlags top_of_pipe_flags
=
3782 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
3783 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
;
3785 if (!(stageMask
& ~top_of_pipe_flags
)) {
3786 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3787 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3788 tu_cs_emit(cs
, value
);
3790 /* Use a RB_DONE_TS event to wait for everything to complete. */
3791 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 4);
3792 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS
));
3793 tu_cs_emit_qw(cs
, event
->bo
.iova
);
3794 tu_cs_emit(cs
, value
);
3799 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3801 VkPipelineStageFlags stageMask
)
3803 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3804 TU_FROM_HANDLE(tu_event
, event
, _event
);
3806 write_event(cmd
, event
, stageMask
, 1);
3810 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3812 VkPipelineStageFlags stageMask
)
3814 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3815 TU_FROM_HANDLE(tu_event
, event
, _event
);
3817 write_event(cmd
, event
, stageMask
, 0);
3821 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3822 uint32_t eventCount
,
3823 const VkEvent
*pEvents
,
3824 VkPipelineStageFlags srcStageMask
,
3825 VkPipelineStageFlags dstStageMask
,
3826 uint32_t memoryBarrierCount
,
3827 const VkMemoryBarrier
*pMemoryBarriers
,
3828 uint32_t bufferMemoryBarrierCount
,
3829 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3830 uint32_t imageMemoryBarrierCount
,
3831 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3833 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3834 struct tu_barrier_info info
;
3836 info
.eventCount
= eventCount
;
3837 info
.pEvents
= pEvents
;
3838 info
.srcStageMask
= 0;
3840 tu_barrier(cmd
, memoryBarrierCount
, pMemoryBarriers
,
3841 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3842 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3846 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)