src/freedreno/vulkan/tu_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #include "tu_private.h"
  29
  30 #include "registers/adreno_pm4.xml.h"
  31 #include "registers/adreno_common.xml.h"
  32 #include "registers/a6xx.xml.h"
  33
  34 #include "vk_format.h"
  35
  36 #include "tu_cs.h"
  37 #include "tu_blit.h"
  38
  39 void
  40 tu_bo_list_init(struct tu_bo_list *list)
  41 {
  42    list->count = list->capacity = 0;
  43    list->bo_infos = NULL;
  44 }
  45
  46 void
  47 tu_bo_list_destroy(struct tu_bo_list *list)
  48 {
  49    free(list->bo_infos);
  50 }
  51
  52 void
  53 tu_bo_list_reset(struct tu_bo_list *list)
  54 {
  55    list->count = 0;
  56 }
  57
  58 /**
  59  * \a flags consists of MSM_SUBMIT_BO_FLAGS.
  60  */
  61 static uint32_t
  62 tu_bo_list_add_info(struct tu_bo_list *list,
  63                     const struct drm_msm_gem_submit_bo *bo_info)
  64 {
  65    for (uint32_t i = 0; i < list->count; ++i) {
  66       if (list->bo_infos[i].handle == bo_info->handle) {
  67          assert(list->bo_infos[i].presumed == bo_info->presumed);
  68          list->bo_infos[i].flags |= bo_info->flags;
  69          return i;
  70       }
  71    }
  72
  73    /* grow list->bo_infos if needed */
  74    if (list->count == list->capacity) {
  75       uint32_t new_capacity = MAX2(2 * list->count, 16);
  76       struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
  77          list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
  78       if (!new_bo_infos)
  79          return TU_BO_LIST_FAILED;
  80       list->bo_infos = new_bo_infos;
  81       list->capacity = new_capacity;
  82    }
  83
  84    list->bo_infos[list->count] = *bo_info;
  85    return list->count++;
  86 }
  87
  88 uint32_t
  89 tu_bo_list_add(struct tu_bo_list *list,
  90                const struct tu_bo *bo,
  91                uint32_t flags)
  92 {
  93    return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
  94                                        .flags = flags,
  95                                        .handle = bo->gem_handle,
  96                                        .presumed = bo->iova,
  97                                     });
  98 }
  99
 100 VkResult
 101 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
 102 {
 103    for (uint32_t i = 0; i < other->count; i++) {
 104       if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
 105          return VK_ERROR_OUT_OF_HOST_MEMORY;
 106    }
 107
 108    return VK_SUCCESS;
 109 }
 110
 111 static VkResult
 112 tu_tiling_config_update_gmem_layout(struct tu_tiling_config *tiling,
 113                                     const struct tu_device *dev)
 114 {
 115    const uint32_t gmem_size = dev->physical_device->gmem_size;
 116    uint32_t offset = 0;
 117
 118    for (uint32_t i = 0; i < tiling->buffer_count; i++) {
 119       /* 16KB-aligned */
 120       offset = align(offset, 0x4000);
 121
 122       tiling->gmem_offsets[i] = offset;
 123       offset += tiling->tile0.extent.width * tiling->tile0.extent.height *
 124                 tiling->buffer_cpp[i];
 125    }
 126
 127    return offset <= gmem_size ? VK_SUCCESS : VK_ERROR_OUT_OF_DEVICE_MEMORY;
 128 }
 129
 130 static void
 131 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
 132                                     const struct tu_device *dev)
 133 {
 134    const uint32_t tile_align_w = dev->physical_device->tile_align_w;
 135    const uint32_t tile_align_h = dev->physical_device->tile_align_h;
 136    const uint32_t max_tile_width = 1024; /* A6xx */
 137
 138    tiling->tile0.offset = (VkOffset2D) {
 139       .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
 140       .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
 141    };
 142
 143    const uint32_t ra_width =
 144       tiling->render_area.extent.width +
 145       (tiling->render_area.offset.x - tiling->tile0.offset.x);
 146    const uint32_t ra_height =
 147       tiling->render_area.extent.height +
 148       (tiling->render_area.offset.y - tiling->tile0.offset.y);
 149
 150    /* start from 1 tile */
 151    tiling->tile_count = (VkExtent2D) {
 152       .width = 1,
 153       .height = 1,
 154    };
 155    tiling->tile0.extent = (VkExtent2D) {
 156       .width = align(ra_width, tile_align_w),
 157       .height = align(ra_height, tile_align_h),
 158    };
 159
 160    /* do not exceed max tile width */
 161    while (tiling->tile0.extent.width > max_tile_width) {
 162       tiling->tile_count.width++;
 163       tiling->tile0.extent.width =
 164          align(ra_width / tiling->tile_count.width, tile_align_w);
 165    }
 166
 167    /* do not exceed gmem size */
 168    while (tu_tiling_config_update_gmem_layout(tiling, dev) != VK_SUCCESS) {
 169       if (tiling->tile0.extent.width > tiling->tile0.extent.height) {
 170          tiling->tile_count.width++;
 171          tiling->tile0.extent.width =
 172             align(ra_width / tiling->tile_count.width, tile_align_w);
 173       } else {
 174          tiling->tile_count.height++;
 175          tiling->tile0.extent.height =
 176             align(ra_height / tiling->tile_count.height, tile_align_h);
 177       }
 178    }
 179 }
 180
 181 static void
 182 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
 183                                     const struct tu_device *dev)
 184 {
 185    const uint32_t max_pipe_count = 32; /* A6xx */
 186
 187    /* start from 1 tile per pipe */
 188    tiling->pipe0 = (VkExtent2D) {
 189       .width = 1,
 190       .height = 1,
 191    };
 192    tiling->pipe_count = tiling->tile_count;
 193
 194    /* do not exceed max pipe count vertically */
 195    while (tiling->pipe_count.height > max_pipe_count) {
 196       tiling->pipe0.height += 2;
 197       tiling->pipe_count.height =
 198          (tiling->tile_count.height + tiling->pipe0.height - 1) /
 199          tiling->pipe0.height;
 200    }
 201
 202    /* do not exceed max pipe count */
 203    while (tiling->pipe_count.width * tiling->pipe_count.height >
 204           max_pipe_count) {
 205       tiling->pipe0.width += 1;
 206       tiling->pipe_count.width =
 207          (tiling->tile_count.width + tiling->pipe0.width - 1) /
 208          tiling->pipe0.width;
 209    }
 210 }
 211
 212 static void
 213 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
 214                               const struct tu_device *dev)
 215 {
 216    const uint32_t max_pipe_count = 32; /* A6xx */
 217    const uint32_t used_pipe_count =
 218       tiling->pipe_count.width * tiling->pipe_count.height;
 219    const VkExtent2D last_pipe = {
 220       .width = tiling->tile_count.width % tiling->pipe0.width,
 221       .height = tiling->tile_count.height % tiling->pipe0.height,
 222    };
 223
 224    assert(used_pipe_count <= max_pipe_count);
 225    assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
 226
 227    for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
 228       for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
 229          const uint32_t pipe_x = tiling->pipe0.width * x;
 230          const uint32_t pipe_y = tiling->pipe0.height * y;
 231          const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
 232                                     ? last_pipe.width
 233                                     : tiling->pipe0.width;
 234          const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
 235                                     ? last_pipe.height
 236                                     : tiling->pipe0.height;
 237          const uint32_t n = tiling->pipe_count.width * y + x;
 238
 239          tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
 240                                   A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
 241                                   A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
 242                                   A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
 243          tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
 244       }
 245    }
 246
 247    memset(tiling->pipe_config + used_pipe_count, 0,
 248           sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
 249 }
 250
 251 static void
 252 tu_tiling_config_update(struct tu_tiling_config *tiling,
 253                         const struct tu_device *dev,
 254                         const uint32_t *buffer_cpp,
 255                         uint32_t buffer_count,
 256                         const VkRect2D *render_area)
 257 {
 258    /* see if there is any real change */
 259    const bool ra_changed =
 260       render_area &&
 261       memcmp(&tiling->render_area, render_area, sizeof(*render_area));
 262    const bool buf_changed = tiling->buffer_count != buffer_count ||
 263                             memcmp(tiling->buffer_cpp, buffer_cpp,
 264                                    sizeof(*buffer_cpp) * buffer_count);
 265    if (!ra_changed && !buf_changed)
 266       return;
 267
 268    if (ra_changed)
 269       tiling->render_area = *render_area;
 270
 271    if (buf_changed) {
 272       memcpy(tiling->buffer_cpp, buffer_cpp,
 273              sizeof(*buffer_cpp) * buffer_count);
 274       tiling->buffer_count = buffer_count;
 275    }
 276
 277    tu_tiling_config_update_tile_layout(tiling, dev);
 278    tu_tiling_config_update_pipe_layout(tiling, dev);
 279    tu_tiling_config_update_pipes(tiling, dev);
 280 }
 281
 282 static void
 283 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
 284                           const struct tu_device *dev,
 285                           uint32_t tx,
 286                           uint32_t ty,
 287                           struct tu_tile *tile)
 288 {
 289    /* find the pipe and the slot for tile (tx, ty) */
 290    const uint32_t px = tx / tiling->pipe0.width;
 291    const uint32_t py = ty / tiling->pipe0.height;
 292    const uint32_t sx = tx - tiling->pipe0.width * px;
 293    const uint32_t sy = ty - tiling->pipe0.height * py;
 294
 295    assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
 296    assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
 297    assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
 298
 299    /* convert to 1D indices */
 300    tile->pipe = tiling->pipe_count.width * py + px;
 301    tile->slot = tiling->pipe0.width * sy + sx;
 302
 303    /* get the blit area for the tile */
 304    tile->begin = (VkOffset2D) {
 305       .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
 306       .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
 307    };
 308    tile->end.x =
 309       (tx == tiling->tile_count.width - 1)
 310          ? tiling->render_area.offset.x + tiling->render_area.extent.width
 311          : tile->begin.x + tiling->tile0.extent.width;
 312    tile->end.y =
 313       (ty == tiling->tile_count.height - 1)
 314          ? tiling->render_area.offset.y + tiling->render_area.extent.height
 315          : tile->begin.y + tiling->tile0.extent.height;
 316 }
 317
 318 enum a3xx_msaa_samples
 319 tu_msaa_samples(uint32_t samples)
 320 {
 321    switch (samples) {
 322    case 1:
 323       return MSAA_ONE;
 324    case 2:
 325       return MSAA_TWO;
 326    case 4:
 327       return MSAA_FOUR;
 328    case 8:
 329       return MSAA_EIGHT;
 330    default:
 331       assert(!"invalid sample count");
 332       return MSAA_ONE;
 333    }
 334 }
 335
 336 static enum a4xx_index_size
 337 tu6_index_size(VkIndexType type)
 338 {
 339    switch (type) {
 340    case VK_INDEX_TYPE_UINT16:
 341       return INDEX4_SIZE_16_BIT;
 342    case VK_INDEX_TYPE_UINT32:
 343       return INDEX4_SIZE_32_BIT;
 344    default:
 345       unreachable("invalid VkIndexType");
 346       return INDEX4_SIZE_8_BIT;
 347    }
 348 }
 349
 350 static void
 351 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 352 {
 353    tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
 354 }
 355
 356 void
 357 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
 358                      struct tu_cs *cs,
 359                      enum vgt_event_type event,
 360                      bool need_seqno)
 361 {
 362    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
 363    tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
 364    if (need_seqno) {
 365       tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 366       tu_cs_emit(cs, ++cmd->scratch_seqno);
 367    }
 368 }
 369
 370 static void
 371 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 372 {
 373    tu6_emit_event_write(cmd, cs, 0x31, false);
 374 }
 375
 376 static void
 377 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 378 {
 379    tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
 380 }
 381
 382 static void
 383 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 384 {
 385    if (cmd->wait_for_idle) {
 386       tu_cs_emit_wfi(cs);
 387       cmd->wait_for_idle = false;
 388    }
 389 }
 390
 391 static void
 392 tu6_emit_zs(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 393 {
 394    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 395    const struct tu_subpass *subpass = cmd->state.subpass;
 396    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 397
 398    const uint32_t a = subpass->depth_stencil_attachment.attachment;
 399    if (a == VK_ATTACHMENT_UNUSED) {
 400       tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
 401       tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
 402       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
 403       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
 404       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
 405       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
 406       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
 407
 408       tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
 409       tu_cs_emit(cs,
 410                  A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
 411
 412       tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
 413       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
 414       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
 415       tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
 416       tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
 417       tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
 418
 419       tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
 420       tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
 421
 422       return;
 423    }
 424
 425    uint32_t gmem_index = 0;
 426    for (uint32_t i = 0; i < subpass->color_count; ++i) {
 427       uint32_t a = subpass->color_attachments[i].attachment;
 428       if (a != VK_ATTACHMENT_UNUSED)
 429          gmem_index++;
 430    }
 431
 432    const struct tu_image_view *iview = fb->attachments[a].attachment;
 433    const struct tu_image_level *slice = &iview->image->levels[iview->base_mip];
 434    enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
 435
 436    uint32_t offset = slice->offset + slice->size * iview->base_layer;
 437    uint32_t stride = slice->pitch * iview->image->cpp;
 438
 439    tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
 440    tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
 441    tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(stride));
 442    tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(slice->size));
 443    tu_cs_emit_qw(cs, iview->image->bo->iova + iview->image->bo_offset + offset);
 444    tu_cs_emit(cs, tiling->gmem_offsets[gmem_index]);
 445
 446    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
 447    tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
 448
 449    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
 450    tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
 451    tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
 452    tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
 453    tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
 454    tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
 455
 456    tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
 457    tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
 458
 459    /* enable zs? */
 460 }
 461
 462 static void
 463 tu6_emit_mrt(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 464 {
 465    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 466    const struct tu_subpass *subpass = cmd->state.subpass;
 467    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 468    unsigned char mrt_comp[MAX_RTS] = { 0 };
 469    unsigned srgb_cntl = 0;
 470
 471    uint32_t gmem_index = 0;
 472    for (uint32_t i = 0; i < subpass->color_count; ++i) {
 473       uint32_t a = subpass->color_attachments[i].attachment;
 474       if (a == VK_ATTACHMENT_UNUSED)
 475          continue;
 476
 477       const struct tu_image_view *iview = fb->attachments[a].attachment;
 478       const struct tu_image_level *slice =
 479          &iview->image->levels[iview->base_mip];
 480       const enum a6xx_tile_mode tile_mode =
 481          tu6_get_image_tile_mode(iview->image, iview->base_mip);
 482       uint32_t stride = 0;
 483       uint32_t offset = 0;
 484
 485       mrt_comp[i] = 0xf;
 486
 487       if (vk_format_is_srgb(iview->vk_format))
 488          srgb_cntl |= (1 << i);
 489
 490       const struct tu_native_format *format =
 491          tu6_get_native_format(iview->vk_format);
 492       assert(format && format->rb >= 0);
 493
 494       offset = slice->offset + slice->size * iview->base_layer;
 495       stride = slice->pitch * iview->image->cpp;
 496
 497       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
 498       tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
 499                         A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
 500                         A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
 501       tu_cs_emit(cs, A6XX_RB_MRT_PITCH(stride));
 502       tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(slice->size));
 503       tu_cs_emit_qw(cs, iview->image->bo->iova + iview->image->bo_offset +
 504                            offset); /* BASE_LO/HI */
 505       tu_cs_emit(
 506          cs, tiling->gmem_offsets[gmem_index++]); /* RB_MRT[i].BASE_GMEM */
 507
 508       tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
 509       tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb));
 510
 511 #if 0
 512       /* when we support UBWC, these would be the system memory
 513        * addr/pitch/etc:
 514        */
 515       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 4);
 516       tu_cs_emit(cs, 0x00000000);    /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
 517       tu_cs_emit(cs, 0x00000000);    /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
 518       tu_cs_emit(cs, A6XX_RB_MRT_FLAG_BUFFER_PITCH(0));
 519       tu_cs_emit(cs, A6XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
 520 #endif
 521    }
 522
 523    tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
 524    tu_cs_emit(cs, srgb_cntl);
 525
 526    tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
 527    tu_cs_emit(cs, srgb_cntl);
 528
 529    tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
 530    tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
 531                      A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
 532                      A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
 533                      A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
 534                      A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
 535                      A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
 536                      A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
 537                      A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
 538
 539    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
 540    tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
 541                      A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
 542                      A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
 543                      A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
 544                      A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
 545                      A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
 546                      A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
 547                      A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
 548 }
 549
 550 static void
 551 tu6_emit_msaa(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 552 {
 553    const struct tu_subpass *subpass = cmd->state.subpass;
 554    const enum a3xx_msaa_samples samples =
 555       tu_msaa_samples(subpass->max_sample_count);
 556
 557    tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
 558    tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
 559    tu_cs_emit(cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
 560               COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
 561
 562    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
 563    tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
 564    tu_cs_emit(cs, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
 565               COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
 566
 567    tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
 568    tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
 569    tu_cs_emit(cs, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
 570               COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
 571
 572    tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
 573    tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
 574 }
 575
 576 static void
 577 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
 578 {
 579    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 580    const uint32_t bin_w = tiling->tile0.extent.width;
 581    const uint32_t bin_h = tiling->tile0.extent.height;
 582
 583    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
 584    tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
 585                      A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
 586
 587    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
 588    tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
 589                      A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
 590
 591    /* no flag for RB_BIN_CONTROL2... */
 592    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
 593    tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
 594                      A6XX_RB_BIN_CONTROL2_BINH(bin_h));
 595 }
 596
 597 static void
 598 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
 599                      struct tu_cs *cs,
 600                      bool binning)
 601 {
 602    uint32_t cntl = 0;
 603    cntl |= A6XX_RB_RENDER_CNTL_UNK4;
 604    if (binning)
 605       cntl |= A6XX_RB_RENDER_CNTL_BINNING;
 606
 607    tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
 608    tu_cs_emit(cs, 0x2);
 609    tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
 610    tu_cs_emit(cs, cntl);
 611 }
 612
 613 static void
 614 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 615 {
 616    const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
 617    const uint32_t x1 = render_area->offset.x;
 618    const uint32_t y1 = render_area->offset.y;
 619    const uint32_t x2 = x1 + render_area->extent.width - 1;
 620    const uint32_t y2 = y1 + render_area->extent.height - 1;
 621
 622    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
 623    tu_cs_emit(cs,
 624               A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
 625    tu_cs_emit(cs,
 626               A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
 627 }
 628
 629 static void
 630 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
 631                    struct tu_cs *cs,
 632                    const struct tu_image_view *iview,
 633                    uint32_t gmem_offset,
 634                    uint32_t blit_info)
 635 {
 636    const struct tu_image_level *slice =
 637       &iview->image->levels[iview->base_mip];
 638    const uint32_t offset = slice->offset + slice->size * iview->base_layer;
 639    const uint32_t stride = slice->pitch * iview->image->cpp;
 640
 641    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
 642    tu_cs_emit(cs, blit_info);
 643
 644    const struct tu_native_format *format =
 645       tu6_get_native_format(iview->vk_format);
 646    assert(format && format->rb >= 0);
 647
 648    enum a6xx_tile_mode tile_mode =
 649       tu6_get_image_tile_mode(iview->image, iview->base_mip);
 650    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
 651    tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
 652                      A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
 653                      A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
 654                      A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap));
 655    tu_cs_emit_qw(cs,
 656                  iview->image->bo->iova + iview->image->bo_offset + offset);
 657    tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(stride));
 658    tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(slice->size));
 659
 660    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 661    tu_cs_emit(cs, gmem_offset);
 662 }
 663
 664 static void
 665 tu6_emit_blit_clear(struct tu_cmd_buffer *cmd,
 666                     struct tu_cs *cs,
 667                     const struct tu_image_view *iview,
 668                     uint32_t gmem_offset,
 669                     const VkClearValue *clear_value)
 670 {
 671    const struct tu_native_format *format =
 672       tu6_get_native_format(iview->vk_format);
 673    assert(format && format->rb >= 0);
 674    /* must be WZYX; other values are ignored */
 675    const enum a3xx_color_swap swap = WZYX;
 676
 677    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
 678    tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 679                      A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
 680                      A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
 681                      A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap));
 682
 683    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
 684    tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
 685
 686    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 687    tu_cs_emit(cs, gmem_offset);
 688
 689    tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
 690    tu_cs_emit(cs, 0);
 691
 692    /* pack clear_value into WZYX order */
 693    uint32_t clear_vals[4] = { 0 };
 694    tu_pack_clear_value(clear_value, iview->vk_format, clear_vals);
 695
 696    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
 697    tu_cs_emit(cs, clear_vals[0]);
 698    tu_cs_emit(cs, clear_vals[1]);
 699    tu_cs_emit(cs, clear_vals[2]);
 700    tu_cs_emit(cs, clear_vals[3]);
 701 }
 702
 703 static void
 704 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 705 {
 706    tu6_emit_marker(cmd, cs);
 707    tu6_emit_event_write(cmd, cs, BLIT, false);
 708    tu6_emit_marker(cmd, cs);
 709 }
 710
 711 static void
 712 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
 713                         struct tu_cs *cs,
 714                         uint32_t x1,
 715                         uint32_t y1,
 716                         uint32_t x2,
 717                         uint32_t y2)
 718 {
 719    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 720    tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
 721                      A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
 722    tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
 723                      A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
 724
 725    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
 726    tu_cs_emit(
 727       cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
 728    tu_cs_emit(
 729       cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
 730 }
 731
 732 static void
 733 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
 734                        struct tu_cs *cs,
 735                        uint32_t x1,
 736                        uint32_t y1)
 737 {
 738    tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
 739    tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
 740
 741    tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
 742    tu_cs_emit(cs,
 743               A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
 744
 745    tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
 746    tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
 747
 748    tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
 749    tu_cs_emit(
 750       cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
 751 }
 752
 753 static void
 754 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
 755                      struct tu_cs *cs,
 756                      const struct tu_tile *tile)
 757 {
 758    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 759    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
 760
 761    tu6_emit_marker(cmd, cs);
 762    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 763    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
 764    tu6_emit_marker(cmd, cs);
 765
 766    const uint32_t x1 = tile->begin.x;
 767    const uint32_t y1 = tile->begin.y;
 768    const uint32_t x2 = tile->end.x - 1;
 769    const uint32_t y2 = tile->end.y - 1;
 770    tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
 771    tu6_emit_window_offset(cmd, cs, x1, y1);
 772
 773    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
 774    tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
 775
 776    if (false) {
 777       /* hw binning? */
 778    } else {
 779       tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 780       tu_cs_emit(cs, 0x1);
 781
 782       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 783       tu_cs_emit(cs, 0x0);
 784    }
 785 }
 786
 787 static void
 788 tu6_emit_tile_load_attachment(struct tu_cmd_buffer *cmd,
 789                               struct tu_cs *cs,
 790                               uint32_t a,
 791                               uint32_t gmem_index)
 792 {
 793    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 794    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 795    const struct tu_attachment_state *attachments = cmd->state.attachments;
 796
 797    const struct tu_image_view *iview = fb->attachments[a].attachment;
 798    const struct tu_attachment_state *att = attachments + a;
 799    if (att->pending_clear_aspects) {
 800       tu6_emit_blit_clear(cmd, cs, iview,
 801                           tiling->gmem_offsets[gmem_index],
 802                           &att->clear_value);
 803    } else {
 804       tu6_emit_blit_info(cmd, cs, iview,
 805                          tiling->gmem_offsets[gmem_index],
 806                          A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM);
 807    }
 808
 809    tu6_emit_blit(cmd, cs);
 810 }
 811
 812 static void
 813 tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 814 {
 815    const struct tu_subpass *subpass = cmd->state.subpass;
 816
 817    tu6_emit_blit_scissor(cmd, cs);
 818
 819    uint32_t gmem_index = 0;
 820    for (uint32_t i = 0; i < subpass->color_count; ++i) {
 821       const uint32_t a = subpass->color_attachments[i].attachment;
 822       if (a != VK_ATTACHMENT_UNUSED)
 823          tu6_emit_tile_load_attachment(cmd, cs, a, gmem_index++);
 824    }
 825
 826    const uint32_t a = subpass->depth_stencil_attachment.attachment;
 827    if (a != VK_ATTACHMENT_UNUSED)
 828       tu6_emit_tile_load_attachment(cmd, cs, a, gmem_index);
 829 }
 830
 831 static void
 832 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 833 {
 834    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 835    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 836
 837    if (false) {
 838       /* hw binning? */
 839    }
 840
 841    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
 842    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
 843                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
 844                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
 845    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
 846    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
 847
 848    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 849    tu_cs_emit(cs, 0x0);
 850
 851    tu6_emit_marker(cmd, cs);
 852    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 853    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
 854    tu6_emit_marker(cmd, cs);
 855
 856    tu6_emit_blit_scissor(cmd, cs);
 857
 858    uint32_t gmem_index = 0;
 859    for (uint32_t i = 0; i < cmd->state.subpass->color_count; ++i) {
 860       uint32_t a = cmd->state.subpass->color_attachments[i].attachment;
 861       if (a == VK_ATTACHMENT_UNUSED)
 862          continue;
 863
 864       const struct tu_image_view *iview = fb->attachments[a].attachment;
 865       tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[gmem_index++],
 866                          0);
 867       tu6_emit_blit(cmd, cs);
 868    }
 869
 870    const uint32_t a = cmd->state.subpass->depth_stencil_attachment.attachment;
 871    if (a != VK_ATTACHMENT_UNUSED) {
 872       const struct tu_image_view *iview = fb->attachments[a].attachment;
 873       tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[gmem_index],
 874                          0);
 875       tu6_emit_blit(cmd, cs);
 876    }
 877 }
 878
 879 static void
 880 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
 881 {
 882    tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
 883    tu_cs_emit(cs, restart_index);
 884 }
 885
 886 static void
 887 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 888 {
 889    VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
 890    if (result != VK_SUCCESS) {
 891       cmd->record_result = result;
 892       return;
 893    }
 894
 895    tu6_emit_cache_flush(cmd, cs);
 896
 897    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
 898
 899    tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
 900    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
 901    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
 902    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
 903    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
 904    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
 905    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
 906    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
 907    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
 908
 909    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
 910    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
 911    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
 912    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
 913    tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
 914    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
 915    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
 916    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
 917    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
 918    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
 919    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
 920    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
 921    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
 922    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
 923
 924    tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
 925
 926    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
 927    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
 928    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
 929
 930    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
 931    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
 932    tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
 933    tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
 934    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
 935    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
 936    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
 937    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
 938    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
 939    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
 940    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
 941    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
 942
 943    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
 944    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
 945
 946    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
 947    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
 948
 949    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
 950                         A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
 951
 952    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
 953    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
 954    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
 955
 956    tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
 957    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
 958
 959    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
 960
 961    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
 962
 963    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
 964    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
 965    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
 966    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
 967    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
 968    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
 969    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
 970    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
 971    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
 972    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
 973    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
 974    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
 975    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
 976    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
 977    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
 978    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
 979    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
 980    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
 981    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
 982    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
 983    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
 984
 985    tu6_emit_marker(cmd, cs);
 986
 987    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
 988
 989    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
 990
 991    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
 992
 993    /* we don't use this yet.. probably best to disable.. */
 994    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
 995    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
 996                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
 997                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
 998    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
 999    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1000
1001    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1002    tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1003    tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1004    tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1005
1006    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1007    tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1008    tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1009
1010    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1011    tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
1012
1013    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1014    tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
1015
1016    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1017    tu_cs_emit(cs, 0x00000000);
1018    tu_cs_emit(cs, 0x00000000);
1019    tu_cs_emit(cs, 0x00000000);
1020
1021    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1022    tu_cs_emit(cs, 0x00000000);
1023    tu_cs_emit(cs, 0x00000000);
1024    tu_cs_emit(cs, 0x00000000);
1025    tu_cs_emit(cs, 0x00000000);
1026    tu_cs_emit(cs, 0x00000000);
1027    tu_cs_emit(cs, 0x00000000);
1028
1029    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1030    tu_cs_emit(cs, 0x00000000);
1031    tu_cs_emit(cs, 0x00000000);
1032    tu_cs_emit(cs, 0x00000000);
1033    tu_cs_emit(cs, 0x00000000);
1034    tu_cs_emit(cs, 0x00000000);
1035    tu_cs_emit(cs, 0x00000000);
1036
1037    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1038    tu_cs_emit(cs, 0x00000000);
1039    tu_cs_emit(cs, 0x00000000);
1040    tu_cs_emit(cs, 0x00000000);
1041
1042    tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
1043    tu_cs_emit(cs, 0x00000000);
1044
1045    tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1046    tu_cs_emit(cs, 0x00000000);
1047
1048    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1049    tu_cs_emit(cs, 0x00000000);
1050
1051    tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1052    tu_cs_emit(cs, 0x00000000);
1053
1054    tu_cs_sanity_check(cs);
1055 }
1056
1057 static void
1058 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1059 {
1060    VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
1061    if (result != VK_SUCCESS) {
1062       cmd->record_result = result;
1063       return;
1064    }
1065
1066    tu6_emit_lrz_flush(cmd, cs);
1067
1068    /* lrz clear? */
1069
1070    tu6_emit_cache_flush(cmd, cs);
1071
1072    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1073    tu_cs_emit(cs, 0x0);
1074
1075    /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1076    tu6_emit_wfi(cmd, cs);
1077    tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1078    tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1079
1080    tu6_emit_zs(cmd, cs);
1081    tu6_emit_mrt(cmd, cs);
1082    tu6_emit_msaa(cmd, cs);
1083
1084    if (false) {
1085       /* hw binning? */
1086    } else {
1087       tu6_emit_bin_size(cmd, cs, 0x6000000);
1088       /* no draws */
1089    }
1090
1091    tu6_emit_render_cntl(cmd, cs, false);
1092
1093    tu_cs_sanity_check(cs);
1094 }
1095
1096 static void
1097 tu6_render_tile(struct tu_cmd_buffer *cmd,
1098                 struct tu_cs *cs,
1099                 const struct tu_tile *tile)
1100 {
1101    const uint32_t render_tile_space = 64 + tu_cs_get_call_size(&cmd->draw_cs);
1102    VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1103    if (result != VK_SUCCESS) {
1104       cmd->record_result = result;
1105       return;
1106    }
1107
1108    tu6_emit_tile_select(cmd, cs, tile);
1109    tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1110
1111    tu_cs_emit_call(cs, &cmd->draw_cs);
1112    cmd->wait_for_idle = true;
1113
1114    tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1115
1116    tu_cs_sanity_check(cs);
1117 }
1118
1119 static void
1120 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1121 {
1122    const struct tu_subpass *subpass = cmd->state.subpass;
1123    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1124
1125    VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1126    if (result != VK_SUCCESS) {
1127       cmd->record_result = result;
1128       return;
1129    }
1130
1131    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1132    tu_cs_emit(cs, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1133
1134    tu6_emit_lrz_flush(cmd, cs);
1135
1136    tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1137
1138    if (subpass->has_resolve) {
1139       for (uint32_t i = 0; i < subpass->color_count; ++i) {
1140          struct tu_subpass_attachment src_att = subpass->color_attachments[i];
1141          struct tu_subpass_attachment dst_att = subpass->resolve_attachments[i];
1142
1143          if (dst_att.attachment == VK_ATTACHMENT_UNUSED)
1144             continue;
1145
1146          struct tu_image *src_img = fb->attachments[src_att.attachment].attachment->image;
1147          struct tu_image *dst_img = fb->attachments[dst_att.attachment].attachment->image;
1148
1149          assert(src_img->extent.width == dst_img->extent.width);
1150          assert(src_img->extent.height == dst_img->extent.height);
1151
1152          tu_bo_list_add(&cmd->bo_list, src_img->bo, MSM_SUBMIT_BO_READ);
1153          tu_bo_list_add(&cmd->bo_list, dst_img->bo, MSM_SUBMIT_BO_WRITE);
1154
1155          tu_blit(cmd, &(struct tu_blit) {
1156             .dst = tu_blit_surf_whole(dst_img),
1157             .src = tu_blit_surf_whole(src_img),
1158             .layers = 1,
1159          }, false);
1160       }
1161    }
1162
1163    tu_cs_sanity_check(cs);
1164 }
1165
1166 static void
1167 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1168 {
1169    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1170
1171    tu6_render_begin(cmd, &cmd->cs);
1172
1173    for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1174       for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1175          struct tu_tile tile;
1176          tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1177          tu6_render_tile(cmd, &cmd->cs, &tile);
1178       }
1179    }
1180
1181    tu6_render_end(cmd, &cmd->cs);
1182 }
1183
1184 static void
1185 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd)
1186 {
1187    const uint32_t tile_load_space = 16 + 32 * MAX_RTS;
1188    const struct tu_subpass *subpass = cmd->state.subpass;
1189    struct tu_attachment_state *attachments = cmd->state.attachments;
1190    struct tu_cs sub_cs;
1191
1192    VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1193                                             tile_load_space, &sub_cs);
1194    if (result != VK_SUCCESS) {
1195       cmd->record_result = result;
1196       return;
1197    }
1198
1199    /* emit to tile-load sub_cs */
1200    tu6_emit_tile_load(cmd, &sub_cs);
1201
1202    cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1203
1204    for (uint32_t i = 0; i < subpass->color_count; ++i) {
1205       const uint32_t a = subpass->color_attachments[i].attachment;
1206       if (a != VK_ATTACHMENT_UNUSED)
1207          attachments[a].pending_clear_aspects = 0;
1208    }
1209 }
1210
1211 static void
1212 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1213 {
1214    const uint32_t tile_store_space = 32 + 32 * MAX_RTS;
1215    struct tu_cs sub_cs;
1216
1217    VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1218                                             tile_store_space, &sub_cs);
1219    if (result != VK_SUCCESS) {
1220       cmd->record_result = result;
1221       return;
1222    }
1223
1224    /* emit to tile-store sub_cs */
1225    tu6_emit_tile_store(cmd, &sub_cs);
1226
1227    cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1228 }
1229
1230 static void
1231 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1232                             const VkRect2D *render_area)
1233 {
1234    const struct tu_device *dev = cmd->device;
1235    const struct tu_render_pass *pass = cmd->state.pass;
1236    const struct tu_subpass *subpass = cmd->state.subpass;
1237    struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1238
1239    uint32_t buffer_cpp[MAX_RTS + 2];
1240    uint32_t buffer_count = 0;
1241
1242    for (uint32_t i = 0; i < subpass->color_count; ++i) {
1243       const uint32_t a = subpass->color_attachments[i].attachment;
1244       if (a == VK_ATTACHMENT_UNUSED)
1245          continue;
1246
1247       const struct tu_render_pass_attachment *att = &pass->attachments[a];
1248       buffer_cpp[buffer_count++] =
1249          vk_format_get_blocksize(att->format) * att->samples;
1250    }
1251
1252    if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1253       const uint32_t a = subpass->depth_stencil_attachment.attachment;
1254       const struct tu_render_pass_attachment *att = &pass->attachments[a];
1255
1256       /* TODO */
1257       assert(att->format != VK_FORMAT_D32_SFLOAT_S8_UINT);
1258
1259       buffer_cpp[buffer_count++] =
1260          vk_format_get_blocksize(att->format) * att->samples;
1261    }
1262
1263    tu_tiling_config_update(tiling, dev, buffer_cpp, buffer_count,
1264                            render_area);
1265 }
1266
1267 const struct tu_dynamic_state default_dynamic_state = {
1268    .viewport =
1269      {
1270        .count = 0,
1271      },
1272    .scissor =
1273      {
1274        .count = 0,
1275      },
1276    .line_width = 1.0f,
1277    .depth_bias =
1278      {
1279        .bias = 0.0f,
1280        .clamp = 0.0f,
1281        .slope = 0.0f,
1282      },
1283    .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1284    .depth_bounds =
1285      {
1286        .min = 0.0f,
1287        .max = 1.0f,
1288      },
1289    .stencil_compare_mask =
1290      {
1291        .front = ~0u,
1292        .back = ~0u,
1293      },
1294    .stencil_write_mask =
1295      {
1296        .front = ~0u,
1297        .back = ~0u,
1298      },
1299    .stencil_reference =
1300      {
1301        .front = 0u,
1302        .back = 0u,
1303      },
1304 };
1305
1306 static void UNUSED /* FINISHME */
1307 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1308                       const struct tu_dynamic_state *src)
1309 {
1310    struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1311    uint32_t copy_mask = src->mask;
1312    uint32_t dest_mask = 0;
1313
1314    tu_use_args(cmd_buffer); /* FINISHME */
1315
1316    /* Make sure to copy the number of viewports/scissors because they can
1317     * only be specified at pipeline creation time.
1318     */
1319    dest->viewport.count = src->viewport.count;
1320    dest->scissor.count = src->scissor.count;
1321    dest->discard_rectangle.count = src->discard_rectangle.count;
1322
1323    if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1324       if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1325                  src->viewport.count * sizeof(VkViewport))) {
1326          typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1327                       src->viewport.count);
1328          dest_mask |= TU_DYNAMIC_VIEWPORT;
1329       }
1330    }
1331
1332    if (copy_mask & TU_DYNAMIC_SCISSOR) {
1333       if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1334                  src->scissor.count * sizeof(VkRect2D))) {
1335          typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1336                       src->scissor.count);
1337          dest_mask |= TU_DYNAMIC_SCISSOR;
1338       }
1339    }
1340
1341    if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1342       if (dest->line_width != src->line_width) {
1343          dest->line_width = src->line_width;
1344          dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1345       }
1346    }
1347
1348    if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1349       if (memcmp(&dest->depth_bias, &src->depth_bias,
1350                  sizeof(src->depth_bias))) {
1351          dest->depth_bias = src->depth_bias;
1352          dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1353       }
1354    }
1355
1356    if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1357       if (memcmp(&dest->blend_constants, &src->blend_constants,
1358                  sizeof(src->blend_constants))) {
1359          typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1360          dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1361       }
1362    }
1363
1364    if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1365       if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1366                  sizeof(src->depth_bounds))) {
1367          dest->depth_bounds = src->depth_bounds;
1368          dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1369       }
1370    }
1371
1372    if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1373       if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1374                  sizeof(src->stencil_compare_mask))) {
1375          dest->stencil_compare_mask = src->stencil_compare_mask;
1376          dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1377       }
1378    }
1379
1380    if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1381       if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1382                  sizeof(src->stencil_write_mask))) {
1383          dest->stencil_write_mask = src->stencil_write_mask;
1384          dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1385       }
1386    }
1387
1388    if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1389       if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1390                  sizeof(src->stencil_reference))) {
1391          dest->stencil_reference = src->stencil_reference;
1392          dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1393       }
1394    }
1395
1396    if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1397       if (memcmp(&dest->discard_rectangle.rectangles,
1398                  &src->discard_rectangle.rectangles,
1399                  src->discard_rectangle.count * sizeof(VkRect2D))) {
1400          typed_memcpy(dest->discard_rectangle.rectangles,
1401                       src->discard_rectangle.rectangles,
1402                       src->discard_rectangle.count);
1403          dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1404       }
1405    }
1406 }
1407
1408 static VkResult
1409 tu_create_cmd_buffer(struct tu_device *device,
1410                      struct tu_cmd_pool *pool,
1411                      VkCommandBufferLevel level,
1412                      VkCommandBuffer *pCommandBuffer)
1413 {
1414    struct tu_cmd_buffer *cmd_buffer;
1415    cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1416                           VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1417    if (cmd_buffer == NULL)
1418       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1419
1420    cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1421    cmd_buffer->device = device;
1422    cmd_buffer->pool = pool;
1423    cmd_buffer->level = level;
1424
1425    if (pool) {
1426       list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1427       cmd_buffer->queue_family_index = pool->queue_family_index;
1428
1429    } else {
1430       /* Init the pool_link so we can safely call list_del when we destroy
1431        * the command buffer
1432        */
1433       list_inithead(&cmd_buffer->pool_link);
1434       cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1435    }
1436
1437    tu_bo_list_init(&cmd_buffer->bo_list);
1438    tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1439    tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1440    tu_cs_init(&cmd_buffer->draw_state, TU_CS_MODE_SUB_STREAM, 2048);
1441    tu_cs_init(&cmd_buffer->tile_cs, TU_CS_MODE_SUB_STREAM, 1024);
1442
1443    *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1444
1445    list_inithead(&cmd_buffer->upload.list);
1446
1447    cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1448       cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1449
1450    VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1451    if (result != VK_SUCCESS)
1452       return result;
1453
1454    return VK_SUCCESS;
1455 }
1456
1457 static void
1458 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1459 {
1460    tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1461
1462    list_del(&cmd_buffer->pool_link);
1463
1464    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1465       free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1466
1467    tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1468    tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1469    tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_state);
1470    tu_cs_finish(cmd_buffer->device, &cmd_buffer->tile_cs);
1471
1472    tu_bo_list_destroy(&cmd_buffer->bo_list);
1473    vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1474 }
1475
1476 static VkResult
1477 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1478 {
1479    cmd_buffer->wait_for_idle = true;
1480
1481    cmd_buffer->record_result = VK_SUCCESS;
1482
1483    tu_bo_list_reset(&cmd_buffer->bo_list);
1484    tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1485    tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1486    tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_state);
1487    tu_cs_reset(cmd_buffer->device, &cmd_buffer->tile_cs);
1488
1489    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1490       cmd_buffer->descriptors[i].dirty = 0;
1491       cmd_buffer->descriptors[i].valid = 0;
1492       cmd_buffer->descriptors[i].push_dirty = false;
1493    }
1494
1495    cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1496
1497    return cmd_buffer->record_result;
1498 }
1499
1500 static VkResult
1501 tu_cmd_state_setup_attachments(struct tu_cmd_buffer *cmd_buffer,
1502                                const VkRenderPassBeginInfo *info)
1503 {
1504    struct tu_cmd_state *state = &cmd_buffer->state;
1505    const struct tu_framebuffer *fb = state->framebuffer;
1506    const struct tu_render_pass *pass = state->pass;
1507
1508    for (uint32_t i = 0; i < fb->attachment_count; ++i) {
1509       const struct tu_image_view *iview = fb->attachments[i].attachment;
1510       tu_bo_list_add(&cmd_buffer->bo_list, iview->image->bo,
1511                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1512    }
1513
1514    if (pass->attachment_count == 0) {
1515       state->attachments = NULL;
1516       return VK_SUCCESS;
1517    }
1518
1519    state->attachments =
1520       vk_alloc(&cmd_buffer->pool->alloc,
1521                pass->attachment_count * sizeof(state->attachments[0]), 8,
1522                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1523    if (state->attachments == NULL) {
1524       cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1525       return cmd_buffer->record_result;
1526    }
1527
1528    for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1529       const struct tu_render_pass_attachment *att = &pass->attachments[i];
1530       VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1531       VkImageAspectFlags clear_aspects = 0;
1532
1533       if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1534          /* color attachment */
1535          if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1536             clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1537          }
1538       } else {
1539          /* depthstencil attachment */
1540          if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1541              att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1542             clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1543             if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1544                 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1545                clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1546          }
1547          if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1548              att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1549             clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1550          }
1551       }
1552
1553       state->attachments[i].pending_clear_aspects = clear_aspects;
1554       state->attachments[i].cleared_views = 0;
1555       if (clear_aspects && info) {
1556          assert(info->clearValueCount > i);
1557          state->attachments[i].clear_value = info->pClearValues[i];
1558       }
1559
1560       state->attachments[i].current_layout = att->initial_layout;
1561    }
1562
1563    return VK_SUCCESS;
1564 }
1565
1566 VkResult
1567 tu_AllocateCommandBuffers(VkDevice _device,
1568                           const VkCommandBufferAllocateInfo *pAllocateInfo,
1569                           VkCommandBuffer *pCommandBuffers)
1570 {
1571    TU_FROM_HANDLE(tu_device, device, _device);
1572    TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1573
1574    VkResult result = VK_SUCCESS;
1575    uint32_t i;
1576
1577    for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1578
1579       if (!list_empty(&pool->free_cmd_buffers)) {
1580          struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1581             &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1582
1583          list_del(&cmd_buffer->pool_link);
1584          list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1585
1586          result = tu_reset_cmd_buffer(cmd_buffer);
1587          cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1588          cmd_buffer->level = pAllocateInfo->level;
1589
1590          pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1591       } else {
1592          result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1593                                        &pCommandBuffers[i]);
1594       }
1595       if (result != VK_SUCCESS)
1596          break;
1597    }
1598
1599    if (result != VK_SUCCESS) {
1600       tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1601                             pCommandBuffers);
1602
1603       /* From the Vulkan 1.0.66 spec:
1604        *
1605        * "vkAllocateCommandBuffers can be used to create multiple
1606        *  command buffers. If the creation of any of those command
1607        *  buffers fails, the implementation must destroy all
1608        *  successfully created command buffer objects from this
1609        *  command, set all entries of the pCommandBuffers array to
1610        *  NULL and return the error."
1611        */
1612       memset(pCommandBuffers, 0,
1613              sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1614    }
1615
1616    return result;
1617 }
1618
1619 void
1620 tu_FreeCommandBuffers(VkDevice device,
1621                       VkCommandPool commandPool,
1622                       uint32_t commandBufferCount,
1623                       const VkCommandBuffer *pCommandBuffers)
1624 {
1625    for (uint32_t i = 0; i < commandBufferCount; i++) {
1626       TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1627
1628       if (cmd_buffer) {
1629          if (cmd_buffer->pool) {
1630             list_del(&cmd_buffer->pool_link);
1631             list_addtail(&cmd_buffer->pool_link,
1632                          &cmd_buffer->pool->free_cmd_buffers);
1633          } else
1634             tu_cmd_buffer_destroy(cmd_buffer);
1635       }
1636    }
1637 }
1638
1639 VkResult
1640 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1641                       VkCommandBufferResetFlags flags)
1642 {
1643    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1644    return tu_reset_cmd_buffer(cmd_buffer);
1645 }
1646
1647 VkResult
1648 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1649                       const VkCommandBufferBeginInfo *pBeginInfo)
1650 {
1651    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1652    VkResult result = VK_SUCCESS;
1653
1654    if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1655       /* If the command buffer has already been resetted with
1656        * vkResetCommandBuffer, no need to do it again.
1657        */
1658       result = tu_reset_cmd_buffer(cmd_buffer);
1659       if (result != VK_SUCCESS)
1660          return result;
1661    }
1662
1663    memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1664    cmd_buffer->usage_flags = pBeginInfo->flags;
1665
1666    tu_cs_begin(&cmd_buffer->cs);
1667
1668    cmd_buffer->marker_seqno = 0;
1669    cmd_buffer->scratch_seqno = 0;
1670
1671    /* setup initial configuration into command buffer */
1672    if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1673       switch (cmd_buffer->queue_family_index) {
1674       case TU_QUEUE_GENERAL:
1675          tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1676          break;
1677       default:
1678          break;
1679       }
1680    }
1681
1682    cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1683
1684    return VK_SUCCESS;
1685 }
1686
1687 void
1688 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1689                         uint32_t firstBinding,
1690                         uint32_t bindingCount,
1691                         const VkBuffer *pBuffers,
1692                         const VkDeviceSize *pOffsets)
1693 {
1694    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1695
1696    assert(firstBinding + bindingCount <= MAX_VBS);
1697
1698    for (uint32_t i = 0; i < bindingCount; i++) {
1699       cmd->state.vb.buffers[firstBinding + i] =
1700          tu_buffer_from_handle(pBuffers[i]);
1701       cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1702    }
1703
1704    /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1705    cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1706 }
1707
1708 void
1709 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1710                       VkBuffer buffer,
1711                       VkDeviceSize offset,
1712                       VkIndexType indexType)
1713 {
1714    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1715    TU_FROM_HANDLE(tu_buffer, buf, buffer);
1716
1717    /* initialize/update the restart index */
1718    if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1719       struct tu_cs *draw_cs = &cmd->draw_cs;
1720       VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1721       if (result != VK_SUCCESS) {
1722          cmd->record_result = result;
1723          return;
1724       }
1725
1726       tu6_emit_restart_index(
1727          draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1728
1729       tu_cs_sanity_check(draw_cs);
1730    }
1731
1732    /* track the BO */
1733    if (cmd->state.index_buffer != buf)
1734       tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1735
1736    cmd->state.index_buffer = buf;
1737    cmd->state.index_offset = offset;
1738    cmd->state.index_type = indexType;
1739 }
1740
1741 void
1742 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1743                          VkPipelineBindPoint pipelineBindPoint,
1744                          VkPipelineLayout _layout,
1745                          uint32_t firstSet,
1746                          uint32_t descriptorSetCount,
1747                          const VkDescriptorSet *pDescriptorSets,
1748                          uint32_t dynamicOffsetCount,
1749                          const uint32_t *pDynamicOffsets)
1750 {
1751    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1752    TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1753    unsigned dyn_idx = 0;
1754
1755    struct tu_descriptor_state *descriptors_state =
1756       tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1757
1758    for (unsigned i = 0; i < descriptorSetCount; ++i) {
1759       unsigned idx = i + firstSet;
1760       TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1761
1762       descriptors_state->sets[idx] = set;
1763       descriptors_state->valid |= (1u << idx);
1764
1765       for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1766          unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1767          assert(dyn_idx < dynamicOffsetCount);
1768
1769          descriptors_state->dynamic_buffers[idx] =
1770          set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
1771       }
1772    }
1773
1774    cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1775 }
1776
1777 void
1778 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1779                     VkPipelineLayout layout,
1780                     VkShaderStageFlags stageFlags,
1781                     uint32_t offset,
1782                     uint32_t size,
1783                     const void *pValues)
1784 {
1785    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1786    memcpy((void*) cmd_buffer->push_constants + offset, pValues, size);
1787 }
1788
1789 VkResult
1790 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1791 {
1792    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1793
1794    if (cmd_buffer->scratch_seqno) {
1795       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1796                      MSM_SUBMIT_BO_WRITE);
1797    }
1798
1799    for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1800       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1801                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1802    }
1803
1804    for (uint32_t i = 0; i < cmd_buffer->draw_state.bo_count; i++) {
1805       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_state.bos[i],
1806                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1807    }
1808
1809    for (uint32_t i = 0; i < cmd_buffer->tile_cs.bo_count; i++) {
1810       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->tile_cs.bos[i],
1811                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1812    }
1813
1814    tu_cs_end(&cmd_buffer->cs);
1815
1816    assert(!cmd_buffer->state.attachments);
1817
1818    cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1819
1820    return cmd_buffer->record_result;
1821 }
1822
1823 void
1824 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
1825                    VkPipelineBindPoint pipelineBindPoint,
1826                    VkPipeline _pipeline)
1827 {
1828    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1829    TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1830
1831    switch (pipelineBindPoint) {
1832    case VK_PIPELINE_BIND_POINT_GRAPHICS:
1833       cmd->state.pipeline = pipeline;
1834       cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
1835       break;
1836    case VK_PIPELINE_BIND_POINT_COMPUTE:
1837       tu_finishme("binding compute pipeline");
1838       break;
1839    default:
1840       unreachable("unrecognized pipeline bind point");
1841       break;
1842    }
1843 }
1844
1845 void
1846 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
1847                   uint32_t firstViewport,
1848                   uint32_t viewportCount,
1849                   const VkViewport *pViewports)
1850 {
1851    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1852    struct tu_cs *draw_cs = &cmd->draw_cs;
1853
1854    VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
1855    if (result != VK_SUCCESS) {
1856       cmd->record_result = result;
1857       return;
1858    }
1859
1860    assert(firstViewport == 0 && viewportCount == 1);
1861    tu6_emit_viewport(draw_cs, pViewports);
1862
1863    tu_cs_sanity_check(draw_cs);
1864 }
1865
1866 void
1867 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
1868                  uint32_t firstScissor,
1869                  uint32_t scissorCount,
1870                  const VkRect2D *pScissors)
1871 {
1872    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1873    struct tu_cs *draw_cs = &cmd->draw_cs;
1874
1875    VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
1876    if (result != VK_SUCCESS) {
1877       cmd->record_result = result;
1878       return;
1879    }
1880
1881    assert(firstScissor == 0 && scissorCount == 1);
1882    tu6_emit_scissor(draw_cs, pScissors);
1883
1884    tu_cs_sanity_check(draw_cs);
1885 }
1886
1887 void
1888 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
1889 {
1890    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1891
1892    cmd->state.dynamic.line_width = lineWidth;
1893
1894    /* line width depends on VkPipelineRasterizationStateCreateInfo */
1895    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1896 }
1897
1898 void
1899 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
1900                    float depthBiasConstantFactor,
1901                    float depthBiasClamp,
1902                    float depthBiasSlopeFactor)
1903 {
1904    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1905    struct tu_cs *draw_cs = &cmd->draw_cs;
1906
1907    VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
1908    if (result != VK_SUCCESS) {
1909       cmd->record_result = result;
1910       return;
1911    }
1912
1913    tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
1914                        depthBiasSlopeFactor);
1915
1916    tu_cs_sanity_check(draw_cs);
1917 }
1918
1919 void
1920 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
1921                         const float blendConstants[4])
1922 {
1923    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1924    struct tu_cs *draw_cs = &cmd->draw_cs;
1925
1926    VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
1927    if (result != VK_SUCCESS) {
1928       cmd->record_result = result;
1929       return;
1930    }
1931
1932    tu6_emit_blend_constants(draw_cs, blendConstants);
1933
1934    tu_cs_sanity_check(draw_cs);
1935 }
1936
1937 void
1938 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
1939                      float minDepthBounds,
1940                      float maxDepthBounds)
1941 {
1942 }
1943
1944 void
1945 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
1946                             VkStencilFaceFlags faceMask,
1947                             uint32_t compareMask)
1948 {
1949    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1950
1951    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1952       cmd->state.dynamic.stencil_compare_mask.front = compareMask;
1953    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1954       cmd->state.dynamic.stencil_compare_mask.back = compareMask;
1955
1956    /* the front/back compare masks must be updated together */
1957    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1958 }
1959
1960 void
1961 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
1962                           VkStencilFaceFlags faceMask,
1963                           uint32_t writeMask)
1964 {
1965    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1966
1967    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1968       cmd->state.dynamic.stencil_write_mask.front = writeMask;
1969    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1970       cmd->state.dynamic.stencil_write_mask.back = writeMask;
1971
1972    /* the front/back write masks must be updated together */
1973    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1974 }
1975
1976 void
1977 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
1978                           VkStencilFaceFlags faceMask,
1979                           uint32_t reference)
1980 {
1981    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1982
1983    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1984       cmd->state.dynamic.stencil_reference.front = reference;
1985    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1986       cmd->state.dynamic.stencil_reference.back = reference;
1987
1988    /* the front/back references must be updated together */
1989    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1990 }
1991
1992 void
1993 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
1994                       uint32_t commandBufferCount,
1995                       const VkCommandBuffer *pCmdBuffers)
1996 {
1997 }
1998
1999 VkResult
2000 tu_CreateCommandPool(VkDevice _device,
2001                      const VkCommandPoolCreateInfo *pCreateInfo,
2002                      const VkAllocationCallbacks *pAllocator,
2003                      VkCommandPool *pCmdPool)
2004 {
2005    TU_FROM_HANDLE(tu_device, device, _device);
2006    struct tu_cmd_pool *pool;
2007
2008    pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2009                     VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2010    if (pool == NULL)
2011       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2012
2013    if (pAllocator)
2014       pool->alloc = *pAllocator;
2015    else
2016       pool->alloc = device->alloc;
2017
2018    list_inithead(&pool->cmd_buffers);
2019    list_inithead(&pool->free_cmd_buffers);
2020
2021    pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2022
2023    *pCmdPool = tu_cmd_pool_to_handle(pool);
2024
2025    return VK_SUCCESS;
2026 }
2027
2028 void
2029 tu_DestroyCommandPool(VkDevice _device,
2030                       VkCommandPool commandPool,
2031                       const VkAllocationCallbacks *pAllocator)
2032 {
2033    TU_FROM_HANDLE(tu_device, device, _device);
2034    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2035
2036    if (!pool)
2037       return;
2038
2039    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2040                             &pool->cmd_buffers, pool_link)
2041    {
2042       tu_cmd_buffer_destroy(cmd_buffer);
2043    }
2044
2045    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2046                             &pool->free_cmd_buffers, pool_link)
2047    {
2048       tu_cmd_buffer_destroy(cmd_buffer);
2049    }
2050
2051    vk_free2(&device->alloc, pAllocator, pool);
2052 }
2053
2054 VkResult
2055 tu_ResetCommandPool(VkDevice device,
2056                     VkCommandPool commandPool,
2057                     VkCommandPoolResetFlags flags)
2058 {
2059    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2060    VkResult result;
2061
2062    list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2063                        pool_link)
2064    {
2065       result = tu_reset_cmd_buffer(cmd_buffer);
2066       if (result != VK_SUCCESS)
2067          return result;
2068    }
2069
2070    return VK_SUCCESS;
2071 }
2072
2073 void
2074 tu_TrimCommandPool(VkDevice device,
2075                    VkCommandPool commandPool,
2076                    VkCommandPoolTrimFlags flags)
2077 {
2078    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2079
2080    if (!pool)
2081       return;
2082
2083    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2084                             &pool->free_cmd_buffers, pool_link)
2085    {
2086       tu_cmd_buffer_destroy(cmd_buffer);
2087    }
2088 }
2089
2090 void
2091 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2092                       const VkRenderPassBeginInfo *pRenderPassBegin,
2093                       VkSubpassContents contents)
2094 {
2095    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2096    TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2097    TU_FROM_HANDLE(tu_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2098    VkResult result;
2099
2100    cmd_buffer->state.pass = pass;
2101    cmd_buffer->state.subpass = pass->subpasses;
2102    cmd_buffer->state.framebuffer = framebuffer;
2103
2104    result = tu_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
2105    if (result != VK_SUCCESS)
2106       return;
2107
2108    tu_cmd_update_tiling_config(cmd_buffer, &pRenderPassBegin->renderArea);
2109    tu_cmd_prepare_tile_load_ib(cmd_buffer);
2110    tu_cmd_prepare_tile_store_ib(cmd_buffer);
2111
2112    /* draw_cs should contain entries only for this render pass */
2113    assert(!cmd_buffer->draw_cs.entry_count);
2114    tu_cs_begin(&cmd_buffer->draw_cs);
2115 }
2116
2117 void
2118 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer,
2119                           const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2120                           const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2121 {
2122    tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2123                          pSubpassBeginInfo->contents);
2124 }
2125
2126 void
2127 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2128 {
2129    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2130
2131    tu_cmd_render_tiles(cmd);
2132
2133    cmd->state.subpass++;
2134
2135    tu_cmd_update_tiling_config(cmd, NULL);
2136    tu_cmd_prepare_tile_load_ib(cmd);
2137    tu_cmd_prepare_tile_store_ib(cmd);
2138 }
2139
2140 void
2141 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer,
2142                       const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2143                       const VkSubpassEndInfoKHR *pSubpassEndInfo)
2144 {
2145    tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2146 }
2147
2148 struct tu_draw_info
2149 {
2150    /**
2151     * Number of vertices.
2152     */
2153    uint32_t count;
2154
2155    /**
2156     * Index of the first vertex.
2157     */
2158    int32_t vertex_offset;
2159
2160    /**
2161     * First instance id.
2162     */
2163    uint32_t first_instance;
2164
2165    /**
2166     * Number of instances.
2167     */
2168    uint32_t instance_count;
2169
2170    /**
2171     * First index (indexed draws only).
2172     */
2173    uint32_t first_index;
2174
2175    /**
2176     * Whether it's an indexed draw.
2177     */
2178    bool indexed;
2179
2180    /**
2181     * Indirect draw parameters resource.
2182     */
2183    struct tu_buffer *indirect;
2184    uint64_t indirect_offset;
2185    uint32_t stride;
2186
2187    /**
2188     * Draw count parameters resource.
2189     */
2190    struct tu_buffer *count_buffer;
2191    uint64_t count_buffer_offset;
2192 };
2193
2194 enum tu_draw_state_group_id
2195 {
2196    TU_DRAW_STATE_PROGRAM,
2197    TU_DRAW_STATE_PROGRAM_BINNING,
2198    TU_DRAW_STATE_VI,
2199    TU_DRAW_STATE_VI_BINNING,
2200    TU_DRAW_STATE_VP,
2201    TU_DRAW_STATE_RAST,
2202    TU_DRAW_STATE_DS,
2203    TU_DRAW_STATE_BLEND,
2204    TU_DRAW_STATE_VS_CONST,
2205    TU_DRAW_STATE_FS_CONST,
2206    TU_DRAW_STATE_VS_TEX,
2207    TU_DRAW_STATE_FS_TEX,
2208
2209    TU_DRAW_STATE_COUNT,
2210 };
2211
2212 struct tu_draw_state_group
2213 {
2214    enum tu_draw_state_group_id id;
2215    uint32_t enable_mask;
2216    struct tu_cs_entry ib;
2217 };
2218
2219 static struct tu_sampler*
2220 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2221             const struct tu_descriptor_map *map, unsigned i)
2222 {
2223    assert(descriptors_state->valid & (1 << map->set[i]));
2224
2225    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2226    assert(map->binding[i] < set->layout->binding_count);
2227
2228    const struct tu_descriptor_set_binding_layout *layout =
2229       &set->layout->binding[map->binding[i]];
2230
2231    switch (layout->type) {
2232    case VK_DESCRIPTOR_TYPE_SAMPLER:
2233       return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2234    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2235       return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS];
2236    default:
2237       unreachable("unimplemented descriptor type");
2238       break;
2239    }
2240 }
2241
2242 static uint32_t*
2243 texture_ptr(struct tu_descriptor_state *descriptors_state,
2244             const struct tu_descriptor_map *map, unsigned i)
2245 {
2246    assert(descriptors_state->valid & (1 << map->set[i]));
2247
2248    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2249    assert(map->binding[i] < set->layout->binding_count);
2250
2251    const struct tu_descriptor_set_binding_layout *layout =
2252       &set->layout->binding[map->binding[i]];
2253
2254    switch (layout->type) {
2255    case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2256    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2257       return &set->mapped_ptr[layout->offset / 4];
2258    case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2259    case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2260       return &set->mapped_ptr[layout->offset / 4];
2261    default:
2262       unreachable("unimplemented descriptor type");
2263       break;
2264    }
2265 }
2266
2267 static uint64_t
2268 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2269            const struct tu_descriptor_map *map,
2270            unsigned i)
2271 {
2272    assert(descriptors_state->valid & (1 << map->set[i]));
2273
2274    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2275    assert(map->binding[i] < set->layout->binding_count);
2276
2277    const struct tu_descriptor_set_binding_layout *layout =
2278       &set->layout->binding[map->binding[i]];
2279
2280    switch (layout->type) {
2281    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2282    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2283       return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset];
2284    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2285    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2286       return (uint64_t) set->mapped_ptr[layout->offset / 4 + 1] << 32 |
2287                         set->mapped_ptr[layout->offset / 4];
2288    default:
2289       unreachable("unimplemented descriptor type");
2290       break;
2291    }
2292 }
2293
2294 static inline uint32_t
2295 tu6_stage2opcode(gl_shader_stage type)
2296 {
2297    switch (type) {
2298    case MESA_SHADER_VERTEX:
2299    case MESA_SHADER_TESS_CTRL:
2300    case MESA_SHADER_TESS_EVAL:
2301    case MESA_SHADER_GEOMETRY:
2302       return CP_LOAD_STATE6_GEOM;
2303    case MESA_SHADER_FRAGMENT:
2304    case MESA_SHADER_COMPUTE:
2305    case MESA_SHADER_KERNEL:
2306       return CP_LOAD_STATE6_FRAG;
2307    default:
2308       unreachable("bad shader type");
2309    }
2310 }
2311
2312 static inline enum a6xx_state_block
2313 tu6_stage2shadersb(gl_shader_stage type)
2314 {
2315    switch (type) {
2316    case MESA_SHADER_VERTEX:
2317       return SB6_VS_SHADER;
2318    case MESA_SHADER_FRAGMENT:
2319       return SB6_FS_SHADER;
2320    case MESA_SHADER_COMPUTE:
2321    case MESA_SHADER_KERNEL:
2322       return SB6_CS_SHADER;
2323    default:
2324       unreachable("bad shader type");
2325       return ~0;
2326    }
2327 }
2328
2329 static void
2330 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2331                      struct tu_descriptor_state *descriptors_state,
2332                      gl_shader_stage type,
2333                      uint32_t *push_constants)
2334 {
2335    const struct tu_program_descriptor_linkage *link =
2336       &pipeline->program.link[type];
2337    const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2338
2339    for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2340       if (state->range[i].start < state->range[i].end) {
2341          uint32_t size = state->range[i].end - state->range[i].start;
2342          uint32_t offset = state->range[i].start;
2343
2344          /* and even if the start of the const buffer is before
2345           * first_immediate, the end may not be:
2346           */
2347          size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2348
2349          if (size == 0)
2350             continue;
2351
2352          /* things should be aligned to vec4: */
2353          debug_assert((state->range[i].offset % 16) == 0);
2354          debug_assert((size % 16) == 0);
2355          debug_assert((offset % 16) == 0);
2356
2357          if (i == 0) {
2358             /* push constants */
2359             tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2360             tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2361                   CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2362                   CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2363                   CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2364                   CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2365             tu_cs_emit(cs, 0);
2366             tu_cs_emit(cs, 0);
2367             for (unsigned i = 0; i < size / 4; i++)
2368                tu_cs_emit(cs, push_constants[i + offset / 4]);
2369             continue;
2370          }
2371
2372          uint64_t va = buffer_ptr(descriptors_state, &link->ubo_map, i - 1);
2373
2374          tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2375          tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2376                CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2377                CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2378                CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2379                CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2380          tu_cs_emit_qw(cs, va + offset);
2381       }
2382    }
2383 }
2384
2385 static void
2386 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2387               struct tu_descriptor_state *descriptors_state,
2388               gl_shader_stage type)
2389 {
2390    const struct tu_program_descriptor_linkage *link =
2391       &pipeline->program.link[type];
2392
2393    uint32_t num = MIN2(link->ubo_map.num, link->const_state.num_ubos);
2394    uint32_t anum = align(num, 2);
2395    uint32_t i;
2396
2397    if (!num)
2398       return;
2399
2400    tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2401    tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2402          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2403          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2404          CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2405          CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2406    tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2407    tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2408
2409    for (i = 0; i < num; i++)
2410       tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i));
2411
2412    for (; i < anum; i++) {
2413       tu_cs_emit(cs, 0xffffffff);
2414       tu_cs_emit(cs, 0xffffffff);
2415    }
2416 }
2417
2418 static struct tu_cs_entry
2419 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2420                 const struct tu_pipeline *pipeline,
2421                 struct tu_descriptor_state *descriptors_state,
2422                 gl_shader_stage type)
2423 {
2424    struct tu_cs cs;
2425    tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, 512, &cs); /* TODO: maximum size? */
2426
2427    tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2428    tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2429
2430    return tu_cs_end_sub_stream(&cmd->draw_state, &cs);
2431 }
2432
2433 static struct tu_cs_entry
2434 tu6_emit_textures(struct tu_device *device, struct tu_cs *draw_state,
2435                   const struct tu_pipeline *pipeline,
2436                   struct tu_descriptor_state *descriptors_state,
2437                   gl_shader_stage type, bool *needs_border)
2438 {
2439    const struct tu_program_descriptor_linkage *link =
2440       &pipeline->program.link[type];
2441
2442    uint32_t size = link->texture_map.num * A6XX_TEX_CONST_DWORDS +
2443                    link->sampler_map.num * A6XX_TEX_SAMP_DWORDS;
2444    if (!size)
2445       return (struct tu_cs_entry) {};
2446
2447    unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
2448    enum a6xx_state_block sb;
2449
2450    switch (type) {
2451    case MESA_SHADER_VERTEX:
2452       sb = SB6_VS_TEX;
2453       opcode = CP_LOAD_STATE6_GEOM;
2454       tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2455       tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2456       tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2457       break;
2458    case MESA_SHADER_FRAGMENT:
2459       sb = SB6_FS_TEX;
2460       opcode = CP_LOAD_STATE6_FRAG;
2461       tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2462       tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2463       tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2464       break;
2465    case MESA_SHADER_COMPUTE:
2466       sb = SB6_CS_TEX;
2467       opcode = CP_LOAD_STATE6_FRAG;
2468       tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2469       tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2470       tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2471       break;
2472    default:
2473       unreachable("bad state block");
2474    }
2475
2476    struct tu_cs cs;
2477    tu_cs_begin_sub_stream(device, draw_state, size, &cs);
2478
2479    for (unsigned i = 0; i < link->texture_map.num; i++) {
2480       uint32_t *ptr = texture_ptr(descriptors_state, &link->texture_map, i);
2481
2482       for (unsigned j = 0; j < A6XX_TEX_CONST_DWORDS; j++)
2483          tu_cs_emit(&cs, ptr[j]);
2484    }
2485
2486    for (unsigned i = 0; i < link->sampler_map.num; i++) {
2487       struct tu_sampler *sampler = sampler_ptr(descriptors_state, &link->sampler_map, i);
2488
2489       for (unsigned j = 0; j < A6XX_TEX_SAMP_DWORDS; j++)
2490          tu_cs_emit(&cs, sampler->state[j]);
2491
2492       *needs_border |= sampler->needs_border;
2493    }
2494
2495    struct tu_cs_entry entry = tu_cs_end_sub_stream(draw_state, &cs);
2496
2497    uint64_t tex_addr = entry.bo->iova + entry.offset;
2498    uint64_t samp_addr = tex_addr + link->texture_map.num * A6XX_TEX_CONST_DWORDS*4;
2499
2500    tu_cs_begin_sub_stream(device, draw_state, 64, &cs);
2501
2502    /* output sampler state: */
2503    tu_cs_emit_pkt7(&cs, opcode, 3);
2504    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2505       CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2506       CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2507       CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2508       CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num));
2509    tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2510
2511    tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2512    tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2513
2514    /* emit texture state: */
2515    tu_cs_emit_pkt7(&cs, opcode, 3);
2516    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2517       CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2518       CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2519       CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2520       CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num));
2521    tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2522
2523    tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2524    tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2525
2526    tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2527    tu_cs_emit(&cs, link->texture_map.num);
2528
2529    return tu_cs_end_sub_stream(draw_state, &cs);
2530 }
2531
2532 static void
2533 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
2534                       struct tu_cs *cs)
2535 {
2536    const struct tu_pipeline *pipeline = cmd->state.pipeline;
2537
2538 #define A6XX_BORDER_COLOR_DWORDS (128/4)
2539    uint32_t size = A6XX_BORDER_COLOR_DWORDS *
2540       (pipeline->program.link[MESA_SHADER_VERTEX].sampler_map.num +
2541        pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map.num) +
2542       A6XX_BORDER_COLOR_DWORDS - 1; /* room for alignment */
2543
2544    struct tu_cs border_cs;
2545    tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, size, &border_cs);
2546
2547    /* TODO: actually fill with border color */
2548    for (unsigned i = 0; i < size; i++)
2549       tu_cs_emit(&border_cs, 0);
2550
2551    struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->draw_state, &border_cs);
2552
2553    tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
2554         tu_cs_emit_qw(cs, align(entry.bo->iova + entry.offset, 128));
2555 }
2556
2557 static void
2558 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2559                      struct tu_cs *cs,
2560                      const struct tu_draw_info *draw)
2561 {
2562    const struct tu_pipeline *pipeline = cmd->state.pipeline;
2563    const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
2564    struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
2565    uint32_t draw_state_group_count = 0;
2566
2567    struct tu_descriptor_state *descriptors_state =
2568       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2569
2570    VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
2571    if (result != VK_SUCCESS) {
2572       cmd->record_result = result;
2573       return;
2574    }
2575
2576    /* TODO lrz */
2577
2578    uint32_t pc_primitive_cntl = 0;
2579    if (pipeline->ia.primitive_restart && draw->indexed)
2580       pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
2581
2582    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
2583    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
2584    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
2585
2586    tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
2587    tu_cs_emit(cs, pc_primitive_cntl);
2588
2589    if (cmd->state.dirty &
2590           (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
2591        (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
2592       tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
2593                             dynamic->line_width);
2594    }
2595
2596    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
2597        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2598       tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
2599                                     dynamic->stencil_compare_mask.back);
2600    }
2601
2602    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
2603        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2604       tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2605                                   dynamic->stencil_write_mask.back);
2606    }
2607
2608    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
2609        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2610       tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
2611                                  dynamic->stencil_reference.back);
2612    }
2613
2614    if (cmd->state.dirty &
2615        (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
2616       for (uint32_t i = 0; i < pipeline->vi.count; i++) {
2617          const uint32_t binding = pipeline->vi.bindings[i];
2618          const uint32_t stride = pipeline->vi.strides[i];
2619          const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
2620          const VkDeviceSize offset = buf->bo_offset +
2621                                      cmd->state.vb.offsets[binding] +
2622                                      pipeline->vi.offsets[i];
2623          const VkDeviceSize size =
2624             offset < buf->bo->size ? buf->bo->size - offset : 0;
2625
2626          tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
2627          tu_cs_emit_qw(cs, buf->bo->iova + offset);
2628          tu_cs_emit(cs, size);
2629          tu_cs_emit(cs, stride);
2630       }
2631    }
2632
2633    if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2634       draw_state_groups[draw_state_group_count++] =
2635          (struct tu_draw_state_group) {
2636             .id = TU_DRAW_STATE_PROGRAM,
2637             .enable_mask = 0x6,
2638             .ib = pipeline->program.state_ib,
2639          };
2640       draw_state_groups[draw_state_group_count++] =
2641          (struct tu_draw_state_group) {
2642             .id = TU_DRAW_STATE_PROGRAM_BINNING,
2643             .enable_mask = 0x1,
2644             .ib = pipeline->program.binning_state_ib,
2645          };
2646       draw_state_groups[draw_state_group_count++] =
2647          (struct tu_draw_state_group) {
2648             .id = TU_DRAW_STATE_VI,
2649             .enable_mask = 0x6,
2650             .ib = pipeline->vi.state_ib,
2651          };
2652       draw_state_groups[draw_state_group_count++] =
2653          (struct tu_draw_state_group) {
2654             .id = TU_DRAW_STATE_VI_BINNING,
2655             .enable_mask = 0x1,
2656             .ib = pipeline->vi.binning_state_ib,
2657          };
2658       draw_state_groups[draw_state_group_count++] =
2659          (struct tu_draw_state_group) {
2660             .id = TU_DRAW_STATE_VP,
2661             .enable_mask = 0x7,
2662             .ib = pipeline->vp.state_ib,
2663          };
2664       draw_state_groups[draw_state_group_count++] =
2665          (struct tu_draw_state_group) {
2666             .id = TU_DRAW_STATE_RAST,
2667             .enable_mask = 0x7,
2668             .ib = pipeline->rast.state_ib,
2669          };
2670       draw_state_groups[draw_state_group_count++] =
2671          (struct tu_draw_state_group) {
2672             .id = TU_DRAW_STATE_DS,
2673             .enable_mask = 0x7,
2674             .ib = pipeline->ds.state_ib,
2675          };
2676       draw_state_groups[draw_state_group_count++] =
2677          (struct tu_draw_state_group) {
2678             .id = TU_DRAW_STATE_BLEND,
2679             .enable_mask = 0x7,
2680             .ib = pipeline->blend.state_ib,
2681          };
2682    }
2683
2684    if (cmd->state.dirty &
2685          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
2686       bool needs_border = false;
2687
2688       draw_state_groups[draw_state_group_count++] =
2689          (struct tu_draw_state_group) {
2690             .id = TU_DRAW_STATE_VS_CONST,
2691             .enable_mask = 0x7,
2692             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
2693          };
2694       draw_state_groups[draw_state_group_count++] =
2695          (struct tu_draw_state_group) {
2696             .id = TU_DRAW_STATE_FS_CONST,
2697             .enable_mask = 0x6,
2698             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
2699          };
2700       draw_state_groups[draw_state_group_count++] =
2701          (struct tu_draw_state_group) {
2702             .id = TU_DRAW_STATE_VS_TEX,
2703             .enable_mask = 0x7,
2704             .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2705                                     descriptors_state, MESA_SHADER_VERTEX,
2706                                     &needs_border)
2707          };
2708       draw_state_groups[draw_state_group_count++] =
2709          (struct tu_draw_state_group) {
2710             .id = TU_DRAW_STATE_FS_TEX,
2711             .enable_mask = 0x6,
2712             .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2713                                     descriptors_state, MESA_SHADER_FRAGMENT,
2714                                     &needs_border)
2715          };
2716
2717       if (needs_border)
2718          tu6_emit_border_color(cmd, cs);
2719    }
2720
2721    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
2722    for (uint32_t i = 0; i < draw_state_group_count; i++) {
2723       const struct tu_draw_state_group *group = &draw_state_groups[i];
2724
2725       uint32_t cp_set_draw_state =
2726          CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
2727          CP_SET_DRAW_STATE__0_ENABLE_MASK(group->enable_mask) |
2728          CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
2729       uint64_t iova;
2730       if (group->ib.size) {
2731          iova = group->ib.bo->iova + group->ib.offset;
2732       } else {
2733          cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
2734          iova = 0;
2735       }
2736
2737       tu_cs_emit(cs, cp_set_draw_state);
2738       tu_cs_emit_qw(cs, iova);
2739    }
2740
2741    tu_cs_sanity_check(cs);
2742
2743    /* track BOs */
2744    if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2745       tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2746                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2747       for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2748          tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2749                         MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2750       }
2751    }
2752    if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
2753       for (uint32_t i = 0; i < MAX_VBS; i++) {
2754          const struct tu_buffer *buf = cmd->state.vb.buffers[i];
2755          if (buf)
2756             tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2757       }
2758    }
2759    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
2760       unsigned i;
2761       for_each_bit(i, descriptors_state->valid) {
2762          struct tu_descriptor_set *set = descriptors_state->sets[i];
2763          for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2764             if (set->descriptors[j]) {
2765                tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
2766                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2767             }
2768       }
2769    }
2770    cmd->state.dirty = 0;
2771 }
2772
2773 static void
2774 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
2775                      struct tu_cs *cs,
2776                      const struct tu_draw_info *draw)
2777 {
2778
2779    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
2780
2781    tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
2782    tu_cs_emit(cs, draw->vertex_offset);
2783    tu_cs_emit(cs, draw->first_instance);
2784
2785    /* TODO hw binning */
2786    if (draw->indexed) {
2787       const enum a4xx_index_size index_size =
2788          tu6_index_size(cmd->state.index_type);
2789       const uint32_t index_bytes =
2790          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
2791       const struct tu_buffer *buf = cmd->state.index_buffer;
2792       const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
2793                                   index_bytes * draw->first_index;
2794       const uint32_t size = index_bytes * draw->count;
2795
2796       const uint32_t cp_draw_indx =
2797          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2798          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
2799          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
2800          CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2801
2802       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
2803       tu_cs_emit(cs, cp_draw_indx);
2804       tu_cs_emit(cs, draw->instance_count);
2805       tu_cs_emit(cs, draw->count);
2806       tu_cs_emit(cs, 0x0); /* XXX */
2807       tu_cs_emit_qw(cs, buf->bo->iova + offset);
2808       tu_cs_emit(cs, size);
2809    } else {
2810       const uint32_t cp_draw_indx =
2811          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2812          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
2813          CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2814
2815       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
2816       tu_cs_emit(cs, cp_draw_indx);
2817       tu_cs_emit(cs, draw->instance_count);
2818       tu_cs_emit(cs, draw->count);
2819    }
2820 }
2821
2822 static void
2823 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
2824 {
2825    struct tu_cs *cs = &cmd->draw_cs;
2826
2827    tu6_bind_draw_states(cmd, cs, draw);
2828
2829    VkResult result = tu_cs_reserve_space(cmd->device, cs, 32);
2830    if (result != VK_SUCCESS) {
2831       cmd->record_result = result;
2832       return;
2833    }
2834
2835    if (draw->indirect) {
2836       tu_finishme("indirect draw");
2837       return;
2838    }
2839
2840    /* TODO tu6_emit_marker should pick different regs depending on cs */
2841    tu6_emit_marker(cmd, cs);
2842    tu6_emit_draw_direct(cmd, cs, draw);
2843    tu6_emit_marker(cmd, cs);
2844
2845    cmd->wait_for_idle = true;
2846
2847    tu_cs_sanity_check(cs);
2848 }
2849
2850 void
2851 tu_CmdDraw(VkCommandBuffer commandBuffer,
2852            uint32_t vertexCount,
2853            uint32_t instanceCount,
2854            uint32_t firstVertex,
2855            uint32_t firstInstance)
2856 {
2857    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2858    struct tu_draw_info info = {};
2859
2860    info.count = vertexCount;
2861    info.instance_count = instanceCount;
2862    info.first_instance = firstInstance;
2863    info.vertex_offset = firstVertex;
2864
2865    tu_draw(cmd_buffer, &info);
2866 }
2867
2868 void
2869 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
2870                   uint32_t indexCount,
2871                   uint32_t instanceCount,
2872                   uint32_t firstIndex,
2873                   int32_t vertexOffset,
2874                   uint32_t firstInstance)
2875 {
2876    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2877    struct tu_draw_info info = {};
2878
2879    info.indexed = true;
2880    info.count = indexCount;
2881    info.instance_count = instanceCount;
2882    info.first_index = firstIndex;
2883    info.vertex_offset = vertexOffset;
2884    info.first_instance = firstInstance;
2885
2886    tu_draw(cmd_buffer, &info);
2887 }
2888
2889 void
2890 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
2891                    VkBuffer _buffer,
2892                    VkDeviceSize offset,
2893                    uint32_t drawCount,
2894                    uint32_t stride)
2895 {
2896    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2897    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2898    struct tu_draw_info info = {};
2899
2900    info.count = drawCount;
2901    info.indirect = buffer;
2902    info.indirect_offset = offset;
2903    info.stride = stride;
2904
2905    tu_draw(cmd_buffer, &info);
2906 }
2907
2908 void
2909 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
2910                           VkBuffer _buffer,
2911                           VkDeviceSize offset,
2912                           uint32_t drawCount,
2913                           uint32_t stride)
2914 {
2915    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2916    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2917    struct tu_draw_info info = {};
2918
2919    info.indexed = true;
2920    info.count = drawCount;
2921    info.indirect = buffer;
2922    info.indirect_offset = offset;
2923    info.stride = stride;
2924
2925    tu_draw(cmd_buffer, &info);
2926 }
2927
2928 struct tu_dispatch_info
2929 {
2930    /**
2931     * Determine the layout of the grid (in block units) to be used.
2932     */
2933    uint32_t blocks[3];
2934
2935    /**
2936     * A starting offset for the grid. If unaligned is set, the offset
2937     * must still be aligned.
2938     */
2939    uint32_t offsets[3];
2940    /**
2941     * Whether it's an unaligned compute dispatch.
2942     */
2943    bool unaligned;
2944
2945    /**
2946     * Indirect compute parameters resource.
2947     */
2948    struct tu_buffer *indirect;
2949    uint64_t indirect_offset;
2950 };
2951
2952 static void
2953 tu_dispatch(struct tu_cmd_buffer *cmd_buffer,
2954             const struct tu_dispatch_info *info)
2955 {
2956 }
2957
2958 void
2959 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
2960                    uint32_t base_x,
2961                    uint32_t base_y,
2962                    uint32_t base_z,
2963                    uint32_t x,
2964                    uint32_t y,
2965                    uint32_t z)
2966 {
2967    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2968    struct tu_dispatch_info info = {};
2969
2970    info.blocks[0] = x;
2971    info.blocks[1] = y;
2972    info.blocks[2] = z;
2973
2974    info.offsets[0] = base_x;
2975    info.offsets[1] = base_y;
2976    info.offsets[2] = base_z;
2977    tu_dispatch(cmd_buffer, &info);
2978 }
2979
2980 void
2981 tu_CmdDispatch(VkCommandBuffer commandBuffer,
2982                uint32_t x,
2983                uint32_t y,
2984                uint32_t z)
2985 {
2986    tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
2987 }
2988
2989 void
2990 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
2991                        VkBuffer _buffer,
2992                        VkDeviceSize offset)
2993 {
2994    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2995    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2996    struct tu_dispatch_info info = {};
2997
2998    info.indirect = buffer;
2999    info.indirect_offset = offset;
3000
3001    tu_dispatch(cmd_buffer, &info);
3002 }
3003
3004 void
3005 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3006 {
3007    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3008
3009    tu_cs_end(&cmd_buffer->draw_cs);
3010
3011    tu_cmd_render_tiles(cmd_buffer);
3012
3013    /* discard draw_cs entries now that the tiles are rendered */
3014    tu_cs_discard_entries(&cmd_buffer->draw_cs);
3015
3016    vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3017    cmd_buffer->state.attachments = NULL;
3018
3019    cmd_buffer->state.pass = NULL;
3020    cmd_buffer->state.subpass = NULL;
3021    cmd_buffer->state.framebuffer = NULL;
3022 }
3023
3024 void
3025 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer,
3026                         const VkSubpassEndInfoKHR *pSubpassEndInfo)
3027 {
3028    tu_CmdEndRenderPass(commandBuffer);
3029 }
3030
3031 struct tu_barrier_info
3032 {
3033    uint32_t eventCount;
3034    const VkEvent *pEvents;
3035    VkPipelineStageFlags srcStageMask;
3036 };
3037
3038 static void
3039 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
3040            uint32_t memoryBarrierCount,
3041            const VkMemoryBarrier *pMemoryBarriers,
3042            uint32_t bufferMemoryBarrierCount,
3043            const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3044            uint32_t imageMemoryBarrierCount,
3045            const VkImageMemoryBarrier *pImageMemoryBarriers,
3046            const struct tu_barrier_info *info)
3047 {
3048 }
3049
3050 void
3051 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3052                       VkPipelineStageFlags srcStageMask,
3053                       VkPipelineStageFlags destStageMask,
3054                       VkBool32 byRegion,
3055                       uint32_t memoryBarrierCount,
3056                       const VkMemoryBarrier *pMemoryBarriers,
3057                       uint32_t bufferMemoryBarrierCount,
3058                       const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3059                       uint32_t imageMemoryBarrierCount,
3060                       const VkImageMemoryBarrier *pImageMemoryBarriers)
3061 {
3062    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3063    struct tu_barrier_info info;
3064
3065    info.eventCount = 0;
3066    info.pEvents = NULL;
3067    info.srcStageMask = srcStageMask;
3068
3069    tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3070               bufferMemoryBarrierCount, pBufferMemoryBarriers,
3071               imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3072 }
3073
3074 static void
3075 write_event(struct tu_cmd_buffer *cmd_buffer,
3076             struct tu_event *event,
3077             VkPipelineStageFlags stageMask,
3078             unsigned value)
3079 {
3080 }
3081
3082 void
3083 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3084                VkEvent _event,
3085                VkPipelineStageFlags stageMask)
3086 {
3087    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3088    TU_FROM_HANDLE(tu_event, event, _event);
3089
3090    write_event(cmd_buffer, event, stageMask, 1);
3091 }
3092
3093 void
3094 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3095                  VkEvent _event,
3096                  VkPipelineStageFlags stageMask)
3097 {
3098    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3099    TU_FROM_HANDLE(tu_event, event, _event);
3100
3101    write_event(cmd_buffer, event, stageMask, 0);
3102 }
3103
3104 void
3105 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3106                  uint32_t eventCount,
3107                  const VkEvent *pEvents,
3108                  VkPipelineStageFlags srcStageMask,
3109                  VkPipelineStageFlags dstStageMask,
3110                  uint32_t memoryBarrierCount,
3111                  const VkMemoryBarrier *pMemoryBarriers,
3112                  uint32_t bufferMemoryBarrierCount,
3113                  const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3114                  uint32_t imageMemoryBarrierCount,
3115                  const VkImageMemoryBarrier *pImageMemoryBarriers)
3116 {
3117    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3118    struct tu_barrier_info info;
3119
3120    info.eventCount = eventCount;
3121    info.pEvents = pEvents;
3122    info.srcStageMask = 0;
3123
3124    tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3125               bufferMemoryBarrierCount, pBufferMemoryBarriers,
3126               imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3127 }
3128
3129 void
3130 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3131 {
3132    /* No-op */
3133 }