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turnip: remove compute emit_border_color
[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
33
34 #include "vk_format.h"
35
36 #include "tu_cs.h"
37 #include "tu_blit.h"
38
39 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
40
41 void
42 tu_bo_list_init(struct tu_bo_list *list)
43 {
44 list->count = list->capacity = 0;
45 list->bo_infos = NULL;
46 }
47
48 void
49 tu_bo_list_destroy(struct tu_bo_list *list)
50 {
51 free(list->bo_infos);
52 }
53
54 void
55 tu_bo_list_reset(struct tu_bo_list *list)
56 {
57 list->count = 0;
58 }
59
60 /**
61 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
62 */
63 static uint32_t
64 tu_bo_list_add_info(struct tu_bo_list *list,
65 const struct drm_msm_gem_submit_bo *bo_info)
66 {
67 assert(bo_info->handle != 0);
68
69 for (uint32_t i = 0; i < list->count; ++i) {
70 if (list->bo_infos[i].handle == bo_info->handle) {
71 assert(list->bo_infos[i].presumed == bo_info->presumed);
72 list->bo_infos[i].flags |= bo_info->flags;
73 return i;
74 }
75 }
76
77 /* grow list->bo_infos if needed */
78 if (list->count == list->capacity) {
79 uint32_t new_capacity = MAX2(2 * list->count, 16);
80 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
81 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
82 if (!new_bo_infos)
83 return TU_BO_LIST_FAILED;
84 list->bo_infos = new_bo_infos;
85 list->capacity = new_capacity;
86 }
87
88 list->bo_infos[list->count] = *bo_info;
89 return list->count++;
90 }
91
92 uint32_t
93 tu_bo_list_add(struct tu_bo_list *list,
94 const struct tu_bo *bo,
95 uint32_t flags)
96 {
97 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
98 .flags = flags,
99 .handle = bo->gem_handle,
100 .presumed = bo->iova,
101 });
102 }
103
104 VkResult
105 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
106 {
107 for (uint32_t i = 0; i < other->count; i++) {
108 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
109 return VK_ERROR_OUT_OF_HOST_MEMORY;
110 }
111
112 return VK_SUCCESS;
113 }
114
115 static VkResult
116 tu_tiling_config_update_gmem_layout(struct tu_tiling_config *tiling,
117 const struct tu_device *dev)
118 {
119 const uint32_t gmem_size = dev->physical_device->gmem_size;
120 uint32_t offset = 0;
121
122 for (uint32_t i = 0; i < tiling->buffer_count; i++) {
123 /* 16KB-aligned */
124 offset = align(offset, 0x4000);
125
126 tiling->gmem_offsets[i] = offset;
127 offset += tiling->tile0.extent.width * tiling->tile0.extent.height *
128 tiling->buffer_cpp[i];
129 }
130
131 return offset <= gmem_size ? VK_SUCCESS : VK_ERROR_OUT_OF_DEVICE_MEMORY;
132 }
133
134 static void
135 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
136 const struct tu_device *dev)
137 {
138 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
139 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
140 const uint32_t max_tile_width = 1024; /* A6xx */
141
142 tiling->tile0.offset = (VkOffset2D) {
143 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
144 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
145 };
146
147 const uint32_t ra_width =
148 tiling->render_area.extent.width +
149 (tiling->render_area.offset.x - tiling->tile0.offset.x);
150 const uint32_t ra_height =
151 tiling->render_area.extent.height +
152 (tiling->render_area.offset.y - tiling->tile0.offset.y);
153
154 /* start from 1 tile */
155 tiling->tile_count = (VkExtent2D) {
156 .width = 1,
157 .height = 1,
158 };
159 tiling->tile0.extent = (VkExtent2D) {
160 .width = align(ra_width, tile_align_w),
161 .height = align(ra_height, tile_align_h),
162 };
163
164 /* do not exceed max tile width */
165 while (tiling->tile0.extent.width > max_tile_width) {
166 tiling->tile_count.width++;
167 tiling->tile0.extent.width =
168 align(ra_width / tiling->tile_count.width, tile_align_w);
169 }
170
171 /* do not exceed gmem size */
172 while (tu_tiling_config_update_gmem_layout(tiling, dev) != VK_SUCCESS) {
173 if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
174 tiling->tile_count.width++;
175 tiling->tile0.extent.width =
176 align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
177 } else {
178 /* if this assert fails then layout is impossible.. */
179 assert(tiling->tile0.extent.height > tile_align_h);
180 tiling->tile_count.height++;
181 tiling->tile0.extent.height =
182 align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
183 }
184 }
185 }
186
187 static void
188 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
189 const struct tu_device *dev)
190 {
191 const uint32_t max_pipe_count = 32; /* A6xx */
192
193 /* start from 1 tile per pipe */
194 tiling->pipe0 = (VkExtent2D) {
195 .width = 1,
196 .height = 1,
197 };
198 tiling->pipe_count = tiling->tile_count;
199
200 /* do not exceed max pipe count vertically */
201 while (tiling->pipe_count.height > max_pipe_count) {
202 tiling->pipe0.height += 2;
203 tiling->pipe_count.height =
204 (tiling->tile_count.height + tiling->pipe0.height - 1) /
205 tiling->pipe0.height;
206 }
207
208 /* do not exceed max pipe count */
209 while (tiling->pipe_count.width * tiling->pipe_count.height >
210 max_pipe_count) {
211 tiling->pipe0.width += 1;
212 tiling->pipe_count.width =
213 (tiling->tile_count.width + tiling->pipe0.width - 1) /
214 tiling->pipe0.width;
215 }
216 }
217
218 static void
219 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
220 const struct tu_device *dev)
221 {
222 const uint32_t max_pipe_count = 32; /* A6xx */
223 const uint32_t used_pipe_count =
224 tiling->pipe_count.width * tiling->pipe_count.height;
225 const VkExtent2D last_pipe = {
226 .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
227 .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
228 };
229
230 assert(used_pipe_count <= max_pipe_count);
231 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
232
233 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
234 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
235 const uint32_t pipe_x = tiling->pipe0.width * x;
236 const uint32_t pipe_y = tiling->pipe0.height * y;
237 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
238 ? last_pipe.width
239 : tiling->pipe0.width;
240 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
241 ? last_pipe.height
242 : tiling->pipe0.height;
243 const uint32_t n = tiling->pipe_count.width * y + x;
244
245 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
246 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
247 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
248 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
249 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
250 }
251 }
252
253 memset(tiling->pipe_config + used_pipe_count, 0,
254 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
255 }
256
257 static void
258 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
259 const struct tu_device *dev,
260 uint32_t tx,
261 uint32_t ty,
262 struct tu_tile *tile)
263 {
264 /* find the pipe and the slot for tile (tx, ty) */
265 const uint32_t px = tx / tiling->pipe0.width;
266 const uint32_t py = ty / tiling->pipe0.height;
267 const uint32_t sx = tx - tiling->pipe0.width * px;
268 const uint32_t sy = ty - tiling->pipe0.height * py;
269
270 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
271 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
272 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
273
274 /* convert to 1D indices */
275 tile->pipe = tiling->pipe_count.width * py + px;
276 tile->slot = tiling->pipe0.width * sy + sx;
277
278 /* get the blit area for the tile */
279 tile->begin = (VkOffset2D) {
280 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
281 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
282 };
283 tile->end.x =
284 (tx == tiling->tile_count.width - 1)
285 ? tiling->render_area.offset.x + tiling->render_area.extent.width
286 : tile->begin.x + tiling->tile0.extent.width;
287 tile->end.y =
288 (ty == tiling->tile_count.height - 1)
289 ? tiling->render_area.offset.y + tiling->render_area.extent.height
290 : tile->begin.y + tiling->tile0.extent.height;
291 }
292
293 enum a3xx_msaa_samples
294 tu_msaa_samples(uint32_t samples)
295 {
296 switch (samples) {
297 case 1:
298 return MSAA_ONE;
299 case 2:
300 return MSAA_TWO;
301 case 4:
302 return MSAA_FOUR;
303 case 8:
304 return MSAA_EIGHT;
305 default:
306 assert(!"invalid sample count");
307 return MSAA_ONE;
308 }
309 }
310
311 static enum a4xx_index_size
312 tu6_index_size(VkIndexType type)
313 {
314 switch (type) {
315 case VK_INDEX_TYPE_UINT16:
316 return INDEX4_SIZE_16_BIT;
317 case VK_INDEX_TYPE_UINT32:
318 return INDEX4_SIZE_32_BIT;
319 default:
320 unreachable("invalid VkIndexType");
321 return INDEX4_SIZE_8_BIT;
322 }
323 }
324
325 static void
326 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
327 {
328 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
329 }
330
331 unsigned
332 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
333 struct tu_cs *cs,
334 enum vgt_event_type event,
335 bool need_seqno)
336 {
337 unsigned seqno = 0;
338
339 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
340 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
341 if (need_seqno) {
342 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
343 seqno = ++cmd->scratch_seqno;
344 tu_cs_emit(cs, seqno);
345 }
346
347 return seqno;
348 }
349
350 static void
351 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
352 {
353 tu6_emit_event_write(cmd, cs, 0x31, false);
354 }
355
356 static void
357 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
358 {
359 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
360 }
361
362 static void
363 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
364 {
365 if (cmd->wait_for_idle) {
366 tu_cs_emit_wfi(cs);
367 cmd->wait_for_idle = false;
368 }
369 }
370
371 static void
372 tu6_emit_flag_buffer(struct tu_cs *cs, const struct tu_image_view *iview)
373 {
374 uint64_t va = tu_image_ubwc_base(iview->image, iview->base_mip, iview->base_layer);
375 uint32_t pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip);
376 uint32_t size = tu_image_ubwc_size(iview->image, iview->base_mip);
377 if (iview->image->layout.ubwc_size) {
378 tu_cs_emit_qw(cs, va);
379 tu_cs_emit(cs, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(pitch) |
380 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(size >> 2));
381 } else {
382 tu_cs_emit_qw(cs, 0);
383 tu_cs_emit(cs, 0);
384 }
385 }
386
387 static void
388 tu6_emit_zs(struct tu_cmd_buffer *cmd,
389 const struct tu_subpass *subpass,
390 struct tu_cs *cs)
391 {
392 const struct tu_framebuffer *fb = cmd->state.framebuffer;
393 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
394
395 const uint32_t a = subpass->depth_stencil_attachment.attachment;
396 if (a == VK_ATTACHMENT_UNUSED) {
397 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
398 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
399 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
400 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
401 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
402 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
403 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
404
405 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
406 tu_cs_emit(cs,
407 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
408
409 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
410 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
411 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
412 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
413 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
414 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
415
416 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
417 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
418
419 return;
420 }
421
422 const struct tu_image_view *iview = fb->attachments[a].attachment;
423 enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
424
425 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
426 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
427 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)));
428 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layout.layer_size));
429 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
430 tu_cs_emit(cs, tiling->gmem_offsets[a]);
431
432 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
433 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
434
435 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
436 tu6_emit_flag_buffer(cs, iview);
437
438 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
439 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
440 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
441 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
442 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
443 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
444
445 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
446 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
447
448 /* enable zs? */
449 }
450
451 static void
452 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
453 const struct tu_subpass *subpass,
454 struct tu_cs *cs)
455 {
456 const struct tu_framebuffer *fb = cmd->state.framebuffer;
457 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
458 unsigned char mrt_comp[MAX_RTS] = { 0 };
459 unsigned srgb_cntl = 0;
460
461 for (uint32_t i = 0; i < subpass->color_count; ++i) {
462 uint32_t a = subpass->color_attachments[i].attachment;
463 if (a == VK_ATTACHMENT_UNUSED)
464 continue;
465
466 const struct tu_image_view *iview = fb->attachments[a].attachment;
467 const enum a6xx_tile_mode tile_mode =
468 tu6_get_image_tile_mode(iview->image, iview->base_mip);
469
470 mrt_comp[i] = 0xf;
471
472 if (vk_format_is_srgb(iview->vk_format))
473 srgb_cntl |= (1 << i);
474
475 const struct tu_native_format *format =
476 tu6_get_native_format(iview->vk_format);
477 assert(format && format->rb >= 0);
478
479 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
480 tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
481 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
482 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
483 tu_cs_emit(cs, A6XX_RB_MRT_PITCH(tu_image_stride(iview->image, iview->base_mip)));
484 tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(iview->image->layout.layer_size));
485 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
486 tu_cs_emit(
487 cs, tiling->gmem_offsets[a]); /* RB_MRT[i].BASE_GMEM */
488
489 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
490 tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb) |
491 COND(vk_format_is_sint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_SINT) |
492 COND(vk_format_is_uint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_UINT));
493
494 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
495 tu6_emit_flag_buffer(cs, iview);
496 }
497
498 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
499 tu_cs_emit(cs, srgb_cntl);
500
501 tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
502 tu_cs_emit(cs, srgb_cntl);
503
504 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
505 tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
506 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
507 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
508 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
509 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
510 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
511 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
512 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
513
514 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
515 tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
516 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
517 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
518 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
519 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
520 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
521 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
522 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
523 }
524
525 static void
526 tu6_emit_msaa(struct tu_cmd_buffer *cmd,
527 const struct tu_subpass *subpass,
528 struct tu_cs *cs)
529 {
530 const enum a3xx_msaa_samples samples = tu_msaa_samples(subpass->samples);
531
532 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
533 tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
534 tu_cs_emit(cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
535 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
536
537 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
538 tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
539 tu_cs_emit(cs, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
540 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
541
542 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
543 tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
544 tu_cs_emit(cs, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
545 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
546
547 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
548 tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
549 }
550
551 static void
552 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
553 {
554 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
555 const uint32_t bin_w = tiling->tile0.extent.width;
556 const uint32_t bin_h = tiling->tile0.extent.height;
557
558 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
559 tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
560 A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
561
562 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
563 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
564 A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
565
566 /* no flag for RB_BIN_CONTROL2... */
567 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
568 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
569 A6XX_RB_BIN_CONTROL2_BINH(bin_h));
570 }
571
572 static void
573 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
574 struct tu_cs *cs,
575 bool binning)
576 {
577 uint32_t cntl = 0;
578 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
579 if (binning)
580 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
581
582 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
583 tu_cs_emit(cs, 0x2);
584 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
585 tu_cs_emit(cs, cntl);
586 }
587
588 static void
589 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
590 {
591 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
592 uint32_t x1 = render_area->offset.x;
593 uint32_t y1 = render_area->offset.y;
594 uint32_t x2 = x1 + render_area->extent.width - 1;
595 uint32_t y2 = y1 + render_area->extent.height - 1;
596
597 /* TODO: alignment requirement seems to be less than tile_align_w/h */
598 if (align) {
599 x1 = x1 & ~cmd->device->physical_device->tile_align_w;
600 y1 = y1 & ~cmd->device->physical_device->tile_align_h;
601 x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
602 y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
603 }
604
605 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
606 tu_cs_emit(cs,
607 A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
608 tu_cs_emit(cs,
609 A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
610 }
611
612 static void
613 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
614 struct tu_cs *cs,
615 const struct tu_image_view *iview,
616 uint32_t gmem_offset,
617 bool resolve)
618 {
619 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
620 tu_cs_emit(cs, resolve ? 0 : (A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM));
621
622 const struct tu_native_format *format =
623 tu6_get_native_format(iview->vk_format);
624 assert(format && format->rb >= 0);
625
626 enum a6xx_tile_mode tile_mode =
627 tu6_get_image_tile_mode(iview->image, iview->base_mip);
628 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
629 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
630 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
631 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
632 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap) |
633 COND(iview->image->layout.ubwc_size,
634 A6XX_RB_BLIT_DST_INFO_FLAGS));
635 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
636 tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)));
637 tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layout.layer_size));
638
639 if (iview->image->layout.ubwc_size) {
640 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
641 tu6_emit_flag_buffer(cs, iview);
642 }
643
644 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
645 tu_cs_emit(cs, gmem_offset);
646 }
647
648 static void
649 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
650 {
651 tu6_emit_marker(cmd, cs);
652 tu6_emit_event_write(cmd, cs, BLIT, false);
653 tu6_emit_marker(cmd, cs);
654 }
655
656 static void
657 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
658 struct tu_cs *cs,
659 uint32_t x1,
660 uint32_t y1,
661 uint32_t x2,
662 uint32_t y2)
663 {
664 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
665 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
666 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
667 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
668 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
669
670 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
671 tu_cs_emit(
672 cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
673 tu_cs_emit(
674 cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
675 }
676
677 static void
678 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
679 struct tu_cs *cs,
680 uint32_t x1,
681 uint32_t y1)
682 {
683 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
684 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
685
686 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
687 tu_cs_emit(cs,
688 A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
689
690 tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
691 tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
692
693 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
694 tu_cs_emit(
695 cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
696 }
697
698 static bool
699 use_hw_binning(struct tu_cmd_buffer *cmd)
700 {
701 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
702
703 if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
704 return false;
705
706 return (tiling->tile_count.width * tiling->tile_count.height) > 2;
707 }
708
709 static void
710 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
711 struct tu_cs *cs,
712 const struct tu_tile *tile)
713 {
714 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
715 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
716
717 tu6_emit_marker(cmd, cs);
718 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
719 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
720 tu6_emit_marker(cmd, cs);
721
722 const uint32_t x1 = tile->begin.x;
723 const uint32_t y1 = tile->begin.y;
724 const uint32_t x2 = tile->end.x - 1;
725 const uint32_t y2 = tile->end.y - 1;
726 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
727 tu6_emit_window_offset(cmd, cs, x1, y1);
728
729 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
730 tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
731
732 if (use_hw_binning(cmd)) {
733 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
734
735 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
736 tu_cs_emit(cs, 0x0);
737
738 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
739 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
740 A6XX_CP_REG_TEST_0_BIT(0) |
741 A6XX_CP_REG_TEST_0_UNK25);
742
743 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
744 tu_cs_emit(cs, 0x10000000);
745 tu_cs_emit(cs, 11); /* conditionally execute next 11 dwords */
746
747 /* if (no overflow) */ {
748 tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
749 tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
750 CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
751 tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
752 tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
753 tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
754
755 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
756 tu_cs_emit(cs, 0x0);
757
758 /* use a NOP packet to skip over the 'else' side: */
759 tu_cs_emit_pkt7(cs, CP_NOP, 2);
760 } /* else */ {
761 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
762 tu_cs_emit(cs, 0x1);
763 }
764
765 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
766 tu_cs_emit(cs, 0x0);
767
768 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_8804, 1);
769 tu_cs_emit(cs, 0x0);
770
771 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 1);
772 tu_cs_emit(cs, 0x0);
773
774 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 1);
775 tu_cs_emit(cs, 0x0);
776 } else {
777 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
778 tu_cs_emit(cs, 0x1);
779
780 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
781 tu_cs_emit(cs, 0x0);
782 }
783 }
784
785 static void
786 tu6_emit_load_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a)
787 {
788 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
789 const struct tu_framebuffer *fb = cmd->state.framebuffer;
790 const struct tu_image_view *iview = fb->attachments[a].attachment;
791 const struct tu_render_pass_attachment *attachment =
792 &cmd->state.pass->attachments[a];
793
794 if (!attachment->needs_gmem)
795 return;
796
797 const uint32_t x1 = tiling->render_area.offset.x;
798 const uint32_t y1 = tiling->render_area.offset.y;
799 const uint32_t x2 = x1 + tiling->render_area.extent.width;
800 const uint32_t y2 = y1 + tiling->render_area.extent.height;
801 const uint32_t tile_x2 =
802 tiling->tile0.offset.x + tiling->tile0.extent.width * tiling->tile_count.width;
803 const uint32_t tile_y2 =
804 tiling->tile0.offset.y + tiling->tile0.extent.height * tiling->tile_count.height;
805 bool need_load =
806 x1 != tiling->tile0.offset.x || x2 != MIN2(fb->width, tile_x2) ||
807 y1 != tiling->tile0.offset.y || y2 != MIN2(fb->height, tile_y2);
808
809 if (need_load)
810 tu_finishme("improve handling of unaligned render area");
811
812 if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
813 need_load = true;
814
815 if (vk_format_has_stencil(iview->vk_format) &&
816 attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
817 need_load = true;
818
819 if (need_load) {
820 tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[a], false);
821 tu6_emit_blit(cmd, cs);
822 }
823 }
824
825 static void
826 tu6_emit_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
827 uint32_t a,
828 const VkRenderPassBeginInfo *info)
829 {
830 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
831 const struct tu_framebuffer *fb = cmd->state.framebuffer;
832 const struct tu_image_view *iview = fb->attachments[a].attachment;
833 const struct tu_render_pass_attachment *attachment =
834 &cmd->state.pass->attachments[a];
835 unsigned clear_mask = 0;
836
837 /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
838 if (!attachment->needs_gmem)
839 return;
840
841 if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
842 clear_mask = 0xf;
843
844 if (vk_format_has_stencil(iview->vk_format)) {
845 clear_mask &= 0x1;
846 if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
847 clear_mask |= 0x2;
848 }
849 if (!clear_mask)
850 return;
851
852 const struct tu_native_format *format =
853 tu6_get_native_format(iview->vk_format);
854 assert(format && format->rb >= 0);
855
856 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
857 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb));
858
859 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
860 tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(clear_mask));
861
862 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
863 tu_cs_emit(cs, tiling->gmem_offsets[a]);
864
865 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
866 tu_cs_emit(cs, 0);
867
868 uint32_t clear_vals[4] = { 0 };
869 tu_pack_clear_value(&info->pClearValues[a], iview->vk_format, clear_vals);
870
871 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
872 tu_cs_emit(cs, clear_vals[0]);
873 tu_cs_emit(cs, clear_vals[1]);
874 tu_cs_emit(cs, clear_vals[2]);
875 tu_cs_emit(cs, clear_vals[3]);
876
877 tu6_emit_blit(cmd, cs);
878 }
879
880 static void
881 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
882 struct tu_cs *cs,
883 uint32_t a,
884 uint32_t gmem_a)
885 {
886 if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
887 return;
888
889 tu6_emit_blit_info(cmd, cs,
890 cmd->state.framebuffer->attachments[a].attachment,
891 cmd->state.tiling_config.gmem_offsets[gmem_a], true);
892 tu6_emit_blit(cmd, cs);
893 }
894
895 static void
896 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
897 {
898 const struct tu_render_pass *pass = cmd->state.pass;
899 const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
900
901 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
902 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
903 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
904 CP_SET_DRAW_STATE__0_GROUP_ID(0));
905 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
906 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
907
908 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
909 tu_cs_emit(cs, 0x0);
910
911 tu6_emit_marker(cmd, cs);
912 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
913 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
914 tu6_emit_marker(cmd, cs);
915
916 tu6_emit_blit_scissor(cmd, cs, true);
917
918 for (uint32_t a = 0; a < pass->attachment_count; ++a) {
919 if (pass->attachments[a].needs_gmem)
920 tu6_emit_store_attachment(cmd, cs, a, a);
921 }
922
923 if (subpass->resolve_attachments) {
924 for (unsigned i = 0; i < subpass->color_count; i++) {
925 uint32_t a = subpass->resolve_attachments[i].attachment;
926 if (a != VK_ATTACHMENT_UNUSED)
927 tu6_emit_store_attachment(cmd, cs, a,
928 subpass->color_attachments[i].attachment);
929 }
930 }
931 }
932
933 static void
934 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
935 {
936 tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
937 tu_cs_emit(cs, restart_index);
938 }
939
940 static void
941 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
942 {
943 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
944 if (result != VK_SUCCESS) {
945 cmd->record_result = result;
946 return;
947 }
948
949 tu6_emit_cache_flush(cmd, cs);
950
951 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
952
953 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
954 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
955 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
956 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
957 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
958 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
959 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
960 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
961 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
962
963 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
964 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
965 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
966 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
967 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
968 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
969 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
970 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
971 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
972 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
973 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
974 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
975 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
976 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
977
978 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
979
980 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
981 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
982 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
983
984 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
985 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
986 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
987 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
988 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
989 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
990 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
991 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
992 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
993 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
994 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
995 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
996
997 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
998 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
999
1000 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
1001 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
1002
1003 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
1004 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1005
1006 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
1007 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
1008 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
1009
1010 tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
1011 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
1012
1013 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
1014
1015 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
1016
1017 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
1018 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
1019 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1020 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1021 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
1022 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
1023 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
1024 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
1025 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
1026 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1027 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1028 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1029 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
1030 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1031 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1032 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1033 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
1034 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
1035 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
1036 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
1037 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1038
1039 tu6_emit_marker(cmd, cs);
1040
1041 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
1042
1043 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
1044
1045 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
1046
1047 /* we don't use this yet.. probably best to disable.. */
1048 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1049 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1050 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1051 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1052 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1053 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1054
1055 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1056 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1057 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1058 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1059
1060 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1061 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1062 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1063
1064 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1065 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
1066
1067 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1068 tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
1069
1070 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1071 tu_cs_emit(cs, 0x00000000);
1072 tu_cs_emit(cs, 0x00000000);
1073 tu_cs_emit(cs, 0x00000000);
1074
1075 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1076 tu_cs_emit(cs, 0x00000000);
1077 tu_cs_emit(cs, 0x00000000);
1078 tu_cs_emit(cs, 0x00000000);
1079 tu_cs_emit(cs, 0x00000000);
1080 tu_cs_emit(cs, 0x00000000);
1081 tu_cs_emit(cs, 0x00000000);
1082
1083 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1084 tu_cs_emit(cs, 0x00000000);
1085 tu_cs_emit(cs, 0x00000000);
1086 tu_cs_emit(cs, 0x00000000);
1087 tu_cs_emit(cs, 0x00000000);
1088 tu_cs_emit(cs, 0x00000000);
1089 tu_cs_emit(cs, 0x00000000);
1090
1091 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1092 tu_cs_emit(cs, 0x00000000);
1093 tu_cs_emit(cs, 0x00000000);
1094 tu_cs_emit(cs, 0x00000000);
1095
1096 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
1097 tu_cs_emit(cs, 0x00000000);
1098
1099 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1100 tu_cs_emit(cs, 0x00000000);
1101
1102 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1103 tu_cs_emit(cs, 0x00000000);
1104
1105 tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1106 tu_cs_emit(cs, 0x00000000);
1107
1108 tu_cs_sanity_check(cs);
1109 }
1110
1111 static void
1112 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1113 {
1114 unsigned seqno;
1115
1116 seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_AND_INV_EVENT, true);
1117
1118 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
1119 tu_cs_emit(cs, 0x00000013);
1120 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1121 tu_cs_emit(cs, seqno);
1122 tu_cs_emit(cs, 0xffffffff);
1123 tu_cs_emit(cs, 0x00000010);
1124
1125 seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1126
1127 tu_cs_emit_pkt7(cs, CP_UNK_A6XX_14, 4);
1128 tu_cs_emit(cs, 0x00000000);
1129 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1130 tu_cs_emit(cs, seqno);
1131 }
1132
1133 static void
1134 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1135 {
1136 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1137
1138 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_BIN_SIZE, 3);
1139 tu_cs_emit(cs, A6XX_VSC_BIN_SIZE_WIDTH(tiling->tile0.extent.width) |
1140 A6XX_VSC_BIN_SIZE_HEIGHT(tiling->tile0.extent.height));
1141 tu_cs_emit_qw(cs, cmd->vsc_data.iova + 32 * cmd->vsc_data_pitch); /* VSC_SIZE_ADDRESS_LO/HI */
1142
1143 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_BIN_COUNT, 1);
1144 tu_cs_emit(cs, A6XX_VSC_BIN_COUNT_NX(tiling->tile_count.width) |
1145 A6XX_VSC_BIN_COUNT_NY(tiling->tile_count.height));
1146
1147 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1148 for (unsigned i = 0; i < 32; i++)
1149 tu_cs_emit(cs, tiling->pipe_config[i]);
1150
1151 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO, 4);
1152 tu_cs_emit_qw(cs, cmd->vsc_data2.iova);
1153 tu_cs_emit(cs, cmd->vsc_data2_pitch);
1154 tu_cs_emit(cs, cmd->vsc_data2.size);
1155
1156 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO, 4);
1157 tu_cs_emit_qw(cs, cmd->vsc_data.iova);
1158 tu_cs_emit(cs, cmd->vsc_data_pitch);
1159 tu_cs_emit(cs, cmd->vsc_data.size);
1160 }
1161
1162 static void
1163 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1164 {
1165 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1166 const uint32_t used_pipe_count =
1167 tiling->pipe_count.width * tiling->pipe_count.height;
1168
1169 /* Clear vsc_scratch: */
1170 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
1171 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1172 tu_cs_emit(cs, 0x0);
1173
1174 /* Check for overflow, write vsc_scratch if detected: */
1175 for (int i = 0; i < used_pipe_count; i++) {
1176 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1177 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1178 CP_COND_WRITE5_0_WRITE_MEMORY);
1179 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
1180 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1181 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
1182 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1183 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1184 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
1185
1186 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1187 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1188 CP_COND_WRITE5_0_WRITE_MEMORY);
1189 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
1190 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1191 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
1192 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1193 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1194 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
1195 }
1196
1197 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1198
1199 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1200
1201 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
1202 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
1203 CP_MEM_TO_REG_0_CNT(1 - 1));
1204 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1205
1206 /*
1207 * This is a bit awkward, we really want a way to invert the
1208 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1209 * execute cmds to use hwbinning when a bit is *not* set. This
1210 * dance is to invert OVERFLOW_FLAG_REG
1211 *
1212 * A CP_NOP packet is used to skip executing the 'else' clause
1213 * if (b0 set)..
1214 */
1215
1216 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1217 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1218 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1219 A6XX_CP_REG_TEST_0_BIT(0) |
1220 A6XX_CP_REG_TEST_0_UNK25);
1221
1222 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1223 tu_cs_emit(cs, 0x10000000);
1224 tu_cs_emit(cs, 7); /* conditionally execute next 7 dwords */
1225
1226 /* if (b0 set) */ {
1227 /*
1228 * On overflow, mirror the value to control->vsc_overflow
1229 * which CPU is checking to detect overflow (see
1230 * check_vsc_overflow())
1231 */
1232 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1233 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1234 CP_REG_TO_MEM_0_CNT(1 - 1));
1235 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_OVERFLOW);
1236
1237 tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1238 tu_cs_emit(cs, 0x0);
1239
1240 tu_cs_emit_pkt7(cs, CP_NOP, 2); /* skip 'else' when 'if' is taken */
1241 } /* else */ {
1242 tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1243 tu_cs_emit(cs, 0x1);
1244 }
1245 }
1246
1247 static void
1248 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1249 {
1250 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1251
1252 uint32_t x1 = tiling->tile0.offset.x;
1253 uint32_t y1 = tiling->tile0.offset.y;
1254 uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1255 uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1256
1257 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
1258
1259 tu6_emit_marker(cmd, cs);
1260 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1261 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1262 tu6_emit_marker(cmd, cs);
1263
1264 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1265 tu_cs_emit(cs, 0x1);
1266
1267 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1268 tu_cs_emit(cs, 0x1);
1269
1270 tu_cs_emit_wfi(cs);
1271
1272 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_MODE_CNTL, 1);
1273 tu_cs_emit(cs, A6XX_VFD_MODE_CNTL_BINNING_PASS);
1274
1275 update_vsc_pipe(cmd, cs);
1276
1277 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9805, 1);
1278 tu_cs_emit(cs, 0x1);
1279
1280 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A0F8, 1);
1281 tu_cs_emit(cs, 0x1);
1282
1283 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1284 tu_cs_emit(cs, UNK_2C);
1285
1286 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
1287 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(0) |
1288 A6XX_RB_WINDOW_OFFSET_Y(0));
1289
1290 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
1291 tu_cs_emit(cs, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
1292 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
1293
1294 /* emit IB to binning drawcmds: */
1295 tu_cs_emit_call(cs, &cmd->draw_cs);
1296
1297 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1298 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1299 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1300 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1301 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1302 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1303
1304 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1305 tu_cs_emit(cs, UNK_2D);
1306
1307 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1308 tu6_cache_flush(cmd, cs);
1309
1310 tu_cs_emit_wfi(cs);
1311
1312 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1313
1314 emit_vsc_overflow_test(cmd, cs);
1315
1316 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1317 tu_cs_emit(cs, 0x0);
1318
1319 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1320 tu_cs_emit(cs, 0x0);
1321
1322 tu_cs_emit_wfi(cs);
1323
1324 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1325 tu_cs_emit(cs, 0x7c400004);
1326
1327 cmd->wait_for_idle = false;
1328 }
1329
1330 static void
1331 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1332 {
1333 VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
1334 if (result != VK_SUCCESS) {
1335 cmd->record_result = result;
1336 return;
1337 }
1338
1339 tu6_emit_lrz_flush(cmd, cs);
1340
1341 /* lrz clear? */
1342
1343 tu6_emit_cache_flush(cmd, cs);
1344
1345 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1346 tu_cs_emit(cs, 0x0);
1347
1348 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1349 tu6_emit_wfi(cmd, cs);
1350 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1351 tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1352
1353 if (use_hw_binning(cmd)) {
1354 tu6_emit_bin_size(cmd, cs, A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1355
1356 tu6_emit_render_cntl(cmd, cs, true);
1357
1358 tu6_emit_binning_pass(cmd, cs);
1359
1360 tu6_emit_bin_size(cmd, cs, A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1361
1362 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_MODE_CNTL, 1);
1363 tu_cs_emit(cs, 0x0);
1364
1365 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9805, 1);
1366 tu_cs_emit(cs, 0x1);
1367
1368 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A0F8, 1);
1369 tu_cs_emit(cs, 0x1);
1370
1371 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1372 tu_cs_emit(cs, 0x1);
1373 } else {
1374 tu6_emit_bin_size(cmd, cs, 0x6000000);
1375 }
1376
1377 tu6_emit_render_cntl(cmd, cs, false);
1378
1379 tu_cs_sanity_check(cs);
1380 }
1381
1382 static void
1383 tu6_render_tile(struct tu_cmd_buffer *cmd,
1384 struct tu_cs *cs,
1385 const struct tu_tile *tile)
1386 {
1387 const uint32_t render_tile_space = 256 + tu_cs_get_call_size(&cmd->draw_cs);
1388 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1389 if (result != VK_SUCCESS) {
1390 cmd->record_result = result;
1391 return;
1392 }
1393
1394 tu6_emit_tile_select(cmd, cs, tile);
1395 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1396
1397 tu_cs_emit_call(cs, &cmd->draw_cs);
1398 cmd->wait_for_idle = true;
1399
1400 if (use_hw_binning(cmd)) {
1401 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1402 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1403 A6XX_CP_REG_TEST_0_BIT(0) |
1404 A6XX_CP_REG_TEST_0_UNK25);
1405
1406 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1407 tu_cs_emit(cs, 0x10000000);
1408 tu_cs_emit(cs, 2); /* conditionally execute next 2 dwords */
1409
1410 /* if (no overflow) */ {
1411 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1412 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1413 }
1414 }
1415
1416 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1417
1418 tu_cs_sanity_check(cs);
1419 }
1420
1421 static void
1422 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1423 {
1424 VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1425 if (result != VK_SUCCESS) {
1426 cmd->record_result = result;
1427 return;
1428 }
1429
1430 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1431 tu_cs_emit(cs, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1432
1433 tu6_emit_lrz_flush(cmd, cs);
1434
1435 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1436
1437 tu_cs_sanity_check(cs);
1438 }
1439
1440 static void
1441 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1442 {
1443 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1444
1445 tu6_render_begin(cmd, &cmd->cs);
1446
1447 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1448 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1449 struct tu_tile tile;
1450 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1451 tu6_render_tile(cmd, &cmd->cs, &tile);
1452 }
1453 }
1454
1455 tu6_render_end(cmd, &cmd->cs);
1456 }
1457
1458 static void
1459 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd,
1460 const VkRenderPassBeginInfo *info)
1461 {
1462 const uint32_t tile_load_space =
1463 6 + (23+19) * cmd->state.pass->attachment_count +
1464 21 + (13 * cmd->state.subpass->color_count + 8) + 11;
1465
1466 struct tu_cs sub_cs;
1467
1468 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs,
1469 tile_load_space, &sub_cs);
1470 if (result != VK_SUCCESS) {
1471 cmd->record_result = result;
1472 return;
1473 }
1474
1475 tu6_emit_blit_scissor(cmd, &sub_cs, true);
1476
1477 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1478 tu6_emit_load_attachment(cmd, &sub_cs, i);
1479
1480 tu6_emit_blit_scissor(cmd, &sub_cs, false);
1481
1482 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1483 tu6_emit_clear_attachment(cmd, &sub_cs, i, info);
1484
1485 tu6_emit_zs(cmd, cmd->state.subpass, &sub_cs);
1486 tu6_emit_mrt(cmd, cmd->state.subpass, &sub_cs);
1487 tu6_emit_msaa(cmd, cmd->state.subpass, &sub_cs);
1488
1489 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1490 }
1491
1492 static void
1493 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1494 {
1495 const uint32_t tile_store_space = 32 + 23 * cmd->state.pass->attachment_count;
1496 struct tu_cs sub_cs;
1497
1498 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs,
1499 tile_store_space, &sub_cs);
1500 if (result != VK_SUCCESS) {
1501 cmd->record_result = result;
1502 return;
1503 }
1504
1505 /* emit to tile-store sub_cs */
1506 tu6_emit_tile_store(cmd, &sub_cs);
1507
1508 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1509 }
1510
1511 static void
1512 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1513 const VkRect2D *render_area)
1514 {
1515 const struct tu_device *dev = cmd->device;
1516 const struct tu_render_pass *pass = cmd->state.pass;
1517 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1518
1519 tiling->render_area = *render_area;
1520 for (uint32_t a = 0; a < pass->attachment_count; a++) {
1521 if (pass->attachments[a].needs_gmem)
1522 tiling->buffer_cpp[a] = pass->attachments[a].cpp;
1523 else
1524 tiling->buffer_cpp[a] = 0;
1525 }
1526 tiling->buffer_count = pass->attachment_count;
1527
1528 tu_tiling_config_update_tile_layout(tiling, dev);
1529 tu_tiling_config_update_pipe_layout(tiling, dev);
1530 tu_tiling_config_update_pipes(tiling, dev);
1531 }
1532
1533 const struct tu_dynamic_state default_dynamic_state = {
1534 .viewport =
1535 {
1536 .count = 0,
1537 },
1538 .scissor =
1539 {
1540 .count = 0,
1541 },
1542 .line_width = 1.0f,
1543 .depth_bias =
1544 {
1545 .bias = 0.0f,
1546 .clamp = 0.0f,
1547 .slope = 0.0f,
1548 },
1549 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1550 .depth_bounds =
1551 {
1552 .min = 0.0f,
1553 .max = 1.0f,
1554 },
1555 .stencil_compare_mask =
1556 {
1557 .front = ~0u,
1558 .back = ~0u,
1559 },
1560 .stencil_write_mask =
1561 {
1562 .front = ~0u,
1563 .back = ~0u,
1564 },
1565 .stencil_reference =
1566 {
1567 .front = 0u,
1568 .back = 0u,
1569 },
1570 };
1571
1572 static void UNUSED /* FINISHME */
1573 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1574 const struct tu_dynamic_state *src)
1575 {
1576 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1577 uint32_t copy_mask = src->mask;
1578 uint32_t dest_mask = 0;
1579
1580 tu_use_args(cmd_buffer); /* FINISHME */
1581
1582 /* Make sure to copy the number of viewports/scissors because they can
1583 * only be specified at pipeline creation time.
1584 */
1585 dest->viewport.count = src->viewport.count;
1586 dest->scissor.count = src->scissor.count;
1587 dest->discard_rectangle.count = src->discard_rectangle.count;
1588
1589 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1590 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1591 src->viewport.count * sizeof(VkViewport))) {
1592 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1593 src->viewport.count);
1594 dest_mask |= TU_DYNAMIC_VIEWPORT;
1595 }
1596 }
1597
1598 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1599 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1600 src->scissor.count * sizeof(VkRect2D))) {
1601 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1602 src->scissor.count);
1603 dest_mask |= TU_DYNAMIC_SCISSOR;
1604 }
1605 }
1606
1607 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1608 if (dest->line_width != src->line_width) {
1609 dest->line_width = src->line_width;
1610 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1611 }
1612 }
1613
1614 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1615 if (memcmp(&dest->depth_bias, &src->depth_bias,
1616 sizeof(src->depth_bias))) {
1617 dest->depth_bias = src->depth_bias;
1618 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1619 }
1620 }
1621
1622 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1623 if (memcmp(&dest->blend_constants, &src->blend_constants,
1624 sizeof(src->blend_constants))) {
1625 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1626 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1627 }
1628 }
1629
1630 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1631 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1632 sizeof(src->depth_bounds))) {
1633 dest->depth_bounds = src->depth_bounds;
1634 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1635 }
1636 }
1637
1638 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1639 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1640 sizeof(src->stencil_compare_mask))) {
1641 dest->stencil_compare_mask = src->stencil_compare_mask;
1642 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1643 }
1644 }
1645
1646 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1647 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1648 sizeof(src->stencil_write_mask))) {
1649 dest->stencil_write_mask = src->stencil_write_mask;
1650 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1651 }
1652 }
1653
1654 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1655 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1656 sizeof(src->stencil_reference))) {
1657 dest->stencil_reference = src->stencil_reference;
1658 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1659 }
1660 }
1661
1662 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1663 if (memcmp(&dest->discard_rectangle.rectangles,
1664 &src->discard_rectangle.rectangles,
1665 src->discard_rectangle.count * sizeof(VkRect2D))) {
1666 typed_memcpy(dest->discard_rectangle.rectangles,
1667 src->discard_rectangle.rectangles,
1668 src->discard_rectangle.count);
1669 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1670 }
1671 }
1672 }
1673
1674 static VkResult
1675 tu_create_cmd_buffer(struct tu_device *device,
1676 struct tu_cmd_pool *pool,
1677 VkCommandBufferLevel level,
1678 VkCommandBuffer *pCommandBuffer)
1679 {
1680 struct tu_cmd_buffer *cmd_buffer;
1681 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1682 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1683 if (cmd_buffer == NULL)
1684 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1685
1686 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1687 cmd_buffer->device = device;
1688 cmd_buffer->pool = pool;
1689 cmd_buffer->level = level;
1690
1691 if (pool) {
1692 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1693 cmd_buffer->queue_family_index = pool->queue_family_index;
1694
1695 } else {
1696 /* Init the pool_link so we can safely call list_del when we destroy
1697 * the command buffer
1698 */
1699 list_inithead(&cmd_buffer->pool_link);
1700 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1701 }
1702
1703 tu_bo_list_init(&cmd_buffer->bo_list);
1704 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1705 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1706 tu_cs_init(&cmd_buffer->sub_cs, TU_CS_MODE_SUB_STREAM, 2048);
1707
1708 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1709
1710 list_inithead(&cmd_buffer->upload.list);
1711
1712 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1713 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1714
1715 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1716 if (result != VK_SUCCESS)
1717 return result;
1718
1719 #define VSC_DATA_SIZE(pitch) ((pitch) * 32 + 0x100) /* extra size to store VSC_SIZE */
1720 #define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
1721
1722 /* TODO: resize on overflow or compute a max size from # of vertices in renderpass?? */
1723 cmd_buffer->vsc_data_pitch = 0x440 * 4;
1724 cmd_buffer->vsc_data2_pitch = 0x1040 * 4;
1725
1726 result = tu_bo_init_new(device, &cmd_buffer->vsc_data, VSC_DATA_SIZE(cmd_buffer->vsc_data_pitch));
1727 if (result != VK_SUCCESS)
1728 goto fail_vsc_data;
1729
1730 result = tu_bo_init_new(device, &cmd_buffer->vsc_data2, VSC_DATA2_SIZE(cmd_buffer->vsc_data2_pitch));
1731 if (result != VK_SUCCESS)
1732 goto fail_vsc_data2;
1733
1734 return VK_SUCCESS;
1735
1736 fail_vsc_data2:
1737 tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data);
1738 fail_vsc_data:
1739 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1740 return result;
1741 }
1742
1743 static void
1744 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1745 {
1746 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1747 tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data);
1748 tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data2);
1749
1750 list_del(&cmd_buffer->pool_link);
1751
1752 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1753 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1754
1755 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1756 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1757 tu_cs_finish(cmd_buffer->device, &cmd_buffer->sub_cs);
1758
1759 tu_bo_list_destroy(&cmd_buffer->bo_list);
1760 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1761 }
1762
1763 static VkResult
1764 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1765 {
1766 cmd_buffer->wait_for_idle = true;
1767
1768 cmd_buffer->record_result = VK_SUCCESS;
1769
1770 tu_bo_list_reset(&cmd_buffer->bo_list);
1771 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1772 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1773 tu_cs_reset(cmd_buffer->device, &cmd_buffer->sub_cs);
1774
1775 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1776 cmd_buffer->descriptors[i].dirty = 0;
1777 cmd_buffer->descriptors[i].valid = 0;
1778 cmd_buffer->descriptors[i].push_dirty = false;
1779 }
1780
1781 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1782
1783 return cmd_buffer->record_result;
1784 }
1785
1786 VkResult
1787 tu_AllocateCommandBuffers(VkDevice _device,
1788 const VkCommandBufferAllocateInfo *pAllocateInfo,
1789 VkCommandBuffer *pCommandBuffers)
1790 {
1791 TU_FROM_HANDLE(tu_device, device, _device);
1792 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1793
1794 VkResult result = VK_SUCCESS;
1795 uint32_t i;
1796
1797 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1798
1799 if (!list_is_empty(&pool->free_cmd_buffers)) {
1800 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1801 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1802
1803 list_del(&cmd_buffer->pool_link);
1804 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1805
1806 result = tu_reset_cmd_buffer(cmd_buffer);
1807 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1808 cmd_buffer->level = pAllocateInfo->level;
1809
1810 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1811 } else {
1812 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1813 &pCommandBuffers[i]);
1814 }
1815 if (result != VK_SUCCESS)
1816 break;
1817 }
1818
1819 if (result != VK_SUCCESS) {
1820 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1821 pCommandBuffers);
1822
1823 /* From the Vulkan 1.0.66 spec:
1824 *
1825 * "vkAllocateCommandBuffers can be used to create multiple
1826 * command buffers. If the creation of any of those command
1827 * buffers fails, the implementation must destroy all
1828 * successfully created command buffer objects from this
1829 * command, set all entries of the pCommandBuffers array to
1830 * NULL and return the error."
1831 */
1832 memset(pCommandBuffers, 0,
1833 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1834 }
1835
1836 return result;
1837 }
1838
1839 void
1840 tu_FreeCommandBuffers(VkDevice device,
1841 VkCommandPool commandPool,
1842 uint32_t commandBufferCount,
1843 const VkCommandBuffer *pCommandBuffers)
1844 {
1845 for (uint32_t i = 0; i < commandBufferCount; i++) {
1846 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1847
1848 if (cmd_buffer) {
1849 if (cmd_buffer->pool) {
1850 list_del(&cmd_buffer->pool_link);
1851 list_addtail(&cmd_buffer->pool_link,
1852 &cmd_buffer->pool->free_cmd_buffers);
1853 } else
1854 tu_cmd_buffer_destroy(cmd_buffer);
1855 }
1856 }
1857 }
1858
1859 VkResult
1860 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1861 VkCommandBufferResetFlags flags)
1862 {
1863 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1864 return tu_reset_cmd_buffer(cmd_buffer);
1865 }
1866
1867 VkResult
1868 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1869 const VkCommandBufferBeginInfo *pBeginInfo)
1870 {
1871 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1872 VkResult result = VK_SUCCESS;
1873
1874 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1875 /* If the command buffer has already been resetted with
1876 * vkResetCommandBuffer, no need to do it again.
1877 */
1878 result = tu_reset_cmd_buffer(cmd_buffer);
1879 if (result != VK_SUCCESS)
1880 return result;
1881 }
1882
1883 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1884 cmd_buffer->usage_flags = pBeginInfo->flags;
1885
1886 tu_cs_begin(&cmd_buffer->cs);
1887 tu_cs_begin(&cmd_buffer->draw_cs);
1888
1889 cmd_buffer->marker_seqno = 0;
1890 cmd_buffer->scratch_seqno = 0;
1891
1892 /* setup initial configuration into command buffer */
1893 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1894 switch (cmd_buffer->queue_family_index) {
1895 case TU_QUEUE_GENERAL:
1896 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1897 break;
1898 default:
1899 break;
1900 }
1901 }
1902
1903 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1904
1905 return VK_SUCCESS;
1906 }
1907
1908 void
1909 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1910 uint32_t firstBinding,
1911 uint32_t bindingCount,
1912 const VkBuffer *pBuffers,
1913 const VkDeviceSize *pOffsets)
1914 {
1915 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1916
1917 assert(firstBinding + bindingCount <= MAX_VBS);
1918
1919 for (uint32_t i = 0; i < bindingCount; i++) {
1920 cmd->state.vb.buffers[firstBinding + i] =
1921 tu_buffer_from_handle(pBuffers[i]);
1922 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1923 }
1924
1925 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1926 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1927 }
1928
1929 void
1930 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1931 VkBuffer buffer,
1932 VkDeviceSize offset,
1933 VkIndexType indexType)
1934 {
1935 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1936 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1937
1938 /* initialize/update the restart index */
1939 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1940 struct tu_cs *draw_cs = &cmd->draw_cs;
1941 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1942 if (result != VK_SUCCESS) {
1943 cmd->record_result = result;
1944 return;
1945 }
1946
1947 tu6_emit_restart_index(
1948 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1949
1950 tu_cs_sanity_check(draw_cs);
1951 }
1952
1953 /* track the BO */
1954 if (cmd->state.index_buffer != buf)
1955 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1956
1957 cmd->state.index_buffer = buf;
1958 cmd->state.index_offset = offset;
1959 cmd->state.index_type = indexType;
1960 }
1961
1962 void
1963 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1964 VkPipelineBindPoint pipelineBindPoint,
1965 VkPipelineLayout _layout,
1966 uint32_t firstSet,
1967 uint32_t descriptorSetCount,
1968 const VkDescriptorSet *pDescriptorSets,
1969 uint32_t dynamicOffsetCount,
1970 const uint32_t *pDynamicOffsets)
1971 {
1972 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1973 TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1974 unsigned dyn_idx = 0;
1975
1976 struct tu_descriptor_state *descriptors_state =
1977 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1978
1979 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1980 unsigned idx = i + firstSet;
1981 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1982
1983 descriptors_state->sets[idx] = set;
1984 descriptors_state->valid |= (1u << idx);
1985
1986 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1987 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1988 assert(dyn_idx < dynamicOffsetCount);
1989
1990 descriptors_state->dynamic_buffers[idx] =
1991 set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
1992 }
1993 }
1994
1995 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1996 }
1997
1998 void
1999 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
2000 VkPipelineLayout layout,
2001 VkShaderStageFlags stageFlags,
2002 uint32_t offset,
2003 uint32_t size,
2004 const void *pValues)
2005 {
2006 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2007 memcpy((void*) cmd->push_constants + offset, pValues, size);
2008 cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
2009 }
2010
2011 VkResult
2012 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
2013 {
2014 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2015
2016 if (cmd_buffer->scratch_seqno) {
2017 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
2018 MSM_SUBMIT_BO_WRITE);
2019 }
2020
2021 if (cmd_buffer->use_vsc_data) {
2022 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
2023 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2024 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
2025 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2026 }
2027
2028 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
2029 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
2030 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2031 }
2032
2033 for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
2034 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
2035 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2036 }
2037
2038 tu_cs_end(&cmd_buffer->cs);
2039 tu_cs_end(&cmd_buffer->draw_cs);
2040
2041 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
2042
2043 return cmd_buffer->record_result;
2044 }
2045
2046 void
2047 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
2048 VkPipelineBindPoint pipelineBindPoint,
2049 VkPipeline _pipeline)
2050 {
2051 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2052 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2053
2054 switch (pipelineBindPoint) {
2055 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2056 cmd->state.pipeline = pipeline;
2057 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
2058 break;
2059 case VK_PIPELINE_BIND_POINT_COMPUTE:
2060 cmd->state.compute_pipeline = pipeline;
2061 cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2062 break;
2063 default:
2064 unreachable("unrecognized pipeline bind point");
2065 break;
2066 }
2067
2068 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2069 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2070 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2071 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2072 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2073 }
2074 }
2075
2076 void
2077 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2078 uint32_t firstViewport,
2079 uint32_t viewportCount,
2080 const VkViewport *pViewports)
2081 {
2082 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2083 struct tu_cs *draw_cs = &cmd->draw_cs;
2084
2085 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
2086 if (result != VK_SUCCESS) {
2087 cmd->record_result = result;
2088 return;
2089 }
2090
2091 assert(firstViewport == 0 && viewportCount == 1);
2092 tu6_emit_viewport(draw_cs, pViewports);
2093
2094 tu_cs_sanity_check(draw_cs);
2095 }
2096
2097 void
2098 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2099 uint32_t firstScissor,
2100 uint32_t scissorCount,
2101 const VkRect2D *pScissors)
2102 {
2103 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2104 struct tu_cs *draw_cs = &cmd->draw_cs;
2105
2106 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
2107 if (result != VK_SUCCESS) {
2108 cmd->record_result = result;
2109 return;
2110 }
2111
2112 assert(firstScissor == 0 && scissorCount == 1);
2113 tu6_emit_scissor(draw_cs, pScissors);
2114
2115 tu_cs_sanity_check(draw_cs);
2116 }
2117
2118 void
2119 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2120 {
2121 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2122
2123 cmd->state.dynamic.line_width = lineWidth;
2124
2125 /* line width depends on VkPipelineRasterizationStateCreateInfo */
2126 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2127 }
2128
2129 void
2130 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2131 float depthBiasConstantFactor,
2132 float depthBiasClamp,
2133 float depthBiasSlopeFactor)
2134 {
2135 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2136 struct tu_cs *draw_cs = &cmd->draw_cs;
2137
2138 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
2139 if (result != VK_SUCCESS) {
2140 cmd->record_result = result;
2141 return;
2142 }
2143
2144 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2145 depthBiasSlopeFactor);
2146
2147 tu_cs_sanity_check(draw_cs);
2148 }
2149
2150 void
2151 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2152 const float blendConstants[4])
2153 {
2154 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2155 struct tu_cs *draw_cs = &cmd->draw_cs;
2156
2157 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
2158 if (result != VK_SUCCESS) {
2159 cmd->record_result = result;
2160 return;
2161 }
2162
2163 tu6_emit_blend_constants(draw_cs, blendConstants);
2164
2165 tu_cs_sanity_check(draw_cs);
2166 }
2167
2168 void
2169 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2170 float minDepthBounds,
2171 float maxDepthBounds)
2172 {
2173 }
2174
2175 void
2176 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2177 VkStencilFaceFlags faceMask,
2178 uint32_t compareMask)
2179 {
2180 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2181
2182 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2183 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2184 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2185 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2186
2187 /* the front/back compare masks must be updated together */
2188 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2189 }
2190
2191 void
2192 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2193 VkStencilFaceFlags faceMask,
2194 uint32_t writeMask)
2195 {
2196 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2197
2198 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2199 cmd->state.dynamic.stencil_write_mask.front = writeMask;
2200 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2201 cmd->state.dynamic.stencil_write_mask.back = writeMask;
2202
2203 /* the front/back write masks must be updated together */
2204 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2205 }
2206
2207 void
2208 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2209 VkStencilFaceFlags faceMask,
2210 uint32_t reference)
2211 {
2212 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2213
2214 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2215 cmd->state.dynamic.stencil_reference.front = reference;
2216 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2217 cmd->state.dynamic.stencil_reference.back = reference;
2218
2219 /* the front/back references must be updated together */
2220 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2221 }
2222
2223 void
2224 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2225 uint32_t commandBufferCount,
2226 const VkCommandBuffer *pCmdBuffers)
2227 {
2228 }
2229
2230 VkResult
2231 tu_CreateCommandPool(VkDevice _device,
2232 const VkCommandPoolCreateInfo *pCreateInfo,
2233 const VkAllocationCallbacks *pAllocator,
2234 VkCommandPool *pCmdPool)
2235 {
2236 TU_FROM_HANDLE(tu_device, device, _device);
2237 struct tu_cmd_pool *pool;
2238
2239 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2240 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2241 if (pool == NULL)
2242 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2243
2244 if (pAllocator)
2245 pool->alloc = *pAllocator;
2246 else
2247 pool->alloc = device->alloc;
2248
2249 list_inithead(&pool->cmd_buffers);
2250 list_inithead(&pool->free_cmd_buffers);
2251
2252 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2253
2254 *pCmdPool = tu_cmd_pool_to_handle(pool);
2255
2256 return VK_SUCCESS;
2257 }
2258
2259 void
2260 tu_DestroyCommandPool(VkDevice _device,
2261 VkCommandPool commandPool,
2262 const VkAllocationCallbacks *pAllocator)
2263 {
2264 TU_FROM_HANDLE(tu_device, device, _device);
2265 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2266
2267 if (!pool)
2268 return;
2269
2270 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2271 &pool->cmd_buffers, pool_link)
2272 {
2273 tu_cmd_buffer_destroy(cmd_buffer);
2274 }
2275
2276 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2277 &pool->free_cmd_buffers, pool_link)
2278 {
2279 tu_cmd_buffer_destroy(cmd_buffer);
2280 }
2281
2282 vk_free2(&device->alloc, pAllocator, pool);
2283 }
2284
2285 VkResult
2286 tu_ResetCommandPool(VkDevice device,
2287 VkCommandPool commandPool,
2288 VkCommandPoolResetFlags flags)
2289 {
2290 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2291 VkResult result;
2292
2293 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2294 pool_link)
2295 {
2296 result = tu_reset_cmd_buffer(cmd_buffer);
2297 if (result != VK_SUCCESS)
2298 return result;
2299 }
2300
2301 return VK_SUCCESS;
2302 }
2303
2304 void
2305 tu_TrimCommandPool(VkDevice device,
2306 VkCommandPool commandPool,
2307 VkCommandPoolTrimFlags flags)
2308 {
2309 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2310
2311 if (!pool)
2312 return;
2313
2314 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2315 &pool->free_cmd_buffers, pool_link)
2316 {
2317 tu_cmd_buffer_destroy(cmd_buffer);
2318 }
2319 }
2320
2321 void
2322 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2323 const VkRenderPassBeginInfo *pRenderPassBegin,
2324 VkSubpassContents contents)
2325 {
2326 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2327 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2328 TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2329 VkResult result;
2330
2331 cmd->state.pass = pass;
2332 cmd->state.subpass = pass->subpasses;
2333 cmd->state.framebuffer = fb;
2334
2335 tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2336 tu_cmd_prepare_tile_load_ib(cmd, pRenderPassBegin);
2337 tu_cmd_prepare_tile_store_ib(cmd);
2338
2339 /* note: use_hw_binning only checks tiling config */
2340 if (use_hw_binning(cmd))
2341 cmd->use_vsc_data = true;
2342
2343 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2344 const struct tu_image_view *iview = fb->attachments[i].attachment;
2345 tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2346 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2347 }
2348 }
2349
2350 void
2351 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer,
2352 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2353 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2354 {
2355 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2356 pSubpassBeginInfo->contents);
2357 }
2358
2359 void
2360 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2361 {
2362 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2363 const struct tu_render_pass *pass = cmd->state.pass;
2364 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2365 struct tu_cs *cs = &cmd->draw_cs;
2366
2367 VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
2368 if (result != VK_SUCCESS) {
2369 cmd->record_result = result;
2370 return;
2371 }
2372
2373 const struct tu_subpass *subpass = cmd->state.subpass++;
2374 /* TODO:
2375 * if msaa samples change between subpasses,
2376 * attachment store is broken for some attachments
2377 */
2378 if (subpass->resolve_attachments) {
2379 tu6_emit_blit_scissor(cmd, cs, true);
2380 for (unsigned i = 0; i < subpass->color_count; i++) {
2381 uint32_t a = subpass->resolve_attachments[i].attachment;
2382 if (a != VK_ATTACHMENT_UNUSED) {
2383 tu6_emit_store_attachment(cmd, cs, a,
2384 subpass->color_attachments[i].attachment);
2385 }
2386 }
2387 }
2388
2389 /* emit mrt/zs/msaa state for the subpass that is starting */
2390 tu6_emit_zs(cmd, cmd->state.subpass, cs);
2391 tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2392 tu6_emit_msaa(cmd, cmd->state.subpass, cs);
2393
2394 /* TODO:
2395 * since we don't know how to do GMEM->GMEM resolve,
2396 * resolve attachments are resolved to memory then loaded to GMEM again if needed
2397 */
2398 if (subpass->resolve_attachments) {
2399 for (unsigned i = 0; i < subpass->color_count; i++) {
2400 uint32_t a = subpass->resolve_attachments[i].attachment;
2401 const struct tu_image_view *iview =
2402 cmd->state.framebuffer->attachments[a].attachment;
2403 if (a != VK_ATTACHMENT_UNUSED && pass->attachments[a].needs_gmem) {
2404 tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
2405 tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[a], false);
2406 tu6_emit_blit(cmd, cs);
2407 }
2408 }
2409 }
2410 }
2411
2412 void
2413 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer,
2414 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2415 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2416 {
2417 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2418 }
2419
2420 struct tu_draw_info
2421 {
2422 /**
2423 * Number of vertices.
2424 */
2425 uint32_t count;
2426
2427 /**
2428 * Index of the first vertex.
2429 */
2430 int32_t vertex_offset;
2431
2432 /**
2433 * First instance id.
2434 */
2435 uint32_t first_instance;
2436
2437 /**
2438 * Number of instances.
2439 */
2440 uint32_t instance_count;
2441
2442 /**
2443 * First index (indexed draws only).
2444 */
2445 uint32_t first_index;
2446
2447 /**
2448 * Whether it's an indexed draw.
2449 */
2450 bool indexed;
2451
2452 /**
2453 * Indirect draw parameters resource.
2454 */
2455 struct tu_buffer *indirect;
2456 uint64_t indirect_offset;
2457 uint32_t stride;
2458
2459 /**
2460 * Draw count parameters resource.
2461 */
2462 struct tu_buffer *count_buffer;
2463 uint64_t count_buffer_offset;
2464 };
2465
2466 enum tu_draw_state_group_id
2467 {
2468 TU_DRAW_STATE_PROGRAM,
2469 TU_DRAW_STATE_PROGRAM_BINNING,
2470 TU_DRAW_STATE_VI,
2471 TU_DRAW_STATE_VI_BINNING,
2472 TU_DRAW_STATE_VP,
2473 TU_DRAW_STATE_RAST,
2474 TU_DRAW_STATE_DS,
2475 TU_DRAW_STATE_BLEND,
2476 TU_DRAW_STATE_VS_CONST,
2477 TU_DRAW_STATE_FS_CONST,
2478 TU_DRAW_STATE_VS_TEX,
2479 TU_DRAW_STATE_FS_TEX,
2480 TU_DRAW_STATE_FS_IBO,
2481
2482 TU_DRAW_STATE_COUNT,
2483 };
2484
2485 struct tu_draw_state_group
2486 {
2487 enum tu_draw_state_group_id id;
2488 uint32_t enable_mask;
2489 struct tu_cs_entry ib;
2490 };
2491
2492 static struct tu_sampler*
2493 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2494 const struct tu_descriptor_map *map, unsigned i)
2495 {
2496 assert(descriptors_state->valid & (1 << map->set[i]));
2497
2498 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2499 assert(map->binding[i] < set->layout->binding_count);
2500
2501 const struct tu_descriptor_set_binding_layout *layout =
2502 &set->layout->binding[map->binding[i]];
2503
2504 switch (layout->type) {
2505 case VK_DESCRIPTOR_TYPE_SAMPLER:
2506 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2507 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2508 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS];
2509 default:
2510 unreachable("unimplemented descriptor type");
2511 break;
2512 }
2513 }
2514
2515 static void
2516 write_tex_const(struct tu_cmd_buffer *cmd,
2517 uint32_t *dst,
2518 struct tu_descriptor_state *descriptors_state,
2519 const struct tu_descriptor_map *map,
2520 unsigned i)
2521 {
2522 assert(descriptors_state->valid & (1 << map->set[i]));
2523
2524 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2525 assert(map->binding[i] < set->layout->binding_count);
2526
2527 const struct tu_descriptor_set_binding_layout *layout =
2528 &set->layout->binding[map->binding[i]];
2529
2530 switch (layout->type) {
2531 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2532 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2533 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2534 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2535 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2536 memcpy(dst, &set->mapped_ptr[layout->offset / 4], A6XX_TEX_CONST_DWORDS*4);
2537 break;
2538 default:
2539 unreachable("unimplemented descriptor type");
2540 break;
2541 }
2542
2543 if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
2544 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2545 uint32_t a = cmd->state.subpass->input_attachments[map->value[i]].attachment;
2546
2547 assert(cmd->state.pass->attachments[a].needs_gmem);
2548 dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2549 dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2550 dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2551 dst[2] |=
2552 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2553 A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * tiling->buffer_cpp[a]);
2554 dst[3] = 0;
2555 dst[4] = 0x100000 + tiling->gmem_offsets[a];
2556 dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2557 for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2558 dst[i] = 0;
2559 }
2560 }
2561
2562 static uint64_t
2563 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2564 const struct tu_descriptor_map *map,
2565 unsigned i)
2566 {
2567 assert(descriptors_state->valid & (1 << map->set[i]));
2568
2569 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2570 assert(map->binding[i] < set->layout->binding_count);
2571
2572 const struct tu_descriptor_set_binding_layout *layout =
2573 &set->layout->binding[map->binding[i]];
2574
2575 switch (layout->type) {
2576 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2577 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2578 return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset];
2579 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2580 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2581 return (uint64_t) set->mapped_ptr[layout->offset / 4 + 1] << 32 |
2582 set->mapped_ptr[layout->offset / 4];
2583 default:
2584 unreachable("unimplemented descriptor type");
2585 break;
2586 }
2587 }
2588
2589 static inline uint32_t
2590 tu6_stage2opcode(gl_shader_stage type)
2591 {
2592 switch (type) {
2593 case MESA_SHADER_VERTEX:
2594 case MESA_SHADER_TESS_CTRL:
2595 case MESA_SHADER_TESS_EVAL:
2596 case MESA_SHADER_GEOMETRY:
2597 return CP_LOAD_STATE6_GEOM;
2598 case MESA_SHADER_FRAGMENT:
2599 case MESA_SHADER_COMPUTE:
2600 case MESA_SHADER_KERNEL:
2601 return CP_LOAD_STATE6_FRAG;
2602 default:
2603 unreachable("bad shader type");
2604 }
2605 }
2606
2607 static inline enum a6xx_state_block
2608 tu6_stage2shadersb(gl_shader_stage type)
2609 {
2610 switch (type) {
2611 case MESA_SHADER_VERTEX:
2612 return SB6_VS_SHADER;
2613 case MESA_SHADER_FRAGMENT:
2614 return SB6_FS_SHADER;
2615 case MESA_SHADER_COMPUTE:
2616 case MESA_SHADER_KERNEL:
2617 return SB6_CS_SHADER;
2618 default:
2619 unreachable("bad shader type");
2620 return ~0;
2621 }
2622 }
2623
2624 static void
2625 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2626 struct tu_descriptor_state *descriptors_state,
2627 gl_shader_stage type,
2628 uint32_t *push_constants)
2629 {
2630 const struct tu_program_descriptor_linkage *link =
2631 &pipeline->program.link[type];
2632 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2633
2634 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2635 if (state->range[i].start < state->range[i].end) {
2636 uint32_t size = state->range[i].end - state->range[i].start;
2637 uint32_t offset = state->range[i].start;
2638
2639 /* and even if the start of the const buffer is before
2640 * first_immediate, the end may not be:
2641 */
2642 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2643
2644 if (size == 0)
2645 continue;
2646
2647 /* things should be aligned to vec4: */
2648 debug_assert((state->range[i].offset % 16) == 0);
2649 debug_assert((size % 16) == 0);
2650 debug_assert((offset % 16) == 0);
2651
2652 if (i == 0) {
2653 /* push constants */
2654 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2655 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2656 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2657 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2658 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2659 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2660 tu_cs_emit(cs, 0);
2661 tu_cs_emit(cs, 0);
2662 for (unsigned i = 0; i < size / 4; i++)
2663 tu_cs_emit(cs, push_constants[i + offset / 4]);
2664 continue;
2665 }
2666
2667 uint64_t va = buffer_ptr(descriptors_state, &link->ubo_map, i - 1);
2668
2669 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2670 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2671 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2672 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2673 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2674 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2675 tu_cs_emit_qw(cs, va + offset);
2676 }
2677 }
2678 }
2679
2680 static void
2681 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2682 struct tu_descriptor_state *descriptors_state,
2683 gl_shader_stage type)
2684 {
2685 const struct tu_program_descriptor_linkage *link =
2686 &pipeline->program.link[type];
2687
2688 uint32_t num = MIN2(link->ubo_map.num, link->const_state.num_ubos);
2689 uint32_t anum = align(num, 2);
2690 uint32_t i;
2691
2692 if (!num)
2693 return;
2694
2695 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2696 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2697 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2698 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2699 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2700 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2701 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2702 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2703
2704 for (i = 0; i < num; i++)
2705 tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i));
2706
2707 for (; i < anum; i++) {
2708 tu_cs_emit(cs, 0xffffffff);
2709 tu_cs_emit(cs, 0xffffffff);
2710 }
2711 }
2712
2713 static struct tu_cs_entry
2714 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2715 const struct tu_pipeline *pipeline,
2716 struct tu_descriptor_state *descriptors_state,
2717 gl_shader_stage type)
2718 {
2719 struct tu_cs cs;
2720 tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
2721
2722 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2723 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2724
2725 return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2726 }
2727
2728 static VkResult
2729 tu6_emit_textures(struct tu_cmd_buffer *cmd,
2730 const struct tu_pipeline *pipeline,
2731 struct tu_descriptor_state *descriptors_state,
2732 gl_shader_stage type,
2733 struct tu_cs_entry *entry,
2734 bool *needs_border)
2735 {
2736 struct tu_device *device = cmd->device;
2737 struct tu_cs *draw_state = &cmd->sub_cs;
2738 const struct tu_program_descriptor_linkage *link =
2739 &pipeline->program.link[type];
2740 VkResult result;
2741
2742 if (link->texture_map.num == 0 && link->sampler_map.num == 0) {
2743 *entry = (struct tu_cs_entry) {};
2744 return VK_SUCCESS;
2745 }
2746
2747 /* allocate and fill texture state */
2748 struct ts_cs_memory tex_const;
2749 result = tu_cs_alloc(device, draw_state, link->texture_map.num, A6XX_TEX_CONST_DWORDS, &tex_const);
2750 if (result != VK_SUCCESS)
2751 return result;
2752
2753 for (unsigned i = 0; i < link->texture_map.num; i++) {
2754 write_tex_const(cmd,
2755 &tex_const.map[A6XX_TEX_CONST_DWORDS*i],
2756 descriptors_state, &link->texture_map, i);
2757 }
2758
2759 /* allocate and fill sampler state */
2760 struct ts_cs_memory tex_samp;
2761 result = tu_cs_alloc(device, draw_state, link->sampler_map.num, A6XX_TEX_SAMP_DWORDS, &tex_samp);
2762 if (result != VK_SUCCESS)
2763 return result;
2764
2765 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2766 struct tu_sampler *sampler = sampler_ptr(descriptors_state, &link->sampler_map, i);
2767 memcpy(&tex_samp.map[A6XX_TEX_SAMP_DWORDS*i], sampler->state, sizeof(sampler->state));
2768 *needs_border |= sampler->needs_border;
2769 }
2770
2771 unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
2772 enum a6xx_state_block sb;
2773
2774 switch (type) {
2775 case MESA_SHADER_VERTEX:
2776 sb = SB6_VS_TEX;
2777 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2778 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2779 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2780 break;
2781 case MESA_SHADER_FRAGMENT:
2782 sb = SB6_FS_TEX;
2783 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2784 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2785 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2786 break;
2787 case MESA_SHADER_COMPUTE:
2788 sb = SB6_CS_TEX;
2789 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2790 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2791 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2792 break;
2793 default:
2794 unreachable("bad state block");
2795 }
2796
2797 struct tu_cs cs;
2798 result = tu_cs_begin_sub_stream(device, draw_state, 16, &cs);
2799 if (result != VK_SUCCESS)
2800 return result;
2801
2802 /* output sampler state: */
2803 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2804 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2805 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2806 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2807 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2808 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num));
2809 tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2810
2811 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2812 tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2813
2814 /* emit texture state: */
2815 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2816 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2817 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2818 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2819 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2820 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num));
2821 tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2822
2823 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2824 tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2825
2826 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2827 tu_cs_emit(&cs, link->texture_map.num);
2828
2829 *entry = tu_cs_end_sub_stream(draw_state, &cs);
2830 return VK_SUCCESS;
2831 }
2832
2833 static struct tu_cs_entry
2834 tu6_emit_ibo(struct tu_device *device, struct tu_cs *draw_state,
2835 const struct tu_pipeline *pipeline,
2836 struct tu_descriptor_state *descriptors_state,
2837 gl_shader_stage type)
2838 {
2839 const struct tu_program_descriptor_linkage *link =
2840 &pipeline->program.link[type];
2841
2842 uint32_t size = link->image_mapping.num_ibo * A6XX_TEX_CONST_DWORDS;
2843 if (!size)
2844 return (struct tu_cs_entry) {};
2845
2846 struct tu_cs cs;
2847 tu_cs_begin_sub_stream(device, draw_state, size, &cs);
2848
2849 for (unsigned i = 0; i < link->image_mapping.num_ibo; i++) {
2850 unsigned idx = link->image_mapping.ibo_to_image[i];
2851
2852 if (idx & IBO_SSBO) {
2853 idx &= ~IBO_SSBO;
2854
2855 uint64_t va = buffer_ptr(descriptors_state, &link->ssbo_map, idx);
2856 /* We don't expose robustBufferAccess, so leave the size unlimited. */
2857 uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
2858
2859 tu_cs_emit(&cs, A6XX_IBO_0_FMT(TFMT6_32_UINT));
2860 tu_cs_emit(&cs,
2861 A6XX_IBO_1_WIDTH(sz & MASK(15)) |
2862 A6XX_IBO_1_HEIGHT(sz >> 15));
2863 tu_cs_emit(&cs,
2864 A6XX_IBO_2_UNK4 |
2865 A6XX_IBO_2_UNK31 |
2866 A6XX_IBO_2_TYPE(A6XX_TEX_1D));
2867 tu_cs_emit(&cs, 0);
2868 tu_cs_emit_qw(&cs, va);
2869 for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2870 tu_cs_emit(&cs, 0);
2871 } else {
2872 tu_finishme("Emit images");
2873 }
2874 }
2875
2876 struct tu_cs_entry entry = tu_cs_end_sub_stream(draw_state, &cs);
2877
2878 uint64_t ibo_addr = entry.bo->iova + entry.offset;
2879
2880 tu_cs_begin_sub_stream(device, draw_state, 64, &cs);
2881
2882 /* emit texture state: */
2883 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6, 3);
2884 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2885 CP_LOAD_STATE6_0_STATE_TYPE(type == MESA_SHADER_COMPUTE ?
2886 ST6_IBO : ST6_SHADER) |
2887 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2888 CP_LOAD_STATE6_0_STATE_BLOCK(type == MESA_SHADER_COMPUTE ?
2889 SB6_CS_SHADER : SB6_IBO) |
2890 CP_LOAD_STATE6_0_NUM_UNIT(link->image_mapping.num_ibo));
2891 tu_cs_emit_qw(&cs, ibo_addr); /* SRC_ADDR_LO/HI */
2892
2893 tu_cs_emit_pkt4(&cs,
2894 type == MESA_SHADER_COMPUTE ?
2895 REG_A6XX_SP_IBO_LO : REG_A6XX_SP_CS_IBO_LO, 2);
2896 tu_cs_emit_qw(&cs, ibo_addr); /* SRC_ADDR_LO/HI */
2897
2898 return tu_cs_end_sub_stream(draw_state, &cs);
2899 }
2900
2901 struct PACKED bcolor_entry {
2902 uint32_t fp32[4];
2903 uint16_t ui16[4];
2904 int16_t si16[4];
2905 uint16_t fp16[4];
2906 uint16_t rgb565;
2907 uint16_t rgb5a1;
2908 uint16_t rgba4;
2909 uint8_t __pad0[2];
2910 uint8_t ui8[4];
2911 int8_t si8[4];
2912 uint32_t rgb10a2;
2913 uint32_t z24; /* also s8? */
2914 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
2915 uint8_t __pad1[56];
2916 } border_color[] = {
2917 [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = {},
2918 [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK] = {},
2919 [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = {
2920 .fp32[3] = 0x3f800000,
2921 .ui16[3] = 0xffff,
2922 .si16[3] = 0x7fff,
2923 .fp16[3] = 0x3c00,
2924 .rgb5a1 = 0x8000,
2925 .rgba4 = 0xf000,
2926 .ui8[3] = 0xff,
2927 .si8[3] = 0x7f,
2928 .rgb10a2 = 0xc0000000,
2929 .srgb[3] = 0x3c00,
2930 },
2931 [VK_BORDER_COLOR_INT_OPAQUE_BLACK] = {
2932 .fp32[3] = 1,
2933 .fp16[3] = 1,
2934 },
2935 [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] = {
2936 .fp32[0 ... 3] = 0x3f800000,
2937 .ui16[0 ... 3] = 0xffff,
2938 .si16[0 ... 3] = 0x7fff,
2939 .fp16[0 ... 3] = 0x3c00,
2940 .rgb565 = 0xffff,
2941 .rgb5a1 = 0xffff,
2942 .rgba4 = 0xffff,
2943 .ui8[0 ... 3] = 0xff,
2944 .si8[0 ... 3] = 0x7f,
2945 .rgb10a2 = 0xffffffff,
2946 .z24 = 0xffffff,
2947 .srgb[0 ... 3] = 0x3c00,
2948 },
2949 [VK_BORDER_COLOR_INT_OPAQUE_WHITE] = {
2950 .fp32[0 ... 3] = 1,
2951 .fp16[0 ... 3] = 1,
2952 },
2953 };
2954
2955 static VkResult
2956 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
2957 struct tu_cs *cs)
2958 {
2959 STATIC_ASSERT(sizeof(struct bcolor_entry) == 128);
2960
2961 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2962 struct tu_descriptor_state *descriptors_state =
2963 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2964 const struct tu_descriptor_map *vs_sampler =
2965 &pipeline->program.link[MESA_SHADER_VERTEX].sampler_map;
2966 const struct tu_descriptor_map *fs_sampler =
2967 &pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map;
2968 struct ts_cs_memory ptr;
2969
2970 VkResult result = tu_cs_alloc(cmd->device, &cmd->sub_cs,
2971 vs_sampler->num + fs_sampler->num, 128 / 4,
2972 &ptr);
2973 if (result != VK_SUCCESS)
2974 return result;
2975
2976 for (unsigned i = 0; i < vs_sampler->num; i++) {
2977 struct tu_sampler *sampler = sampler_ptr(descriptors_state, vs_sampler, i);
2978 memcpy(ptr.map, &border_color[sampler->border], 128);
2979 ptr.map += 128 / 4;
2980 }
2981
2982 for (unsigned i = 0; i < fs_sampler->num; i++) {
2983 struct tu_sampler *sampler = sampler_ptr(descriptors_state, fs_sampler, i);
2984 memcpy(ptr.map, &border_color[sampler->border], 128);
2985 ptr.map += 128 / 4;
2986 }
2987
2988 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
2989 tu_cs_emit_qw(cs, ptr.iova);
2990 return VK_SUCCESS;
2991 }
2992
2993 static VkResult
2994 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2995 struct tu_cs *cs,
2996 const struct tu_draw_info *draw)
2997 {
2998 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2999 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
3000 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
3001 uint32_t draw_state_group_count = 0;
3002
3003 struct tu_descriptor_state *descriptors_state =
3004 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3005
3006 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3007 if (result != VK_SUCCESS)
3008 return result;
3009
3010 /* TODO lrz */
3011
3012 uint32_t pc_primitive_cntl = 0;
3013 if (pipeline->ia.primitive_restart && draw->indexed)
3014 pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
3015
3016 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
3017 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
3018 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
3019
3020 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
3021 tu_cs_emit(cs, pc_primitive_cntl);
3022
3023 if (cmd->state.dirty &
3024 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
3025 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
3026 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
3027 dynamic->line_width);
3028 }
3029
3030 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
3031 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
3032 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
3033 dynamic->stencil_compare_mask.back);
3034 }
3035
3036 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
3037 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
3038 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
3039 dynamic->stencil_write_mask.back);
3040 }
3041
3042 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
3043 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
3044 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
3045 dynamic->stencil_reference.back);
3046 }
3047
3048 if (cmd->state.dirty &
3049 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
3050 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
3051 const uint32_t binding = pipeline->vi.bindings[i];
3052 const uint32_t stride = pipeline->vi.strides[i];
3053 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
3054 const VkDeviceSize offset = buf->bo_offset +
3055 cmd->state.vb.offsets[binding] +
3056 pipeline->vi.offsets[i];
3057 const VkDeviceSize size =
3058 offset < buf->bo->size ? buf->bo->size - offset : 0;
3059
3060 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
3061 tu_cs_emit_qw(cs, buf->bo->iova + offset);
3062 tu_cs_emit(cs, size);
3063 tu_cs_emit(cs, stride);
3064 }
3065 }
3066
3067 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
3068 draw_state_groups[draw_state_group_count++] =
3069 (struct tu_draw_state_group) {
3070 .id = TU_DRAW_STATE_PROGRAM,
3071 .enable_mask = 0x6,
3072 .ib = pipeline->program.state_ib,
3073 };
3074 draw_state_groups[draw_state_group_count++] =
3075 (struct tu_draw_state_group) {
3076 .id = TU_DRAW_STATE_PROGRAM_BINNING,
3077 .enable_mask = 0x1,
3078 .ib = pipeline->program.binning_state_ib,
3079 };
3080 draw_state_groups[draw_state_group_count++] =
3081 (struct tu_draw_state_group) {
3082 .id = TU_DRAW_STATE_VI,
3083 .enable_mask = 0x6,
3084 .ib = pipeline->vi.state_ib,
3085 };
3086 draw_state_groups[draw_state_group_count++] =
3087 (struct tu_draw_state_group) {
3088 .id = TU_DRAW_STATE_VI_BINNING,
3089 .enable_mask = 0x1,
3090 .ib = pipeline->vi.binning_state_ib,
3091 };
3092 draw_state_groups[draw_state_group_count++] =
3093 (struct tu_draw_state_group) {
3094 .id = TU_DRAW_STATE_VP,
3095 .enable_mask = 0x7,
3096 .ib = pipeline->vp.state_ib,
3097 };
3098 draw_state_groups[draw_state_group_count++] =
3099 (struct tu_draw_state_group) {
3100 .id = TU_DRAW_STATE_RAST,
3101 .enable_mask = 0x7,
3102 .ib = pipeline->rast.state_ib,
3103 };
3104 draw_state_groups[draw_state_group_count++] =
3105 (struct tu_draw_state_group) {
3106 .id = TU_DRAW_STATE_DS,
3107 .enable_mask = 0x7,
3108 .ib = pipeline->ds.state_ib,
3109 };
3110 draw_state_groups[draw_state_group_count++] =
3111 (struct tu_draw_state_group) {
3112 .id = TU_DRAW_STATE_BLEND,
3113 .enable_mask = 0x7,
3114 .ib = pipeline->blend.state_ib,
3115 };
3116 }
3117
3118 if (cmd->state.dirty &
3119 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
3120 draw_state_groups[draw_state_group_count++] =
3121 (struct tu_draw_state_group) {
3122 .id = TU_DRAW_STATE_VS_CONST,
3123 .enable_mask = 0x7,
3124 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
3125 };
3126 draw_state_groups[draw_state_group_count++] =
3127 (struct tu_draw_state_group) {
3128 .id = TU_DRAW_STATE_FS_CONST,
3129 .enable_mask = 0x6,
3130 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
3131 };
3132 }
3133
3134 if (cmd->state.dirty &
3135 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
3136 bool needs_border = false;
3137 struct tu_cs_entry vs_tex, fs_tex;
3138
3139 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3140 MESA_SHADER_VERTEX, &vs_tex, &needs_border);
3141 if (result != VK_SUCCESS)
3142 return result;
3143
3144 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3145 MESA_SHADER_FRAGMENT, &fs_tex, &needs_border);
3146 if (result != VK_SUCCESS)
3147 return result;
3148
3149 draw_state_groups[draw_state_group_count++] =
3150 (struct tu_draw_state_group) {
3151 .id = TU_DRAW_STATE_VS_TEX,
3152 .enable_mask = 0x7,
3153 .ib = vs_tex,
3154 };
3155 draw_state_groups[draw_state_group_count++] =
3156 (struct tu_draw_state_group) {
3157 .id = TU_DRAW_STATE_FS_TEX,
3158 .enable_mask = 0x6,
3159 .ib = fs_tex,
3160 };
3161 draw_state_groups[draw_state_group_count++] =
3162 (struct tu_draw_state_group) {
3163 .id = TU_DRAW_STATE_FS_IBO,
3164 .enable_mask = 0x6,
3165 .ib = tu6_emit_ibo(cmd->device, &cmd->sub_cs, pipeline,
3166 descriptors_state, MESA_SHADER_FRAGMENT)
3167 };
3168
3169 if (needs_border) {
3170 result = tu6_emit_border_color(cmd, cs);
3171 if (result != VK_SUCCESS)
3172 return result;
3173 }
3174 }
3175
3176 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3177 for (uint32_t i = 0; i < draw_state_group_count; i++) {
3178 const struct tu_draw_state_group *group = &draw_state_groups[i];
3179
3180 uint32_t cp_set_draw_state =
3181 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3182 CP_SET_DRAW_STATE__0_ENABLE_MASK(group->enable_mask) |
3183 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3184 uint64_t iova;
3185 if (group->ib.size) {
3186 iova = group->ib.bo->iova + group->ib.offset;
3187 } else {
3188 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3189 iova = 0;
3190 }
3191
3192 tu_cs_emit(cs, cp_set_draw_state);
3193 tu_cs_emit_qw(cs, iova);
3194 }
3195
3196 tu_cs_sanity_check(cs);
3197
3198 /* track BOs */
3199 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3200 for (uint32_t i = 0; i < MAX_VBS; i++) {
3201 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3202 if (buf)
3203 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3204 }
3205 }
3206 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3207 unsigned i;
3208 for_each_bit(i, descriptors_state->valid) {
3209 struct tu_descriptor_set *set = descriptors_state->sets[i];
3210 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3211 if (set->descriptors[j]) {
3212 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3213 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3214 }
3215 }
3216 }
3217
3218 /* Fragment shader state overwrites compute shader state, so flag the
3219 * compute pipeline for re-emit.
3220 */
3221 cmd->state.dirty = TU_CMD_DIRTY_COMPUTE_PIPELINE;
3222 return VK_SUCCESS;
3223 }
3224
3225 static void
3226 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3227 struct tu_cs *cs,
3228 const struct tu_draw_info *draw)
3229 {
3230
3231 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3232
3233 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
3234 tu_cs_emit(cs, draw->vertex_offset);
3235 tu_cs_emit(cs, draw->first_instance);
3236
3237 /* TODO hw binning */
3238 if (draw->indexed) {
3239 const enum a4xx_index_size index_size =
3240 tu6_index_size(cmd->state.index_type);
3241 const uint32_t index_bytes =
3242 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3243 const struct tu_buffer *buf = cmd->state.index_buffer;
3244 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3245 index_bytes * draw->first_index;
3246 const uint32_t size = index_bytes * draw->count;
3247
3248 const uint32_t cp_draw_indx =
3249 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3250 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3251 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3252 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3253
3254 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3255 tu_cs_emit(cs, cp_draw_indx);
3256 tu_cs_emit(cs, draw->instance_count);
3257 tu_cs_emit(cs, draw->count);
3258 tu_cs_emit(cs, 0x0); /* XXX */
3259 tu_cs_emit_qw(cs, buf->bo->iova + offset);
3260 tu_cs_emit(cs, size);
3261 } else {
3262 const uint32_t cp_draw_indx =
3263 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3264 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3265 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3266
3267 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3268 tu_cs_emit(cs, cp_draw_indx);
3269 tu_cs_emit(cs, draw->instance_count);
3270 tu_cs_emit(cs, draw->count);
3271 }
3272 }
3273
3274 static void
3275 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3276 {
3277 struct tu_cs *cs = &cmd->draw_cs;
3278 VkResult result;
3279
3280 result = tu6_bind_draw_states(cmd, cs, draw);
3281 if (result != VK_SUCCESS) {
3282 cmd->record_result = result;
3283 return;
3284 }
3285
3286 result = tu_cs_reserve_space(cmd->device, cs, 32);
3287 if (result != VK_SUCCESS) {
3288 cmd->record_result = result;
3289 return;
3290 }
3291
3292 if (draw->indirect) {
3293 tu_finishme("indirect draw");
3294 return;
3295 }
3296
3297 /* TODO tu6_emit_marker should pick different regs depending on cs */
3298
3299 tu6_emit_marker(cmd, cs);
3300 tu6_emit_draw_direct(cmd, cs, draw);
3301 tu6_emit_marker(cmd, cs);
3302
3303 cmd->wait_for_idle = true;
3304
3305 tu_cs_sanity_check(cs);
3306 }
3307
3308 void
3309 tu_CmdDraw(VkCommandBuffer commandBuffer,
3310 uint32_t vertexCount,
3311 uint32_t instanceCount,
3312 uint32_t firstVertex,
3313 uint32_t firstInstance)
3314 {
3315 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3316 struct tu_draw_info info = {};
3317
3318 info.count = vertexCount;
3319 info.instance_count = instanceCount;
3320 info.first_instance = firstInstance;
3321 info.vertex_offset = firstVertex;
3322
3323 tu_draw(cmd_buffer, &info);
3324 }
3325
3326 void
3327 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3328 uint32_t indexCount,
3329 uint32_t instanceCount,
3330 uint32_t firstIndex,
3331 int32_t vertexOffset,
3332 uint32_t firstInstance)
3333 {
3334 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3335 struct tu_draw_info info = {};
3336
3337 info.indexed = true;
3338 info.count = indexCount;
3339 info.instance_count = instanceCount;
3340 info.first_index = firstIndex;
3341 info.vertex_offset = vertexOffset;
3342 info.first_instance = firstInstance;
3343
3344 tu_draw(cmd_buffer, &info);
3345 }
3346
3347 void
3348 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3349 VkBuffer _buffer,
3350 VkDeviceSize offset,
3351 uint32_t drawCount,
3352 uint32_t stride)
3353 {
3354 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3355 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3356 struct tu_draw_info info = {};
3357
3358 info.count = drawCount;
3359 info.indirect = buffer;
3360 info.indirect_offset = offset;
3361 info.stride = stride;
3362
3363 tu_draw(cmd_buffer, &info);
3364 }
3365
3366 void
3367 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3368 VkBuffer _buffer,
3369 VkDeviceSize offset,
3370 uint32_t drawCount,
3371 uint32_t stride)
3372 {
3373 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3374 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3375 struct tu_draw_info info = {};
3376
3377 info.indexed = true;
3378 info.count = drawCount;
3379 info.indirect = buffer;
3380 info.indirect_offset = offset;
3381 info.stride = stride;
3382
3383 tu_draw(cmd_buffer, &info);
3384 }
3385
3386 struct tu_dispatch_info
3387 {
3388 /**
3389 * Determine the layout of the grid (in block units) to be used.
3390 */
3391 uint32_t blocks[3];
3392
3393 /**
3394 * A starting offset for the grid. If unaligned is set, the offset
3395 * must still be aligned.
3396 */
3397 uint32_t offsets[3];
3398 /**
3399 * Whether it's an unaligned compute dispatch.
3400 */
3401 bool unaligned;
3402
3403 /**
3404 * Indirect compute parameters resource.
3405 */
3406 struct tu_buffer *indirect;
3407 uint64_t indirect_offset;
3408 };
3409
3410 static void
3411 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3412 const struct tu_dispatch_info *info)
3413 {
3414 gl_shader_stage type = MESA_SHADER_COMPUTE;
3415 const struct tu_program_descriptor_linkage *link =
3416 &pipeline->program.link[type];
3417 const struct ir3_const_state *const_state = &link->const_state;
3418 uint32_t offset_dwords = const_state->offsets.driver_param;
3419
3420 if (link->constlen <= offset_dwords)
3421 return;
3422
3423 if (!info->indirect) {
3424 uint32_t driver_params[] = {
3425 info->blocks[0],
3426 info->blocks[1],
3427 info->blocks[2],
3428 pipeline->compute.local_size[0],
3429 pipeline->compute.local_size[1],
3430 pipeline->compute.local_size[2],
3431 };
3432 uint32_t num_consts = MIN2(const_state->num_driver_params,
3433 link->constlen - offset_dwords);
3434 uint32_t align_size = align(num_consts, 4);
3435
3436 /* push constants */
3437 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + align_size);
3438 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset_dwords / 4) |
3439 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3440 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3441 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3442 CP_LOAD_STATE6_0_NUM_UNIT(align_size / 4));
3443 tu_cs_emit(cs, 0);
3444 tu_cs_emit(cs, 0);
3445 uint32_t i;
3446 for (i = 0; i < num_consts; i++)
3447 tu_cs_emit(cs, driver_params[i]);
3448 for (; i < align_size; i++)
3449 tu_cs_emit(cs, 0);
3450 } else {
3451 tu_finishme("Indirect driver params");
3452 }
3453 }
3454
3455 static void
3456 tu_dispatch(struct tu_cmd_buffer *cmd,
3457 const struct tu_dispatch_info *info)
3458 {
3459 struct tu_cs *cs = &cmd->cs;
3460 struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3461 struct tu_descriptor_state *descriptors_state =
3462 &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3463
3464 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3465 if (result != VK_SUCCESS) {
3466 cmd->record_result = result;
3467 return;
3468 }
3469
3470 if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3471 tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3472
3473 struct tu_cs_entry ib;
3474
3475 ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3476 if (ib.size)
3477 tu_cs_emit_ib(cs, &ib);
3478
3479 tu_emit_compute_driver_params(cs, pipeline, info);
3480
3481 bool needs_border;
3482 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3483 MESA_SHADER_COMPUTE, &ib, &needs_border);
3484 if (result != VK_SUCCESS) {
3485 cmd->record_result = result;
3486 return;
3487 }
3488
3489 if (ib.size)
3490 tu_cs_emit_ib(cs, &ib);
3491
3492 if (needs_border)
3493 tu_finishme("compute border color");
3494
3495 ib = tu6_emit_ibo(cmd->device, &cmd->sub_cs, pipeline,
3496 descriptors_state, MESA_SHADER_COMPUTE);
3497 if (ib.size)
3498 tu_cs_emit_ib(cs, &ib);
3499
3500 /* track BOs */
3501 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3502 unsigned i;
3503 for_each_bit(i, descriptors_state->valid) {
3504 struct tu_descriptor_set *set = descriptors_state->sets[i];
3505 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3506 if (set->descriptors[j]) {
3507 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3508 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3509 }
3510 }
3511 }
3512
3513 /* Compute shader state overwrites fragment shader state, so we flag the
3514 * graphics pipeline for re-emit.
3515 */
3516 cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
3517
3518 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3519 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x8));
3520
3521 const uint32_t *local_size = pipeline->compute.local_size;
3522 const uint32_t *num_groups = info->blocks;
3523 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_NDRANGE_0, 7);
3524 tu_cs_emit(cs,
3525 A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(3) |
3526 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
3527 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
3528 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
3529 tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size[0] * num_groups[0]));
3530 tu_cs_emit(cs, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
3531 tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size[1] * num_groups[1]));
3532 tu_cs_emit(cs, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
3533 tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size[2] * num_groups[2]));
3534 tu_cs_emit(cs, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
3535
3536 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X, 3);
3537 tu_cs_emit(cs, 1); /* HLSQ_CS_KERNEL_GROUP_X */
3538 tu_cs_emit(cs, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
3539 tu_cs_emit(cs, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
3540
3541 if (info->indirect) {
3542 uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3543
3544 tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3545 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3546
3547 tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3548 tu_cs_emit(cs, 0x00000000);
3549 tu_cs_emit_qw(cs, iova);
3550 tu_cs_emit(cs,
3551 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3552 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3553 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3554 } else {
3555 tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3556 tu_cs_emit(cs, 0x00000000);
3557 tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3558 tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3559 tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3560 }
3561
3562 tu_cs_emit_wfi(cs);
3563
3564 tu6_emit_cache_flush(cmd, cs);
3565 }
3566
3567 void
3568 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
3569 uint32_t base_x,
3570 uint32_t base_y,
3571 uint32_t base_z,
3572 uint32_t x,
3573 uint32_t y,
3574 uint32_t z)
3575 {
3576 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3577 struct tu_dispatch_info info = {};
3578
3579 info.blocks[0] = x;
3580 info.blocks[1] = y;
3581 info.blocks[2] = z;
3582
3583 info.offsets[0] = base_x;
3584 info.offsets[1] = base_y;
3585 info.offsets[2] = base_z;
3586 tu_dispatch(cmd_buffer, &info);
3587 }
3588
3589 void
3590 tu_CmdDispatch(VkCommandBuffer commandBuffer,
3591 uint32_t x,
3592 uint32_t y,
3593 uint32_t z)
3594 {
3595 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3596 }
3597
3598 void
3599 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
3600 VkBuffer _buffer,
3601 VkDeviceSize offset)
3602 {
3603 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3604 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3605 struct tu_dispatch_info info = {};
3606
3607 info.indirect = buffer;
3608 info.indirect_offset = offset;
3609
3610 tu_dispatch(cmd_buffer, &info);
3611 }
3612
3613 void
3614 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3615 {
3616 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3617
3618 tu_cs_end(&cmd_buffer->draw_cs);
3619
3620 tu_cmd_render_tiles(cmd_buffer);
3621
3622 /* discard draw_cs entries now that the tiles are rendered */
3623 tu_cs_discard_entries(&cmd_buffer->draw_cs);
3624 tu_cs_begin(&cmd_buffer->draw_cs);
3625
3626 cmd_buffer->state.pass = NULL;
3627 cmd_buffer->state.subpass = NULL;
3628 cmd_buffer->state.framebuffer = NULL;
3629 }
3630
3631 void
3632 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer,
3633 const VkSubpassEndInfoKHR *pSubpassEndInfo)
3634 {
3635 tu_CmdEndRenderPass(commandBuffer);
3636 }
3637
3638 struct tu_barrier_info
3639 {
3640 uint32_t eventCount;
3641 const VkEvent *pEvents;
3642 VkPipelineStageFlags srcStageMask;
3643 };
3644
3645 static void
3646 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
3647 uint32_t memoryBarrierCount,
3648 const VkMemoryBarrier *pMemoryBarriers,
3649 uint32_t bufferMemoryBarrierCount,
3650 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3651 uint32_t imageMemoryBarrierCount,
3652 const VkImageMemoryBarrier *pImageMemoryBarriers,
3653 const struct tu_barrier_info *info)
3654 {
3655 }
3656
3657 void
3658 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3659 VkPipelineStageFlags srcStageMask,
3660 VkPipelineStageFlags destStageMask,
3661 VkBool32 byRegion,
3662 uint32_t memoryBarrierCount,
3663 const VkMemoryBarrier *pMemoryBarriers,
3664 uint32_t bufferMemoryBarrierCount,
3665 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3666 uint32_t imageMemoryBarrierCount,
3667 const VkImageMemoryBarrier *pImageMemoryBarriers)
3668 {
3669 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3670 struct tu_barrier_info info;
3671
3672 info.eventCount = 0;
3673 info.pEvents = NULL;
3674 info.srcStageMask = srcStageMask;
3675
3676 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3677 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3678 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3679 }
3680
3681 static void
3682 write_event(struct tu_cmd_buffer *cmd_buffer,
3683 struct tu_event *event,
3684 VkPipelineStageFlags stageMask,
3685 unsigned value)
3686 {
3687 }
3688
3689 void
3690 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3691 VkEvent _event,
3692 VkPipelineStageFlags stageMask)
3693 {
3694 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3695 TU_FROM_HANDLE(tu_event, event, _event);
3696
3697 write_event(cmd_buffer, event, stageMask, 1);
3698 }
3699
3700 void
3701 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3702 VkEvent _event,
3703 VkPipelineStageFlags stageMask)
3704 {
3705 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3706 TU_FROM_HANDLE(tu_event, event, _event);
3707
3708 write_event(cmd_buffer, event, stageMask, 0);
3709 }
3710
3711 void
3712 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3713 uint32_t eventCount,
3714 const VkEvent *pEvents,
3715 VkPipelineStageFlags srcStageMask,
3716 VkPipelineStageFlags dstStageMask,
3717 uint32_t memoryBarrierCount,
3718 const VkMemoryBarrier *pMemoryBarriers,
3719 uint32_t bufferMemoryBarrierCount,
3720 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3721 uint32_t imageMemoryBarrierCount,
3722 const VkImageMemoryBarrier *pImageMemoryBarriers)
3723 {
3724 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3725 struct tu_barrier_info info;
3726
3727 info.eventCount = eventCount;
3728 info.pEvents = pEvents;
3729 info.srcStageMask = 0;
3730
3731 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3732 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3733 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3734 }
3735
3736 void
3737 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3738 {
3739 /* No-op */
3740 }