1c32e60000ac1b34191149edf1f89cee2764da21
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #include "vk_format.h"
81
82 #define MAX_VBS 32
83 #define MAX_VERTEX_ATTRIBS 32
84 #define MAX_RTS 8
85 #define MAX_VSC_PIPES 32
86 #define MAX_VIEWPORTS 1
87 #define MAX_SCISSORS 16
88 #define MAX_DISCARD_RECTANGLES 4
89 #define MAX_PUSH_CONSTANTS_SIZE 128
90 #define MAX_PUSH_DESCRIPTORS 32
91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
93 #define MAX_DYNAMIC_BUFFERS \
94 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
95 #define MAX_SAMPLES_LOG2 4
96 #define NUM_META_FS_KEYS 13
97 #define TU_MAX_DRM_DEVICES 8
98 #define MAX_VIEWS 8
99 #define MAX_BIND_POINTS 2 /* compute + graphics */
100 /* The Qualcomm driver exposes 0x20000058 */
101 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
102 /* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
103 * expose the same maximum range.
104 * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
105 * range might be higher.
106 */
107 #define MAX_UNIFORM_BUFFER_RANGE 0x10000
108
109 #define NUM_DEPTH_CLEAR_PIPELINES 3
110
111 /*
112 * This is the point we switch from using CP to compute shader
113 * for certain buffer operations.
114 */
115 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
116
117 #define A6XX_TEX_CONST_DWORDS 16
118 #define A6XX_TEX_SAMP_DWORDS 4
119
120 enum tu_mem_heap
121 {
122 TU_MEM_HEAP_VRAM,
123 TU_MEM_HEAP_VRAM_CPU_ACCESS,
124 TU_MEM_HEAP_GTT,
125 TU_MEM_HEAP_COUNT
126 };
127
128 enum tu_mem_type
129 {
130 TU_MEM_TYPE_VRAM,
131 TU_MEM_TYPE_GTT_WRITE_COMBINE,
132 TU_MEM_TYPE_VRAM_CPU_ACCESS,
133 TU_MEM_TYPE_GTT_CACHED,
134 TU_MEM_TYPE_COUNT
135 };
136
137 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
138
139 static inline uint32_t
140 align_u32(uint32_t v, uint32_t a)
141 {
142 assert(a != 0 && a == (a & -a));
143 return (v + a - 1) & ~(a - 1);
144 }
145
146 static inline uint32_t
147 align_u32_npot(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a * a;
150 }
151
152 static inline uint64_t
153 align_u64(uint64_t v, uint64_t a)
154 {
155 assert(a != 0 && a == (a & -a));
156 return (v + a - 1) & ~(a - 1);
157 }
158
159 static inline int32_t
160 align_i32(int32_t v, int32_t a)
161 {
162 assert(a != 0 && a == (a & -a));
163 return (v + a - 1) & ~(a - 1);
164 }
165
166 /** Alignment must be a power of 2. */
167 static inline bool
168 tu_is_aligned(uintmax_t n, uintmax_t a)
169 {
170 assert(a == (a & -a));
171 return (n & (a - 1)) == 0;
172 }
173
174 static inline uint32_t
175 round_up_u32(uint32_t v, uint32_t a)
176 {
177 return (v + a - 1) / a;
178 }
179
180 static inline uint64_t
181 round_up_u64(uint64_t v, uint64_t a)
182 {
183 return (v + a - 1) / a;
184 }
185
186 static inline uint32_t
187 tu_minify(uint32_t n, uint32_t levels)
188 {
189 if (unlikely(n == 0))
190 return 0;
191 else
192 return MAX2(n >> levels, 1);
193 }
194 static inline float
195 tu_clamp_f(float f, float min, float max)
196 {
197 assert(min < max);
198
199 if (f > max)
200 return max;
201 else if (f < min)
202 return min;
203 else
204 return f;
205 }
206
207 static inline bool
208 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
209 {
210 if (*inout_mask & clear_mask) {
211 *inout_mask &= ~clear_mask;
212 return true;
213 } else {
214 return false;
215 }
216 }
217
218 #define for_each_bit(b, dword) \
219 for (uint32_t __dword = (dword); \
220 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
221
222 #define typed_memcpy(dest, src, count) \
223 ({ \
224 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
225 memcpy((dest), (src), (count) * sizeof(*(src))); \
226 })
227
228 #define COND(bool, val) ((bool) ? (val) : 0)
229
230 /* Whenever we generate an error, pass it through this function. Useful for
231 * debugging, where we can break on it. Only call at error site, not when
232 * propagating errors. Might be useful to plug in a stack trace here.
233 */
234
235 struct tu_instance;
236
237 VkResult
238 __vk_errorf(struct tu_instance *instance,
239 VkResult error,
240 const char *file,
241 int line,
242 const char *format,
243 ...);
244
245 #define vk_error(instance, error) \
246 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
247 #define vk_errorf(instance, error, format, ...) \
248 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
249
250 void
251 __tu_finishme(const char *file, int line, const char *format, ...)
252 tu_printflike(3, 4);
253 void
254 tu_loge(const char *format, ...) tu_printflike(1, 2);
255 void
256 tu_loge_v(const char *format, va_list va);
257 void
258 tu_logi(const char *format, ...) tu_printflike(1, 2);
259 void
260 tu_logi_v(const char *format, va_list va);
261
262 /**
263 * Print a FINISHME message, including its source location.
264 */
265 #define tu_finishme(format, ...) \
266 do { \
267 static bool reported = false; \
268 if (!reported) { \
269 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
270 reported = true; \
271 } \
272 } while (0)
273
274 /* A non-fatal assert. Useful for debugging. */
275 #ifdef DEBUG
276 #define tu_assert(x) \
277 ({ \
278 if (unlikely(!(x))) \
279 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
280 })
281 #else
282 #define tu_assert(x)
283 #endif
284
285 /* Suppress -Wunused in stub functions */
286 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
287 static inline void
288 __tu_use_args(int ignore, ...)
289 {
290 }
291
292 #define tu_stub() \
293 do { \
294 tu_finishme("stub %s", __func__); \
295 } while (0)
296
297 void *
298 tu_lookup_entrypoint_unchecked(const char *name);
299 void *
300 tu_lookup_entrypoint_checked(
301 const char *name,
302 uint32_t core_version,
303 const struct tu_instance_extension_table *instance,
304 const struct tu_device_extension_table *device);
305
306 struct tu_physical_device
307 {
308 VK_LOADER_DATA _loader_data;
309
310 struct tu_instance *instance;
311
312 char path[20];
313 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
314 uint8_t driver_uuid[VK_UUID_SIZE];
315 uint8_t device_uuid[VK_UUID_SIZE];
316 uint8_t cache_uuid[VK_UUID_SIZE];
317
318 struct wsi_device wsi_device;
319
320 int local_fd;
321 int master_fd;
322
323 unsigned gpu_id;
324 uint32_t gmem_size;
325 uint64_t gmem_base;
326 uint32_t ccu_offset_gmem;
327 uint32_t ccu_offset_bypass;
328 /* alignment for size of tiles */
329 uint32_t tile_align_w;
330 #define TILE_ALIGN_H 16
331 /* gmem store/load granularity */
332 #define GMEM_ALIGN_W 16
333 #define GMEM_ALIGN_H 4
334
335 struct {
336 uint32_t PC_UNKNOWN_9805;
337 uint32_t SP_UNKNOWN_A0F8;
338 } magic;
339
340 /* This is the drivers on-disk cache used as a fallback as opposed to
341 * the pipeline cache defined by apps.
342 */
343 struct disk_cache *disk_cache;
344
345 struct tu_device_extension_table supported_extensions;
346 };
347
348 enum tu_debug_flags
349 {
350 TU_DEBUG_STARTUP = 1 << 0,
351 TU_DEBUG_NIR = 1 << 1,
352 TU_DEBUG_IR3 = 1 << 2,
353 TU_DEBUG_NOBIN = 1 << 3,
354 TU_DEBUG_SYSMEM = 1 << 4,
355 TU_DEBUG_FORCEBIN = 1 << 5,
356 };
357
358 struct tu_instance
359 {
360 VK_LOADER_DATA _loader_data;
361
362 VkAllocationCallbacks alloc;
363
364 uint32_t api_version;
365 int physical_device_count;
366 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
367
368 enum tu_debug_flags debug_flags;
369
370 struct vk_debug_report_instance debug_report_callbacks;
371
372 struct tu_instance_extension_table enabled_extensions;
373 };
374
375 VkResult
376 tu_wsi_init(struct tu_physical_device *physical_device);
377 void
378 tu_wsi_finish(struct tu_physical_device *physical_device);
379
380 bool
381 tu_instance_extension_supported(const char *name);
382 uint32_t
383 tu_physical_device_api_version(struct tu_physical_device *dev);
384 bool
385 tu_physical_device_extension_supported(struct tu_physical_device *dev,
386 const char *name);
387
388 struct cache_entry;
389
390 struct tu_pipeline_cache
391 {
392 struct tu_device *device;
393 pthread_mutex_t mutex;
394
395 uint32_t total_size;
396 uint32_t table_size;
397 uint32_t kernel_count;
398 struct cache_entry **hash_table;
399 bool modified;
400
401 VkAllocationCallbacks alloc;
402 };
403
404 struct tu_pipeline_key
405 {
406 };
407
408 void
409 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
410 struct tu_device *device);
411 void
412 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
413 void
414 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
415 const void *data,
416 size_t size);
417
418 struct tu_shader_variant;
419
420 bool
421 tu_create_shader_variants_from_pipeline_cache(
422 struct tu_device *device,
423 struct tu_pipeline_cache *cache,
424 const unsigned char *sha1,
425 struct tu_shader_variant **variants);
426
427 void
428 tu_pipeline_cache_insert_shaders(struct tu_device *device,
429 struct tu_pipeline_cache *cache,
430 const unsigned char *sha1,
431 struct tu_shader_variant **variants,
432 const void *const *codes,
433 const unsigned *code_sizes);
434
435 struct tu_meta_state
436 {
437 VkAllocationCallbacks alloc;
438
439 struct tu_pipeline_cache cache;
440 };
441
442 /* queue types */
443 #define TU_QUEUE_GENERAL 0
444
445 #define TU_MAX_QUEUE_FAMILIES 1
446
447 struct tu_fence
448 {
449 struct wsi_fence *fence_wsi;
450 bool signaled;
451 int fd;
452 };
453
454 void
455 tu_fence_init(struct tu_fence *fence, bool signaled);
456 void
457 tu_fence_finish(struct tu_fence *fence);
458 void
459 tu_fence_update_fd(struct tu_fence *fence, int fd);
460 void
461 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
462 void
463 tu_fence_signal(struct tu_fence *fence);
464 void
465 tu_fence_wait_idle(struct tu_fence *fence);
466
467 struct tu_queue
468 {
469 VK_LOADER_DATA _loader_data;
470 struct tu_device *device;
471 uint32_t queue_family_index;
472 int queue_idx;
473 VkDeviceQueueCreateFlags flags;
474
475 uint32_t msm_queue_id;
476 struct tu_fence submit_fence;
477 };
478
479 struct tu_bo
480 {
481 uint32_t gem_handle;
482 uint64_t size;
483 uint64_t iova;
484 void *map;
485 };
486
487 struct tu_device
488 {
489 VK_LOADER_DATA _loader_data;
490
491 VkAllocationCallbacks alloc;
492
493 struct tu_instance *instance;
494
495 struct tu_meta_state meta_state;
496
497 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
498 int queue_count[TU_MAX_QUEUE_FAMILIES];
499
500 struct tu_physical_device *physical_device;
501
502 struct ir3_compiler *compiler;
503
504 /* Backup in-memory cache to be used if the app doesn't provide one */
505 struct tu_pipeline_cache *mem_cache;
506
507 struct tu_bo vsc_draw_strm;
508 struct tu_bo vsc_prim_strm;
509 uint32_t vsc_draw_strm_pitch;
510 uint32_t vsc_prim_strm_pitch;
511
512 #define MIN_SCRATCH_BO_SIZE_LOG2 12 /* A page */
513
514 /* Currently the kernel driver uses a 32-bit GPU address space, but it
515 * should be impossible to go beyond 48 bits.
516 */
517 struct {
518 struct tu_bo bo;
519 mtx_t construct_mtx;
520 bool initialized;
521 } scratch_bos[48 - MIN_SCRATCH_BO_SIZE_LOG2];
522
523 struct tu_bo border_color;
524
525 struct list_head shader_slabs;
526 mtx_t shader_slab_mutex;
527
528 struct tu_device_extension_table enabled_extensions;
529 };
530
531 VkResult
532 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
533 VkResult
534 tu_bo_init_dmabuf(struct tu_device *dev,
535 struct tu_bo *bo,
536 uint64_t size,
537 int fd);
538 int
539 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
540 void
541 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
542 VkResult
543 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
544
545 /* Get a scratch bo for use inside a command buffer. This will always return
546 * the same bo given the same size or similar sizes, so only one scratch bo
547 * can be used at the same time. It's meant for short-lived things where we
548 * need to write to some piece of memory, read from it, and then immediately
549 * discard it.
550 */
551 VkResult
552 tu_get_scratch_bo(struct tu_device *dev, uint64_t size, struct tu_bo **bo);
553
554 struct tu_cs_entry
555 {
556 /* No ownership */
557 const struct tu_bo *bo;
558
559 uint32_t size;
560 uint32_t offset;
561 };
562
563 struct ts_cs_memory {
564 uint32_t *map;
565 uint64_t iova;
566 };
567
568 enum tu_cs_mode
569 {
570
571 /*
572 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
573 * is full. tu_cs_begin must be called before command packet emission and
574 * tu_cs_end must be called after.
575 *
576 * This mode may create multiple entries internally. The entries must be
577 * submitted together.
578 */
579 TU_CS_MODE_GROW,
580
581 /*
582 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
583 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
584 * effect on it.
585 *
586 * This mode does not create any entry or any BO.
587 */
588 TU_CS_MODE_EXTERNAL,
589
590 /*
591 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
592 * command packet emission. tu_cs_begin_sub_stream must be called to get a
593 * sub-stream to emit comamnd packets to. When done with the sub-stream,
594 * tu_cs_end_sub_stream must be called.
595 *
596 * This mode does not create any entry internally.
597 */
598 TU_CS_MODE_SUB_STREAM,
599 };
600
601 struct tu_cs
602 {
603 uint32_t *start;
604 uint32_t *cur;
605 uint32_t *reserved_end;
606 uint32_t *end;
607
608 struct tu_device *device;
609 enum tu_cs_mode mode;
610 uint32_t next_bo_size;
611
612 struct tu_cs_entry *entries;
613 uint32_t entry_count;
614 uint32_t entry_capacity;
615
616 struct tu_bo **bos;
617 uint32_t bo_count;
618 uint32_t bo_capacity;
619
620 /* state for cond_exec_start/cond_exec_end */
621 uint32_t cond_flags;
622 uint32_t *cond_dwords;
623 };
624
625 struct tu_device_memory
626 {
627 struct tu_bo bo;
628 VkDeviceSize size;
629
630 /* for dedicated allocations */
631 struct tu_image *image;
632 struct tu_buffer *buffer;
633
634 uint32_t type_index;
635 void *map;
636 void *user_ptr;
637 };
638
639 struct tu_descriptor_range
640 {
641 uint64_t va;
642 uint32_t size;
643 };
644
645 struct tu_descriptor_set
646 {
647 const struct tu_descriptor_set_layout *layout;
648 struct tu_descriptor_pool *pool;
649 uint32_t size;
650
651 uint64_t va;
652 uint32_t *mapped_ptr;
653
654 uint32_t *dynamic_descriptors;
655
656 struct tu_bo *buffers[0];
657 };
658
659 struct tu_push_descriptor_set
660 {
661 struct tu_descriptor_set set;
662 uint32_t capacity;
663 };
664
665 struct tu_descriptor_pool_entry
666 {
667 uint32_t offset;
668 uint32_t size;
669 struct tu_descriptor_set *set;
670 };
671
672 struct tu_descriptor_pool
673 {
674 struct tu_bo bo;
675 uint64_t current_offset;
676 uint64_t size;
677
678 uint8_t *host_memory_base;
679 uint8_t *host_memory_ptr;
680 uint8_t *host_memory_end;
681
682 uint32_t entry_count;
683 uint32_t max_entry_count;
684 struct tu_descriptor_pool_entry entries[0];
685 };
686
687 struct tu_descriptor_update_template_entry
688 {
689 VkDescriptorType descriptor_type;
690
691 /* The number of descriptors to update */
692 uint32_t descriptor_count;
693
694 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
695 */
696 uint32_t dst_offset;
697
698 /* In dwords. Not valid/used for dynamic descriptors */
699 uint32_t dst_stride;
700
701 uint32_t buffer_offset;
702
703 /* Only valid for combined image samplers and samplers */
704 uint16_t has_sampler;
705
706 /* In bytes */
707 size_t src_offset;
708 size_t src_stride;
709
710 /* For push descriptors */
711 const uint32_t *immutable_samplers;
712 };
713
714 struct tu_descriptor_update_template
715 {
716 uint32_t entry_count;
717 struct tu_descriptor_update_template_entry entry[0];
718 };
719
720 struct tu_buffer
721 {
722 VkDeviceSize size;
723
724 VkBufferUsageFlags usage;
725 VkBufferCreateFlags flags;
726
727 struct tu_bo *bo;
728 VkDeviceSize bo_offset;
729 };
730
731 static inline uint64_t
732 tu_buffer_iova(struct tu_buffer *buffer)
733 {
734 return buffer->bo->iova + buffer->bo_offset;
735 }
736
737 enum tu_dynamic_state_bits
738 {
739 TU_DYNAMIC_VIEWPORT = 1 << 0,
740 TU_DYNAMIC_SCISSOR = 1 << 1,
741 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
742 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
743 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
744 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
745 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
746 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
747 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
748 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
749 TU_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
750 TU_DYNAMIC_ALL = (1 << 11) - 1,
751 };
752
753 struct tu_vertex_binding
754 {
755 struct tu_buffer *buffer;
756 VkDeviceSize offset;
757 };
758
759 struct tu_viewport_state
760 {
761 uint32_t count;
762 VkViewport viewports[MAX_VIEWPORTS];
763 };
764
765 struct tu_scissor_state
766 {
767 uint32_t count;
768 VkRect2D scissors[MAX_SCISSORS];
769 };
770
771 struct tu_discard_rectangle_state
772 {
773 uint32_t count;
774 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
775 };
776
777 struct tu_dynamic_state
778 {
779 /**
780 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
781 * Defines the set of saved dynamic state.
782 */
783 uint32_t mask;
784
785 struct tu_viewport_state viewport;
786
787 struct tu_scissor_state scissor;
788
789 float line_width;
790
791 struct
792 {
793 float bias;
794 float clamp;
795 float slope;
796 } depth_bias;
797
798 float blend_constants[4];
799
800 struct
801 {
802 float min;
803 float max;
804 } depth_bounds;
805
806 struct
807 {
808 uint32_t front;
809 uint32_t back;
810 } stencil_compare_mask;
811
812 struct
813 {
814 uint32_t front;
815 uint32_t back;
816 } stencil_write_mask;
817
818 struct
819 {
820 uint32_t front;
821 uint32_t back;
822 } stencil_reference;
823
824 struct tu_discard_rectangle_state discard_rectangle;
825 };
826
827 extern const struct tu_dynamic_state default_dynamic_state;
828
829 const char *
830 tu_get_debug_option_name(int id);
831
832 const char *
833 tu_get_perftest_option_name(int id);
834
835 struct tu_descriptor_state
836 {
837 struct tu_descriptor_set *sets[MAX_SETS];
838 uint32_t valid;
839 struct tu_push_descriptor_set push_set;
840 bool push_dirty;
841 uint32_t dynamic_descriptors[MAX_DYNAMIC_BUFFERS * A6XX_TEX_CONST_DWORDS];
842 uint32_t input_attachments[MAX_RTS * A6XX_TEX_CONST_DWORDS];
843 };
844
845 struct tu_tile
846 {
847 uint8_t pipe;
848 uint8_t slot;
849 VkOffset2D begin;
850 VkOffset2D end;
851 };
852
853 struct tu_tiling_config
854 {
855 VkRect2D render_area;
856
857 /* position and size of the first tile */
858 VkRect2D tile0;
859 /* number of tiles */
860 VkExtent2D tile_count;
861
862 /* size of the first VSC pipe */
863 VkExtent2D pipe0;
864 /* number of VSC pipes */
865 VkExtent2D pipe_count;
866
867 /* pipe register values */
868 uint32_t pipe_config[MAX_VSC_PIPES];
869 uint32_t pipe_sizes[MAX_VSC_PIPES];
870
871 /* Whether sysmem rendering must be used */
872 bool force_sysmem;
873 };
874
875 enum tu_cmd_dirty_bits
876 {
877 TU_CMD_DIRTY_PIPELINE = 1 << 0,
878 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
879 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
880 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
881 TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS = 1 << 4,
882 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 5,
883 TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 6,
884 TU_CMD_DIRTY_INPUT_ATTACHMENTS = 1 << 7,
885
886 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
887 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
888 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
889 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
890 TU_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 20,
891 TU_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 21,
892 };
893
894 struct tu_streamout_state {
895 uint16_t stride[IR3_MAX_SO_BUFFERS];
896 uint32_t ncomp[IR3_MAX_SO_BUFFERS];
897 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
898 uint32_t prog_count;
899 uint32_t vpc_so_buf_cntl;
900 };
901
902 struct tu_cmd_state
903 {
904 uint32_t dirty;
905
906 struct tu_pipeline *pipeline;
907 struct tu_pipeline *compute_pipeline;
908
909 /* Vertex buffers */
910 struct
911 {
912 struct tu_buffer *buffers[MAX_VBS];
913 VkDeviceSize offsets[MAX_VBS];
914 } vb;
915
916 struct tu_dynamic_state dynamic;
917
918 /* Stream output buffers */
919 struct
920 {
921 struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
922 VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
923 VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
924 } streamout_buf;
925
926 uint8_t streamout_reset;
927 uint8_t streamout_enabled;
928
929 /* Index buffer */
930 struct tu_buffer *index_buffer;
931 uint64_t index_offset;
932 uint32_t index_type;
933 uint32_t max_index_count;
934 uint64_t index_va;
935
936 const struct tu_render_pass *pass;
937 const struct tu_subpass *subpass;
938 const struct tu_framebuffer *framebuffer;
939
940 struct tu_tiling_config tiling_config;
941
942 struct tu_cs_entry tile_store_ib;
943 };
944
945 struct tu_cmd_pool
946 {
947 VkAllocationCallbacks alloc;
948 struct list_head cmd_buffers;
949 struct list_head free_cmd_buffers;
950 uint32_t queue_family_index;
951 };
952
953 struct tu_cmd_buffer_upload
954 {
955 uint8_t *map;
956 unsigned offset;
957 uint64_t size;
958 struct list_head list;
959 };
960
961 enum tu_cmd_buffer_status
962 {
963 TU_CMD_BUFFER_STATUS_INVALID,
964 TU_CMD_BUFFER_STATUS_INITIAL,
965 TU_CMD_BUFFER_STATUS_RECORDING,
966 TU_CMD_BUFFER_STATUS_EXECUTABLE,
967 TU_CMD_BUFFER_STATUS_PENDING,
968 };
969
970 struct tu_bo_list
971 {
972 uint32_t count;
973 uint32_t capacity;
974 struct drm_msm_gem_submit_bo *bo_infos;
975 };
976
977 #define TU_BO_LIST_FAILED (~0)
978
979 void
980 tu_bo_list_init(struct tu_bo_list *list);
981 void
982 tu_bo_list_destroy(struct tu_bo_list *list);
983 void
984 tu_bo_list_reset(struct tu_bo_list *list);
985 uint32_t
986 tu_bo_list_add(struct tu_bo_list *list,
987 const struct tu_bo *bo,
988 uint32_t flags);
989 VkResult
990 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
991
992 /* This struct defines the layout of the scratch_bo */
993 struct tu6_control
994 {
995 uint32_t seqno; /* seqno for async CP_EVENT_WRITE, etc */
996 uint32_t _pad0;
997 volatile uint32_t vsc_overflow;
998 uint32_t _pad1;
999 /* flag set from cmdstream when VSC overflow detected: */
1000 uint32_t vsc_scratch;
1001 uint32_t _pad2;
1002 uint32_t _pad3;
1003 uint32_t _pad4;
1004
1005 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
1006 struct {
1007 uint32_t offset;
1008 uint32_t pad[7];
1009 } flush_base[4];
1010 };
1011
1012 #define ctrl_offset(member) offsetof(struct tu6_control, member)
1013
1014 struct tu_cmd_buffer
1015 {
1016 VK_LOADER_DATA _loader_data;
1017
1018 struct tu_device *device;
1019
1020 struct tu_cmd_pool *pool;
1021 struct list_head pool_link;
1022
1023 VkCommandBufferUsageFlags usage_flags;
1024 VkCommandBufferLevel level;
1025 enum tu_cmd_buffer_status status;
1026
1027 struct tu_cmd_state state;
1028 struct tu_vertex_binding vertex_bindings[MAX_VBS];
1029 uint32_t queue_family_index;
1030
1031 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
1032 VkShaderStageFlags push_constant_stages;
1033 struct tu_descriptor_set meta_push_descriptors;
1034
1035 struct tu_descriptor_state descriptors[MAX_BIND_POINTS];
1036
1037 struct tu_cmd_buffer_upload upload;
1038
1039 VkResult record_result;
1040
1041 struct tu_bo_list bo_list;
1042 struct tu_cs cs;
1043 struct tu_cs draw_cs;
1044 struct tu_cs draw_epilogue_cs;
1045 struct tu_cs sub_cs;
1046
1047 struct tu_bo scratch_bo;
1048 uint32_t scratch_seqno;
1049
1050 struct tu_bo vsc_draw_strm;
1051 struct tu_bo vsc_prim_strm;
1052 uint32_t vsc_draw_strm_pitch;
1053 uint32_t vsc_prim_strm_pitch;
1054 bool use_vsc_data;
1055
1056 bool wait_for_idle;
1057 };
1058
1059 /* Temporary struct for tracking a register state to be written, used by
1060 * a6xx-pack.h and tu_cs_emit_regs()
1061 */
1062 struct tu_reg_value {
1063 uint32_t reg;
1064 uint64_t value;
1065 bool is_address;
1066 struct tu_bo *bo;
1067 bool bo_write;
1068 uint32_t bo_offset;
1069 uint32_t bo_shift;
1070 };
1071
1072 unsigned
1073 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
1074 struct tu_cs *cs,
1075 enum vgt_event_type event,
1076 bool need_seqno);
1077
1078 bool
1079 tu_get_memory_fd(struct tu_device *device,
1080 struct tu_device_memory *memory,
1081 int *pFD);
1082
1083 static inline struct tu_descriptor_state *
1084 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1085 VkPipelineBindPoint bind_point)
1086 {
1087 return &cmd_buffer->descriptors[bind_point];
1088 }
1089
1090 /*
1091 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1092 *
1093 * Limitations: Can't call normal dispatch functions without binding or
1094 * rebinding
1095 * the compute pipeline.
1096 */
1097 void
1098 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1099 uint32_t x,
1100 uint32_t y,
1101 uint32_t z);
1102
1103 struct tu_event
1104 {
1105 struct tu_bo bo;
1106 };
1107
1108 struct tu_shader_module;
1109
1110 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1111 #define TU_HASH_SHADER_SISCHED (1 << 1)
1112 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1113 void
1114 tu_hash_shaders(unsigned char *hash,
1115 const VkPipelineShaderStageCreateInfo **stages,
1116 const struct tu_pipeline_layout *layout,
1117 const struct tu_pipeline_key *key,
1118 uint32_t flags);
1119
1120 static inline gl_shader_stage
1121 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1122 {
1123 assert(__builtin_popcount(vk_stage) == 1);
1124 return ffs(vk_stage) - 1;
1125 }
1126
1127 static inline VkShaderStageFlagBits
1128 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1129 {
1130 return (1 << mesa_stage);
1131 }
1132
1133 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1134
1135 #define tu_foreach_stage(stage, stage_bits) \
1136 for (gl_shader_stage stage, \
1137 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1138 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1139
1140 struct tu_shader_module
1141 {
1142 unsigned char sha1[20];
1143
1144 uint32_t code_size;
1145 const uint32_t *code[0];
1146 };
1147
1148 struct tu_shader_compile_options
1149 {
1150 struct ir3_shader_key key;
1151
1152 bool optimize;
1153 bool include_binning_pass;
1154 };
1155
1156 struct tu_push_constant_range
1157 {
1158 uint32_t lo;
1159 uint32_t count;
1160 };
1161
1162 struct tu_shader
1163 {
1164 struct ir3_shader ir3_shader;
1165
1166 struct tu_push_constant_range push_consts;
1167 unsigned attachment_idx[MAX_RTS];
1168
1169 /* This may be true for vertex shaders. When true, variants[1] is the
1170 * binning variant and binning_binary is non-NULL.
1171 */
1172 bool has_binning_pass;
1173
1174 void *binary;
1175 void *binning_binary;
1176
1177 struct ir3_shader_variant variants[0];
1178 };
1179
1180 struct tu_shader *
1181 tu_shader_create(struct tu_device *dev,
1182 gl_shader_stage stage,
1183 const VkPipelineShaderStageCreateInfo *stage_info,
1184 struct tu_pipeline_layout *layout,
1185 const VkAllocationCallbacks *alloc);
1186
1187 void
1188 tu_shader_destroy(struct tu_device *dev,
1189 struct tu_shader *shader,
1190 const VkAllocationCallbacks *alloc);
1191
1192 void
1193 tu_shader_compile_options_init(
1194 struct tu_shader_compile_options *options,
1195 const VkGraphicsPipelineCreateInfo *pipeline_info);
1196
1197 VkResult
1198 tu_shader_compile(struct tu_device *dev,
1199 struct tu_shader *shader,
1200 const struct tu_shader *next_stage,
1201 const struct tu_shader_compile_options *options,
1202 const VkAllocationCallbacks *alloc);
1203
1204 struct tu_program_descriptor_linkage
1205 {
1206 struct ir3_ubo_analysis_state ubo_state;
1207 struct ir3_const_state const_state;
1208
1209 uint32_t constlen;
1210
1211 struct tu_push_constant_range push_consts;
1212 };
1213
1214 struct tu_pipeline
1215 {
1216 struct tu_cs cs;
1217
1218 struct tu_dynamic_state dynamic_state;
1219
1220 struct tu_pipeline_layout *layout;
1221
1222 bool need_indirect_descriptor_sets;
1223 VkShaderStageFlags active_stages;
1224
1225 struct tu_streamout_state streamout;
1226
1227 struct
1228 {
1229 struct tu_bo binary_bo;
1230 struct tu_cs_entry state_ib;
1231 struct tu_cs_entry binning_state_ib;
1232
1233 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1234 unsigned input_attachment_idx[MAX_RTS];
1235 } program;
1236
1237 struct
1238 {
1239 struct tu_cs_entry state_ib;
1240 } load_state;
1241
1242 struct
1243 {
1244 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1245 uint32_t count;
1246
1247 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1248 uint32_t binning_count;
1249
1250 struct tu_cs_entry state_ib;
1251 struct tu_cs_entry binning_state_ib;
1252 } vi;
1253
1254 struct
1255 {
1256 enum pc_di_primtype primtype;
1257 bool primitive_restart;
1258 } ia;
1259
1260 struct
1261 {
1262 struct tu_cs_entry state_ib;
1263 } vp;
1264
1265 struct
1266 {
1267 uint32_t gras_su_cntl;
1268 struct tu_cs_entry state_ib;
1269 } rast;
1270
1271 struct
1272 {
1273 struct tu_cs_entry state_ib;
1274 } ds;
1275
1276 struct
1277 {
1278 struct tu_cs_entry state_ib;
1279 } blend;
1280
1281 struct
1282 {
1283 uint32_t local_size[3];
1284 } compute;
1285 };
1286
1287 void
1288 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1289
1290 void
1291 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1292
1293 void
1294 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc);
1295
1296 void
1297 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1298 uint32_t gras_su_cntl,
1299 float line_width);
1300
1301 void
1302 tu6_emit_depth_bias(struct tu_cs *cs,
1303 float constant_factor,
1304 float clamp,
1305 float slope_factor);
1306
1307 void
1308 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1309 uint32_t front,
1310 uint32_t back);
1311
1312 void
1313 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1314
1315 void
1316 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1317
1318 void
1319 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1320
1321 void tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits samples);
1322
1323 void tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2);
1324
1325 void tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1);
1326
1327 struct tu_image_view;
1328
1329 void
1330 tu_resolve_sysmem(struct tu_cmd_buffer *cmd,
1331 struct tu_cs *cs,
1332 struct tu_image_view *src,
1333 struct tu_image_view *dst,
1334 uint32_t layers,
1335 const VkRect2D *rect);
1336
1337 void
1338 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1339 struct tu_cs *cs,
1340 uint32_t a,
1341 const VkRenderPassBeginInfo *info);
1342
1343 void
1344 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1345 struct tu_cs *cs,
1346 uint32_t a,
1347 const VkRenderPassBeginInfo *info);
1348
1349 void
1350 tu_load_gmem_attachment(struct tu_cmd_buffer *cmd,
1351 struct tu_cs *cs,
1352 uint32_t a,
1353 bool force_load);
1354
1355 /* expose this function to be able to emit load without checking LOAD_OP */
1356 void
1357 tu_emit_load_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a);
1358
1359 /* note: gmem store can also resolve */
1360 void
1361 tu_store_gmem_attachment(struct tu_cmd_buffer *cmd,
1362 struct tu_cs *cs,
1363 uint32_t a,
1364 uint32_t gmem_a);
1365
1366 struct tu_userdata_info *
1367 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1368 gl_shader_stage stage,
1369 int idx);
1370
1371 struct tu_shader_variant *
1372 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1373
1374 struct tu_graphics_pipeline_create_info
1375 {
1376 bool use_rectlist;
1377 bool db_depth_clear;
1378 bool db_stencil_clear;
1379 bool db_depth_disable_expclear;
1380 bool db_stencil_disable_expclear;
1381 bool db_flush_depth_inplace;
1382 bool db_flush_stencil_inplace;
1383 bool db_resummarize;
1384 uint32_t custom_blend_mode;
1385 };
1386
1387 enum tu_supported_formats {
1388 FMT_VERTEX = 1,
1389 FMT_TEXTURE = 2,
1390 FMT_COLOR = 4,
1391 };
1392
1393 struct tu_native_format
1394 {
1395 enum a6xx_format fmt : 8;
1396 enum a3xx_color_swap swap : 8;
1397 enum a6xx_tile_mode tile_mode : 8;
1398 enum tu_supported_formats supported : 8;
1399 };
1400
1401 struct tu_native_format tu6_format_vtx(VkFormat format);
1402 struct tu_native_format tu6_format_color(VkFormat format, enum a6xx_tile_mode tile_mode);
1403 struct tu_native_format tu6_format_texture(VkFormat format, enum a6xx_tile_mode tile_mode);
1404
1405 static inline enum a6xx_format
1406 tu6_base_format(VkFormat format)
1407 {
1408 /* note: tu6_format_color doesn't care about tiling for .fmt field */
1409 return tu6_format_color(format, TILE6_LINEAR).fmt;
1410 }
1411
1412 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1413
1414 struct tu_image
1415 {
1416 VkImageType type;
1417 /* The original VkFormat provided by the client. This may not match any
1418 * of the actual surface formats.
1419 */
1420 VkFormat vk_format;
1421 VkImageAspectFlags aspects;
1422 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1423 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1424 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1425 VkExtent3D extent;
1426 uint32_t level_count;
1427 uint32_t layer_count;
1428 VkSampleCountFlagBits samples;
1429
1430 struct fdl_layout layout;
1431
1432 unsigned queue_family_mask;
1433 bool exclusive;
1434 bool shareable;
1435
1436 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1437 VkDeviceMemory owned_memory;
1438
1439 /* Set when bound */
1440 struct tu_bo *bo;
1441 VkDeviceSize bo_offset;
1442 };
1443
1444 unsigned
1445 tu_image_queue_family_mask(const struct tu_image *image,
1446 uint32_t family,
1447 uint32_t queue_family);
1448
1449 static inline uint32_t
1450 tu_get_layerCount(const struct tu_image *image,
1451 const VkImageSubresourceRange *range)
1452 {
1453 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1454 ? image->layer_count - range->baseArrayLayer
1455 : range->layerCount;
1456 }
1457
1458 static inline uint32_t
1459 tu_get_levelCount(const struct tu_image *image,
1460 const VkImageSubresourceRange *range)
1461 {
1462 return range->levelCount == VK_REMAINING_MIP_LEVELS
1463 ? image->level_count - range->baseMipLevel
1464 : range->levelCount;
1465 }
1466
1467 enum a3xx_msaa_samples
1468 tu_msaa_samples(uint32_t samples);
1469 enum a6xx_tex_fetchsize
1470 tu6_fetchsize(VkFormat format);
1471
1472 struct tu_image_view
1473 {
1474 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1475
1476 uint64_t base_addr;
1477 uint64_t ubwc_addr;
1478 uint32_t layer_size;
1479 uint32_t ubwc_layer_size;
1480
1481 /* used to determine if fast gmem store path can be used */
1482 VkExtent2D extent;
1483 bool need_y2_align;
1484
1485 bool ubwc_enabled;
1486
1487 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1488
1489 /* Descriptor for use as a storage image as opposed to a sampled image.
1490 * This has a few differences for cube maps (e.g. type).
1491 */
1492 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1493
1494 /* pre-filled register values */
1495 uint32_t PITCH;
1496 uint32_t FLAG_BUFFER_PITCH;
1497
1498 uint32_t RB_MRT_BUF_INFO;
1499 uint32_t SP_FS_MRT_REG;
1500
1501 uint32_t SP_PS_2D_SRC_INFO;
1502 uint32_t SP_PS_2D_SRC_SIZE;
1503
1504 uint32_t RB_2D_DST_INFO;
1505
1506 uint32_t RB_BLIT_DST_INFO;
1507 };
1508
1509 struct tu_sampler {
1510 uint32_t descriptor[A6XX_TEX_SAMP_DWORDS];
1511 };
1512
1513 void
1514 tu_cs_image_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
1515
1516 void
1517 tu_cs_image_ref_2d(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer, bool src);
1518
1519 void
1520 tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
1521
1522 VkResult
1523 tu_image_create(VkDevice _device,
1524 const VkImageCreateInfo *pCreateInfo,
1525 const VkAllocationCallbacks *alloc,
1526 VkImage *pImage,
1527 uint64_t modifier);
1528
1529 VkResult
1530 tu_image_from_gralloc(VkDevice device_h,
1531 const VkImageCreateInfo *base_info,
1532 const VkNativeBufferANDROID *gralloc_info,
1533 const VkAllocationCallbacks *alloc,
1534 VkImage *out_image_h);
1535
1536 void
1537 tu_image_view_init(struct tu_image_view *view,
1538 const VkImageViewCreateInfo *pCreateInfo);
1539
1540 struct tu_buffer_view
1541 {
1542 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1543
1544 struct tu_buffer *buffer;
1545 };
1546 void
1547 tu_buffer_view_init(struct tu_buffer_view *view,
1548 struct tu_device *device,
1549 const VkBufferViewCreateInfo *pCreateInfo);
1550
1551 static inline struct VkExtent3D
1552 tu_sanitize_image_extent(const VkImageType imageType,
1553 const struct VkExtent3D imageExtent)
1554 {
1555 switch (imageType) {
1556 case VK_IMAGE_TYPE_1D:
1557 return (VkExtent3D) { imageExtent.width, 1, 1 };
1558 case VK_IMAGE_TYPE_2D:
1559 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1560 case VK_IMAGE_TYPE_3D:
1561 return imageExtent;
1562 default:
1563 unreachable("invalid image type");
1564 }
1565 }
1566
1567 static inline struct VkOffset3D
1568 tu_sanitize_image_offset(const VkImageType imageType,
1569 const struct VkOffset3D imageOffset)
1570 {
1571 switch (imageType) {
1572 case VK_IMAGE_TYPE_1D:
1573 return (VkOffset3D) { imageOffset.x, 0, 0 };
1574 case VK_IMAGE_TYPE_2D:
1575 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1576 case VK_IMAGE_TYPE_3D:
1577 return imageOffset;
1578 default:
1579 unreachable("invalid image type");
1580 }
1581 }
1582
1583 struct tu_attachment_info
1584 {
1585 struct tu_image_view *attachment;
1586 };
1587
1588 struct tu_framebuffer
1589 {
1590 uint32_t width;
1591 uint32_t height;
1592 uint32_t layers;
1593
1594 uint32_t attachment_count;
1595 struct tu_attachment_info attachments[0];
1596 };
1597
1598 struct tu_subpass_attachment
1599 {
1600 uint32_t attachment;
1601 };
1602
1603 struct tu_subpass
1604 {
1605 uint32_t input_count;
1606 uint32_t color_count;
1607 struct tu_subpass_attachment *input_attachments;
1608 struct tu_subpass_attachment *color_attachments;
1609 struct tu_subpass_attachment *resolve_attachments;
1610 struct tu_subpass_attachment depth_stencil_attachment;
1611
1612 VkSampleCountFlagBits samples;
1613
1614 /* pre-filled register values */
1615 uint32_t render_components;
1616 uint32_t srgb_cntl;
1617 };
1618
1619 struct tu_render_pass_attachment
1620 {
1621 VkFormat format;
1622 uint32_t samples;
1623 uint32_t cpp;
1624 VkImageAspectFlags clear_mask;
1625 bool load;
1626 bool store;
1627 int32_t gmem_offset;
1628 };
1629
1630 struct tu_render_pass
1631 {
1632 uint32_t attachment_count;
1633 uint32_t subpass_count;
1634 uint32_t gmem_pixels;
1635 uint32_t tile_align_w;
1636 struct tu_subpass_attachment *subpass_attachments;
1637 struct tu_render_pass_attachment *attachments;
1638 struct tu_subpass subpasses[0];
1639 };
1640
1641 VkResult
1642 tu_device_init_meta(struct tu_device *device);
1643 void
1644 tu_device_finish_meta(struct tu_device *device);
1645
1646 struct tu_query_pool
1647 {
1648 VkQueryType type;
1649 uint32_t stride;
1650 uint64_t size;
1651 uint32_t pipeline_statistics;
1652 struct tu_bo bo;
1653 };
1654
1655 struct tu_semaphore
1656 {
1657 uint32_t syncobj;
1658 uint32_t temp_syncobj;
1659 };
1660
1661 void
1662 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1663 VkPipelineBindPoint bind_point,
1664 struct tu_descriptor_set *set,
1665 unsigned idx);
1666
1667 void
1668 tu_update_descriptor_sets(struct tu_device *device,
1669 struct tu_cmd_buffer *cmd_buffer,
1670 VkDescriptorSet overrideSet,
1671 uint32_t descriptorWriteCount,
1672 const VkWriteDescriptorSet *pDescriptorWrites,
1673 uint32_t descriptorCopyCount,
1674 const VkCopyDescriptorSet *pDescriptorCopies);
1675
1676 void
1677 tu_update_descriptor_set_with_template(
1678 struct tu_device *device,
1679 struct tu_cmd_buffer *cmd_buffer,
1680 struct tu_descriptor_set *set,
1681 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1682 const void *pData);
1683
1684 void
1685 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1686 VkPipelineBindPoint pipelineBindPoint,
1687 VkPipelineLayout _layout,
1688 uint32_t set,
1689 uint32_t descriptorWriteCount,
1690 const VkWriteDescriptorSet *pDescriptorWrites);
1691
1692 int
1693 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1694
1695 int
1696 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1697
1698 int
1699 tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
1700
1701 int
1702 tu_drm_submitqueue_new(const struct tu_device *dev,
1703 int priority,
1704 uint32_t *queue_id);
1705
1706 void
1707 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1708
1709 uint32_t
1710 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1711 uint32_t
1712 tu_gem_import_dmabuf(const struct tu_device *dev,
1713 int prime_fd,
1714 uint64_t size);
1715 int
1716 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1717 void
1718 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1719 uint64_t
1720 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1721 uint64_t
1722 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1723
1724 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1725 \
1726 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1727 { \
1728 return (struct __tu_type *) _handle; \
1729 } \
1730 \
1731 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1732 { \
1733 return (__VkType) _obj; \
1734 }
1735
1736 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1737 \
1738 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1739 { \
1740 return (struct __tu_type *) (uintptr_t) _handle; \
1741 } \
1742 \
1743 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1744 { \
1745 return (__VkType)(uintptr_t) _obj; \
1746 }
1747
1748 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1749 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1750
1751 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1752 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1753 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1754 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1755 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1756
1757 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1758 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1759 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1760 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1761 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1762 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1763 VkDescriptorSetLayout)
1764 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1765 VkDescriptorUpdateTemplate)
1766 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1767 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1768 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1769 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1770 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1771 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1772 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1773 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1774 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1775 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1776 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1777 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1778 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1779 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1780
1781 #endif /* TU_PRIVATE_H */