turnip: new clear/blit implementation with shader path fallback
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #include "vk_format.h"
81
82 #define MAX_VBS 32
83 #define MAX_VERTEX_ATTRIBS 32
84 #define MAX_RTS 8
85 #define MAX_VSC_PIPES 32
86 #define MAX_VIEWPORTS 1
87 #define MAX_SCISSORS 16
88 #define MAX_DISCARD_RECTANGLES 4
89 #define MAX_PUSH_CONSTANTS_SIZE 128
90 #define MAX_PUSH_DESCRIPTORS 32
91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
93 #define MAX_DYNAMIC_BUFFERS \
94 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
95 #define MAX_SAMPLES_LOG2 4
96 #define NUM_META_FS_KEYS 13
97 #define TU_MAX_DRM_DEVICES 8
98 #define MAX_VIEWS 8
99 /* The Qualcomm driver exposes 0x20000058 */
100 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
101
102 #define NUM_DEPTH_CLEAR_PIPELINES 3
103
104 /*
105 * This is the point we switch from using CP to compute shader
106 * for certain buffer operations.
107 */
108 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
109
110 #define A6XX_TEX_CONST_DWORDS 16
111 #define A6XX_TEX_SAMP_DWORDS 4
112
113 enum tu_mem_heap
114 {
115 TU_MEM_HEAP_VRAM,
116 TU_MEM_HEAP_VRAM_CPU_ACCESS,
117 TU_MEM_HEAP_GTT,
118 TU_MEM_HEAP_COUNT
119 };
120
121 enum tu_mem_type
122 {
123 TU_MEM_TYPE_VRAM,
124 TU_MEM_TYPE_GTT_WRITE_COMBINE,
125 TU_MEM_TYPE_VRAM_CPU_ACCESS,
126 TU_MEM_TYPE_GTT_CACHED,
127 TU_MEM_TYPE_COUNT
128 };
129
130 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
131
132 static inline uint32_t
133 align_u32(uint32_t v, uint32_t a)
134 {
135 assert(a != 0 && a == (a & -a));
136 return (v + a - 1) & ~(a - 1);
137 }
138
139 static inline uint32_t
140 align_u32_npot(uint32_t v, uint32_t a)
141 {
142 return (v + a - 1) / a * a;
143 }
144
145 static inline uint64_t
146 align_u64(uint64_t v, uint64_t a)
147 {
148 assert(a != 0 && a == (a & -a));
149 return (v + a - 1) & ~(a - 1);
150 }
151
152 static inline int32_t
153 align_i32(int32_t v, int32_t a)
154 {
155 assert(a != 0 && a == (a & -a));
156 return (v + a - 1) & ~(a - 1);
157 }
158
159 /** Alignment must be a power of 2. */
160 static inline bool
161 tu_is_aligned(uintmax_t n, uintmax_t a)
162 {
163 assert(a == (a & -a));
164 return (n & (a - 1)) == 0;
165 }
166
167 static inline uint32_t
168 round_up_u32(uint32_t v, uint32_t a)
169 {
170 return (v + a - 1) / a;
171 }
172
173 static inline uint64_t
174 round_up_u64(uint64_t v, uint64_t a)
175 {
176 return (v + a - 1) / a;
177 }
178
179 static inline uint32_t
180 tu_minify(uint32_t n, uint32_t levels)
181 {
182 if (unlikely(n == 0))
183 return 0;
184 else
185 return MAX2(n >> levels, 1);
186 }
187 static inline float
188 tu_clamp_f(float f, float min, float max)
189 {
190 assert(min < max);
191
192 if (f > max)
193 return max;
194 else if (f < min)
195 return min;
196 else
197 return f;
198 }
199
200 static inline bool
201 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
202 {
203 if (*inout_mask & clear_mask) {
204 *inout_mask &= ~clear_mask;
205 return true;
206 } else {
207 return false;
208 }
209 }
210
211 #define for_each_bit(b, dword) \
212 for (uint32_t __dword = (dword); \
213 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
214
215 #define typed_memcpy(dest, src, count) \
216 ({ \
217 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
218 memcpy((dest), (src), (count) * sizeof(*(src))); \
219 })
220
221 #define COND(bool, val) ((bool) ? (val) : 0)
222
223 /* Whenever we generate an error, pass it through this function. Useful for
224 * debugging, where we can break on it. Only call at error site, not when
225 * propagating errors. Might be useful to plug in a stack trace here.
226 */
227
228 struct tu_instance;
229
230 VkResult
231 __vk_errorf(struct tu_instance *instance,
232 VkResult error,
233 const char *file,
234 int line,
235 const char *format,
236 ...);
237
238 #define vk_error(instance, error) \
239 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
240 #define vk_errorf(instance, error, format, ...) \
241 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
242
243 void
244 __tu_finishme(const char *file, int line, const char *format, ...)
245 tu_printflike(3, 4);
246 void
247 tu_loge(const char *format, ...) tu_printflike(1, 2);
248 void
249 tu_loge_v(const char *format, va_list va);
250 void
251 tu_logi(const char *format, ...) tu_printflike(1, 2);
252 void
253 tu_logi_v(const char *format, va_list va);
254
255 /**
256 * Print a FINISHME message, including its source location.
257 */
258 #define tu_finishme(format, ...) \
259 do { \
260 static bool reported = false; \
261 if (!reported) { \
262 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
263 reported = true; \
264 } \
265 } while (0)
266
267 /* A non-fatal assert. Useful for debugging. */
268 #ifdef DEBUG
269 #define tu_assert(x) \
270 ({ \
271 if (unlikely(!(x))) \
272 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
273 })
274 #else
275 #define tu_assert(x)
276 #endif
277
278 /* Suppress -Wunused in stub functions */
279 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
280 static inline void
281 __tu_use_args(int ignore, ...)
282 {
283 }
284
285 #define tu_stub() \
286 do { \
287 tu_finishme("stub %s", __func__); \
288 } while (0)
289
290 void *
291 tu_lookup_entrypoint_unchecked(const char *name);
292 void *
293 tu_lookup_entrypoint_checked(
294 const char *name,
295 uint32_t core_version,
296 const struct tu_instance_extension_table *instance,
297 const struct tu_device_extension_table *device);
298
299 struct tu_physical_device
300 {
301 VK_LOADER_DATA _loader_data;
302
303 struct tu_instance *instance;
304
305 char path[20];
306 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
307 uint8_t driver_uuid[VK_UUID_SIZE];
308 uint8_t device_uuid[VK_UUID_SIZE];
309 uint8_t cache_uuid[VK_UUID_SIZE];
310
311 struct wsi_device wsi_device;
312
313 int local_fd;
314 int master_fd;
315
316 unsigned gpu_id;
317 uint32_t gmem_size;
318 uint64_t gmem_base;
319 uint32_t ccu_offset_gmem;
320 uint32_t ccu_offset_bypass;
321 #define GMEM_ALIGN_W 16
322 #define GMEM_ALIGN_H 4
323
324 struct {
325 uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */
326 uint32_t PC_UNKNOWN_9805;
327 uint32_t SP_UNKNOWN_A0F8;
328 } magic;
329
330 /* This is the drivers on-disk cache used as a fallback as opposed to
331 * the pipeline cache defined by apps.
332 */
333 struct disk_cache *disk_cache;
334
335 struct tu_device_extension_table supported_extensions;
336 };
337
338 enum tu_debug_flags
339 {
340 TU_DEBUG_STARTUP = 1 << 0,
341 TU_DEBUG_NIR = 1 << 1,
342 TU_DEBUG_IR3 = 1 << 2,
343 TU_DEBUG_NOBIN = 1 << 3,
344 TU_DEBUG_SYSMEM = 1 << 4,
345 TU_DEBUG_FORCEBIN = 1 << 5,
346 };
347
348 struct tu_instance
349 {
350 VK_LOADER_DATA _loader_data;
351
352 VkAllocationCallbacks alloc;
353
354 uint32_t api_version;
355 int physical_device_count;
356 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
357
358 enum tu_debug_flags debug_flags;
359
360 struct vk_debug_report_instance debug_report_callbacks;
361
362 struct tu_instance_extension_table enabled_extensions;
363 };
364
365 VkResult
366 tu_wsi_init(struct tu_physical_device *physical_device);
367 void
368 tu_wsi_finish(struct tu_physical_device *physical_device);
369
370 bool
371 tu_instance_extension_supported(const char *name);
372 uint32_t
373 tu_physical_device_api_version(struct tu_physical_device *dev);
374 bool
375 tu_physical_device_extension_supported(struct tu_physical_device *dev,
376 const char *name);
377
378 struct cache_entry;
379
380 struct tu_pipeline_cache
381 {
382 struct tu_device *device;
383 pthread_mutex_t mutex;
384
385 uint32_t total_size;
386 uint32_t table_size;
387 uint32_t kernel_count;
388 struct cache_entry **hash_table;
389 bool modified;
390
391 VkAllocationCallbacks alloc;
392 };
393
394 struct tu_pipeline_key
395 {
396 };
397
398 void
399 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
400 struct tu_device *device);
401 void
402 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
403 void
404 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
405 const void *data,
406 size_t size);
407
408 struct tu_shader_variant;
409
410 bool
411 tu_create_shader_variants_from_pipeline_cache(
412 struct tu_device *device,
413 struct tu_pipeline_cache *cache,
414 const unsigned char *sha1,
415 struct tu_shader_variant **variants);
416
417 void
418 tu_pipeline_cache_insert_shaders(struct tu_device *device,
419 struct tu_pipeline_cache *cache,
420 const unsigned char *sha1,
421 struct tu_shader_variant **variants,
422 const void *const *codes,
423 const unsigned *code_sizes);
424
425 struct tu_meta_state
426 {
427 VkAllocationCallbacks alloc;
428
429 struct tu_pipeline_cache cache;
430 };
431
432 /* queue types */
433 #define TU_QUEUE_GENERAL 0
434
435 #define TU_MAX_QUEUE_FAMILIES 1
436
437 struct tu_fence
438 {
439 struct wsi_fence *fence_wsi;
440 bool signaled;
441 int fd;
442 };
443
444 void
445 tu_fence_init(struct tu_fence *fence, bool signaled);
446 void
447 tu_fence_finish(struct tu_fence *fence);
448 void
449 tu_fence_update_fd(struct tu_fence *fence, int fd);
450 void
451 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
452 void
453 tu_fence_signal(struct tu_fence *fence);
454 void
455 tu_fence_wait_idle(struct tu_fence *fence);
456
457 struct tu_queue
458 {
459 VK_LOADER_DATA _loader_data;
460 struct tu_device *device;
461 uint32_t queue_family_index;
462 int queue_idx;
463 VkDeviceQueueCreateFlags flags;
464
465 uint32_t msm_queue_id;
466 struct tu_fence submit_fence;
467 };
468
469 struct tu_bo
470 {
471 uint32_t gem_handle;
472 uint64_t size;
473 uint64_t iova;
474 void *map;
475 };
476
477 struct tu_device
478 {
479 VK_LOADER_DATA _loader_data;
480
481 VkAllocationCallbacks alloc;
482
483 struct tu_instance *instance;
484
485 struct tu_meta_state meta_state;
486
487 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
488 int queue_count[TU_MAX_QUEUE_FAMILIES];
489
490 struct tu_physical_device *physical_device;
491
492 struct ir3_compiler *compiler;
493
494 /* Backup in-memory cache to be used if the app doesn't provide one */
495 struct tu_pipeline_cache *mem_cache;
496
497 struct tu_bo vsc_data;
498 struct tu_bo vsc_data2;
499 uint32_t vsc_data_pitch;
500 uint32_t vsc_data2_pitch;
501
502 struct tu_bo border_color;
503
504 struct list_head shader_slabs;
505 mtx_t shader_slab_mutex;
506
507 struct tu_device_extension_table enabled_extensions;
508 };
509
510 VkResult
511 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
512 VkResult
513 tu_bo_init_dmabuf(struct tu_device *dev,
514 struct tu_bo *bo,
515 uint64_t size,
516 int fd);
517 int
518 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
519 void
520 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
521 VkResult
522 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
523
524 struct tu_cs_entry
525 {
526 /* No ownership */
527 const struct tu_bo *bo;
528
529 uint32_t size;
530 uint32_t offset;
531 };
532
533 struct ts_cs_memory {
534 uint32_t *map;
535 uint64_t iova;
536 };
537
538 enum tu_cs_mode
539 {
540
541 /*
542 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
543 * is full. tu_cs_begin must be called before command packet emission and
544 * tu_cs_end must be called after.
545 *
546 * This mode may create multiple entries internally. The entries must be
547 * submitted together.
548 */
549 TU_CS_MODE_GROW,
550
551 /*
552 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
553 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
554 * effect on it.
555 *
556 * This mode does not create any entry or any BO.
557 */
558 TU_CS_MODE_EXTERNAL,
559
560 /*
561 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
562 * command packet emission. tu_cs_begin_sub_stream must be called to get a
563 * sub-stream to emit comamnd packets to. When done with the sub-stream,
564 * tu_cs_end_sub_stream must be called.
565 *
566 * This mode does not create any entry internally.
567 */
568 TU_CS_MODE_SUB_STREAM,
569 };
570
571 struct tu_cs
572 {
573 uint32_t *start;
574 uint32_t *cur;
575 uint32_t *reserved_end;
576 uint32_t *end;
577
578 struct tu_device *device;
579 enum tu_cs_mode mode;
580 uint32_t next_bo_size;
581
582 struct tu_cs_entry *entries;
583 uint32_t entry_count;
584 uint32_t entry_capacity;
585
586 struct tu_bo **bos;
587 uint32_t bo_count;
588 uint32_t bo_capacity;
589
590 /* state for cond_exec_start/cond_exec_end */
591 uint32_t cond_flags;
592 uint32_t *cond_dwords;
593 };
594
595 struct tu_device_memory
596 {
597 struct tu_bo bo;
598 VkDeviceSize size;
599
600 /* for dedicated allocations */
601 struct tu_image *image;
602 struct tu_buffer *buffer;
603
604 uint32_t type_index;
605 void *map;
606 void *user_ptr;
607 };
608
609 struct tu_descriptor_range
610 {
611 uint64_t va;
612 uint32_t size;
613 };
614
615 struct tu_descriptor_set
616 {
617 const struct tu_descriptor_set_layout *layout;
618 uint32_t size;
619
620 uint64_t va;
621 uint32_t *mapped_ptr;
622 struct tu_descriptor_range *dynamic_descriptors;
623
624 struct tu_bo *descriptors[0];
625 };
626
627 struct tu_push_descriptor_set
628 {
629 struct tu_descriptor_set set;
630 uint32_t capacity;
631 };
632
633 struct tu_descriptor_pool_entry
634 {
635 uint32_t offset;
636 uint32_t size;
637 struct tu_descriptor_set *set;
638 };
639
640 struct tu_descriptor_pool
641 {
642 struct tu_bo bo;
643 uint64_t current_offset;
644 uint64_t size;
645
646 uint8_t *host_memory_base;
647 uint8_t *host_memory_ptr;
648 uint8_t *host_memory_end;
649
650 uint32_t entry_count;
651 uint32_t max_entry_count;
652 struct tu_descriptor_pool_entry entries[0];
653 };
654
655 struct tu_descriptor_update_template_entry
656 {
657 VkDescriptorType descriptor_type;
658
659 /* The number of descriptors to update */
660 uint32_t descriptor_count;
661
662 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
663 */
664 uint32_t dst_offset;
665
666 /* In dwords. Not valid/used for dynamic descriptors */
667 uint32_t dst_stride;
668
669 uint32_t buffer_offset;
670
671 /* Only valid for combined image samplers and samplers */
672 uint16_t has_sampler;
673
674 /* In bytes */
675 size_t src_offset;
676 size_t src_stride;
677
678 /* For push descriptors */
679 const uint32_t *immutable_samplers;
680 };
681
682 struct tu_descriptor_update_template
683 {
684 uint32_t entry_count;
685 VkPipelineBindPoint bind_point;
686 struct tu_descriptor_update_template_entry entry[0];
687 };
688
689 struct tu_buffer
690 {
691 VkDeviceSize size;
692
693 VkBufferUsageFlags usage;
694 VkBufferCreateFlags flags;
695
696 struct tu_bo *bo;
697 VkDeviceSize bo_offset;
698 };
699
700 static inline uint64_t
701 tu_buffer_iova(struct tu_buffer *buffer)
702 {
703 return buffer->bo->iova + buffer->bo_offset;
704 }
705
706 enum tu_dynamic_state_bits
707 {
708 TU_DYNAMIC_VIEWPORT = 1 << 0,
709 TU_DYNAMIC_SCISSOR = 1 << 1,
710 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
711 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
712 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
713 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
714 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
715 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
716 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
717 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
718 TU_DYNAMIC_ALL = (1 << 10) - 1,
719 };
720
721 struct tu_vertex_binding
722 {
723 struct tu_buffer *buffer;
724 VkDeviceSize offset;
725 };
726
727 struct tu_viewport_state
728 {
729 uint32_t count;
730 VkViewport viewports[MAX_VIEWPORTS];
731 };
732
733 struct tu_scissor_state
734 {
735 uint32_t count;
736 VkRect2D scissors[MAX_SCISSORS];
737 };
738
739 struct tu_discard_rectangle_state
740 {
741 uint32_t count;
742 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
743 };
744
745 struct tu_dynamic_state
746 {
747 /**
748 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
749 * Defines the set of saved dynamic state.
750 */
751 uint32_t mask;
752
753 struct tu_viewport_state viewport;
754
755 struct tu_scissor_state scissor;
756
757 float line_width;
758
759 struct
760 {
761 float bias;
762 float clamp;
763 float slope;
764 } depth_bias;
765
766 float blend_constants[4];
767
768 struct
769 {
770 float min;
771 float max;
772 } depth_bounds;
773
774 struct
775 {
776 uint32_t front;
777 uint32_t back;
778 } stencil_compare_mask;
779
780 struct
781 {
782 uint32_t front;
783 uint32_t back;
784 } stencil_write_mask;
785
786 struct
787 {
788 uint32_t front;
789 uint32_t back;
790 } stencil_reference;
791
792 struct tu_discard_rectangle_state discard_rectangle;
793 };
794
795 extern const struct tu_dynamic_state default_dynamic_state;
796
797 const char *
798 tu_get_debug_option_name(int id);
799
800 const char *
801 tu_get_perftest_option_name(int id);
802
803 struct tu_descriptor_state
804 {
805 struct tu_descriptor_set *sets[MAX_SETS];
806 uint32_t valid;
807 struct tu_push_descriptor_set push_set;
808 bool push_dirty;
809 uint64_t dynamic_buffers[MAX_DYNAMIC_BUFFERS];
810 };
811
812 struct tu_tile
813 {
814 uint8_t pipe;
815 uint8_t slot;
816 VkOffset2D begin;
817 VkOffset2D end;
818 };
819
820 struct tu_tiling_config
821 {
822 VkRect2D render_area;
823
824 /* position and size of the first tile */
825 VkRect2D tile0;
826 /* number of tiles */
827 VkExtent2D tile_count;
828
829 /* size of the first VSC pipe */
830 VkExtent2D pipe0;
831 /* number of VSC pipes */
832 VkExtent2D pipe_count;
833
834 /* pipe register values */
835 uint32_t pipe_config[MAX_VSC_PIPES];
836 uint32_t pipe_sizes[MAX_VSC_PIPES];
837
838 /* Whether sysmem rendering must be used */
839 bool force_sysmem;
840 };
841
842 enum tu_cmd_dirty_bits
843 {
844 TU_CMD_DIRTY_PIPELINE = 1 << 0,
845 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
846 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
847 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
848 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
849 TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 5,
850
851 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
852 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
853 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
854 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
855 TU_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 20,
856 TU_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 21,
857 };
858
859 struct tu_streamout_state {
860 uint16_t stride[IR3_MAX_SO_BUFFERS];
861 uint32_t ncomp[IR3_MAX_SO_BUFFERS];
862 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
863 uint32_t prog_count;
864 uint32_t vpc_so_buf_cntl;
865 };
866
867 struct tu_cmd_state
868 {
869 uint32_t dirty;
870
871 struct tu_pipeline *pipeline;
872 struct tu_pipeline *compute_pipeline;
873
874 /* Vertex buffers */
875 struct
876 {
877 struct tu_buffer *buffers[MAX_VBS];
878 VkDeviceSize offsets[MAX_VBS];
879 } vb;
880
881 struct tu_dynamic_state dynamic;
882
883 /* Stream output buffers */
884 struct
885 {
886 struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
887 VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
888 VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
889 } streamout_buf;
890
891 uint8_t streamout_reset;
892 uint8_t streamout_enabled;
893
894 /* Index buffer */
895 struct tu_buffer *index_buffer;
896 uint64_t index_offset;
897 uint32_t index_type;
898 uint32_t max_index_count;
899 uint64_t index_va;
900
901 const struct tu_render_pass *pass;
902 const struct tu_subpass *subpass;
903 const struct tu_framebuffer *framebuffer;
904
905 struct tu_tiling_config tiling_config;
906
907 struct tu_cs_entry tile_store_ib;
908 };
909
910 struct tu_cmd_pool
911 {
912 VkAllocationCallbacks alloc;
913 struct list_head cmd_buffers;
914 struct list_head free_cmd_buffers;
915 uint32_t queue_family_index;
916 };
917
918 struct tu_cmd_buffer_upload
919 {
920 uint8_t *map;
921 unsigned offset;
922 uint64_t size;
923 struct list_head list;
924 };
925
926 enum tu_cmd_buffer_status
927 {
928 TU_CMD_BUFFER_STATUS_INVALID,
929 TU_CMD_BUFFER_STATUS_INITIAL,
930 TU_CMD_BUFFER_STATUS_RECORDING,
931 TU_CMD_BUFFER_STATUS_EXECUTABLE,
932 TU_CMD_BUFFER_STATUS_PENDING,
933 };
934
935 struct tu_bo_list
936 {
937 uint32_t count;
938 uint32_t capacity;
939 struct drm_msm_gem_submit_bo *bo_infos;
940 };
941
942 #define TU_BO_LIST_FAILED (~0)
943
944 void
945 tu_bo_list_init(struct tu_bo_list *list);
946 void
947 tu_bo_list_destroy(struct tu_bo_list *list);
948 void
949 tu_bo_list_reset(struct tu_bo_list *list);
950 uint32_t
951 tu_bo_list_add(struct tu_bo_list *list,
952 const struct tu_bo *bo,
953 uint32_t flags);
954 VkResult
955 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
956
957 /* This struct defines the layout of the scratch_bo */
958 struct tu6_control
959 {
960 uint32_t seqno; /* seqno for async CP_EVENT_WRITE, etc */
961 uint32_t _pad0;
962 volatile uint32_t vsc_overflow;
963 uint32_t _pad1;
964 /* flag set from cmdstream when VSC overflow detected: */
965 uint32_t vsc_scratch;
966 uint32_t _pad2;
967 uint32_t _pad3;
968 uint32_t _pad4;
969
970 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
971 struct {
972 uint32_t offset;
973 uint32_t pad[7];
974 } flush_base[4];
975 };
976
977 #define ctrl_offset(member) offsetof(struct tu6_control, member)
978
979 struct tu_cmd_buffer
980 {
981 VK_LOADER_DATA _loader_data;
982
983 struct tu_device *device;
984
985 struct tu_cmd_pool *pool;
986 struct list_head pool_link;
987
988 VkCommandBufferUsageFlags usage_flags;
989 VkCommandBufferLevel level;
990 enum tu_cmd_buffer_status status;
991
992 struct tu_cmd_state state;
993 struct tu_vertex_binding vertex_bindings[MAX_VBS];
994 uint32_t queue_family_index;
995
996 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
997 VkShaderStageFlags push_constant_stages;
998 struct tu_descriptor_set meta_push_descriptors;
999
1000 struct tu_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1001
1002 struct tu_cmd_buffer_upload upload;
1003
1004 VkResult record_result;
1005
1006 struct tu_bo_list bo_list;
1007 struct tu_cs cs;
1008 struct tu_cs draw_cs;
1009 struct tu_cs draw_epilogue_cs;
1010 struct tu_cs sub_cs;
1011
1012 struct tu_bo scratch_bo;
1013 uint32_t scratch_seqno;
1014
1015 struct tu_bo vsc_data;
1016 struct tu_bo vsc_data2;
1017 uint32_t vsc_data_pitch;
1018 uint32_t vsc_data2_pitch;
1019 bool use_vsc_data;
1020
1021 bool wait_for_idle;
1022 };
1023
1024 /* Temporary struct for tracking a register state to be written, used by
1025 * a6xx-pack.h and tu_cs_emit_regs()
1026 */
1027 struct tu_reg_value {
1028 uint32_t reg;
1029 uint64_t value;
1030 bool is_address;
1031 struct tu_bo *bo;
1032 bool bo_write;
1033 uint32_t bo_offset;
1034 uint32_t bo_shift;
1035 };
1036
1037 unsigned
1038 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
1039 struct tu_cs *cs,
1040 enum vgt_event_type event,
1041 bool need_seqno);
1042
1043 bool
1044 tu_get_memory_fd(struct tu_device *device,
1045 struct tu_device_memory *memory,
1046 int *pFD);
1047
1048 static inline struct tu_descriptor_state *
1049 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1050 VkPipelineBindPoint bind_point)
1051 {
1052 return &cmd_buffer->descriptors[bind_point];
1053 }
1054
1055 /*
1056 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1057 *
1058 * Limitations: Can't call normal dispatch functions without binding or
1059 * rebinding
1060 * the compute pipeline.
1061 */
1062 void
1063 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1064 uint32_t x,
1065 uint32_t y,
1066 uint32_t z);
1067
1068 struct tu_event
1069 {
1070 struct tu_bo bo;
1071 };
1072
1073 struct tu_shader_module;
1074
1075 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1076 #define TU_HASH_SHADER_SISCHED (1 << 1)
1077 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1078 void
1079 tu_hash_shaders(unsigned char *hash,
1080 const VkPipelineShaderStageCreateInfo **stages,
1081 const struct tu_pipeline_layout *layout,
1082 const struct tu_pipeline_key *key,
1083 uint32_t flags);
1084
1085 static inline gl_shader_stage
1086 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1087 {
1088 assert(__builtin_popcount(vk_stage) == 1);
1089 return ffs(vk_stage) - 1;
1090 }
1091
1092 static inline VkShaderStageFlagBits
1093 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1094 {
1095 return (1 << mesa_stage);
1096 }
1097
1098 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1099
1100 #define tu_foreach_stage(stage, stage_bits) \
1101 for (gl_shader_stage stage, \
1102 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1103 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1104
1105 struct tu_shader_module
1106 {
1107 unsigned char sha1[20];
1108
1109 uint32_t code_size;
1110 const uint32_t *code[0];
1111 };
1112
1113 struct tu_shader_compile_options
1114 {
1115 struct ir3_shader_key key;
1116
1117 bool optimize;
1118 bool include_binning_pass;
1119 };
1120
1121 struct tu_descriptor_map
1122 {
1123 /* TODO: avoid fixed size array/justify the size */
1124 unsigned num; /* number of array entries */
1125 unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
1126 int set[128];
1127 int binding[128];
1128 int value[128];
1129 int array_size[128];
1130 };
1131
1132 struct tu_shader
1133 {
1134 struct ir3_shader ir3_shader;
1135
1136 struct tu_descriptor_map texture_map;
1137 struct tu_descriptor_map sampler_map;
1138 struct tu_descriptor_map ubo_map;
1139 struct tu_descriptor_map ssbo_map;
1140 struct tu_descriptor_map image_map;
1141
1142 /* This may be true for vertex shaders. When true, variants[1] is the
1143 * binning variant and binning_binary is non-NULL.
1144 */
1145 bool has_binning_pass;
1146
1147 void *binary;
1148 void *binning_binary;
1149
1150 struct ir3_shader_variant variants[0];
1151 };
1152
1153 struct tu_shader *
1154 tu_shader_create(struct tu_device *dev,
1155 gl_shader_stage stage,
1156 const VkPipelineShaderStageCreateInfo *stage_info,
1157 struct tu_pipeline_layout *layout,
1158 const VkAllocationCallbacks *alloc);
1159
1160 void
1161 tu_shader_destroy(struct tu_device *dev,
1162 struct tu_shader *shader,
1163 const VkAllocationCallbacks *alloc);
1164
1165 void
1166 tu_shader_compile_options_init(
1167 struct tu_shader_compile_options *options,
1168 const VkGraphicsPipelineCreateInfo *pipeline_info);
1169
1170 VkResult
1171 tu_shader_compile(struct tu_device *dev,
1172 struct tu_shader *shader,
1173 const struct tu_shader *next_stage,
1174 const struct tu_shader_compile_options *options,
1175 const VkAllocationCallbacks *alloc);
1176
1177 struct tu_program_descriptor_linkage
1178 {
1179 struct ir3_ubo_analysis_state ubo_state;
1180 struct ir3_const_state const_state;
1181
1182 uint32_t constlen;
1183
1184 struct tu_descriptor_map texture_map;
1185 struct tu_descriptor_map sampler_map;
1186 struct tu_descriptor_map ubo_map;
1187 struct tu_descriptor_map ssbo_map;
1188 struct tu_descriptor_map image_map;
1189 };
1190
1191 struct tu_pipeline
1192 {
1193 struct tu_cs cs;
1194
1195 struct tu_dynamic_state dynamic_state;
1196
1197 struct tu_pipeline_layout *layout;
1198
1199 bool need_indirect_descriptor_sets;
1200 VkShaderStageFlags active_stages;
1201
1202 struct tu_streamout_state streamout;
1203
1204 struct
1205 {
1206 struct tu_bo binary_bo;
1207 struct tu_cs_entry state_ib;
1208 struct tu_cs_entry binning_state_ib;
1209
1210 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1211 } program;
1212
1213 struct
1214 {
1215 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1216 uint32_t count;
1217
1218 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1219 uint32_t binning_count;
1220
1221 struct tu_cs_entry state_ib;
1222 struct tu_cs_entry binning_state_ib;
1223 } vi;
1224
1225 struct
1226 {
1227 enum pc_di_primtype primtype;
1228 bool primitive_restart;
1229 } ia;
1230
1231 struct
1232 {
1233 struct tu_cs_entry state_ib;
1234 } vp;
1235
1236 struct
1237 {
1238 uint32_t gras_su_cntl;
1239 struct tu_cs_entry state_ib;
1240 } rast;
1241
1242 struct
1243 {
1244 struct tu_cs_entry state_ib;
1245 } ds;
1246
1247 struct
1248 {
1249 struct tu_cs_entry state_ib;
1250 } blend;
1251
1252 struct
1253 {
1254 uint32_t local_size[3];
1255 } compute;
1256 };
1257
1258 void
1259 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1260
1261 void
1262 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1263
1264 void
1265 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1266 uint32_t gras_su_cntl,
1267 float line_width);
1268
1269 void
1270 tu6_emit_depth_bias(struct tu_cs *cs,
1271 float constant_factor,
1272 float clamp,
1273 float slope_factor);
1274
1275 void
1276 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1277 uint32_t front,
1278 uint32_t back);
1279
1280 void
1281 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1282
1283 void
1284 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1285
1286 void
1287 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1288
1289 void tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits samples);
1290
1291 void tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2);
1292
1293 void tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1);
1294
1295 struct tu_image_view;
1296
1297 void
1298 tu_resolve_sysmem(struct tu_cmd_buffer *cmd,
1299 struct tu_cs *cs,
1300 struct tu_image_view *src,
1301 struct tu_image_view *dst,
1302 uint32_t layers,
1303 const VkRect2D *rect);
1304
1305 void
1306 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1307 struct tu_cs *cs,
1308 uint32_t a,
1309 const VkRenderPassBeginInfo *info);
1310
1311 void
1312 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1313 struct tu_cs *cs,
1314 uint32_t a,
1315 const VkRenderPassBeginInfo *info);
1316
1317 void
1318 tu_load_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a);
1319
1320 /* expose this function to be able to emit load without checking LOAD_OP */
1321 void
1322 tu_emit_load_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a);
1323
1324 /* note: gmem store can also resolve */
1325 void
1326 tu_store_gmem_attachment(struct tu_cmd_buffer *cmd,
1327 struct tu_cs *cs,
1328 uint32_t a,
1329 uint32_t gmem_a);
1330
1331 struct tu_userdata_info *
1332 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1333 gl_shader_stage stage,
1334 int idx);
1335
1336 struct tu_shader_variant *
1337 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1338
1339 struct tu_graphics_pipeline_create_info
1340 {
1341 bool use_rectlist;
1342 bool db_depth_clear;
1343 bool db_stencil_clear;
1344 bool db_depth_disable_expclear;
1345 bool db_stencil_disable_expclear;
1346 bool db_flush_depth_inplace;
1347 bool db_flush_stencil_inplace;
1348 bool db_resummarize;
1349 uint32_t custom_blend_mode;
1350 };
1351
1352 enum tu_supported_formats {
1353 FMT_VERTEX = 1,
1354 FMT_TEXTURE = 2,
1355 FMT_COLOR = 4,
1356 };
1357
1358 struct tu_native_format
1359 {
1360 enum a6xx_format fmt : 8;
1361 enum a3xx_color_swap swap : 8;
1362 enum a6xx_tile_mode tile_mode : 8;
1363 enum tu_supported_formats supported : 8;
1364 };
1365
1366 struct tu_native_format tu6_format_vtx(VkFormat format);
1367 struct tu_native_format tu6_format_color(VkFormat format, enum a6xx_tile_mode tile_mode);
1368 struct tu_native_format tu6_format_texture(VkFormat format, enum a6xx_tile_mode tile_mode);
1369
1370 static inline enum a6xx_format
1371 tu6_base_format(VkFormat format)
1372 {
1373 /* note: tu6_format_color doesn't care about tiling for .fmt field */
1374 return tu6_format_color(format, TILE6_LINEAR).fmt;
1375 }
1376
1377 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1378
1379 struct tu_image
1380 {
1381 VkImageType type;
1382 /* The original VkFormat provided by the client. This may not match any
1383 * of the actual surface formats.
1384 */
1385 VkFormat vk_format;
1386 VkImageAspectFlags aspects;
1387 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1388 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1389 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1390 VkExtent3D extent;
1391 uint32_t level_count;
1392 uint32_t layer_count;
1393 VkSampleCountFlagBits samples;
1394
1395 struct fdl_layout layout;
1396
1397 unsigned queue_family_mask;
1398 bool exclusive;
1399 bool shareable;
1400
1401 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1402 VkDeviceMemory owned_memory;
1403
1404 /* Set when bound */
1405 struct tu_bo *bo;
1406 VkDeviceSize bo_offset;
1407 };
1408
1409 unsigned
1410 tu_image_queue_family_mask(const struct tu_image *image,
1411 uint32_t family,
1412 uint32_t queue_family);
1413
1414 static inline uint32_t
1415 tu_get_layerCount(const struct tu_image *image,
1416 const VkImageSubresourceRange *range)
1417 {
1418 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1419 ? image->layer_count - range->baseArrayLayer
1420 : range->layerCount;
1421 }
1422
1423 static inline uint32_t
1424 tu_get_levelCount(const struct tu_image *image,
1425 const VkImageSubresourceRange *range)
1426 {
1427 return range->levelCount == VK_REMAINING_MIP_LEVELS
1428 ? image->level_count - range->baseMipLevel
1429 : range->levelCount;
1430 }
1431
1432 static inline VkDeviceSize
1433 tu_layer_size(struct tu_image *image, int level)
1434 {
1435 return fdl_layer_stride(&image->layout, level);
1436 }
1437
1438 static inline uint32_t
1439 tu_image_stride(struct tu_image *image, int level)
1440 {
1441 return image->layout.slices[level].pitch * image->layout.cpp;
1442 }
1443
1444 /* to get the right pitch for compressed formats */
1445 static inline uint32_t
1446 tu_image_pitch(struct tu_image *image, int level)
1447 {
1448 uint32_t stride = tu_image_stride(image, level);
1449 return stride / vk_format_get_blockwidth(image->vk_format);
1450 }
1451
1452 static inline uint64_t
1453 tu_image_base(struct tu_image *image, int level, int layer)
1454 {
1455 return image->bo->iova + image->bo_offset +
1456 fdl_surface_offset(&image->layout, level, layer);
1457 }
1458
1459 #define tu_image_base_ref(image, level, layer) \
1460 .bo = image->bo, \
1461 .bo_offset = (image->bo_offset + fdl_surface_offset(&image->layout, \
1462 level, layer))
1463
1464 #define tu_image_view_base_ref(iview) \
1465 tu_image_base_ref(iview->image, iview->base_mip, iview->base_layer)
1466
1467 static inline VkDeviceSize
1468 tu_image_ubwc_size(struct tu_image *image, int level)
1469 {
1470 return image->layout.ubwc_layer_size;
1471 }
1472
1473 static inline uint32_t
1474 tu_image_ubwc_pitch(struct tu_image *image, int level)
1475 {
1476 return image->layout.ubwc_slices[level].pitch;
1477 }
1478
1479 static inline uint64_t
1480 tu_image_ubwc_surface_offset(struct tu_image *image, int level, int layer)
1481 {
1482 return image->layout.ubwc_slices[level].offset +
1483 layer * tu_image_ubwc_size(image, level);
1484 }
1485
1486 static inline uint64_t
1487 tu_image_ubwc_base(struct tu_image *image, int level, int layer)
1488 {
1489 return image->bo->iova + image->bo_offset +
1490 tu_image_ubwc_surface_offset(image, level, layer);
1491 }
1492
1493 #define tu_image_ubwc_base_ref(image, level, layer) \
1494 .bo = image->bo, \
1495 .bo_offset = (image->bo_offset + tu_image_ubwc_surface_offset(image, \
1496 level, layer))
1497
1498 #define tu_image_view_ubwc_base_ref(iview) \
1499 tu_image_ubwc_base_ref(iview->image, iview->base_mip, iview->base_layer)
1500
1501 #define tu_image_view_ubwc_pitches(iview) \
1502 .pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip), \
1503 .array_pitch = tu_image_ubwc_size(iview->image, iview->base_mip) >> 2
1504
1505 enum a6xx_tile_mode
1506 tu6_get_image_tile_mode(struct tu_image *image, int level);
1507 enum a3xx_msaa_samples
1508 tu_msaa_samples(uint32_t samples);
1509 enum a6xx_tex_fetchsize
1510 tu6_fetchsize(VkFormat format);
1511
1512 static inline struct tu_native_format
1513 tu6_format_image(struct tu_image *image, VkFormat format, uint32_t level)
1514 {
1515 struct tu_native_format fmt =
1516 tu6_format_color(format, image->layout.tile_mode);
1517 fmt.tile_mode = tu6_get_image_tile_mode(image, level);
1518 return fmt;
1519 }
1520
1521 static inline struct tu_native_format
1522 tu6_format_image_src(struct tu_image *image, VkFormat format, uint32_t level)
1523 {
1524 struct tu_native_format fmt =
1525 tu6_format_texture(format, image->layout.tile_mode);
1526 fmt.tile_mode = tu6_get_image_tile_mode(image, level);
1527 return fmt;
1528 }
1529
1530 struct tu_image_view
1531 {
1532 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1533
1534 VkImageViewType type;
1535 VkImageAspectFlags aspect_mask;
1536 VkFormat vk_format;
1537 uint32_t base_layer;
1538 uint32_t layer_count;
1539 uint32_t base_mip;
1540 uint32_t level_count;
1541 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1542
1543 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1544
1545 /* Descriptor for use as a storage image as opposed to a sampled image.
1546 * This has a few differences for cube maps (e.g. type).
1547 */
1548 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1549 };
1550
1551 struct tu_sampler {
1552 uint32_t descriptor[A6XX_TEX_SAMP_DWORDS];
1553 };
1554
1555 VkResult
1556 tu_image_create(VkDevice _device,
1557 const VkImageCreateInfo *pCreateInfo,
1558 const VkAllocationCallbacks *alloc,
1559 VkImage *pImage,
1560 uint64_t modifier);
1561
1562 VkResult
1563 tu_image_from_gralloc(VkDevice device_h,
1564 const VkImageCreateInfo *base_info,
1565 const VkNativeBufferANDROID *gralloc_info,
1566 const VkAllocationCallbacks *alloc,
1567 VkImage *out_image_h);
1568
1569 void
1570 tu_image_view_init(struct tu_image_view *view,
1571 struct tu_device *device,
1572 const VkImageViewCreateInfo *pCreateInfo);
1573
1574 struct tu_buffer_view
1575 {
1576 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1577
1578 struct tu_buffer *buffer;
1579 };
1580 void
1581 tu_buffer_view_init(struct tu_buffer_view *view,
1582 struct tu_device *device,
1583 const VkBufferViewCreateInfo *pCreateInfo);
1584
1585 static inline struct VkExtent3D
1586 tu_sanitize_image_extent(const VkImageType imageType,
1587 const struct VkExtent3D imageExtent)
1588 {
1589 switch (imageType) {
1590 case VK_IMAGE_TYPE_1D:
1591 return (VkExtent3D) { imageExtent.width, 1, 1 };
1592 case VK_IMAGE_TYPE_2D:
1593 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1594 case VK_IMAGE_TYPE_3D:
1595 return imageExtent;
1596 default:
1597 unreachable("invalid image type");
1598 }
1599 }
1600
1601 static inline struct VkOffset3D
1602 tu_sanitize_image_offset(const VkImageType imageType,
1603 const struct VkOffset3D imageOffset)
1604 {
1605 switch (imageType) {
1606 case VK_IMAGE_TYPE_1D:
1607 return (VkOffset3D) { imageOffset.x, 0, 0 };
1608 case VK_IMAGE_TYPE_2D:
1609 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1610 case VK_IMAGE_TYPE_3D:
1611 return imageOffset;
1612 default:
1613 unreachable("invalid image type");
1614 }
1615 }
1616
1617 struct tu_attachment_info
1618 {
1619 struct tu_image_view *attachment;
1620 };
1621
1622 struct tu_framebuffer
1623 {
1624 uint32_t width;
1625 uint32_t height;
1626 uint32_t layers;
1627
1628 uint32_t attachment_count;
1629 struct tu_attachment_info attachments[0];
1630 };
1631
1632 struct tu_subpass_attachment
1633 {
1634 uint32_t attachment;
1635 };
1636
1637 struct tu_subpass
1638 {
1639 uint32_t input_count;
1640 uint32_t color_count;
1641 struct tu_subpass_attachment *input_attachments;
1642 struct tu_subpass_attachment *color_attachments;
1643 struct tu_subpass_attachment *resolve_attachments;
1644 struct tu_subpass_attachment depth_stencil_attachment;
1645
1646 VkSampleCountFlagBits samples;
1647 };
1648
1649 struct tu_render_pass_attachment
1650 {
1651 VkFormat format;
1652 uint32_t samples;
1653 uint32_t cpp;
1654 VkAttachmentLoadOp load_op;
1655 VkAttachmentLoadOp stencil_load_op;
1656 VkAttachmentStoreOp store_op;
1657 VkAttachmentStoreOp stencil_store_op;
1658 int32_t gmem_offset;
1659 };
1660
1661 struct tu_render_pass
1662 {
1663 uint32_t attachment_count;
1664 uint32_t subpass_count;
1665 uint32_t gmem_pixels;
1666 struct tu_subpass_attachment *subpass_attachments;
1667 struct tu_render_pass_attachment *attachments;
1668 struct tu_subpass subpasses[0];
1669 };
1670
1671 VkResult
1672 tu_device_init_meta(struct tu_device *device);
1673 void
1674 tu_device_finish_meta(struct tu_device *device);
1675
1676 struct tu_query_pool
1677 {
1678 VkQueryType type;
1679 uint32_t stride;
1680 uint64_t size;
1681 uint32_t pipeline_statistics;
1682 struct tu_bo bo;
1683 };
1684
1685 struct tu_semaphore
1686 {
1687 uint32_t syncobj;
1688 uint32_t temp_syncobj;
1689 };
1690
1691 void
1692 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1693 VkPipelineBindPoint bind_point,
1694 struct tu_descriptor_set *set,
1695 unsigned idx);
1696
1697 void
1698 tu_update_descriptor_sets(struct tu_device *device,
1699 struct tu_cmd_buffer *cmd_buffer,
1700 VkDescriptorSet overrideSet,
1701 uint32_t descriptorWriteCount,
1702 const VkWriteDescriptorSet *pDescriptorWrites,
1703 uint32_t descriptorCopyCount,
1704 const VkCopyDescriptorSet *pDescriptorCopies);
1705
1706 void
1707 tu_update_descriptor_set_with_template(
1708 struct tu_device *device,
1709 struct tu_cmd_buffer *cmd_buffer,
1710 struct tu_descriptor_set *set,
1711 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1712 const void *pData);
1713
1714 void
1715 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1716 VkPipelineBindPoint pipelineBindPoint,
1717 VkPipelineLayout _layout,
1718 uint32_t set,
1719 uint32_t descriptorWriteCount,
1720 const VkWriteDescriptorSet *pDescriptorWrites);
1721
1722 int
1723 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1724
1725 int
1726 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1727
1728 int
1729 tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
1730
1731 int
1732 tu_drm_submitqueue_new(const struct tu_device *dev,
1733 int priority,
1734 uint32_t *queue_id);
1735
1736 void
1737 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1738
1739 uint32_t
1740 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1741 uint32_t
1742 tu_gem_import_dmabuf(const struct tu_device *dev,
1743 int prime_fd,
1744 uint64_t size);
1745 int
1746 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1747 void
1748 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1749 uint64_t
1750 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1751 uint64_t
1752 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1753
1754 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1755 \
1756 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1757 { \
1758 return (struct __tu_type *) _handle; \
1759 } \
1760 \
1761 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1762 { \
1763 return (__VkType) _obj; \
1764 }
1765
1766 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1767 \
1768 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1769 { \
1770 return (struct __tu_type *) (uintptr_t) _handle; \
1771 } \
1772 \
1773 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1774 { \
1775 return (__VkType)(uintptr_t) _obj; \
1776 }
1777
1778 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1779 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1780
1781 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1782 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1783 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1784 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1785 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1786
1787 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1788 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1789 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1790 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1791 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1792 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1793 VkDescriptorSetLayout)
1794 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1795 VkDescriptorUpdateTemplate)
1796 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1797 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1798 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1799 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1800 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1801 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1802 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1803 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1804 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1805 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1806 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1807 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1808 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1809 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1810
1811 #endif /* TU_PRIVATE_H */