tu: Rewrite border color handling
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #define MAX_VBS 32
81 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_RTS 8
83 #define MAX_VSC_PIPES 32
84 #define MAX_VIEWPORTS 1
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
90 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
91 #define MAX_DYNAMIC_BUFFERS \
92 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define TU_MAX_DRM_DEVICES 8
96 #define MAX_VIEWS 8
97 /* The Qualcomm driver exposes 0x20000058 */
98 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
99
100 #define NUM_DEPTH_CLEAR_PIPELINES 3
101
102 /*
103 * This is the point we switch from using CP to compute shader
104 * for certain buffer operations.
105 */
106 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
107
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
110
111 enum tu_mem_heap
112 {
113 TU_MEM_HEAP_VRAM,
114 TU_MEM_HEAP_VRAM_CPU_ACCESS,
115 TU_MEM_HEAP_GTT,
116 TU_MEM_HEAP_COUNT
117 };
118
119 enum tu_mem_type
120 {
121 TU_MEM_TYPE_VRAM,
122 TU_MEM_TYPE_GTT_WRITE_COMBINE,
123 TU_MEM_TYPE_VRAM_CPU_ACCESS,
124 TU_MEM_TYPE_GTT_CACHED,
125 TU_MEM_TYPE_COUNT
126 };
127
128 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 tu_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 tu_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 tu_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
212
213 #define typed_memcpy(dest, src, count) \
214 ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 #define COND(bool, val) ((bool) ? (val) : 0)
220
221 /* Whenever we generate an error, pass it through this function. Useful for
222 * debugging, where we can break on it. Only call at error site, not when
223 * propagating errors. Might be useful to plug in a stack trace here.
224 */
225
226 struct tu_instance;
227
228 VkResult
229 __vk_errorf(struct tu_instance *instance,
230 VkResult error,
231 const char *file,
232 int line,
233 const char *format,
234 ...);
235
236 #define vk_error(instance, error) \
237 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
238 #define vk_errorf(instance, error, format, ...) \
239 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
240
241 void
242 __tu_finishme(const char *file, int line, const char *format, ...)
243 tu_printflike(3, 4);
244 void
245 tu_loge(const char *format, ...) tu_printflike(1, 2);
246 void
247 tu_loge_v(const char *format, va_list va);
248 void
249 tu_logi(const char *format, ...) tu_printflike(1, 2);
250 void
251 tu_logi_v(const char *format, va_list va);
252
253 /**
254 * Print a FINISHME message, including its source location.
255 */
256 #define tu_finishme(format, ...) \
257 do { \
258 static bool reported = false; \
259 if (!reported) { \
260 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
261 reported = true; \
262 } \
263 } while (0)
264
265 /* A non-fatal assert. Useful for debugging. */
266 #ifdef DEBUG
267 #define tu_assert(x) \
268 ({ \
269 if (unlikely(!(x))) \
270 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 })
272 #else
273 #define tu_assert(x)
274 #endif
275
276 /* Suppress -Wunused in stub functions */
277 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
278 static inline void
279 __tu_use_args(int ignore, ...)
280 {
281 }
282
283 #define tu_stub() \
284 do { \
285 tu_finishme("stub %s", __func__); \
286 } while (0)
287
288 void *
289 tu_lookup_entrypoint_unchecked(const char *name);
290 void *
291 tu_lookup_entrypoint_checked(
292 const char *name,
293 uint32_t core_version,
294 const struct tu_instance_extension_table *instance,
295 const struct tu_device_extension_table *device);
296
297 struct tu_physical_device
298 {
299 VK_LOADER_DATA _loader_data;
300
301 struct tu_instance *instance;
302
303 char path[20];
304 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
305 uint8_t driver_uuid[VK_UUID_SIZE];
306 uint8_t device_uuid[VK_UUID_SIZE];
307 uint8_t cache_uuid[VK_UUID_SIZE];
308
309 struct wsi_device wsi_device;
310
311 int local_fd;
312 int master_fd;
313
314 unsigned gpu_id;
315 uint32_t gmem_size;
316 uint64_t gmem_base;
317 uint32_t tile_align_w;
318 uint32_t tile_align_h;
319
320 struct {
321 uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */
322 uint32_t RB_CCU_CNTL_gmem; /* for GMEM */
323 uint32_t PC_UNKNOWN_9805;
324 uint32_t SP_UNKNOWN_A0F8;
325 } magic;
326
327 /* This is the drivers on-disk cache used as a fallback as opposed to
328 * the pipeline cache defined by apps.
329 */
330 struct disk_cache *disk_cache;
331
332 struct tu_device_extension_table supported_extensions;
333 };
334
335 enum tu_debug_flags
336 {
337 TU_DEBUG_STARTUP = 1 << 0,
338 TU_DEBUG_NIR = 1 << 1,
339 TU_DEBUG_IR3 = 1 << 2,
340 TU_DEBUG_NOBIN = 1 << 3,
341 TU_DEBUG_SYSMEM = 1 << 4,
342 TU_DEBUG_FORCEBIN = 1 << 5,
343 };
344
345 struct tu_instance
346 {
347 VK_LOADER_DATA _loader_data;
348
349 VkAllocationCallbacks alloc;
350
351 uint32_t api_version;
352 int physical_device_count;
353 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
354
355 enum tu_debug_flags debug_flags;
356
357 struct vk_debug_report_instance debug_report_callbacks;
358
359 struct tu_instance_extension_table enabled_extensions;
360 };
361
362 VkResult
363 tu_wsi_init(struct tu_physical_device *physical_device);
364 void
365 tu_wsi_finish(struct tu_physical_device *physical_device);
366
367 bool
368 tu_instance_extension_supported(const char *name);
369 uint32_t
370 tu_physical_device_api_version(struct tu_physical_device *dev);
371 bool
372 tu_physical_device_extension_supported(struct tu_physical_device *dev,
373 const char *name);
374
375 struct cache_entry;
376
377 struct tu_pipeline_cache
378 {
379 struct tu_device *device;
380 pthread_mutex_t mutex;
381
382 uint32_t total_size;
383 uint32_t table_size;
384 uint32_t kernel_count;
385 struct cache_entry **hash_table;
386 bool modified;
387
388 VkAllocationCallbacks alloc;
389 };
390
391 struct tu_pipeline_key
392 {
393 };
394
395 void
396 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
397 struct tu_device *device);
398 void
399 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
400 void
401 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
402 const void *data,
403 size_t size);
404
405 struct tu_shader_variant;
406
407 bool
408 tu_create_shader_variants_from_pipeline_cache(
409 struct tu_device *device,
410 struct tu_pipeline_cache *cache,
411 const unsigned char *sha1,
412 struct tu_shader_variant **variants);
413
414 void
415 tu_pipeline_cache_insert_shaders(struct tu_device *device,
416 struct tu_pipeline_cache *cache,
417 const unsigned char *sha1,
418 struct tu_shader_variant **variants,
419 const void *const *codes,
420 const unsigned *code_sizes);
421
422 struct tu_meta_state
423 {
424 VkAllocationCallbacks alloc;
425
426 struct tu_pipeline_cache cache;
427 };
428
429 /* queue types */
430 #define TU_QUEUE_GENERAL 0
431
432 #define TU_MAX_QUEUE_FAMILIES 1
433
434 struct tu_fence
435 {
436 struct wsi_fence *fence_wsi;
437 bool signaled;
438 int fd;
439 };
440
441 void
442 tu_fence_init(struct tu_fence *fence, bool signaled);
443 void
444 tu_fence_finish(struct tu_fence *fence);
445 void
446 tu_fence_update_fd(struct tu_fence *fence, int fd);
447 void
448 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
449 void
450 tu_fence_signal(struct tu_fence *fence);
451 void
452 tu_fence_wait_idle(struct tu_fence *fence);
453
454 struct tu_queue
455 {
456 VK_LOADER_DATA _loader_data;
457 struct tu_device *device;
458 uint32_t queue_family_index;
459 int queue_idx;
460 VkDeviceQueueCreateFlags flags;
461
462 uint32_t msm_queue_id;
463 struct tu_fence submit_fence;
464 };
465
466 struct tu_bo
467 {
468 uint32_t gem_handle;
469 uint64_t size;
470 uint64_t iova;
471 void *map;
472 };
473
474 struct tu_device
475 {
476 VK_LOADER_DATA _loader_data;
477
478 VkAllocationCallbacks alloc;
479
480 struct tu_instance *instance;
481
482 struct tu_meta_state meta_state;
483
484 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
485 int queue_count[TU_MAX_QUEUE_FAMILIES];
486
487 struct tu_physical_device *physical_device;
488
489 struct ir3_compiler *compiler;
490
491 /* Backup in-memory cache to be used if the app doesn't provide one */
492 struct tu_pipeline_cache *mem_cache;
493
494 struct tu_bo vsc_data;
495 struct tu_bo vsc_data2;
496 uint32_t vsc_data_pitch;
497 uint32_t vsc_data2_pitch;
498
499 struct tu_bo border_color;
500
501 struct list_head shader_slabs;
502 mtx_t shader_slab_mutex;
503
504 struct tu_device_extension_table enabled_extensions;
505 };
506
507 VkResult
508 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
509 VkResult
510 tu_bo_init_dmabuf(struct tu_device *dev,
511 struct tu_bo *bo,
512 uint64_t size,
513 int fd);
514 int
515 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
516 void
517 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
518 VkResult
519 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
520
521 struct tu_cs_entry
522 {
523 /* No ownership */
524 const struct tu_bo *bo;
525
526 uint32_t size;
527 uint32_t offset;
528 };
529
530 struct ts_cs_memory {
531 uint32_t *map;
532 uint64_t iova;
533 };
534
535 enum tu_cs_mode
536 {
537
538 /*
539 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
540 * is full. tu_cs_begin must be called before command packet emission and
541 * tu_cs_end must be called after.
542 *
543 * This mode may create multiple entries internally. The entries must be
544 * submitted together.
545 */
546 TU_CS_MODE_GROW,
547
548 /*
549 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
550 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
551 * effect on it.
552 *
553 * This mode does not create any entry or any BO.
554 */
555 TU_CS_MODE_EXTERNAL,
556
557 /*
558 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
559 * command packet emission. tu_cs_begin_sub_stream must be called to get a
560 * sub-stream to emit comamnd packets to. When done with the sub-stream,
561 * tu_cs_end_sub_stream must be called.
562 *
563 * This mode does not create any entry internally.
564 */
565 TU_CS_MODE_SUB_STREAM,
566 };
567
568 struct tu_cs
569 {
570 uint32_t *start;
571 uint32_t *cur;
572 uint32_t *reserved_end;
573 uint32_t *end;
574
575 struct tu_device *device;
576 enum tu_cs_mode mode;
577 uint32_t next_bo_size;
578
579 struct tu_cs_entry *entries;
580 uint32_t entry_count;
581 uint32_t entry_capacity;
582
583 struct tu_bo **bos;
584 uint32_t bo_count;
585 uint32_t bo_capacity;
586
587 /* state for cond_exec_start/cond_exec_end */
588 uint32_t cond_flags;
589 uint32_t *cond_dwords;
590 };
591
592 struct tu_device_memory
593 {
594 struct tu_bo bo;
595 VkDeviceSize size;
596
597 /* for dedicated allocations */
598 struct tu_image *image;
599 struct tu_buffer *buffer;
600
601 uint32_t type_index;
602 void *map;
603 void *user_ptr;
604 };
605
606 struct tu_descriptor_range
607 {
608 uint64_t va;
609 uint32_t size;
610 };
611
612 struct tu_descriptor_set
613 {
614 const struct tu_descriptor_set_layout *layout;
615 uint32_t size;
616
617 uint64_t va;
618 uint32_t *mapped_ptr;
619 struct tu_descriptor_range *dynamic_descriptors;
620
621 struct tu_bo *descriptors[0];
622 };
623
624 struct tu_push_descriptor_set
625 {
626 struct tu_descriptor_set set;
627 uint32_t capacity;
628 };
629
630 struct tu_descriptor_pool_entry
631 {
632 uint32_t offset;
633 uint32_t size;
634 struct tu_descriptor_set *set;
635 };
636
637 struct tu_descriptor_pool
638 {
639 struct tu_bo bo;
640 uint64_t current_offset;
641 uint64_t size;
642
643 uint8_t *host_memory_base;
644 uint8_t *host_memory_ptr;
645 uint8_t *host_memory_end;
646
647 uint32_t entry_count;
648 uint32_t max_entry_count;
649 struct tu_descriptor_pool_entry entries[0];
650 };
651
652 struct tu_descriptor_update_template_entry
653 {
654 VkDescriptorType descriptor_type;
655
656 /* The number of descriptors to update */
657 uint32_t descriptor_count;
658
659 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
660 */
661 uint32_t dst_offset;
662
663 /* In dwords. Not valid/used for dynamic descriptors */
664 uint32_t dst_stride;
665
666 uint32_t buffer_offset;
667
668 /* Only valid for combined image samplers and samplers */
669 uint16_t has_sampler;
670
671 /* In bytes */
672 size_t src_offset;
673 size_t src_stride;
674
675 /* For push descriptors */
676 const uint32_t *immutable_samplers;
677 };
678
679 struct tu_descriptor_update_template
680 {
681 uint32_t entry_count;
682 VkPipelineBindPoint bind_point;
683 struct tu_descriptor_update_template_entry entry[0];
684 };
685
686 struct tu_buffer
687 {
688 VkDeviceSize size;
689
690 VkBufferUsageFlags usage;
691 VkBufferCreateFlags flags;
692
693 struct tu_bo *bo;
694 VkDeviceSize bo_offset;
695 };
696
697 static inline uint64_t
698 tu_buffer_iova(struct tu_buffer *buffer)
699 {
700 return buffer->bo->iova + buffer->bo_offset;
701 }
702
703 enum tu_dynamic_state_bits
704 {
705 TU_DYNAMIC_VIEWPORT = 1 << 0,
706 TU_DYNAMIC_SCISSOR = 1 << 1,
707 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
708 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
709 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
710 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
711 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
712 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
713 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
714 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
715 TU_DYNAMIC_ALL = (1 << 10) - 1,
716 };
717
718 struct tu_vertex_binding
719 {
720 struct tu_buffer *buffer;
721 VkDeviceSize offset;
722 };
723
724 struct tu_viewport_state
725 {
726 uint32_t count;
727 VkViewport viewports[MAX_VIEWPORTS];
728 };
729
730 struct tu_scissor_state
731 {
732 uint32_t count;
733 VkRect2D scissors[MAX_SCISSORS];
734 };
735
736 struct tu_discard_rectangle_state
737 {
738 uint32_t count;
739 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
740 };
741
742 struct tu_dynamic_state
743 {
744 /**
745 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
746 * Defines the set of saved dynamic state.
747 */
748 uint32_t mask;
749
750 struct tu_viewport_state viewport;
751
752 struct tu_scissor_state scissor;
753
754 float line_width;
755
756 struct
757 {
758 float bias;
759 float clamp;
760 float slope;
761 } depth_bias;
762
763 float blend_constants[4];
764
765 struct
766 {
767 float min;
768 float max;
769 } depth_bounds;
770
771 struct
772 {
773 uint32_t front;
774 uint32_t back;
775 } stencil_compare_mask;
776
777 struct
778 {
779 uint32_t front;
780 uint32_t back;
781 } stencil_write_mask;
782
783 struct
784 {
785 uint32_t front;
786 uint32_t back;
787 } stencil_reference;
788
789 struct tu_discard_rectangle_state discard_rectangle;
790 };
791
792 extern const struct tu_dynamic_state default_dynamic_state;
793
794 const char *
795 tu_get_debug_option_name(int id);
796
797 const char *
798 tu_get_perftest_option_name(int id);
799
800 struct tu_descriptor_state
801 {
802 struct tu_descriptor_set *sets[MAX_SETS];
803 uint32_t valid;
804 struct tu_push_descriptor_set push_set;
805 bool push_dirty;
806 uint64_t dynamic_buffers[MAX_DYNAMIC_BUFFERS];
807 };
808
809 struct tu_tile
810 {
811 uint8_t pipe;
812 uint8_t slot;
813 VkOffset2D begin;
814 VkOffset2D end;
815 };
816
817 struct tu_tiling_config
818 {
819 VkRect2D render_area;
820
821 /* position and size of the first tile */
822 VkRect2D tile0;
823 /* number of tiles */
824 VkExtent2D tile_count;
825
826 /* size of the first VSC pipe */
827 VkExtent2D pipe0;
828 /* number of VSC pipes */
829 VkExtent2D pipe_count;
830
831 /* pipe register values */
832 uint32_t pipe_config[MAX_VSC_PIPES];
833 uint32_t pipe_sizes[MAX_VSC_PIPES];
834
835 /* Whether sysmem rendering must be used */
836 bool force_sysmem;
837 };
838
839 enum tu_cmd_dirty_bits
840 {
841 TU_CMD_DIRTY_PIPELINE = 1 << 0,
842 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
843 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
844 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
845 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
846 TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 5,
847
848 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
849 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
850 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
851 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
852 };
853
854 struct tu_streamout_state {
855 uint16_t stride[IR3_MAX_SO_BUFFERS];
856 uint32_t ncomp[IR3_MAX_SO_BUFFERS];
857 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
858 uint32_t prog_count;
859 uint32_t vpc_so_buf_cntl;
860 };
861
862 struct tu_cmd_state
863 {
864 uint32_t dirty;
865
866 struct tu_pipeline *pipeline;
867 struct tu_pipeline *compute_pipeline;
868
869 /* Vertex buffers */
870 struct
871 {
872 struct tu_buffer *buffers[MAX_VBS];
873 VkDeviceSize offsets[MAX_VBS];
874 } vb;
875
876 struct tu_dynamic_state dynamic;
877
878 /* Stream output buffers */
879 struct
880 {
881 struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
882 VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
883 VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
884 } streamout_buf;
885
886 uint8_t streamout_reset;
887 uint8_t streamout_enabled;
888
889 /* Index buffer */
890 struct tu_buffer *index_buffer;
891 uint64_t index_offset;
892 uint32_t index_type;
893 uint32_t max_index_count;
894 uint64_t index_va;
895
896 const struct tu_render_pass *pass;
897 const struct tu_subpass *subpass;
898 const struct tu_framebuffer *framebuffer;
899
900 struct tu_tiling_config tiling_config;
901
902 struct tu_cs_entry tile_store_ib;
903 };
904
905 struct tu_cmd_pool
906 {
907 VkAllocationCallbacks alloc;
908 struct list_head cmd_buffers;
909 struct list_head free_cmd_buffers;
910 uint32_t queue_family_index;
911 };
912
913 struct tu_cmd_buffer_upload
914 {
915 uint8_t *map;
916 unsigned offset;
917 uint64_t size;
918 struct list_head list;
919 };
920
921 enum tu_cmd_buffer_status
922 {
923 TU_CMD_BUFFER_STATUS_INVALID,
924 TU_CMD_BUFFER_STATUS_INITIAL,
925 TU_CMD_BUFFER_STATUS_RECORDING,
926 TU_CMD_BUFFER_STATUS_EXECUTABLE,
927 TU_CMD_BUFFER_STATUS_PENDING,
928 };
929
930 struct tu_bo_list
931 {
932 uint32_t count;
933 uint32_t capacity;
934 struct drm_msm_gem_submit_bo *bo_infos;
935 };
936
937 #define TU_BO_LIST_FAILED (~0)
938
939 void
940 tu_bo_list_init(struct tu_bo_list *list);
941 void
942 tu_bo_list_destroy(struct tu_bo_list *list);
943 void
944 tu_bo_list_reset(struct tu_bo_list *list);
945 uint32_t
946 tu_bo_list_add(struct tu_bo_list *list,
947 const struct tu_bo *bo,
948 uint32_t flags);
949 VkResult
950 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
951
952 /* This struct defines the layout of the scratch_bo */
953 struct tu6_control
954 {
955 uint32_t seqno; /* seqno for async CP_EVENT_WRITE, etc */
956 uint32_t _pad0;
957 volatile uint32_t vsc_overflow;
958 uint32_t _pad1;
959 /* flag set from cmdstream when VSC overflow detected: */
960 uint32_t vsc_scratch;
961 uint32_t _pad2;
962 uint32_t _pad3;
963 uint32_t _pad4;
964
965 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
966 struct {
967 uint32_t offset;
968 uint32_t pad[7];
969 } flush_base[4];
970 };
971
972 #define ctrl_offset(member) offsetof(struct tu6_control, member)
973
974 struct tu_cmd_buffer
975 {
976 VK_LOADER_DATA _loader_data;
977
978 struct tu_device *device;
979
980 struct tu_cmd_pool *pool;
981 struct list_head pool_link;
982
983 VkCommandBufferUsageFlags usage_flags;
984 VkCommandBufferLevel level;
985 enum tu_cmd_buffer_status status;
986
987 struct tu_cmd_state state;
988 struct tu_vertex_binding vertex_bindings[MAX_VBS];
989 uint32_t queue_family_index;
990
991 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
992 VkShaderStageFlags push_constant_stages;
993 struct tu_descriptor_set meta_push_descriptors;
994
995 struct tu_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
996
997 struct tu_cmd_buffer_upload upload;
998
999 VkResult record_result;
1000
1001 struct tu_bo_list bo_list;
1002 struct tu_cs cs;
1003 struct tu_cs draw_cs;
1004 struct tu_cs draw_epilogue_cs;
1005 struct tu_cs sub_cs;
1006
1007 struct tu_bo scratch_bo;
1008 uint32_t scratch_seqno;
1009
1010 struct tu_bo vsc_data;
1011 struct tu_bo vsc_data2;
1012 uint32_t vsc_data_pitch;
1013 uint32_t vsc_data2_pitch;
1014 bool use_vsc_data;
1015
1016 bool wait_for_idle;
1017 };
1018
1019 /* Temporary struct for tracking a register state to be written, used by
1020 * a6xx-pack.h and tu_cs_emit_regs()
1021 */
1022 struct tu_reg_value {
1023 uint32_t reg;
1024 uint64_t value;
1025 bool is_address;
1026 struct tu_bo *bo;
1027 bool bo_write;
1028 uint32_t bo_offset;
1029 uint32_t bo_shift;
1030 };
1031
1032 unsigned
1033 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
1034 struct tu_cs *cs,
1035 enum vgt_event_type event,
1036 bool need_seqno);
1037
1038 bool
1039 tu_get_memory_fd(struct tu_device *device,
1040 struct tu_device_memory *memory,
1041 int *pFD);
1042
1043 static inline struct tu_descriptor_state *
1044 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1045 VkPipelineBindPoint bind_point)
1046 {
1047 return &cmd_buffer->descriptors[bind_point];
1048 }
1049
1050 /*
1051 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1052 *
1053 * Limitations: Can't call normal dispatch functions without binding or
1054 * rebinding
1055 * the compute pipeline.
1056 */
1057 void
1058 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1059 uint32_t x,
1060 uint32_t y,
1061 uint32_t z);
1062
1063 struct tu_event
1064 {
1065 struct tu_bo bo;
1066 };
1067
1068 struct tu_shader_module;
1069
1070 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1071 #define TU_HASH_SHADER_SISCHED (1 << 1)
1072 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1073 void
1074 tu_hash_shaders(unsigned char *hash,
1075 const VkPipelineShaderStageCreateInfo **stages,
1076 const struct tu_pipeline_layout *layout,
1077 const struct tu_pipeline_key *key,
1078 uint32_t flags);
1079
1080 static inline gl_shader_stage
1081 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1082 {
1083 assert(__builtin_popcount(vk_stage) == 1);
1084 return ffs(vk_stage) - 1;
1085 }
1086
1087 static inline VkShaderStageFlagBits
1088 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1089 {
1090 return (1 << mesa_stage);
1091 }
1092
1093 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1094
1095 #define tu_foreach_stage(stage, stage_bits) \
1096 for (gl_shader_stage stage, \
1097 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1098 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1099
1100 struct tu_shader_module
1101 {
1102 unsigned char sha1[20];
1103
1104 uint32_t code_size;
1105 const uint32_t *code[0];
1106 };
1107
1108 struct tu_shader_compile_options
1109 {
1110 struct ir3_shader_key key;
1111
1112 bool optimize;
1113 bool include_binning_pass;
1114 };
1115
1116 struct tu_descriptor_map
1117 {
1118 /* TODO: avoid fixed size array/justify the size */
1119 unsigned num; /* number of array entries */
1120 unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
1121 int set[128];
1122 int binding[128];
1123 int value[128];
1124 int array_size[128];
1125 };
1126
1127 struct tu_shader
1128 {
1129 struct ir3_shader ir3_shader;
1130
1131 struct tu_descriptor_map texture_map;
1132 struct tu_descriptor_map sampler_map;
1133 struct tu_descriptor_map ubo_map;
1134 struct tu_descriptor_map ssbo_map;
1135 struct tu_descriptor_map image_map;
1136
1137 /* This may be true for vertex shaders. When true, variants[1] is the
1138 * binning variant and binning_binary is non-NULL.
1139 */
1140 bool has_binning_pass;
1141
1142 void *binary;
1143 void *binning_binary;
1144
1145 struct ir3_shader_variant variants[0];
1146 };
1147
1148 struct tu_shader *
1149 tu_shader_create(struct tu_device *dev,
1150 gl_shader_stage stage,
1151 const VkPipelineShaderStageCreateInfo *stage_info,
1152 struct tu_pipeline_layout *layout,
1153 const VkAllocationCallbacks *alloc);
1154
1155 void
1156 tu_shader_destroy(struct tu_device *dev,
1157 struct tu_shader *shader,
1158 const VkAllocationCallbacks *alloc);
1159
1160 void
1161 tu_shader_compile_options_init(
1162 struct tu_shader_compile_options *options,
1163 const VkGraphicsPipelineCreateInfo *pipeline_info);
1164
1165 VkResult
1166 tu_shader_compile(struct tu_device *dev,
1167 struct tu_shader *shader,
1168 const struct tu_shader *next_stage,
1169 const struct tu_shader_compile_options *options,
1170 const VkAllocationCallbacks *alloc);
1171
1172 struct tu_program_descriptor_linkage
1173 {
1174 struct ir3_ubo_analysis_state ubo_state;
1175 struct ir3_const_state const_state;
1176
1177 uint32_t constlen;
1178
1179 struct tu_descriptor_map texture_map;
1180 struct tu_descriptor_map sampler_map;
1181 struct tu_descriptor_map ubo_map;
1182 struct tu_descriptor_map ssbo_map;
1183 struct tu_descriptor_map image_map;
1184 };
1185
1186 struct tu_pipeline
1187 {
1188 struct tu_cs cs;
1189
1190 struct tu_dynamic_state dynamic_state;
1191
1192 struct tu_pipeline_layout *layout;
1193
1194 bool need_indirect_descriptor_sets;
1195 VkShaderStageFlags active_stages;
1196
1197 struct tu_streamout_state streamout;
1198
1199 struct
1200 {
1201 struct tu_bo binary_bo;
1202 struct tu_cs_entry state_ib;
1203 struct tu_cs_entry binning_state_ib;
1204
1205 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1206 } program;
1207
1208 struct
1209 {
1210 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1211 uint16_t strides[MAX_VERTEX_ATTRIBS];
1212 uint16_t offsets[MAX_VERTEX_ATTRIBS];
1213 uint32_t count;
1214
1215 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1216 uint16_t binning_strides[MAX_VERTEX_ATTRIBS];
1217 uint16_t binning_offsets[MAX_VERTEX_ATTRIBS];
1218 uint32_t binning_count;
1219
1220 struct tu_cs_entry state_ib;
1221 struct tu_cs_entry binning_state_ib;
1222 } vi;
1223
1224 struct
1225 {
1226 enum pc_di_primtype primtype;
1227 bool primitive_restart;
1228 } ia;
1229
1230 struct
1231 {
1232 struct tu_cs_entry state_ib;
1233 } vp;
1234
1235 struct
1236 {
1237 uint32_t gras_su_cntl;
1238 struct tu_cs_entry state_ib;
1239 } rast;
1240
1241 struct
1242 {
1243 struct tu_cs_entry state_ib;
1244 } ds;
1245
1246 struct
1247 {
1248 struct tu_cs_entry state_ib;
1249 } blend;
1250
1251 struct
1252 {
1253 uint32_t local_size[3];
1254 } compute;
1255 };
1256
1257 void
1258 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1259
1260 void
1261 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1262
1263 void
1264 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1265 uint32_t gras_su_cntl,
1266 float line_width);
1267
1268 void
1269 tu6_emit_depth_bias(struct tu_cs *cs,
1270 float constant_factor,
1271 float clamp,
1272 float slope_factor);
1273
1274 void
1275 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1276 uint32_t front,
1277 uint32_t back);
1278
1279 void
1280 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1281
1282 void
1283 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1284
1285 void
1286 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1287
1288 struct tu_userdata_info *
1289 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1290 gl_shader_stage stage,
1291 int idx);
1292
1293 struct tu_shader_variant *
1294 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1295
1296 struct tu_graphics_pipeline_create_info
1297 {
1298 bool use_rectlist;
1299 bool db_depth_clear;
1300 bool db_stencil_clear;
1301 bool db_depth_disable_expclear;
1302 bool db_stencil_disable_expclear;
1303 bool db_flush_depth_inplace;
1304 bool db_flush_stencil_inplace;
1305 bool db_resummarize;
1306 uint32_t custom_blend_mode;
1307 };
1308
1309 enum tu_supported_formats {
1310 FMT_VERTEX = 1,
1311 FMT_TEXTURE = 2,
1312 FMT_COLOR = 4,
1313 };
1314
1315 struct tu_native_format
1316 {
1317 enum a6xx_format fmt : 8;
1318 enum a3xx_color_swap swap : 8;
1319 enum tu_supported_formats supported : 8;
1320 };
1321
1322 struct tu_native_format tu6_get_native_format(VkFormat format);
1323 struct tu_native_format tu6_format_vtx(VkFormat format);
1324 enum a6xx_format tu6_format_gmem(VkFormat format);
1325 struct tu_native_format tu6_format_color(VkFormat format, bool tiled);
1326 struct tu_native_format tu6_format_texture(VkFormat format, bool tiled);
1327
1328 void
1329 tu_pack_clear_value(const VkClearValue *val,
1330 VkFormat format,
1331 uint32_t buf[4]);
1332
1333 void
1334 tu_2d_clear_color(const VkClearColorValue *val, VkFormat format, uint32_t buf[4]);
1335
1336 void
1337 tu_2d_clear_zs(const VkClearDepthStencilValue *val, VkFormat format, uint32_t buf[4]);
1338
1339 enum a6xx_2d_ifmt tu6_fmt_to_ifmt(enum a6xx_format fmt);
1340 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1341
1342 struct tu_image_level
1343 {
1344 VkDeviceSize offset;
1345 VkDeviceSize size;
1346 uint32_t pitch;
1347 };
1348
1349 struct tu_image
1350 {
1351 VkImageType type;
1352 /* The original VkFormat provided by the client. This may not match any
1353 * of the actual surface formats.
1354 */
1355 VkFormat vk_format;
1356 VkImageAspectFlags aspects;
1357 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1358 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1359 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1360 VkExtent3D extent;
1361 uint32_t level_count;
1362 uint32_t layer_count;
1363 VkSampleCountFlagBits samples;
1364
1365
1366 uint32_t alignment;
1367
1368 struct fdl_layout layout;
1369
1370 unsigned queue_family_mask;
1371 bool exclusive;
1372 bool shareable;
1373
1374 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1375 VkDeviceMemory owned_memory;
1376
1377 /* Set when bound */
1378 struct tu_bo *bo;
1379 VkDeviceSize bo_offset;
1380 };
1381
1382 unsigned
1383 tu_image_queue_family_mask(const struct tu_image *image,
1384 uint32_t family,
1385 uint32_t queue_family);
1386
1387 static inline uint32_t
1388 tu_get_layerCount(const struct tu_image *image,
1389 const VkImageSubresourceRange *range)
1390 {
1391 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1392 ? image->layer_count - range->baseArrayLayer
1393 : range->layerCount;
1394 }
1395
1396 static inline uint32_t
1397 tu_get_levelCount(const struct tu_image *image,
1398 const VkImageSubresourceRange *range)
1399 {
1400 return range->levelCount == VK_REMAINING_MIP_LEVELS
1401 ? image->level_count - range->baseMipLevel
1402 : range->levelCount;
1403 }
1404
1405 static inline VkDeviceSize
1406 tu_layer_size(struct tu_image *image, int level)
1407 {
1408 return fdl_layer_stride(&image->layout, level);
1409 }
1410
1411 static inline uint32_t
1412 tu_image_stride(struct tu_image *image, int level)
1413 {
1414 return image->layout.slices[level].pitch * image->layout.cpp;
1415 }
1416
1417 static inline uint64_t
1418 tu_image_base(struct tu_image *image, int level, int layer)
1419 {
1420 return image->bo->iova + image->bo_offset +
1421 fdl_surface_offset(&image->layout, level, layer);
1422 }
1423
1424 #define tu_image_base_ref(image, level, layer) \
1425 .bo = image->bo, \
1426 .bo_offset = (image->bo_offset + fdl_surface_offset(&image->layout, \
1427 level, layer))
1428
1429 #define tu_image_view_base_ref(iview) \
1430 tu_image_base_ref(iview->image, iview->base_mip, iview->base_layer)
1431
1432 static inline VkDeviceSize
1433 tu_image_ubwc_size(struct tu_image *image, int level)
1434 {
1435 return image->layout.ubwc_layer_size;
1436 }
1437
1438 static inline uint32_t
1439 tu_image_ubwc_pitch(struct tu_image *image, int level)
1440 {
1441 return image->layout.ubwc_slices[level].pitch;
1442 }
1443
1444 static inline uint64_t
1445 tu_image_ubwc_surface_offset(struct tu_image *image, int level, int layer)
1446 {
1447 return image->layout.ubwc_slices[level].offset +
1448 layer * tu_image_ubwc_size(image, level);
1449 }
1450
1451 static inline uint64_t
1452 tu_image_ubwc_base(struct tu_image *image, int level, int layer)
1453 {
1454 return image->bo->iova + image->bo_offset +
1455 tu_image_ubwc_surface_offset(image, level, layer);
1456 }
1457
1458 #define tu_image_ubwc_base_ref(image, level, layer) \
1459 .bo = image->bo, \
1460 .bo_offset = (image->bo_offset + tu_image_ubwc_surface_offset(image, \
1461 level, layer))
1462
1463 #define tu_image_view_ubwc_base_ref(iview) \
1464 tu_image_ubwc_base_ref(iview->image, iview->base_mip, iview->base_layer)
1465
1466 enum a6xx_tile_mode
1467 tu6_get_image_tile_mode(struct tu_image *image, int level);
1468 enum a3xx_msaa_samples
1469 tu_msaa_samples(uint32_t samples);
1470
1471 struct tu_image_view
1472 {
1473 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1474
1475 VkImageViewType type;
1476 VkImageAspectFlags aspect_mask;
1477 VkFormat vk_format;
1478 uint32_t base_layer;
1479 uint32_t layer_count;
1480 uint32_t base_mip;
1481 uint32_t level_count;
1482 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1483
1484 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1485
1486 /* Descriptor for use as a storage image as opposed to a sampled image.
1487 * This has a few differences for cube maps (e.g. type).
1488 */
1489 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1490 };
1491
1492 struct tu_sampler {
1493 uint32_t descriptor[A6XX_TEX_SAMP_DWORDS];
1494 };
1495
1496 VkResult
1497 tu_image_create(VkDevice _device,
1498 const VkImageCreateInfo *pCreateInfo,
1499 const VkAllocationCallbacks *alloc,
1500 VkImage *pImage,
1501 uint64_t modifier);
1502
1503 VkResult
1504 tu_image_from_gralloc(VkDevice device_h,
1505 const VkImageCreateInfo *base_info,
1506 const VkNativeBufferANDROID *gralloc_info,
1507 const VkAllocationCallbacks *alloc,
1508 VkImage *out_image_h);
1509
1510 void
1511 tu_image_view_init(struct tu_image_view *view,
1512 struct tu_device *device,
1513 const VkImageViewCreateInfo *pCreateInfo);
1514
1515 struct tu_buffer_view
1516 {
1517 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1518
1519 struct tu_buffer *buffer;
1520 };
1521 void
1522 tu_buffer_view_init(struct tu_buffer_view *view,
1523 struct tu_device *device,
1524 const VkBufferViewCreateInfo *pCreateInfo);
1525
1526 static inline struct VkExtent3D
1527 tu_sanitize_image_extent(const VkImageType imageType,
1528 const struct VkExtent3D imageExtent)
1529 {
1530 switch (imageType) {
1531 case VK_IMAGE_TYPE_1D:
1532 return (VkExtent3D) { imageExtent.width, 1, 1 };
1533 case VK_IMAGE_TYPE_2D:
1534 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1535 case VK_IMAGE_TYPE_3D:
1536 return imageExtent;
1537 default:
1538 unreachable("invalid image type");
1539 }
1540 }
1541
1542 static inline struct VkOffset3D
1543 tu_sanitize_image_offset(const VkImageType imageType,
1544 const struct VkOffset3D imageOffset)
1545 {
1546 switch (imageType) {
1547 case VK_IMAGE_TYPE_1D:
1548 return (VkOffset3D) { imageOffset.x, 0, 0 };
1549 case VK_IMAGE_TYPE_2D:
1550 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1551 case VK_IMAGE_TYPE_3D:
1552 return imageOffset;
1553 default:
1554 unreachable("invalid image type");
1555 }
1556 }
1557
1558 struct tu_attachment_info
1559 {
1560 struct tu_image_view *attachment;
1561 };
1562
1563 struct tu_framebuffer
1564 {
1565 uint32_t width;
1566 uint32_t height;
1567 uint32_t layers;
1568
1569 uint32_t attachment_count;
1570 struct tu_attachment_info attachments[0];
1571 };
1572
1573 struct tu_subpass_attachment
1574 {
1575 uint32_t attachment;
1576 };
1577
1578 struct tu_subpass
1579 {
1580 uint32_t input_count;
1581 uint32_t color_count;
1582 struct tu_subpass_attachment *input_attachments;
1583 struct tu_subpass_attachment *color_attachments;
1584 struct tu_subpass_attachment *resolve_attachments;
1585 struct tu_subpass_attachment depth_stencil_attachment;
1586
1587 VkSampleCountFlagBits samples;
1588 };
1589
1590 struct tu_render_pass_attachment
1591 {
1592 VkFormat format;
1593 uint32_t cpp;
1594 VkAttachmentLoadOp load_op;
1595 VkAttachmentLoadOp stencil_load_op;
1596 VkAttachmentStoreOp store_op;
1597 VkAttachmentStoreOp stencil_store_op;
1598 int32_t gmem_offset;
1599 };
1600
1601 struct tu_render_pass
1602 {
1603 uint32_t attachment_count;
1604 uint32_t subpass_count;
1605 uint32_t gmem_pixels;
1606 struct tu_subpass_attachment *subpass_attachments;
1607 struct tu_render_pass_attachment *attachments;
1608 struct tu_subpass subpasses[0];
1609 };
1610
1611 VkResult
1612 tu_device_init_meta(struct tu_device *device);
1613 void
1614 tu_device_finish_meta(struct tu_device *device);
1615
1616 struct tu_query_pool
1617 {
1618 VkQueryType type;
1619 uint32_t stride;
1620 uint64_t size;
1621 uint32_t pipeline_statistics;
1622 struct tu_bo bo;
1623 };
1624
1625 struct tu_semaphore
1626 {
1627 uint32_t syncobj;
1628 uint32_t temp_syncobj;
1629 };
1630
1631 void
1632 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1633 VkPipelineBindPoint bind_point,
1634 struct tu_descriptor_set *set,
1635 unsigned idx);
1636
1637 void
1638 tu_update_descriptor_sets(struct tu_device *device,
1639 struct tu_cmd_buffer *cmd_buffer,
1640 VkDescriptorSet overrideSet,
1641 uint32_t descriptorWriteCount,
1642 const VkWriteDescriptorSet *pDescriptorWrites,
1643 uint32_t descriptorCopyCount,
1644 const VkCopyDescriptorSet *pDescriptorCopies);
1645
1646 void
1647 tu_update_descriptor_set_with_template(
1648 struct tu_device *device,
1649 struct tu_cmd_buffer *cmd_buffer,
1650 struct tu_descriptor_set *set,
1651 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1652 const void *pData);
1653
1654 void
1655 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1656 VkPipelineBindPoint pipelineBindPoint,
1657 VkPipelineLayout _layout,
1658 uint32_t set,
1659 uint32_t descriptorWriteCount,
1660 const VkWriteDescriptorSet *pDescriptorWrites);
1661
1662 int
1663 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1664
1665 int
1666 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1667
1668 int
1669 tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
1670
1671 int
1672 tu_drm_submitqueue_new(const struct tu_device *dev,
1673 int priority,
1674 uint32_t *queue_id);
1675
1676 void
1677 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1678
1679 uint32_t
1680 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1681 uint32_t
1682 tu_gem_import_dmabuf(const struct tu_device *dev,
1683 int prime_fd,
1684 uint64_t size);
1685 int
1686 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1687 void
1688 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1689 uint64_t
1690 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1691 uint64_t
1692 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1693
1694
1695 void
1696 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1697 struct tu_cs *cs,
1698 uint32_t attachment,
1699 const VkClearValue *value,
1700 const VkClearRect *rect);
1701
1702 void
1703 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1704 struct tu_cs *cs,
1705 uint32_t attachment,
1706 uint8_t component_mask,
1707 const VkClearValue *value);
1708
1709 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1710 \
1711 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1712 { \
1713 return (struct __tu_type *) _handle; \
1714 } \
1715 \
1716 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1717 { \
1718 return (__VkType) _obj; \
1719 }
1720
1721 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1722 \
1723 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1724 { \
1725 return (struct __tu_type *) (uintptr_t) _handle; \
1726 } \
1727 \
1728 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1729 { \
1730 return (__VkType)(uintptr_t) _obj; \
1731 }
1732
1733 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1734 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1735
1736 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1737 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1738 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1739 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1740 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1741
1742 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1743 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1744 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1745 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1746 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1747 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1748 VkDescriptorSetLayout)
1749 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1750 VkDescriptorUpdateTemplate)
1751 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1752 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1753 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1754 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1755 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1756 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1757 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1758 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1759 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1760 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1761 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1762 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1763 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1764 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1765
1766 #endif /* TU_PRIVATE_H */