turnip: Add support for uniform texel buffers.
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #define MAX_VBS 32
81 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_RTS 8
83 #define MAX_VSC_PIPES 32
84 #define MAX_VIEWPORTS 1
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
90 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
91 #define MAX_DYNAMIC_BUFFERS \
92 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define TU_MAX_DRM_DEVICES 8
96 #define MAX_VIEWS 8
97 /* The Qualcomm driver exposes 0x20000058 */
98 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
99
100 #define NUM_DEPTH_CLEAR_PIPELINES 3
101
102 /*
103 * This is the point we switch from using CP to compute shader
104 * for certain buffer operations.
105 */
106 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
107
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
110
111 enum tu_mem_heap
112 {
113 TU_MEM_HEAP_VRAM,
114 TU_MEM_HEAP_VRAM_CPU_ACCESS,
115 TU_MEM_HEAP_GTT,
116 TU_MEM_HEAP_COUNT
117 };
118
119 enum tu_mem_type
120 {
121 TU_MEM_TYPE_VRAM,
122 TU_MEM_TYPE_GTT_WRITE_COMBINE,
123 TU_MEM_TYPE_VRAM_CPU_ACCESS,
124 TU_MEM_TYPE_GTT_CACHED,
125 TU_MEM_TYPE_COUNT
126 };
127
128 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 tu_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 tu_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 tu_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
212
213 #define typed_memcpy(dest, src, count) \
214 ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 #define COND(bool, val) ((bool) ? (val) : 0)
220
221 /* Whenever we generate an error, pass it through this function. Useful for
222 * debugging, where we can break on it. Only call at error site, not when
223 * propagating errors. Might be useful to plug in a stack trace here.
224 */
225
226 struct tu_instance;
227
228 VkResult
229 __vk_errorf(struct tu_instance *instance,
230 VkResult error,
231 const char *file,
232 int line,
233 const char *format,
234 ...);
235
236 #define vk_error(instance, error) \
237 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
238 #define vk_errorf(instance, error, format, ...) \
239 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
240
241 void
242 __tu_finishme(const char *file, int line, const char *format, ...)
243 tu_printflike(3, 4);
244 void
245 tu_loge(const char *format, ...) tu_printflike(1, 2);
246 void
247 tu_loge_v(const char *format, va_list va);
248 void
249 tu_logi(const char *format, ...) tu_printflike(1, 2);
250 void
251 tu_logi_v(const char *format, va_list va);
252
253 /**
254 * Print a FINISHME message, including its source location.
255 */
256 #define tu_finishme(format, ...) \
257 do { \
258 static bool reported = false; \
259 if (!reported) { \
260 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
261 reported = true; \
262 } \
263 } while (0)
264
265 /* A non-fatal assert. Useful for debugging. */
266 #ifdef DEBUG
267 #define tu_assert(x) \
268 ({ \
269 if (unlikely(!(x))) \
270 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 })
272 #else
273 #define tu_assert(x)
274 #endif
275
276 /* Suppress -Wunused in stub functions */
277 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
278 static inline void
279 __tu_use_args(int ignore, ...)
280 {
281 }
282
283 #define tu_stub() \
284 do { \
285 tu_finishme("stub %s", __func__); \
286 } while (0)
287
288 void *
289 tu_lookup_entrypoint_unchecked(const char *name);
290 void *
291 tu_lookup_entrypoint_checked(
292 const char *name,
293 uint32_t core_version,
294 const struct tu_instance_extension_table *instance,
295 const struct tu_device_extension_table *device);
296
297 struct tu_physical_device
298 {
299 VK_LOADER_DATA _loader_data;
300
301 struct tu_instance *instance;
302
303 char path[20];
304 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
305 uint8_t driver_uuid[VK_UUID_SIZE];
306 uint8_t device_uuid[VK_UUID_SIZE];
307 uint8_t cache_uuid[VK_UUID_SIZE];
308
309 struct wsi_device wsi_device;
310
311 int local_fd;
312 int master_fd;
313
314 unsigned gpu_id;
315 uint32_t gmem_size;
316 uint32_t tile_align_w;
317 uint32_t tile_align_h;
318
319 /* This is the drivers on-disk cache used as a fallback as opposed to
320 * the pipeline cache defined by apps.
321 */
322 struct disk_cache *disk_cache;
323
324 struct tu_device_extension_table supported_extensions;
325 };
326
327 enum tu_debug_flags
328 {
329 TU_DEBUG_STARTUP = 1 << 0,
330 TU_DEBUG_NIR = 1 << 1,
331 TU_DEBUG_IR3 = 1 << 2,
332 TU_DEBUG_NOBIN = 1 << 3,
333 };
334
335 struct tu_instance
336 {
337 VK_LOADER_DATA _loader_data;
338
339 VkAllocationCallbacks alloc;
340
341 uint32_t api_version;
342 int physical_device_count;
343 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
344
345 enum tu_debug_flags debug_flags;
346
347 struct vk_debug_report_instance debug_report_callbacks;
348
349 struct tu_instance_extension_table enabled_extensions;
350 };
351
352 VkResult
353 tu_wsi_init(struct tu_physical_device *physical_device);
354 void
355 tu_wsi_finish(struct tu_physical_device *physical_device);
356
357 bool
358 tu_instance_extension_supported(const char *name);
359 uint32_t
360 tu_physical_device_api_version(struct tu_physical_device *dev);
361 bool
362 tu_physical_device_extension_supported(struct tu_physical_device *dev,
363 const char *name);
364
365 struct cache_entry;
366
367 struct tu_pipeline_cache
368 {
369 struct tu_device *device;
370 pthread_mutex_t mutex;
371
372 uint32_t total_size;
373 uint32_t table_size;
374 uint32_t kernel_count;
375 struct cache_entry **hash_table;
376 bool modified;
377
378 VkAllocationCallbacks alloc;
379 };
380
381 struct tu_pipeline_key
382 {
383 };
384
385 void
386 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
387 struct tu_device *device);
388 void
389 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
390 void
391 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
392 const void *data,
393 size_t size);
394
395 struct tu_shader_variant;
396
397 bool
398 tu_create_shader_variants_from_pipeline_cache(
399 struct tu_device *device,
400 struct tu_pipeline_cache *cache,
401 const unsigned char *sha1,
402 struct tu_shader_variant **variants);
403
404 void
405 tu_pipeline_cache_insert_shaders(struct tu_device *device,
406 struct tu_pipeline_cache *cache,
407 const unsigned char *sha1,
408 struct tu_shader_variant **variants,
409 const void *const *codes,
410 const unsigned *code_sizes);
411
412 struct tu_meta_state
413 {
414 VkAllocationCallbacks alloc;
415
416 struct tu_pipeline_cache cache;
417 };
418
419 /* queue types */
420 #define TU_QUEUE_GENERAL 0
421
422 #define TU_MAX_QUEUE_FAMILIES 1
423
424 struct tu_fence
425 {
426 struct wsi_fence *fence_wsi;
427 bool signaled;
428 int fd;
429 };
430
431 void
432 tu_fence_init(struct tu_fence *fence, bool signaled);
433 void
434 tu_fence_finish(struct tu_fence *fence);
435 void
436 tu_fence_update_fd(struct tu_fence *fence, int fd);
437 void
438 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
439 void
440 tu_fence_signal(struct tu_fence *fence);
441 void
442 tu_fence_wait_idle(struct tu_fence *fence);
443
444 struct tu_queue
445 {
446 VK_LOADER_DATA _loader_data;
447 struct tu_device *device;
448 uint32_t queue_family_index;
449 int queue_idx;
450 VkDeviceQueueCreateFlags flags;
451
452 uint32_t msm_queue_id;
453 struct tu_fence submit_fence;
454 };
455
456 struct tu_device
457 {
458 VK_LOADER_DATA _loader_data;
459
460 VkAllocationCallbacks alloc;
461
462 struct tu_instance *instance;
463
464 struct tu_meta_state meta_state;
465
466 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
467 int queue_count[TU_MAX_QUEUE_FAMILIES];
468
469 struct tu_physical_device *physical_device;
470
471 struct ir3_compiler *compiler;
472
473 /* Backup in-memory cache to be used if the app doesn't provide one */
474 struct tu_pipeline_cache *mem_cache;
475
476 struct list_head shader_slabs;
477 mtx_t shader_slab_mutex;
478
479 struct tu_device_extension_table enabled_extensions;
480 };
481
482 struct tu_bo
483 {
484 uint32_t gem_handle;
485 uint64_t size;
486 uint64_t iova;
487 void *map;
488 };
489
490 VkResult
491 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
492 VkResult
493 tu_bo_init_dmabuf(struct tu_device *dev,
494 struct tu_bo *bo,
495 uint64_t size,
496 int fd);
497 int
498 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
499 void
500 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
501 VkResult
502 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
503
504 struct tu_cs_entry
505 {
506 /* No ownership */
507 const struct tu_bo *bo;
508
509 uint32_t size;
510 uint32_t offset;
511 };
512
513 struct ts_cs_memory {
514 uint32_t *map;
515 uint64_t iova;
516 };
517
518 enum tu_cs_mode
519 {
520
521 /*
522 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
523 * is full. tu_cs_begin must be called before command packet emission and
524 * tu_cs_end must be called after.
525 *
526 * This mode may create multiple entries internally. The entries must be
527 * submitted together.
528 */
529 TU_CS_MODE_GROW,
530
531 /*
532 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
533 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
534 * effect on it.
535 *
536 * This mode does not create any entry or any BO.
537 */
538 TU_CS_MODE_EXTERNAL,
539
540 /*
541 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
542 * command packet emission. tu_cs_begin_sub_stream must be called to get a
543 * sub-stream to emit comamnd packets to. When done with the sub-stream,
544 * tu_cs_end_sub_stream must be called.
545 *
546 * This mode does not create any entry internally.
547 */
548 TU_CS_MODE_SUB_STREAM,
549 };
550
551 struct tu_cs
552 {
553 uint32_t *start;
554 uint32_t *cur;
555 uint32_t *reserved_end;
556 uint32_t *end;
557
558 enum tu_cs_mode mode;
559 uint32_t next_bo_size;
560
561 struct tu_cs_entry *entries;
562 uint32_t entry_count;
563 uint32_t entry_capacity;
564
565 struct tu_bo **bos;
566 uint32_t bo_count;
567 uint32_t bo_capacity;
568 };
569
570 struct tu_device_memory
571 {
572 struct tu_bo bo;
573 VkDeviceSize size;
574
575 /* for dedicated allocations */
576 struct tu_image *image;
577 struct tu_buffer *buffer;
578
579 uint32_t type_index;
580 void *map;
581 void *user_ptr;
582 };
583
584 struct tu_descriptor_range
585 {
586 uint64_t va;
587 uint32_t size;
588 };
589
590 struct tu_descriptor_set
591 {
592 const struct tu_descriptor_set_layout *layout;
593 uint32_t size;
594
595 uint64_t va;
596 uint32_t *mapped_ptr;
597 struct tu_descriptor_range *dynamic_descriptors;
598
599 struct tu_bo *descriptors[0];
600 };
601
602 struct tu_push_descriptor_set
603 {
604 struct tu_descriptor_set set;
605 uint32_t capacity;
606 };
607
608 struct tu_descriptor_pool_entry
609 {
610 uint32_t offset;
611 uint32_t size;
612 struct tu_descriptor_set *set;
613 };
614
615 struct tu_descriptor_pool
616 {
617 struct tu_bo bo;
618 uint64_t current_offset;
619 uint64_t size;
620
621 uint8_t *host_memory_base;
622 uint8_t *host_memory_ptr;
623 uint8_t *host_memory_end;
624
625 uint32_t entry_count;
626 uint32_t max_entry_count;
627 struct tu_descriptor_pool_entry entries[0];
628 };
629
630 struct tu_descriptor_update_template_entry
631 {
632 VkDescriptorType descriptor_type;
633
634 /* The number of descriptors to update */
635 uint32_t descriptor_count;
636
637 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
638 */
639 uint32_t dst_offset;
640
641 /* In dwords. Not valid/used for dynamic descriptors */
642 uint32_t dst_stride;
643
644 uint32_t buffer_offset;
645
646 /* Only valid for combined image samplers and samplers */
647 uint16_t has_sampler;
648
649 /* In bytes */
650 size_t src_offset;
651 size_t src_stride;
652
653 /* For push descriptors */
654 const uint32_t *immutable_samplers;
655 };
656
657 struct tu_descriptor_update_template
658 {
659 uint32_t entry_count;
660 VkPipelineBindPoint bind_point;
661 struct tu_descriptor_update_template_entry entry[0];
662 };
663
664 struct tu_buffer
665 {
666 VkDeviceSize size;
667
668 VkBufferUsageFlags usage;
669 VkBufferCreateFlags flags;
670
671 struct tu_bo *bo;
672 VkDeviceSize bo_offset;
673 };
674
675 static inline uint64_t
676 tu_buffer_iova(struct tu_buffer *buffer)
677 {
678 return buffer->bo->iova + buffer->bo_offset;
679 }
680
681 enum tu_dynamic_state_bits
682 {
683 TU_DYNAMIC_VIEWPORT = 1 << 0,
684 TU_DYNAMIC_SCISSOR = 1 << 1,
685 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
686 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
687 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
688 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
689 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
690 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
691 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
692 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
693 TU_DYNAMIC_ALL = (1 << 10) - 1,
694 };
695
696 struct tu_vertex_binding
697 {
698 struct tu_buffer *buffer;
699 VkDeviceSize offset;
700 };
701
702 struct tu_viewport_state
703 {
704 uint32_t count;
705 VkViewport viewports[MAX_VIEWPORTS];
706 };
707
708 struct tu_scissor_state
709 {
710 uint32_t count;
711 VkRect2D scissors[MAX_SCISSORS];
712 };
713
714 struct tu_discard_rectangle_state
715 {
716 uint32_t count;
717 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
718 };
719
720 struct tu_dynamic_state
721 {
722 /**
723 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
724 * Defines the set of saved dynamic state.
725 */
726 uint32_t mask;
727
728 struct tu_viewport_state viewport;
729
730 struct tu_scissor_state scissor;
731
732 float line_width;
733
734 struct
735 {
736 float bias;
737 float clamp;
738 float slope;
739 } depth_bias;
740
741 float blend_constants[4];
742
743 struct
744 {
745 float min;
746 float max;
747 } depth_bounds;
748
749 struct
750 {
751 uint32_t front;
752 uint32_t back;
753 } stencil_compare_mask;
754
755 struct
756 {
757 uint32_t front;
758 uint32_t back;
759 } stencil_write_mask;
760
761 struct
762 {
763 uint32_t front;
764 uint32_t back;
765 } stencil_reference;
766
767 struct tu_discard_rectangle_state discard_rectangle;
768 };
769
770 extern const struct tu_dynamic_state default_dynamic_state;
771
772 const char *
773 tu_get_debug_option_name(int id);
774
775 const char *
776 tu_get_perftest_option_name(int id);
777
778 struct tu_descriptor_state
779 {
780 struct tu_descriptor_set *sets[MAX_SETS];
781 uint32_t dirty;
782 uint32_t valid;
783 struct tu_push_descriptor_set push_set;
784 bool push_dirty;
785 uint64_t dynamic_buffers[MAX_DYNAMIC_BUFFERS];
786 };
787
788 struct tu_tile
789 {
790 uint8_t pipe;
791 uint8_t slot;
792 VkOffset2D begin;
793 VkOffset2D end;
794 };
795
796 struct tu_tiling_config
797 {
798 VkRect2D render_area;
799
800 /* position and size of the first tile */
801 VkRect2D tile0;
802 /* number of tiles */
803 VkExtent2D tile_count;
804
805 /* size of the first VSC pipe */
806 VkExtent2D pipe0;
807 /* number of VSC pipes */
808 VkExtent2D pipe_count;
809
810 /* pipe register values */
811 uint32_t pipe_config[MAX_VSC_PIPES];
812 uint32_t pipe_sizes[MAX_VSC_PIPES];
813 };
814
815 enum tu_cmd_dirty_bits
816 {
817 TU_CMD_DIRTY_PIPELINE = 1 << 0,
818 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
819 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
820 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
821 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
822
823 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
824 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
825 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
826 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
827 };
828
829 struct tu_cmd_state
830 {
831 uint32_t dirty;
832
833 struct tu_pipeline *pipeline;
834 struct tu_pipeline *compute_pipeline;
835
836 /* Vertex buffers */
837 struct
838 {
839 struct tu_buffer *buffers[MAX_VBS];
840 VkDeviceSize offsets[MAX_VBS];
841 } vb;
842
843 struct tu_dynamic_state dynamic;
844
845 /* Index buffer */
846 struct tu_buffer *index_buffer;
847 uint64_t index_offset;
848 uint32_t index_type;
849 uint32_t max_index_count;
850 uint64_t index_va;
851
852 const struct tu_render_pass *pass;
853 const struct tu_subpass *subpass;
854 const struct tu_framebuffer *framebuffer;
855
856 struct tu_tiling_config tiling_config;
857
858 struct tu_cs_entry tile_load_ib;
859 struct tu_cs_entry tile_store_ib;
860 };
861
862 struct tu_cmd_pool
863 {
864 VkAllocationCallbacks alloc;
865 struct list_head cmd_buffers;
866 struct list_head free_cmd_buffers;
867 uint32_t queue_family_index;
868 };
869
870 struct tu_cmd_buffer_upload
871 {
872 uint8_t *map;
873 unsigned offset;
874 uint64_t size;
875 struct list_head list;
876 };
877
878 enum tu_cmd_buffer_status
879 {
880 TU_CMD_BUFFER_STATUS_INVALID,
881 TU_CMD_BUFFER_STATUS_INITIAL,
882 TU_CMD_BUFFER_STATUS_RECORDING,
883 TU_CMD_BUFFER_STATUS_EXECUTABLE,
884 TU_CMD_BUFFER_STATUS_PENDING,
885 };
886
887 struct tu_bo_list
888 {
889 uint32_t count;
890 uint32_t capacity;
891 struct drm_msm_gem_submit_bo *bo_infos;
892 };
893
894 #define TU_BO_LIST_FAILED (~0)
895
896 void
897 tu_bo_list_init(struct tu_bo_list *list);
898 void
899 tu_bo_list_destroy(struct tu_bo_list *list);
900 void
901 tu_bo_list_reset(struct tu_bo_list *list);
902 uint32_t
903 tu_bo_list_add(struct tu_bo_list *list,
904 const struct tu_bo *bo,
905 uint32_t flags);
906 VkResult
907 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
908
909 struct tu_cmd_buffer
910 {
911 VK_LOADER_DATA _loader_data;
912
913 struct tu_device *device;
914
915 struct tu_cmd_pool *pool;
916 struct list_head pool_link;
917
918 VkCommandBufferUsageFlags usage_flags;
919 VkCommandBufferLevel level;
920 enum tu_cmd_buffer_status status;
921
922 struct tu_cmd_state state;
923 struct tu_vertex_binding vertex_bindings[MAX_VBS];
924 uint32_t queue_family_index;
925
926 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
927 VkShaderStageFlags push_constant_stages;
928 struct tu_descriptor_set meta_push_descriptors;
929
930 struct tu_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
931
932 struct tu_cmd_buffer_upload upload;
933
934 VkResult record_result;
935
936 struct tu_bo_list bo_list;
937 struct tu_cs cs;
938 struct tu_cs draw_cs;
939 struct tu_cs sub_cs;
940
941 uint16_t marker_reg;
942 uint32_t marker_seqno;
943
944 struct tu_bo scratch_bo;
945 uint32_t scratch_seqno;
946 #define VSC_OVERFLOW 0x8
947 #define VSC_SCRATCH 0x10
948
949 struct tu_bo vsc_data;
950 struct tu_bo vsc_data2;
951 uint32_t vsc_data_pitch;
952 uint32_t vsc_data2_pitch;
953 bool use_vsc_data;
954
955 bool wait_for_idle;
956 };
957
958 unsigned
959 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
960 struct tu_cs *cs,
961 enum vgt_event_type event,
962 bool need_seqno);
963
964 bool
965 tu_get_memory_fd(struct tu_device *device,
966 struct tu_device_memory *memory,
967 int *pFD);
968
969 static inline struct tu_descriptor_state *
970 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
971 VkPipelineBindPoint bind_point)
972 {
973 return &cmd_buffer->descriptors[bind_point];
974 }
975
976 /*
977 * Takes x,y,z as exact numbers of invocations, instead of blocks.
978 *
979 * Limitations: Can't call normal dispatch functions without binding or
980 * rebinding
981 * the compute pipeline.
982 */
983 void
984 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
985 uint32_t x,
986 uint32_t y,
987 uint32_t z);
988
989 struct tu_event
990 {
991 struct tu_bo bo;
992 };
993
994 struct tu_shader_module;
995
996 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
997 #define TU_HASH_SHADER_SISCHED (1 << 1)
998 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
999 void
1000 tu_hash_shaders(unsigned char *hash,
1001 const VkPipelineShaderStageCreateInfo **stages,
1002 const struct tu_pipeline_layout *layout,
1003 const struct tu_pipeline_key *key,
1004 uint32_t flags);
1005
1006 static inline gl_shader_stage
1007 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1008 {
1009 assert(__builtin_popcount(vk_stage) == 1);
1010 return ffs(vk_stage) - 1;
1011 }
1012
1013 static inline VkShaderStageFlagBits
1014 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1015 {
1016 return (1 << mesa_stage);
1017 }
1018
1019 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1020
1021 #define tu_foreach_stage(stage, stage_bits) \
1022 for (gl_shader_stage stage, \
1023 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1024 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1025
1026 struct tu_shader_module
1027 {
1028 unsigned char sha1[20];
1029
1030 uint32_t code_size;
1031 const uint32_t *code[0];
1032 };
1033
1034 struct tu_shader_compile_options
1035 {
1036 struct ir3_shader_key key;
1037
1038 bool optimize;
1039 bool include_binning_pass;
1040 };
1041
1042 struct tu_descriptor_map
1043 {
1044 /* TODO: avoid fixed size array/justify the size */
1045 unsigned num; /* number of array entries */
1046 unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
1047 int set[64];
1048 int binding[64];
1049 int value[64];
1050 int array_size[64];
1051 };
1052
1053 struct tu_shader
1054 {
1055 struct ir3_shader ir3_shader;
1056
1057 struct tu_descriptor_map texture_map;
1058 struct tu_descriptor_map sampler_map;
1059 struct tu_descriptor_map ubo_map;
1060 struct tu_descriptor_map ssbo_map;
1061 struct tu_descriptor_map image_map;
1062
1063 /* This may be true for vertex shaders. When true, variants[1] is the
1064 * binning variant and binning_binary is non-NULL.
1065 */
1066 bool has_binning_pass;
1067
1068 void *binary;
1069 void *binning_binary;
1070
1071 struct ir3_shader_variant variants[0];
1072 };
1073
1074 struct tu_shader *
1075 tu_shader_create(struct tu_device *dev,
1076 gl_shader_stage stage,
1077 const VkPipelineShaderStageCreateInfo *stage_info,
1078 struct tu_pipeline_layout *layout,
1079 const VkAllocationCallbacks *alloc);
1080
1081 void
1082 tu_shader_destroy(struct tu_device *dev,
1083 struct tu_shader *shader,
1084 const VkAllocationCallbacks *alloc);
1085
1086 void
1087 tu_shader_compile_options_init(
1088 struct tu_shader_compile_options *options,
1089 const VkGraphicsPipelineCreateInfo *pipeline_info);
1090
1091 VkResult
1092 tu_shader_compile(struct tu_device *dev,
1093 struct tu_shader *shader,
1094 const struct tu_shader *next_stage,
1095 const struct tu_shader_compile_options *options,
1096 const VkAllocationCallbacks *alloc);
1097
1098 struct tu_program_descriptor_linkage
1099 {
1100 struct ir3_ubo_analysis_state ubo_state;
1101 struct ir3_const_state const_state;
1102
1103 uint32_t constlen;
1104
1105 struct tu_descriptor_map texture_map;
1106 struct tu_descriptor_map sampler_map;
1107 struct tu_descriptor_map ubo_map;
1108 struct tu_descriptor_map ssbo_map;
1109 struct tu_descriptor_map image_map;
1110 };
1111
1112 struct tu_pipeline
1113 {
1114 struct tu_cs cs;
1115
1116 struct tu_dynamic_state dynamic_state;
1117
1118 struct tu_pipeline_layout *layout;
1119
1120 bool need_indirect_descriptor_sets;
1121 VkShaderStageFlags active_stages;
1122
1123 struct
1124 {
1125 struct tu_bo binary_bo;
1126 struct tu_cs_entry state_ib;
1127 struct tu_cs_entry binning_state_ib;
1128
1129 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1130 } program;
1131
1132 struct
1133 {
1134 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1135 uint16_t strides[MAX_VERTEX_ATTRIBS];
1136 uint16_t offsets[MAX_VERTEX_ATTRIBS];
1137 uint32_t count;
1138
1139 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1140 uint16_t binning_strides[MAX_VERTEX_ATTRIBS];
1141 uint16_t binning_offsets[MAX_VERTEX_ATTRIBS];
1142 uint32_t binning_count;
1143
1144 struct tu_cs_entry state_ib;
1145 struct tu_cs_entry binning_state_ib;
1146 } vi;
1147
1148 struct
1149 {
1150 enum pc_di_primtype primtype;
1151 bool primitive_restart;
1152 } ia;
1153
1154 struct
1155 {
1156 struct tu_cs_entry state_ib;
1157 } vp;
1158
1159 struct
1160 {
1161 uint32_t gras_su_cntl;
1162 struct tu_cs_entry state_ib;
1163 } rast;
1164
1165 struct
1166 {
1167 struct tu_cs_entry state_ib;
1168 } ds;
1169
1170 struct
1171 {
1172 struct tu_cs_entry state_ib;
1173 } blend;
1174
1175 struct
1176 {
1177 uint32_t local_size[3];
1178 } compute;
1179 };
1180
1181 void
1182 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1183
1184 void
1185 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1186
1187 void
1188 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1189 uint32_t gras_su_cntl,
1190 float line_width);
1191
1192 void
1193 tu6_emit_depth_bias(struct tu_cs *cs,
1194 float constant_factor,
1195 float clamp,
1196 float slope_factor);
1197
1198 void
1199 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1200 uint32_t front,
1201 uint32_t back);
1202
1203 void
1204 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1205
1206 void
1207 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1208
1209 void
1210 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1211
1212 struct tu_userdata_info *
1213 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1214 gl_shader_stage stage,
1215 int idx);
1216
1217 struct tu_shader_variant *
1218 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1219
1220 struct tu_graphics_pipeline_create_info
1221 {
1222 bool use_rectlist;
1223 bool db_depth_clear;
1224 bool db_stencil_clear;
1225 bool db_depth_disable_expclear;
1226 bool db_stencil_disable_expclear;
1227 bool db_flush_depth_inplace;
1228 bool db_flush_stencil_inplace;
1229 bool db_resummarize;
1230 uint32_t custom_blend_mode;
1231 };
1232
1233 struct tu_native_format
1234 {
1235 int vtx; /* VFMTn_xxx or -1 */
1236 int tex; /* TFMTn_xxx or -1 */
1237 int rb; /* RBn_xxx or -1 */
1238 int swap; /* enum a3xx_color_swap */
1239 bool present; /* internal only; always true to external users */
1240 };
1241
1242 const struct tu_native_format *
1243 tu6_get_native_format(VkFormat format);
1244
1245 void
1246 tu_pack_clear_value(const VkClearValue *val,
1247 VkFormat format,
1248 uint32_t buf[4]);
1249
1250 void
1251 tu_2d_clear_color(const VkClearColorValue *val, VkFormat format, uint32_t buf[4]);
1252
1253 void
1254 tu_2d_clear_zs(const VkClearDepthStencilValue *val, VkFormat format, uint32_t buf[4]);
1255
1256 enum a6xx_2d_ifmt tu6_rb_fmt_to_ifmt(enum a6xx_color_fmt fmt);
1257 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1258
1259 struct tu_image_level
1260 {
1261 VkDeviceSize offset;
1262 VkDeviceSize size;
1263 uint32_t pitch;
1264 };
1265
1266 struct tu_image
1267 {
1268 VkImageType type;
1269 /* The original VkFormat provided by the client. This may not match any
1270 * of the actual surface formats.
1271 */
1272 VkFormat vk_format;
1273 VkImageAspectFlags aspects;
1274 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1275 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1276 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1277 VkExtent3D extent;
1278 uint32_t level_count;
1279 uint32_t layer_count;
1280 VkSampleCountFlagBits samples;
1281
1282
1283 uint32_t alignment;
1284
1285 struct fdl_layout layout;
1286
1287 unsigned queue_family_mask;
1288 bool exclusive;
1289 bool shareable;
1290
1291 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1292 VkDeviceMemory owned_memory;
1293
1294 /* Set when bound */
1295 struct tu_bo *bo;
1296 VkDeviceSize bo_offset;
1297 };
1298
1299 unsigned
1300 tu_image_queue_family_mask(const struct tu_image *image,
1301 uint32_t family,
1302 uint32_t queue_family);
1303
1304 static inline uint32_t
1305 tu_get_layerCount(const struct tu_image *image,
1306 const VkImageSubresourceRange *range)
1307 {
1308 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1309 ? image->layer_count - range->baseArrayLayer
1310 : range->layerCount;
1311 }
1312
1313 static inline uint32_t
1314 tu_get_levelCount(const struct tu_image *image,
1315 const VkImageSubresourceRange *range)
1316 {
1317 return range->levelCount == VK_REMAINING_MIP_LEVELS
1318 ? image->level_count - range->baseMipLevel
1319 : range->levelCount;
1320 }
1321
1322 static inline VkDeviceSize
1323 tu_layer_size(struct tu_image *image, int level)
1324 {
1325 return fdl_layer_stride(&image->layout, level);
1326 }
1327
1328 static inline uint32_t
1329 tu_image_stride(struct tu_image *image, int level)
1330 {
1331 return image->layout.slices[level].pitch * image->layout.cpp;
1332 }
1333
1334 static inline uint64_t
1335 tu_image_base(struct tu_image *image, int level, int layer)
1336 {
1337 return image->bo->iova + image->bo_offset +
1338 fdl_surface_offset(&image->layout, level, layer);
1339 }
1340
1341 static inline VkDeviceSize
1342 tu_image_ubwc_size(struct tu_image *image, int level)
1343 {
1344 return image->layout.ubwc_size;
1345 }
1346
1347 static inline uint32_t
1348 tu_image_ubwc_pitch(struct tu_image *image, int level)
1349 {
1350 return image->layout.ubwc_slices[level].pitch;
1351 }
1352
1353 static inline uint64_t
1354 tu_image_ubwc_base(struct tu_image *image, int level, int layer)
1355 {
1356 return image->bo->iova + image->bo_offset +
1357 image->layout.ubwc_slices[level].offset +
1358 layer * tu_image_ubwc_size(image, level);
1359 }
1360
1361 enum a6xx_tile_mode
1362 tu6_get_image_tile_mode(struct tu_image *image, int level);
1363 enum a3xx_msaa_samples
1364 tu_msaa_samples(uint32_t samples);
1365
1366 struct tu_image_view
1367 {
1368 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1369
1370 VkImageViewType type;
1371 VkImageAspectFlags aspect_mask;
1372 VkFormat vk_format;
1373 uint32_t base_layer;
1374 uint32_t layer_count;
1375 uint32_t base_mip;
1376 uint32_t level_count;
1377 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1378
1379 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1380
1381 /* Descriptor for use as a storage image as opposed to a sampled image.
1382 * This has a few differences for cube maps (e.g. type).
1383 */
1384 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1385 };
1386
1387 struct tu_sampler
1388 {
1389 uint32_t state[A6XX_TEX_SAMP_DWORDS];
1390
1391 bool needs_border;
1392 VkBorderColor border;
1393 };
1394
1395 VkResult
1396 tu_image_create(VkDevice _device,
1397 const VkImageCreateInfo *pCreateInfo,
1398 const VkAllocationCallbacks *alloc,
1399 VkImage *pImage,
1400 uint64_t modifier);
1401
1402 VkResult
1403 tu_image_from_gralloc(VkDevice device_h,
1404 const VkImageCreateInfo *base_info,
1405 const VkNativeBufferANDROID *gralloc_info,
1406 const VkAllocationCallbacks *alloc,
1407 VkImage *out_image_h);
1408
1409 void
1410 tu_image_view_init(struct tu_image_view *view,
1411 struct tu_device *device,
1412 const VkImageViewCreateInfo *pCreateInfo);
1413
1414 struct tu_buffer_view
1415 {
1416 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1417
1418 struct tu_buffer *buffer;
1419 };
1420 void
1421 tu_buffer_view_init(struct tu_buffer_view *view,
1422 struct tu_device *device,
1423 const VkBufferViewCreateInfo *pCreateInfo);
1424
1425 static inline struct VkExtent3D
1426 tu_sanitize_image_extent(const VkImageType imageType,
1427 const struct VkExtent3D imageExtent)
1428 {
1429 switch (imageType) {
1430 case VK_IMAGE_TYPE_1D:
1431 return (VkExtent3D) { imageExtent.width, 1, 1 };
1432 case VK_IMAGE_TYPE_2D:
1433 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1434 case VK_IMAGE_TYPE_3D:
1435 return imageExtent;
1436 default:
1437 unreachable("invalid image type");
1438 }
1439 }
1440
1441 static inline struct VkOffset3D
1442 tu_sanitize_image_offset(const VkImageType imageType,
1443 const struct VkOffset3D imageOffset)
1444 {
1445 switch (imageType) {
1446 case VK_IMAGE_TYPE_1D:
1447 return (VkOffset3D) { imageOffset.x, 0, 0 };
1448 case VK_IMAGE_TYPE_2D:
1449 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1450 case VK_IMAGE_TYPE_3D:
1451 return imageOffset;
1452 default:
1453 unreachable("invalid image type");
1454 }
1455 }
1456
1457 struct tu_attachment_info
1458 {
1459 struct tu_image_view *attachment;
1460 };
1461
1462 struct tu_framebuffer
1463 {
1464 uint32_t width;
1465 uint32_t height;
1466 uint32_t layers;
1467
1468 uint32_t attachment_count;
1469 struct tu_attachment_info attachments[0];
1470 };
1471
1472 struct tu_subpass_attachment
1473 {
1474 uint32_t attachment;
1475 };
1476
1477 struct tu_subpass
1478 {
1479 uint32_t input_count;
1480 uint32_t color_count;
1481 struct tu_subpass_attachment *input_attachments;
1482 struct tu_subpass_attachment *color_attachments;
1483 struct tu_subpass_attachment *resolve_attachments;
1484 struct tu_subpass_attachment depth_stencil_attachment;
1485
1486 VkSampleCountFlagBits samples;
1487 };
1488
1489 struct tu_render_pass_attachment
1490 {
1491 VkFormat format;
1492 uint32_t cpp;
1493 VkAttachmentLoadOp load_op;
1494 VkAttachmentLoadOp stencil_load_op;
1495 VkAttachmentStoreOp store_op;
1496 VkAttachmentStoreOp stencil_store_op;
1497 int32_t gmem_offset;
1498 };
1499
1500 struct tu_render_pass
1501 {
1502 uint32_t attachment_count;
1503 uint32_t subpass_count;
1504 uint32_t gmem_pixels;
1505 struct tu_subpass_attachment *subpass_attachments;
1506 struct tu_render_pass_attachment *attachments;
1507 struct tu_subpass subpasses[0];
1508 };
1509
1510 VkResult
1511 tu_device_init_meta(struct tu_device *device);
1512 void
1513 tu_device_finish_meta(struct tu_device *device);
1514
1515 struct tu_query_pool
1516 {
1517 uint32_t stride;
1518 uint32_t availability_offset;
1519 uint64_t size;
1520 char *ptr;
1521 VkQueryType type;
1522 uint32_t pipeline_stats_mask;
1523 };
1524
1525 struct tu_semaphore
1526 {
1527 uint32_t syncobj;
1528 uint32_t temp_syncobj;
1529 };
1530
1531 void
1532 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1533 VkPipelineBindPoint bind_point,
1534 struct tu_descriptor_set *set,
1535 unsigned idx);
1536
1537 void
1538 tu_update_descriptor_sets(struct tu_device *device,
1539 struct tu_cmd_buffer *cmd_buffer,
1540 VkDescriptorSet overrideSet,
1541 uint32_t descriptorWriteCount,
1542 const VkWriteDescriptorSet *pDescriptorWrites,
1543 uint32_t descriptorCopyCount,
1544 const VkCopyDescriptorSet *pDescriptorCopies);
1545
1546 void
1547 tu_update_descriptor_set_with_template(
1548 struct tu_device *device,
1549 struct tu_cmd_buffer *cmd_buffer,
1550 struct tu_descriptor_set *set,
1551 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1552 const void *pData);
1553
1554 void
1555 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1556 VkPipelineBindPoint pipelineBindPoint,
1557 VkPipelineLayout _layout,
1558 uint32_t set,
1559 uint32_t descriptorWriteCount,
1560 const VkWriteDescriptorSet *pDescriptorWrites);
1561
1562 int
1563 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1564
1565 int
1566 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1567
1568 int
1569 tu_drm_submitqueue_new(const struct tu_device *dev,
1570 int priority,
1571 uint32_t *queue_id);
1572
1573 void
1574 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1575
1576 uint32_t
1577 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1578 uint32_t
1579 tu_gem_import_dmabuf(const struct tu_device *dev,
1580 int prime_fd,
1581 uint64_t size);
1582 int
1583 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1584 void
1585 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1586 uint64_t
1587 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1588 uint64_t
1589 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1590
1591 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1592 \
1593 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1594 { \
1595 return (struct __tu_type *) _handle; \
1596 } \
1597 \
1598 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1599 { \
1600 return (__VkType) _obj; \
1601 }
1602
1603 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1604 \
1605 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1606 { \
1607 return (struct __tu_type *) (uintptr_t) _handle; \
1608 } \
1609 \
1610 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1611 { \
1612 return (__VkType)(uintptr_t) _obj; \
1613 }
1614
1615 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1616 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1617
1618 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1619 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1620 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1621 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1622 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1623
1624 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1625 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1626 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1627 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1628 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1629 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1630 VkDescriptorSetLayout)
1631 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1632 VkDescriptorUpdateTemplate)
1633 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1634 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1635 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1636 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1637 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1638 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1639 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1640 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1641 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1642 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1643 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1644 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1645 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1646 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1647
1648 #endif /* TU_PRIVATE_H */