turnip: Add magic register values to tu_physical_device
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #define MAX_VBS 32
81 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_RTS 8
83 #define MAX_VSC_PIPES 32
84 #define MAX_VIEWPORTS 1
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
90 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
91 #define MAX_DYNAMIC_BUFFERS \
92 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define TU_MAX_DRM_DEVICES 8
96 #define MAX_VIEWS 8
97 /* The Qualcomm driver exposes 0x20000058 */
98 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
99
100 #define NUM_DEPTH_CLEAR_PIPELINES 3
101
102 /*
103 * This is the point we switch from using CP to compute shader
104 * for certain buffer operations.
105 */
106 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
107
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
110
111 enum tu_mem_heap
112 {
113 TU_MEM_HEAP_VRAM,
114 TU_MEM_HEAP_VRAM_CPU_ACCESS,
115 TU_MEM_HEAP_GTT,
116 TU_MEM_HEAP_COUNT
117 };
118
119 enum tu_mem_type
120 {
121 TU_MEM_TYPE_VRAM,
122 TU_MEM_TYPE_GTT_WRITE_COMBINE,
123 TU_MEM_TYPE_VRAM_CPU_ACCESS,
124 TU_MEM_TYPE_GTT_CACHED,
125 TU_MEM_TYPE_COUNT
126 };
127
128 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 tu_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 tu_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 tu_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
212
213 #define typed_memcpy(dest, src, count) \
214 ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 #define COND(bool, val) ((bool) ? (val) : 0)
220
221 /* Whenever we generate an error, pass it through this function. Useful for
222 * debugging, where we can break on it. Only call at error site, not when
223 * propagating errors. Might be useful to plug in a stack trace here.
224 */
225
226 struct tu_instance;
227
228 VkResult
229 __vk_errorf(struct tu_instance *instance,
230 VkResult error,
231 const char *file,
232 int line,
233 const char *format,
234 ...);
235
236 #define vk_error(instance, error) \
237 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
238 #define vk_errorf(instance, error, format, ...) \
239 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
240
241 void
242 __tu_finishme(const char *file, int line, const char *format, ...)
243 tu_printflike(3, 4);
244 void
245 tu_loge(const char *format, ...) tu_printflike(1, 2);
246 void
247 tu_loge_v(const char *format, va_list va);
248 void
249 tu_logi(const char *format, ...) tu_printflike(1, 2);
250 void
251 tu_logi_v(const char *format, va_list va);
252
253 /**
254 * Print a FINISHME message, including its source location.
255 */
256 #define tu_finishme(format, ...) \
257 do { \
258 static bool reported = false; \
259 if (!reported) { \
260 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
261 reported = true; \
262 } \
263 } while (0)
264
265 /* A non-fatal assert. Useful for debugging. */
266 #ifdef DEBUG
267 #define tu_assert(x) \
268 ({ \
269 if (unlikely(!(x))) \
270 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 })
272 #else
273 #define tu_assert(x)
274 #endif
275
276 /* Suppress -Wunused in stub functions */
277 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
278 static inline void
279 __tu_use_args(int ignore, ...)
280 {
281 }
282
283 #define tu_stub() \
284 do { \
285 tu_finishme("stub %s", __func__); \
286 } while (0)
287
288 void *
289 tu_lookup_entrypoint_unchecked(const char *name);
290 void *
291 tu_lookup_entrypoint_checked(
292 const char *name,
293 uint32_t core_version,
294 const struct tu_instance_extension_table *instance,
295 const struct tu_device_extension_table *device);
296
297 struct tu_physical_device
298 {
299 VK_LOADER_DATA _loader_data;
300
301 struct tu_instance *instance;
302
303 char path[20];
304 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
305 uint8_t driver_uuid[VK_UUID_SIZE];
306 uint8_t device_uuid[VK_UUID_SIZE];
307 uint8_t cache_uuid[VK_UUID_SIZE];
308
309 struct wsi_device wsi_device;
310
311 int local_fd;
312 int master_fd;
313
314 unsigned gpu_id;
315 uint32_t gmem_size;
316 uint32_t tile_align_w;
317 uint32_t tile_align_h;
318
319 struct {
320 uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */
321 uint32_t RB_CCU_CNTL_gmem; /* for GMEM */
322 uint32_t PC_UNKNOWN_9805;
323 uint32_t SP_UNKNOWN_A0F8;
324 } magic;
325
326 /* This is the drivers on-disk cache used as a fallback as opposed to
327 * the pipeline cache defined by apps.
328 */
329 struct disk_cache *disk_cache;
330
331 struct tu_device_extension_table supported_extensions;
332 };
333
334 enum tu_debug_flags
335 {
336 TU_DEBUG_STARTUP = 1 << 0,
337 TU_DEBUG_NIR = 1 << 1,
338 TU_DEBUG_IR3 = 1 << 2,
339 TU_DEBUG_NOBIN = 1 << 3,
340 };
341
342 struct tu_instance
343 {
344 VK_LOADER_DATA _loader_data;
345
346 VkAllocationCallbacks alloc;
347
348 uint32_t api_version;
349 int physical_device_count;
350 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
351
352 enum tu_debug_flags debug_flags;
353
354 struct vk_debug_report_instance debug_report_callbacks;
355
356 struct tu_instance_extension_table enabled_extensions;
357 };
358
359 VkResult
360 tu_wsi_init(struct tu_physical_device *physical_device);
361 void
362 tu_wsi_finish(struct tu_physical_device *physical_device);
363
364 bool
365 tu_instance_extension_supported(const char *name);
366 uint32_t
367 tu_physical_device_api_version(struct tu_physical_device *dev);
368 bool
369 tu_physical_device_extension_supported(struct tu_physical_device *dev,
370 const char *name);
371
372 struct cache_entry;
373
374 struct tu_pipeline_cache
375 {
376 struct tu_device *device;
377 pthread_mutex_t mutex;
378
379 uint32_t total_size;
380 uint32_t table_size;
381 uint32_t kernel_count;
382 struct cache_entry **hash_table;
383 bool modified;
384
385 VkAllocationCallbacks alloc;
386 };
387
388 struct tu_pipeline_key
389 {
390 };
391
392 void
393 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
394 struct tu_device *device);
395 void
396 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
397 void
398 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
399 const void *data,
400 size_t size);
401
402 struct tu_shader_variant;
403
404 bool
405 tu_create_shader_variants_from_pipeline_cache(
406 struct tu_device *device,
407 struct tu_pipeline_cache *cache,
408 const unsigned char *sha1,
409 struct tu_shader_variant **variants);
410
411 void
412 tu_pipeline_cache_insert_shaders(struct tu_device *device,
413 struct tu_pipeline_cache *cache,
414 const unsigned char *sha1,
415 struct tu_shader_variant **variants,
416 const void *const *codes,
417 const unsigned *code_sizes);
418
419 struct tu_meta_state
420 {
421 VkAllocationCallbacks alloc;
422
423 struct tu_pipeline_cache cache;
424 };
425
426 /* queue types */
427 #define TU_QUEUE_GENERAL 0
428
429 #define TU_MAX_QUEUE_FAMILIES 1
430
431 struct tu_fence
432 {
433 struct wsi_fence *fence_wsi;
434 bool signaled;
435 int fd;
436 };
437
438 void
439 tu_fence_init(struct tu_fence *fence, bool signaled);
440 void
441 tu_fence_finish(struct tu_fence *fence);
442 void
443 tu_fence_update_fd(struct tu_fence *fence, int fd);
444 void
445 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
446 void
447 tu_fence_signal(struct tu_fence *fence);
448 void
449 tu_fence_wait_idle(struct tu_fence *fence);
450
451 struct tu_queue
452 {
453 VK_LOADER_DATA _loader_data;
454 struct tu_device *device;
455 uint32_t queue_family_index;
456 int queue_idx;
457 VkDeviceQueueCreateFlags flags;
458
459 uint32_t msm_queue_id;
460 struct tu_fence submit_fence;
461 };
462
463 struct tu_bo
464 {
465 uint32_t gem_handle;
466 uint64_t size;
467 uint64_t iova;
468 void *map;
469 };
470
471 struct tu_device
472 {
473 VK_LOADER_DATA _loader_data;
474
475 VkAllocationCallbacks alloc;
476
477 struct tu_instance *instance;
478
479 struct tu_meta_state meta_state;
480
481 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
482 int queue_count[TU_MAX_QUEUE_FAMILIES];
483
484 struct tu_physical_device *physical_device;
485
486 struct ir3_compiler *compiler;
487
488 /* Backup in-memory cache to be used if the app doesn't provide one */
489 struct tu_pipeline_cache *mem_cache;
490
491 struct tu_bo vsc_data;
492 struct tu_bo vsc_data2;
493 uint32_t vsc_data_pitch;
494 uint32_t vsc_data2_pitch;
495
496 struct list_head shader_slabs;
497 mtx_t shader_slab_mutex;
498
499 struct tu_device_extension_table enabled_extensions;
500 };
501
502 VkResult
503 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
504 VkResult
505 tu_bo_init_dmabuf(struct tu_device *dev,
506 struct tu_bo *bo,
507 uint64_t size,
508 int fd);
509 int
510 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
511 void
512 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
513 VkResult
514 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
515
516 struct tu_cs_entry
517 {
518 /* No ownership */
519 const struct tu_bo *bo;
520
521 uint32_t size;
522 uint32_t offset;
523 };
524
525 struct ts_cs_memory {
526 uint32_t *map;
527 uint64_t iova;
528 };
529
530 enum tu_cs_mode
531 {
532
533 /*
534 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
535 * is full. tu_cs_begin must be called before command packet emission and
536 * tu_cs_end must be called after.
537 *
538 * This mode may create multiple entries internally. The entries must be
539 * submitted together.
540 */
541 TU_CS_MODE_GROW,
542
543 /*
544 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
545 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
546 * effect on it.
547 *
548 * This mode does not create any entry or any BO.
549 */
550 TU_CS_MODE_EXTERNAL,
551
552 /*
553 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
554 * command packet emission. tu_cs_begin_sub_stream must be called to get a
555 * sub-stream to emit comamnd packets to. When done with the sub-stream,
556 * tu_cs_end_sub_stream must be called.
557 *
558 * This mode does not create any entry internally.
559 */
560 TU_CS_MODE_SUB_STREAM,
561 };
562
563 struct tu_cs
564 {
565 uint32_t *start;
566 uint32_t *cur;
567 uint32_t *reserved_end;
568 uint32_t *end;
569
570 enum tu_cs_mode mode;
571 uint32_t next_bo_size;
572
573 struct tu_cs_entry *entries;
574 uint32_t entry_count;
575 uint32_t entry_capacity;
576
577 struct tu_bo **bos;
578 uint32_t bo_count;
579 uint32_t bo_capacity;
580 };
581
582 struct tu_device_memory
583 {
584 struct tu_bo bo;
585 VkDeviceSize size;
586
587 /* for dedicated allocations */
588 struct tu_image *image;
589 struct tu_buffer *buffer;
590
591 uint32_t type_index;
592 void *map;
593 void *user_ptr;
594 };
595
596 struct tu_descriptor_range
597 {
598 uint64_t va;
599 uint32_t size;
600 };
601
602 struct tu_descriptor_set
603 {
604 const struct tu_descriptor_set_layout *layout;
605 uint32_t size;
606
607 uint64_t va;
608 uint32_t *mapped_ptr;
609 struct tu_descriptor_range *dynamic_descriptors;
610
611 struct tu_bo *descriptors[0];
612 };
613
614 struct tu_push_descriptor_set
615 {
616 struct tu_descriptor_set set;
617 uint32_t capacity;
618 };
619
620 struct tu_descriptor_pool_entry
621 {
622 uint32_t offset;
623 uint32_t size;
624 struct tu_descriptor_set *set;
625 };
626
627 struct tu_descriptor_pool
628 {
629 struct tu_bo bo;
630 uint64_t current_offset;
631 uint64_t size;
632
633 uint8_t *host_memory_base;
634 uint8_t *host_memory_ptr;
635 uint8_t *host_memory_end;
636
637 uint32_t entry_count;
638 uint32_t max_entry_count;
639 struct tu_descriptor_pool_entry entries[0];
640 };
641
642 struct tu_descriptor_update_template_entry
643 {
644 VkDescriptorType descriptor_type;
645
646 /* The number of descriptors to update */
647 uint32_t descriptor_count;
648
649 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
650 */
651 uint32_t dst_offset;
652
653 /* In dwords. Not valid/used for dynamic descriptors */
654 uint32_t dst_stride;
655
656 uint32_t buffer_offset;
657
658 /* Only valid for combined image samplers and samplers */
659 uint16_t has_sampler;
660
661 /* In bytes */
662 size_t src_offset;
663 size_t src_stride;
664
665 /* For push descriptors */
666 const uint32_t *immutable_samplers;
667 };
668
669 struct tu_descriptor_update_template
670 {
671 uint32_t entry_count;
672 VkPipelineBindPoint bind_point;
673 struct tu_descriptor_update_template_entry entry[0];
674 };
675
676 struct tu_buffer
677 {
678 VkDeviceSize size;
679
680 VkBufferUsageFlags usage;
681 VkBufferCreateFlags flags;
682
683 struct tu_bo *bo;
684 VkDeviceSize bo_offset;
685 };
686
687 static inline uint64_t
688 tu_buffer_iova(struct tu_buffer *buffer)
689 {
690 return buffer->bo->iova + buffer->bo_offset;
691 }
692
693 enum tu_dynamic_state_bits
694 {
695 TU_DYNAMIC_VIEWPORT = 1 << 0,
696 TU_DYNAMIC_SCISSOR = 1 << 1,
697 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
698 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
699 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
700 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
701 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
702 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
703 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
704 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
705 TU_DYNAMIC_ALL = (1 << 10) - 1,
706 };
707
708 struct tu_vertex_binding
709 {
710 struct tu_buffer *buffer;
711 VkDeviceSize offset;
712 };
713
714 struct tu_viewport_state
715 {
716 uint32_t count;
717 VkViewport viewports[MAX_VIEWPORTS];
718 };
719
720 struct tu_scissor_state
721 {
722 uint32_t count;
723 VkRect2D scissors[MAX_SCISSORS];
724 };
725
726 struct tu_discard_rectangle_state
727 {
728 uint32_t count;
729 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
730 };
731
732 struct tu_dynamic_state
733 {
734 /**
735 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
736 * Defines the set of saved dynamic state.
737 */
738 uint32_t mask;
739
740 struct tu_viewport_state viewport;
741
742 struct tu_scissor_state scissor;
743
744 float line_width;
745
746 struct
747 {
748 float bias;
749 float clamp;
750 float slope;
751 } depth_bias;
752
753 float blend_constants[4];
754
755 struct
756 {
757 float min;
758 float max;
759 } depth_bounds;
760
761 struct
762 {
763 uint32_t front;
764 uint32_t back;
765 } stencil_compare_mask;
766
767 struct
768 {
769 uint32_t front;
770 uint32_t back;
771 } stencil_write_mask;
772
773 struct
774 {
775 uint32_t front;
776 uint32_t back;
777 } stencil_reference;
778
779 struct tu_discard_rectangle_state discard_rectangle;
780 };
781
782 extern const struct tu_dynamic_state default_dynamic_state;
783
784 const char *
785 tu_get_debug_option_name(int id);
786
787 const char *
788 tu_get_perftest_option_name(int id);
789
790 struct tu_descriptor_state
791 {
792 struct tu_descriptor_set *sets[MAX_SETS];
793 uint32_t valid;
794 struct tu_push_descriptor_set push_set;
795 bool push_dirty;
796 uint64_t dynamic_buffers[MAX_DYNAMIC_BUFFERS];
797 };
798
799 struct tu_tile
800 {
801 uint8_t pipe;
802 uint8_t slot;
803 VkOffset2D begin;
804 VkOffset2D end;
805 };
806
807 struct tu_tiling_config
808 {
809 VkRect2D render_area;
810
811 /* position and size of the first tile */
812 VkRect2D tile0;
813 /* number of tiles */
814 VkExtent2D tile_count;
815
816 /* size of the first VSC pipe */
817 VkExtent2D pipe0;
818 /* number of VSC pipes */
819 VkExtent2D pipe_count;
820
821 /* pipe register values */
822 uint32_t pipe_config[MAX_VSC_PIPES];
823 uint32_t pipe_sizes[MAX_VSC_PIPES];
824 };
825
826 enum tu_cmd_dirty_bits
827 {
828 TU_CMD_DIRTY_PIPELINE = 1 << 0,
829 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
830 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
831 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
832 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
833
834 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
835 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
836 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
837 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
838 };
839
840 struct tu_cmd_state
841 {
842 uint32_t dirty;
843
844 struct tu_pipeline *pipeline;
845 struct tu_pipeline *compute_pipeline;
846
847 /* Vertex buffers */
848 struct
849 {
850 struct tu_buffer *buffers[MAX_VBS];
851 VkDeviceSize offsets[MAX_VBS];
852 } vb;
853
854 struct tu_dynamic_state dynamic;
855
856 /* Index buffer */
857 struct tu_buffer *index_buffer;
858 uint64_t index_offset;
859 uint32_t index_type;
860 uint32_t max_index_count;
861 uint64_t index_va;
862
863 const struct tu_render_pass *pass;
864 const struct tu_subpass *subpass;
865 const struct tu_framebuffer *framebuffer;
866
867 struct tu_tiling_config tiling_config;
868
869 struct tu_cs_entry tile_load_ib;
870 struct tu_cs_entry tile_store_ib;
871 };
872
873 struct tu_cmd_pool
874 {
875 VkAllocationCallbacks alloc;
876 struct list_head cmd_buffers;
877 struct list_head free_cmd_buffers;
878 uint32_t queue_family_index;
879 };
880
881 struct tu_cmd_buffer_upload
882 {
883 uint8_t *map;
884 unsigned offset;
885 uint64_t size;
886 struct list_head list;
887 };
888
889 enum tu_cmd_buffer_status
890 {
891 TU_CMD_BUFFER_STATUS_INVALID,
892 TU_CMD_BUFFER_STATUS_INITIAL,
893 TU_CMD_BUFFER_STATUS_RECORDING,
894 TU_CMD_BUFFER_STATUS_EXECUTABLE,
895 TU_CMD_BUFFER_STATUS_PENDING,
896 };
897
898 struct tu_bo_list
899 {
900 uint32_t count;
901 uint32_t capacity;
902 struct drm_msm_gem_submit_bo *bo_infos;
903 };
904
905 #define TU_BO_LIST_FAILED (~0)
906
907 void
908 tu_bo_list_init(struct tu_bo_list *list);
909 void
910 tu_bo_list_destroy(struct tu_bo_list *list);
911 void
912 tu_bo_list_reset(struct tu_bo_list *list);
913 uint32_t
914 tu_bo_list_add(struct tu_bo_list *list,
915 const struct tu_bo *bo,
916 uint32_t flags);
917 VkResult
918 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
919
920 struct tu_cmd_buffer
921 {
922 VK_LOADER_DATA _loader_data;
923
924 struct tu_device *device;
925
926 struct tu_cmd_pool *pool;
927 struct list_head pool_link;
928
929 VkCommandBufferUsageFlags usage_flags;
930 VkCommandBufferLevel level;
931 enum tu_cmd_buffer_status status;
932
933 struct tu_cmd_state state;
934 struct tu_vertex_binding vertex_bindings[MAX_VBS];
935 uint32_t queue_family_index;
936
937 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
938 VkShaderStageFlags push_constant_stages;
939 struct tu_descriptor_set meta_push_descriptors;
940
941 struct tu_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
942
943 struct tu_cmd_buffer_upload upload;
944
945 VkResult record_result;
946
947 struct tu_bo_list bo_list;
948 struct tu_cs cs;
949 struct tu_cs draw_cs;
950 struct tu_cs draw_epilogue_cs;
951 struct tu_cs sub_cs;
952
953 uint16_t marker_reg;
954 uint32_t marker_seqno;
955
956 struct tu_bo scratch_bo;
957 uint32_t scratch_seqno;
958 #define VSC_OVERFLOW 0x8
959 #define VSC_SCRATCH 0x10
960
961 struct tu_bo vsc_data;
962 struct tu_bo vsc_data2;
963 uint32_t vsc_data_pitch;
964 uint32_t vsc_data2_pitch;
965 bool use_vsc_data;
966
967 bool wait_for_idle;
968 };
969
970 /* Temporary struct for tracking a register state to be written, used by
971 * a6xx-pack.h and tu_cs_emit_regs()
972 */
973 struct tu_reg_value {
974 uint32_t reg;
975 uint64_t value;
976 bool is_address;
977 struct tu_bo *bo;
978 bool bo_write;
979 uint32_t bo_offset;
980 uint32_t bo_shift;
981 };
982
983 unsigned
984 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
985 struct tu_cs *cs,
986 enum vgt_event_type event,
987 bool need_seqno);
988
989 bool
990 tu_get_memory_fd(struct tu_device *device,
991 struct tu_device_memory *memory,
992 int *pFD);
993
994 static inline struct tu_descriptor_state *
995 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
996 VkPipelineBindPoint bind_point)
997 {
998 return &cmd_buffer->descriptors[bind_point];
999 }
1000
1001 /*
1002 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1003 *
1004 * Limitations: Can't call normal dispatch functions without binding or
1005 * rebinding
1006 * the compute pipeline.
1007 */
1008 void
1009 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1010 uint32_t x,
1011 uint32_t y,
1012 uint32_t z);
1013
1014 struct tu_event
1015 {
1016 struct tu_bo bo;
1017 };
1018
1019 struct tu_shader_module;
1020
1021 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1022 #define TU_HASH_SHADER_SISCHED (1 << 1)
1023 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1024 void
1025 tu_hash_shaders(unsigned char *hash,
1026 const VkPipelineShaderStageCreateInfo **stages,
1027 const struct tu_pipeline_layout *layout,
1028 const struct tu_pipeline_key *key,
1029 uint32_t flags);
1030
1031 static inline gl_shader_stage
1032 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1033 {
1034 assert(__builtin_popcount(vk_stage) == 1);
1035 return ffs(vk_stage) - 1;
1036 }
1037
1038 static inline VkShaderStageFlagBits
1039 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1040 {
1041 return (1 << mesa_stage);
1042 }
1043
1044 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1045
1046 #define tu_foreach_stage(stage, stage_bits) \
1047 for (gl_shader_stage stage, \
1048 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1049 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1050
1051 struct tu_shader_module
1052 {
1053 unsigned char sha1[20];
1054
1055 uint32_t code_size;
1056 const uint32_t *code[0];
1057 };
1058
1059 struct tu_shader_compile_options
1060 {
1061 struct ir3_shader_key key;
1062
1063 bool optimize;
1064 bool include_binning_pass;
1065 };
1066
1067 struct tu_descriptor_map
1068 {
1069 /* TODO: avoid fixed size array/justify the size */
1070 unsigned num; /* number of array entries */
1071 unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
1072 int set[64];
1073 int binding[64];
1074 int value[64];
1075 int array_size[64];
1076 };
1077
1078 struct tu_shader
1079 {
1080 struct ir3_shader ir3_shader;
1081
1082 struct tu_descriptor_map texture_map;
1083 struct tu_descriptor_map sampler_map;
1084 struct tu_descriptor_map ubo_map;
1085 struct tu_descriptor_map ssbo_map;
1086 struct tu_descriptor_map image_map;
1087
1088 /* This may be true for vertex shaders. When true, variants[1] is the
1089 * binning variant and binning_binary is non-NULL.
1090 */
1091 bool has_binning_pass;
1092
1093 void *binary;
1094 void *binning_binary;
1095
1096 struct ir3_shader_variant variants[0];
1097 };
1098
1099 struct tu_shader *
1100 tu_shader_create(struct tu_device *dev,
1101 gl_shader_stage stage,
1102 const VkPipelineShaderStageCreateInfo *stage_info,
1103 struct tu_pipeline_layout *layout,
1104 const VkAllocationCallbacks *alloc);
1105
1106 void
1107 tu_shader_destroy(struct tu_device *dev,
1108 struct tu_shader *shader,
1109 const VkAllocationCallbacks *alloc);
1110
1111 void
1112 tu_shader_compile_options_init(
1113 struct tu_shader_compile_options *options,
1114 const VkGraphicsPipelineCreateInfo *pipeline_info);
1115
1116 VkResult
1117 tu_shader_compile(struct tu_device *dev,
1118 struct tu_shader *shader,
1119 const struct tu_shader *next_stage,
1120 const struct tu_shader_compile_options *options,
1121 const VkAllocationCallbacks *alloc);
1122
1123 struct tu_program_descriptor_linkage
1124 {
1125 struct ir3_ubo_analysis_state ubo_state;
1126 struct ir3_const_state const_state;
1127
1128 uint32_t constlen;
1129
1130 struct tu_descriptor_map texture_map;
1131 struct tu_descriptor_map sampler_map;
1132 struct tu_descriptor_map ubo_map;
1133 struct tu_descriptor_map ssbo_map;
1134 struct tu_descriptor_map image_map;
1135 };
1136
1137 struct tu_pipeline
1138 {
1139 struct tu_cs cs;
1140
1141 struct tu_dynamic_state dynamic_state;
1142
1143 struct tu_pipeline_layout *layout;
1144
1145 bool need_indirect_descriptor_sets;
1146 VkShaderStageFlags active_stages;
1147
1148 struct
1149 {
1150 struct tu_bo binary_bo;
1151 struct tu_cs_entry state_ib;
1152 struct tu_cs_entry binning_state_ib;
1153
1154 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1155 } program;
1156
1157 struct
1158 {
1159 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1160 uint16_t strides[MAX_VERTEX_ATTRIBS];
1161 uint16_t offsets[MAX_VERTEX_ATTRIBS];
1162 uint32_t count;
1163
1164 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1165 uint16_t binning_strides[MAX_VERTEX_ATTRIBS];
1166 uint16_t binning_offsets[MAX_VERTEX_ATTRIBS];
1167 uint32_t binning_count;
1168
1169 struct tu_cs_entry state_ib;
1170 struct tu_cs_entry binning_state_ib;
1171 } vi;
1172
1173 struct
1174 {
1175 enum pc_di_primtype primtype;
1176 bool primitive_restart;
1177 } ia;
1178
1179 struct
1180 {
1181 struct tu_cs_entry state_ib;
1182 } vp;
1183
1184 struct
1185 {
1186 uint32_t gras_su_cntl;
1187 struct tu_cs_entry state_ib;
1188 } rast;
1189
1190 struct
1191 {
1192 struct tu_cs_entry state_ib;
1193 } ds;
1194
1195 struct
1196 {
1197 struct tu_cs_entry state_ib;
1198 } blend;
1199
1200 struct
1201 {
1202 uint32_t local_size[3];
1203 } compute;
1204 };
1205
1206 void
1207 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1208
1209 void
1210 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1211
1212 void
1213 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1214 uint32_t gras_su_cntl,
1215 float line_width);
1216
1217 void
1218 tu6_emit_depth_bias(struct tu_cs *cs,
1219 float constant_factor,
1220 float clamp,
1221 float slope_factor);
1222
1223 void
1224 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1225 uint32_t front,
1226 uint32_t back);
1227
1228 void
1229 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1230
1231 void
1232 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1233
1234 void
1235 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1236
1237 struct tu_userdata_info *
1238 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1239 gl_shader_stage stage,
1240 int idx);
1241
1242 struct tu_shader_variant *
1243 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1244
1245 struct tu_graphics_pipeline_create_info
1246 {
1247 bool use_rectlist;
1248 bool db_depth_clear;
1249 bool db_stencil_clear;
1250 bool db_depth_disable_expclear;
1251 bool db_stencil_disable_expclear;
1252 bool db_flush_depth_inplace;
1253 bool db_flush_stencil_inplace;
1254 bool db_resummarize;
1255 uint32_t custom_blend_mode;
1256 };
1257
1258 struct tu_native_format
1259 {
1260 int vtx; /* VFMTn_xxx or -1 */
1261 int tex; /* TFMTn_xxx or -1 */
1262 int rb; /* RBn_xxx or -1 */
1263 int swap; /* enum a3xx_color_swap */
1264 bool present; /* internal only; always true to external users */
1265 };
1266
1267 const struct tu_native_format *
1268 tu6_get_native_format(VkFormat format);
1269
1270 void
1271 tu_pack_clear_value(const VkClearValue *val,
1272 VkFormat format,
1273 uint32_t buf[4]);
1274
1275 void
1276 tu_2d_clear_color(const VkClearColorValue *val, VkFormat format, uint32_t buf[4]);
1277
1278 void
1279 tu_2d_clear_zs(const VkClearDepthStencilValue *val, VkFormat format, uint32_t buf[4]);
1280
1281 enum a6xx_2d_ifmt tu6_fmt_to_ifmt(enum a6xx_format fmt);
1282 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1283
1284 struct tu_image_level
1285 {
1286 VkDeviceSize offset;
1287 VkDeviceSize size;
1288 uint32_t pitch;
1289 };
1290
1291 struct tu_image
1292 {
1293 VkImageType type;
1294 /* The original VkFormat provided by the client. This may not match any
1295 * of the actual surface formats.
1296 */
1297 VkFormat vk_format;
1298 VkImageAspectFlags aspects;
1299 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1300 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1301 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1302 VkExtent3D extent;
1303 uint32_t level_count;
1304 uint32_t layer_count;
1305 VkSampleCountFlagBits samples;
1306
1307
1308 uint32_t alignment;
1309
1310 struct fdl_layout layout;
1311
1312 unsigned queue_family_mask;
1313 bool exclusive;
1314 bool shareable;
1315
1316 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1317 VkDeviceMemory owned_memory;
1318
1319 /* Set when bound */
1320 struct tu_bo *bo;
1321 VkDeviceSize bo_offset;
1322 };
1323
1324 unsigned
1325 tu_image_queue_family_mask(const struct tu_image *image,
1326 uint32_t family,
1327 uint32_t queue_family);
1328
1329 static inline uint32_t
1330 tu_get_layerCount(const struct tu_image *image,
1331 const VkImageSubresourceRange *range)
1332 {
1333 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1334 ? image->layer_count - range->baseArrayLayer
1335 : range->layerCount;
1336 }
1337
1338 static inline uint32_t
1339 tu_get_levelCount(const struct tu_image *image,
1340 const VkImageSubresourceRange *range)
1341 {
1342 return range->levelCount == VK_REMAINING_MIP_LEVELS
1343 ? image->level_count - range->baseMipLevel
1344 : range->levelCount;
1345 }
1346
1347 static inline VkDeviceSize
1348 tu_layer_size(struct tu_image *image, int level)
1349 {
1350 return fdl_layer_stride(&image->layout, level);
1351 }
1352
1353 static inline uint32_t
1354 tu_image_stride(struct tu_image *image, int level)
1355 {
1356 return image->layout.slices[level].pitch * image->layout.cpp;
1357 }
1358
1359 static inline uint64_t
1360 tu_image_base(struct tu_image *image, int level, int layer)
1361 {
1362 return image->bo->iova + image->bo_offset +
1363 fdl_surface_offset(&image->layout, level, layer);
1364 }
1365
1366 #define tu_image_base_ref(image, level, layer) \
1367 .bo = image->bo, \
1368 .bo_offset = (image->bo_offset + fdl_surface_offset(&image->layout, \
1369 level, layer))
1370
1371 #define tu_image_view_base_ref(iview) \
1372 tu_image_base_ref(iview->image, iview->base_mip, iview->base_layer)
1373
1374 static inline VkDeviceSize
1375 tu_image_ubwc_size(struct tu_image *image, int level)
1376 {
1377 return image->layout.ubwc_layer_size;
1378 }
1379
1380 static inline uint32_t
1381 tu_image_ubwc_pitch(struct tu_image *image, int level)
1382 {
1383 return image->layout.ubwc_slices[level].pitch;
1384 }
1385
1386 static inline uint64_t
1387 tu_image_ubwc_surface_offset(struct tu_image *image, int level, int layer)
1388 {
1389 return image->layout.ubwc_slices[level].offset +
1390 layer * tu_image_ubwc_size(image, level);
1391 }
1392
1393 static inline uint64_t
1394 tu_image_ubwc_base(struct tu_image *image, int level, int layer)
1395 {
1396 return image->bo->iova + image->bo_offset +
1397 tu_image_ubwc_surface_offset(image, level, layer);
1398 }
1399
1400 #define tu_image_ubwc_base_ref(image, level, layer) \
1401 .bo = image->bo, \
1402 .bo_offset = (image->bo_offset + tu_image_ubwc_surface_offset(image, \
1403 level, layer))
1404
1405 #define tu_image_view_ubwc_base_ref(iview) \
1406 tu_image_ubwc_base_ref(iview->image, iview->base_mip, iview->base_layer)
1407
1408 enum a6xx_tile_mode
1409 tu6_get_image_tile_mode(struct tu_image *image, int level);
1410 enum a3xx_msaa_samples
1411 tu_msaa_samples(uint32_t samples);
1412
1413 struct tu_image_view
1414 {
1415 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1416
1417 VkImageViewType type;
1418 VkImageAspectFlags aspect_mask;
1419 VkFormat vk_format;
1420 uint32_t base_layer;
1421 uint32_t layer_count;
1422 uint32_t base_mip;
1423 uint32_t level_count;
1424 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1425
1426 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1427
1428 /* Descriptor for use as a storage image as opposed to a sampled image.
1429 * This has a few differences for cube maps (e.g. type).
1430 */
1431 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1432 };
1433
1434 struct tu_sampler
1435 {
1436 uint32_t state[A6XX_TEX_SAMP_DWORDS];
1437
1438 bool needs_border;
1439 VkBorderColor border;
1440 };
1441
1442 VkResult
1443 tu_image_create(VkDevice _device,
1444 const VkImageCreateInfo *pCreateInfo,
1445 const VkAllocationCallbacks *alloc,
1446 VkImage *pImage,
1447 uint64_t modifier);
1448
1449 VkResult
1450 tu_image_from_gralloc(VkDevice device_h,
1451 const VkImageCreateInfo *base_info,
1452 const VkNativeBufferANDROID *gralloc_info,
1453 const VkAllocationCallbacks *alloc,
1454 VkImage *out_image_h);
1455
1456 void
1457 tu_image_view_init(struct tu_image_view *view,
1458 struct tu_device *device,
1459 const VkImageViewCreateInfo *pCreateInfo);
1460
1461 struct tu_buffer_view
1462 {
1463 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1464
1465 struct tu_buffer *buffer;
1466 };
1467 void
1468 tu_buffer_view_init(struct tu_buffer_view *view,
1469 struct tu_device *device,
1470 const VkBufferViewCreateInfo *pCreateInfo);
1471
1472 static inline struct VkExtent3D
1473 tu_sanitize_image_extent(const VkImageType imageType,
1474 const struct VkExtent3D imageExtent)
1475 {
1476 switch (imageType) {
1477 case VK_IMAGE_TYPE_1D:
1478 return (VkExtent3D) { imageExtent.width, 1, 1 };
1479 case VK_IMAGE_TYPE_2D:
1480 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1481 case VK_IMAGE_TYPE_3D:
1482 return imageExtent;
1483 default:
1484 unreachable("invalid image type");
1485 }
1486 }
1487
1488 static inline struct VkOffset3D
1489 tu_sanitize_image_offset(const VkImageType imageType,
1490 const struct VkOffset3D imageOffset)
1491 {
1492 switch (imageType) {
1493 case VK_IMAGE_TYPE_1D:
1494 return (VkOffset3D) { imageOffset.x, 0, 0 };
1495 case VK_IMAGE_TYPE_2D:
1496 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1497 case VK_IMAGE_TYPE_3D:
1498 return imageOffset;
1499 default:
1500 unreachable("invalid image type");
1501 }
1502 }
1503
1504 struct tu_attachment_info
1505 {
1506 struct tu_image_view *attachment;
1507 };
1508
1509 struct tu_framebuffer
1510 {
1511 uint32_t width;
1512 uint32_t height;
1513 uint32_t layers;
1514
1515 uint32_t attachment_count;
1516 struct tu_attachment_info attachments[0];
1517 };
1518
1519 struct tu_subpass_attachment
1520 {
1521 uint32_t attachment;
1522 };
1523
1524 struct tu_subpass
1525 {
1526 uint32_t input_count;
1527 uint32_t color_count;
1528 struct tu_subpass_attachment *input_attachments;
1529 struct tu_subpass_attachment *color_attachments;
1530 struct tu_subpass_attachment *resolve_attachments;
1531 struct tu_subpass_attachment depth_stencil_attachment;
1532
1533 VkSampleCountFlagBits samples;
1534 };
1535
1536 struct tu_render_pass_attachment
1537 {
1538 VkFormat format;
1539 uint32_t cpp;
1540 VkAttachmentLoadOp load_op;
1541 VkAttachmentLoadOp stencil_load_op;
1542 VkAttachmentStoreOp store_op;
1543 VkAttachmentStoreOp stencil_store_op;
1544 int32_t gmem_offset;
1545 };
1546
1547 struct tu_render_pass
1548 {
1549 uint32_t attachment_count;
1550 uint32_t subpass_count;
1551 uint32_t gmem_pixels;
1552 struct tu_subpass_attachment *subpass_attachments;
1553 struct tu_render_pass_attachment *attachments;
1554 struct tu_subpass subpasses[0];
1555 };
1556
1557 VkResult
1558 tu_device_init_meta(struct tu_device *device);
1559 void
1560 tu_device_finish_meta(struct tu_device *device);
1561
1562 struct tu_query_pool
1563 {
1564 VkQueryType type;
1565 uint32_t stride;
1566 uint64_t size;
1567 uint32_t pipeline_statistics;
1568 struct tu_bo bo;
1569 };
1570
1571 struct tu_semaphore
1572 {
1573 uint32_t syncobj;
1574 uint32_t temp_syncobj;
1575 };
1576
1577 void
1578 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1579 VkPipelineBindPoint bind_point,
1580 struct tu_descriptor_set *set,
1581 unsigned idx);
1582
1583 void
1584 tu_update_descriptor_sets(struct tu_device *device,
1585 struct tu_cmd_buffer *cmd_buffer,
1586 VkDescriptorSet overrideSet,
1587 uint32_t descriptorWriteCount,
1588 const VkWriteDescriptorSet *pDescriptorWrites,
1589 uint32_t descriptorCopyCount,
1590 const VkCopyDescriptorSet *pDescriptorCopies);
1591
1592 void
1593 tu_update_descriptor_set_with_template(
1594 struct tu_device *device,
1595 struct tu_cmd_buffer *cmd_buffer,
1596 struct tu_descriptor_set *set,
1597 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1598 const void *pData);
1599
1600 void
1601 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1602 VkPipelineBindPoint pipelineBindPoint,
1603 VkPipelineLayout _layout,
1604 uint32_t set,
1605 uint32_t descriptorWriteCount,
1606 const VkWriteDescriptorSet *pDescriptorWrites);
1607
1608 int
1609 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1610
1611 int
1612 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1613
1614 int
1615 tu_drm_submitqueue_new(const struct tu_device *dev,
1616 int priority,
1617 uint32_t *queue_id);
1618
1619 void
1620 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1621
1622 uint32_t
1623 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1624 uint32_t
1625 tu_gem_import_dmabuf(const struct tu_device *dev,
1626 int prime_fd,
1627 uint64_t size);
1628 int
1629 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1630 void
1631 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1632 uint64_t
1633 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1634 uint64_t
1635 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1636
1637 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1638 \
1639 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1640 { \
1641 return (struct __tu_type *) _handle; \
1642 } \
1643 \
1644 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1645 { \
1646 return (__VkType) _obj; \
1647 }
1648
1649 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1650 \
1651 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1652 { \
1653 return (struct __tu_type *) (uintptr_t) _handle; \
1654 } \
1655 \
1656 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1657 { \
1658 return (__VkType)(uintptr_t) _obj; \
1659 }
1660
1661 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1662 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1663
1664 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1665 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1666 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1667 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1668 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1669
1670 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1671 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1672 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1673 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1674 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1675 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1676 VkDescriptorSetLayout)
1677 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1678 VkDescriptorUpdateTemplate)
1679 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1680 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1681 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1682 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1683 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1684 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1685 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1686 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1687 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1688 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1689 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1690 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1691 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1692 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1693
1694 #endif /* TU_PRIVATE_H */