src/freedreno/vulkan/tu_shader.c

   1 /*
   2  * Copyright © 2019 Google LLC
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "tu_private.h"
  25
  26 #include "spirv/nir_spirv.h"
  27 #include "util/mesa-sha1.h"
  28 #include "nir/nir_xfb_info.h"
  29 #include "nir/nir_vulkan.h"
  30 #include "vk_util.h"
  31
  32 #include "ir3/ir3_nir.h"
  33
  34 static nir_shader *
  35 tu_spirv_to_nir(struct ir3_compiler *compiler,
  36                 const uint32_t *words,
  37                 size_t word_count,
  38                 gl_shader_stage stage,
  39                 const char *entry_point_name,
  40                 const VkSpecializationInfo *spec_info)
  41 {
  42    /* TODO these are made-up */
  43    const struct spirv_to_nir_options spirv_options = {
  44       .frag_coord_is_sysval = true,
  45       .lower_ubo_ssbo_access_to_offsets = true,
  46       .tess_levels_are_sysvals = true,
  47       .lower_tess_levels_to_vec = true,
  48       .caps = {
  49          .transform_feedback = true,
  50          .tessellation = true,
  51          .draw_parameters = true,
  52       },
  53    };
  54    const nir_shader_compiler_options *nir_options =
  55       ir3_get_compiler_options(compiler);
  56
  57    /* convert VkSpecializationInfo */
  58    struct nir_spirv_specialization *spec = NULL;
  59    uint32_t num_spec = 0;
  60    if (spec_info && spec_info->mapEntryCount) {
  61       spec = calloc(spec_info->mapEntryCount, sizeof(*spec));
  62       if (!spec)
  63          return NULL;
  64
  65       for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
  66          const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
  67          const void *data = spec_info->pData + entry->offset;
  68          assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
  69          spec[i].id = entry->constantID;
  70          switch (entry->size) {
  71          case 8:
  72             spec[i].value.u64 = *(const uint64_t *)data;
  73             break;
  74          case 4:
  75             spec[i].value.u32 = *(const uint32_t *)data;
  76             break;
  77          case 2:
  78             spec[i].value.u16 = *(const uint16_t *)data;
  79             break;
  80          case 1:
  81             spec[i].value.u8 = *(const uint8_t *)data;
  82             break;
  83          default:
  84             assert(!"Invalid spec constant size");
  85             break;
  86          }
  87          spec[i].defined_on_module = false;
  88       }
  89
  90       num_spec = spec_info->mapEntryCount;
  91    }
  92
  93    nir_shader *nir =
  94       spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
  95                    &spirv_options, nir_options);
  96
  97    free(spec);
  98
  99    assert(nir->info.stage == stage);
 100    nir_validate_shader(nir, "after spirv_to_nir");
 101
 102    return nir;
 103 }
 104
 105 static void
 106 lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr,
 107                          struct tu_shader *shader)
 108 {
 109    nir_intrinsic_instr *load =
 110       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
 111    load->num_components = instr->num_components;
 112    uint32_t base = nir_intrinsic_base(instr);
 113    assert(base % 4 == 0);
 114    assert(base >= shader->push_consts.lo * 16);
 115    base -= shader->push_consts.lo * 16;
 116    nir_intrinsic_set_base(load, base / 4);
 117    load->src[0] =
 118       nir_src_for_ssa(nir_ushr(b, instr->src[0].ssa, nir_imm_int(b, 2)));
 119    nir_ssa_dest_init(&load->instr, &load->dest,
 120                      load->num_components, instr->dest.ssa.bit_size,
 121                      instr->dest.ssa.name);
 122    nir_builder_instr_insert(b, &load->instr);
 123    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(&load->dest.ssa));
 124
 125    nir_instr_remove(&instr->instr);
 126 }
 127
 128 static void
 129 lower_vulkan_resource_index(nir_builder *b, nir_intrinsic_instr *instr,
 130                             struct tu_shader *shader,
 131                             const struct tu_pipeline_layout *layout)
 132 {
 133    nir_ssa_def *vulkan_idx = instr->src[0].ssa;
 134
 135    unsigned set = nir_intrinsic_desc_set(instr);
 136    unsigned binding = nir_intrinsic_binding(instr);
 137    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 138    struct tu_descriptor_set_binding_layout *binding_layout =
 139       &set_layout->binding[binding];
 140    uint32_t base;
 141
 142    shader->active_desc_sets |= 1u << set;
 143
 144    switch (binding_layout->type) {
 145    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 146    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 147       base = layout->set[set].dynamic_offset_start +
 148          binding_layout->dynamic_offset_offset;
 149       set = MAX_SETS;
 150       break;
 151    default:
 152       base = binding_layout->offset / (4 * A6XX_TEX_CONST_DWORDS);
 153       break;
 154    }
 155
 156    nir_intrinsic_instr *bindless =
 157       nir_intrinsic_instr_create(b->shader,
 158                                  nir_intrinsic_bindless_resource_ir3);
 159    bindless->num_components = 0;
 160    nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 161                      1, 32, NULL);
 162    nir_intrinsic_set_desc_set(bindless, set);
 163    bindless->src[0] = nir_src_for_ssa(nir_iadd(b, nir_imm_int(b, base), vulkan_idx));
 164    nir_builder_instr_insert(b, &bindless->instr);
 165
 166    nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 167                             nir_src_for_ssa(&bindless->dest.ssa));
 168    nir_instr_remove(&instr->instr);
 169 }
 170
 171 static nir_ssa_def *
 172 build_bindless(nir_builder *b, nir_deref_instr *deref, bool is_sampler,
 173                struct tu_shader *shader,
 174                const struct tu_pipeline_layout *layout)
 175 {
 176    nir_variable *var = nir_deref_instr_get_variable(deref);
 177
 178    unsigned set = var->data.descriptor_set;
 179    unsigned binding = var->data.binding;
 180    const struct tu_descriptor_set_binding_layout *bind_layout =
 181       &layout->set[set].layout->binding[binding];
 182
 183    /* input attachments use non bindless workaround */
 184    if (bind_layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
 185       const struct glsl_type *glsl_type = glsl_without_array(var->type);
 186       uint32_t idx = var->data.index * 2;
 187
 188       b->shader->info.textures_used |=
 189          ((1ull << (bind_layout->array_size * 2)) - 1) << (idx * 2);
 190
 191       /* D24S8 workaround: stencil of D24S8 will be sampled as uint */
 192       if (glsl_get_sampler_result_type(glsl_type) == GLSL_TYPE_UINT)
 193          idx += 1;
 194
 195       if (deref->deref_type == nir_deref_type_var)
 196          return nir_imm_int(b, idx);
 197
 198       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 199       return nir_iadd(b, nir_imm_int(b, idx),
 200                       nir_imul_imm(b, arr_index, 2));
 201    }
 202
 203    shader->active_desc_sets |= 1u << set;
 204
 205    nir_ssa_def *desc_offset;
 206    unsigned descriptor_stride;
 207    unsigned offset = 0;
 208    /* Samplers come second in combined image/sampler descriptors, see
 209       * write_combined_image_sampler_descriptor().
 210       */
 211    if (is_sampler && bind_layout->type ==
 212          VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
 213       offset = 1;
 214    }
 215    desc_offset =
 216       nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) +
 217                   offset);
 218    descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS);
 219
 220    if (deref->deref_type != nir_deref_type_var) {
 221       assert(deref->deref_type == nir_deref_type_array);
 222
 223       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 224       desc_offset = nir_iadd(b, desc_offset,
 225                              nir_imul_imm(b, arr_index, descriptor_stride));
 226    }
 227
 228    nir_intrinsic_instr *bindless =
 229       nir_intrinsic_instr_create(b->shader,
 230                                  nir_intrinsic_bindless_resource_ir3);
 231    bindless->num_components = 0;
 232    nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 233                      1, 32, NULL);
 234    nir_intrinsic_set_desc_set(bindless, set);
 235    bindless->src[0] = nir_src_for_ssa(desc_offset);
 236    nir_builder_instr_insert(b, &bindless->instr);
 237
 238    return &bindless->dest.ssa;
 239 }
 240
 241 static void
 242 lower_image_deref(nir_builder *b,
 243                   nir_intrinsic_instr *instr, struct tu_shader *shader,
 244                   const struct tu_pipeline_layout *layout)
 245 {
 246    nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
 247    nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 248    nir_rewrite_image_intrinsic(instr, bindless, true);
 249 }
 250
 251 static bool
 252 lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
 253                 struct tu_shader *shader,
 254                 const struct tu_pipeline_layout *layout)
 255 {
 256    switch (instr->intrinsic) {
 257    case nir_intrinsic_load_layer_id:
 258       /* TODO: remove this when layered rendering is implemented */
 259       nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 260                                nir_src_for_ssa(nir_imm_int(b, 0)));
 261       nir_instr_remove(&instr->instr);
 262       return true;
 263
 264    case nir_intrinsic_load_push_constant:
 265       lower_load_push_constant(b, instr, shader);
 266       return true;
 267
 268    case nir_intrinsic_vulkan_resource_index:
 269       lower_vulkan_resource_index(b, instr, shader, layout);
 270       return true;
 271
 272    case nir_intrinsic_image_deref_load:
 273    case nir_intrinsic_image_deref_store:
 274    case nir_intrinsic_image_deref_atomic_add:
 275    case nir_intrinsic_image_deref_atomic_imin:
 276    case nir_intrinsic_image_deref_atomic_umin:
 277    case nir_intrinsic_image_deref_atomic_imax:
 278    case nir_intrinsic_image_deref_atomic_umax:
 279    case nir_intrinsic_image_deref_atomic_and:
 280    case nir_intrinsic_image_deref_atomic_or:
 281    case nir_intrinsic_image_deref_atomic_xor:
 282    case nir_intrinsic_image_deref_atomic_exchange:
 283    case nir_intrinsic_image_deref_atomic_comp_swap:
 284    case nir_intrinsic_image_deref_size:
 285    case nir_intrinsic_image_deref_samples:
 286       lower_image_deref(b, instr, shader, layout);
 287       return true;
 288
 289    default:
 290       return false;
 291    }
 292 }
 293
 294 static void
 295 lower_tex_ycbcr(const struct tu_pipeline_layout *layout,
 296                 nir_builder *builder,
 297                 nir_tex_instr *tex)
 298 {
 299    int deref_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 300    assert(deref_src_idx >= 0);
 301    nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);
 302
 303    nir_variable *var = nir_deref_instr_get_variable(deref);
 304    const struct tu_descriptor_set_layout *set_layout =
 305       layout->set[var->data.descriptor_set].layout;
 306    const struct tu_descriptor_set_binding_layout *binding =
 307       &set_layout->binding[var->data.binding];
 308    const struct tu_sampler_ycbcr_conversion *ycbcr_samplers =
 309       tu_immutable_ycbcr_samplers(set_layout, binding);
 310
 311    if (!ycbcr_samplers)
 312       return;
 313
 314    /* For the following instructions, we don't apply any change */
 315    if (tex->op == nir_texop_txs ||
 316        tex->op == nir_texop_query_levels ||
 317        tex->op == nir_texop_lod)
 318       return;
 319
 320    assert(tex->texture_index == 0);
 321    unsigned array_index = 0;
 322    if (deref->deref_type != nir_deref_type_var) {
 323       assert(deref->deref_type == nir_deref_type_array);
 324       if (!nir_src_is_const(deref->arr.index))
 325          return;
 326       array_index = nir_src_as_uint(deref->arr.index);
 327       array_index = MIN2(array_index, binding->array_size - 1);
 328    }
 329    const struct tu_sampler_ycbcr_conversion *ycbcr_sampler = ycbcr_samplers + array_index;
 330
 331    if (ycbcr_sampler->ycbcr_model == VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY)
 332       return;
 333
 334    builder->cursor = nir_after_instr(&tex->instr);
 335
 336    uint8_t bits = vk_format_get_component_bits(ycbcr_sampler->format,
 337                                                UTIL_FORMAT_COLORSPACE_RGB,
 338                                                PIPE_SWIZZLE_X);
 339    uint32_t bpcs[3] = {bits, bits, bits}; /* TODO: use right bpc for each channel ? */
 340    nir_ssa_def *result = nir_convert_ycbcr_to_rgb(builder,
 341                                                   ycbcr_sampler->ycbcr_model,
 342                                                   ycbcr_sampler->ycbcr_range,
 343                                                   &tex->dest.ssa,
 344                                                   bpcs);
 345    nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, nir_src_for_ssa(result),
 346                                   result->parent_instr);
 347
 348    builder->cursor = nir_before_instr(&tex->instr);
 349 }
 350
 351 static bool
 352 lower_tex(nir_builder *b, nir_tex_instr *tex,
 353           struct tu_shader *shader, const struct tu_pipeline_layout *layout)
 354 {
 355    lower_tex_ycbcr(layout, b, tex);
 356
 357    int sampler_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_deref);
 358    if (sampler_src_idx >= 0) {
 359       nir_deref_instr *deref = nir_src_as_deref(tex->src[sampler_src_idx].src);
 360       nir_ssa_def *bindless = build_bindless(b, deref, true, shader, layout);
 361       nir_instr_rewrite_src(&tex->instr, &tex->src[sampler_src_idx].src,
 362                             nir_src_for_ssa(bindless));
 363       tex->src[sampler_src_idx].src_type = nir_tex_src_sampler_handle;
 364    }
 365
 366    int tex_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 367    if (tex_src_idx >= 0) {
 368       nir_deref_instr *deref = nir_src_as_deref(tex->src[tex_src_idx].src);
 369       nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 370       nir_instr_rewrite_src(&tex->instr, &tex->src[tex_src_idx].src,
 371                             nir_src_for_ssa(bindless));
 372       tex->src[tex_src_idx].src_type = nir_tex_src_texture_handle;
 373
 374       /* for the input attachment case: */
 375       if (bindless->parent_instr->type != nir_instr_type_intrinsic)
 376          tex->src[tex_src_idx].src_type = nir_tex_src_texture_offset;
 377    }
 378
 379    return true;
 380 }
 381
 382 static bool
 383 lower_impl(nir_function_impl *impl, struct tu_shader *shader,
 384             const struct tu_pipeline_layout *layout)
 385 {
 386    nir_builder b;
 387    nir_builder_init(&b, impl);
 388    bool progress = false;
 389
 390    nir_foreach_block(block, impl) {
 391       nir_foreach_instr_safe(instr, block) {
 392          b.cursor = nir_before_instr(instr);
 393          switch (instr->type) {
 394          case nir_instr_type_tex:
 395             progress |= lower_tex(&b, nir_instr_as_tex(instr), shader, layout);
 396             break;
 397          case nir_instr_type_intrinsic:
 398             progress |= lower_intrinsic(&b, nir_instr_as_intrinsic(instr), shader, layout);
 399             break;
 400          default:
 401             break;
 402          }
 403       }
 404    }
 405
 406    return progress;
 407 }
 408
 409
 410 /* Figure out the range of push constants that we're actually going to push to
 411  * the shader, and tell the backend to reserve this range when pushing UBO
 412  * constants.
 413  */
 414
 415 static void
 416 gather_push_constants(nir_shader *shader, struct tu_shader *tu_shader)
 417 {
 418    uint32_t min = UINT32_MAX, max = 0;
 419    nir_foreach_function(function, shader) {
 420       if (!function->impl)
 421          continue;
 422
 423       nir_foreach_block(block, function->impl) {
 424          nir_foreach_instr_safe(instr, block) {
 425             if (instr->type != nir_instr_type_intrinsic)
 426                continue;
 427
 428             nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 429             if (intrin->intrinsic != nir_intrinsic_load_push_constant)
 430                continue;
 431
 432             uint32_t base = nir_intrinsic_base(intrin);
 433             uint32_t range = nir_intrinsic_range(intrin);
 434             min = MIN2(min, base);
 435             max = MAX2(max, base + range);
 436             break;
 437          }
 438       }
 439    }
 440
 441    if (min >= max) {
 442       tu_shader->push_consts.lo = 0;
 443       tu_shader->push_consts.count = 0;
 444       return;
 445    }
 446
 447    /* CP_LOAD_STATE OFFSET and NUM_UNIT are in units of vec4 (4 dwords),
 448     * however there's an alignment requirement of 4 on OFFSET. Expand the
 449     * range and change units accordingly.
 450     */
 451    tu_shader->push_consts.lo = (min / 16) / 4 * 4;
 452    tu_shader->push_consts.count =
 453       align(max, 16) / 16 - tu_shader->push_consts.lo;
 454 }
 455
 456 static bool
 457 tu_lower_io(nir_shader *shader, struct tu_shader *tu_shader,
 458             const struct tu_pipeline_layout *layout)
 459 {
 460    bool progress = false;
 461
 462    gather_push_constants(shader, tu_shader);
 463
 464    nir_foreach_function(function, shader) {
 465       if (function->impl)
 466          progress |= lower_impl(function->impl, tu_shader, layout);
 467    }
 468
 469    /* Remove now-unused variables so that when we gather the shader info later
 470     * they won't be counted.
 471     */
 472
 473    if (progress)
 474       nir_opt_dce(shader);
 475
 476    progress |=
 477       nir_remove_dead_variables(shader,
 478                                 nir_var_uniform | nir_var_mem_ubo | nir_var_mem_ssbo,
 479                                 NULL);
 480
 481    return progress;
 482 }
 483
 484 static void
 485 tu_gather_xfb_info(nir_shader *nir, struct ir3_stream_output_info *info)
 486 {
 487    nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
 488
 489    if (!xfb)
 490       return;
 491
 492    /* creating a map from VARYING_SLOT_* enums to consecutive index */
 493    uint8_t num_outputs = 0;
 494    uint64_t outputs_written = 0;
 495    for (int i = 0; i < xfb->output_count; i++)
 496       outputs_written |= BITFIELD64_BIT(xfb->outputs[i].location);
 497
 498    uint8_t output_map[VARYING_SLOT_TESS_MAX];
 499    memset(output_map, 0, sizeof(output_map));
 500
 501    for (unsigned attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 502       if (outputs_written & BITFIELD64_BIT(attr))
 503          output_map[attr] = num_outputs++;
 504    }
 505
 506    assert(xfb->output_count < IR3_MAX_SO_OUTPUTS);
 507    info->num_outputs = xfb->output_count;
 508
 509    for (int i = 0; i < IR3_MAX_SO_BUFFERS; i++)
 510       info->stride[i] = xfb->buffers[i].stride / 4;
 511
 512    for (int i = 0; i < xfb->output_count; i++) {
 513       info->output[i].register_index = output_map[xfb->outputs[i].location];
 514       info->output[i].start_component = xfb->outputs[i].component_offset;
 515       info->output[i].num_components =
 516                            util_bitcount(xfb->outputs[i].component_mask);
 517       info->output[i].output_buffer  = xfb->outputs[i].buffer;
 518       info->output[i].dst_offset = xfb->outputs[i].offset / 4;
 519       info->output[i].stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
 520    }
 521
 522    ralloc_free(xfb);
 523 }
 524
 525 struct tu_shader *
 526 tu_shader_create(struct tu_device *dev,
 527                  gl_shader_stage stage,
 528                  const VkPipelineShaderStageCreateInfo *stage_info,
 529                  struct tu_pipeline_layout *layout,
 530                  const VkAllocationCallbacks *alloc)
 531 {
 532    struct tu_shader *shader;
 533
 534    shader = vk_zalloc2(
 535       &dev->alloc, alloc,
 536       sizeof(*shader),
 537       8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
 538    if (!shader)
 539       return NULL;
 540
 541    nir_shader *nir;
 542    if (stage_info) {
 543       /* translate SPIR-V to NIR */
 544       const struct tu_shader_module *module =
 545          tu_shader_module_from_handle(stage_info->module);
 546       assert(module->code_size % 4 == 0);
 547       nir = tu_spirv_to_nir(
 548          dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
 549          stage, stage_info->pName, stage_info->pSpecializationInfo);
 550    } else {
 551       assert(stage == MESA_SHADER_FRAGMENT);
 552       nir_builder fs_b;
 553       const nir_shader_compiler_options *nir_options =
 554          ir3_get_compiler_options(dev->compiler);
 555       nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, nir_options);
 556       fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
 557       nir = fs_b.shader;
 558    }
 559
 560    if (!nir) {
 561       vk_free2(&dev->alloc, alloc, shader);
 562       return NULL;
 563    }
 564
 565    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
 566       fprintf(stderr, "translated nir:\n");
 567       nir_print_shader(nir, stderr);
 568    }
 569
 570    /* multi step inlining procedure */
 571    NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
 572    NIR_PASS_V(nir, nir_lower_returns);
 573    NIR_PASS_V(nir, nir_inline_functions);
 574    NIR_PASS_V(nir, nir_opt_deref);
 575    foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 576       if (!func->is_entrypoint)
 577          exec_node_remove(&func->node);
 578    }
 579    assert(exec_list_length(&nir->functions) == 1);
 580    NIR_PASS_V(nir, nir_lower_variable_initializers, ~nir_var_function_temp);
 581
 582    /* Split member structs.  We do this before lower_io_to_temporaries so that
 583     * it doesn't lower system values to temporaries by accident.
 584     */
 585    NIR_PASS_V(nir, nir_split_var_copies);
 586    NIR_PASS_V(nir, nir_split_per_member_structs);
 587
 588    NIR_PASS_V(nir, nir_remove_dead_variables,
 589               nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
 590               NULL);
 591
 592    /* Gather information for transform feedback.
 593     * This should be called after nir_split_per_member_structs.
 594     * Also needs to be called after nir_remove_dead_variables with varyings,
 595     * so that we could align stream outputs correctly.
 596     */
 597    struct ir3_stream_output_info so_info = {};
 598    if (nir->info.stage == MESA_SHADER_VERTEX ||
 599          nir->info.stage == MESA_SHADER_TESS_EVAL ||
 600          nir->info.stage == MESA_SHADER_GEOMETRY)
 601       tu_gather_xfb_info(nir, &so_info);
 602
 603    NIR_PASS_V(nir, nir_propagate_invariant);
 604
 605    NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true);
 606
 607    NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 608    NIR_PASS_V(nir, nir_split_var_copies);
 609    NIR_PASS_V(nir, nir_lower_var_copies);
 610
 611    NIR_PASS_V(nir, nir_opt_copy_prop_vars);
 612    NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all);
 613
 614    /* ir3 doesn't support indirect input/output */
 615    /* TODO: We shouldn't perform this lowering pass on gl_TessLevelInner
 616     * and gl_TessLevelOuter. Since the tess levels are actually stored in
 617     * a global BO, they can be directly accessed via stg and ldg.
 618     * nir_lower_indirect_derefs will instead generate a big if-ladder which
 619     * isn't *incorrect* but is much less efficient. */
 620    NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
 621
 622    NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 623
 624    nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs, stage);
 625    nir_assign_io_var_locations(&nir->outputs, &nir->num_outputs, stage);
 626
 627    NIR_PASS_V(nir, nir_lower_system_values);
 628    NIR_PASS_V(nir, nir_lower_frexp);
 629
 630    if (stage == MESA_SHADER_FRAGMENT)
 631       NIR_PASS_V(nir, nir_lower_input_attachments, true);
 632
 633    NIR_PASS_V(nir, tu_lower_io, shader, layout);
 634
 635    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 636
 637    ir3_finalize_nir(dev->compiler, nir);
 638
 639    shader->ir3_shader =
 640       ir3_shader_from_nir(dev->compiler, nir,
 641                           align(shader->push_consts.count, 4),
 642                           &so_info);
 643
 644    return shader;
 645 }
 646
 647 void
 648 tu_shader_destroy(struct tu_device *dev,
 649                   struct tu_shader *shader,
 650                   const VkAllocationCallbacks *alloc)
 651 {
 652    ir3_shader_destroy(shader->ir3_shader);
 653
 654    vk_free2(&dev->alloc, alloc, shader);
 655 }
 656
 657 VkResult
 658 tu_CreateShaderModule(VkDevice _device,
 659                       const VkShaderModuleCreateInfo *pCreateInfo,
 660                       const VkAllocationCallbacks *pAllocator,
 661                       VkShaderModule *pShaderModule)
 662 {
 663    TU_FROM_HANDLE(tu_device, device, _device);
 664    struct tu_shader_module *module;
 665
 666    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
 667    assert(pCreateInfo->flags == 0);
 668    assert(pCreateInfo->codeSize % 4 == 0);
 669
 670    module = vk_alloc2(&device->alloc, pAllocator,
 671                       sizeof(*module) + pCreateInfo->codeSize, 8,
 672                       VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 673    if (module == NULL)
 674       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 675
 676    module->code_size = pCreateInfo->codeSize;
 677    memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
 678
 679    _mesa_sha1_compute(module->code, module->code_size, module->sha1);
 680
 681    *pShaderModule = tu_shader_module_to_handle(module);
 682
 683    return VK_SUCCESS;
 684 }
 685
 686 void
 687 tu_DestroyShaderModule(VkDevice _device,
 688                        VkShaderModule _module,
 689                        const VkAllocationCallbacks *pAllocator)
 690 {
 691    TU_FROM_HANDLE(tu_device, device, _device);
 692    TU_FROM_HANDLE(tu_shader_module, module, _module);
 693
 694    if (!module)
 695       return;
 696
 697    vk_free2(&device->alloc, pAllocator, module);
 698 }