turnip: fix binning shader compilation
[mesa.git] / src / freedreno / vulkan / tu_shader.c
1 /*
2 * Copyright © 2019 Google LLC
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "tu_private.h"
25
26 #include "spirv/nir_spirv.h"
27 #include "util/mesa-sha1.h"
28
29 #include "ir3/ir3_nir.h"
30
31 static nir_shader *
32 tu_spirv_to_nir(struct ir3_compiler *compiler,
33 const uint32_t *words,
34 size_t word_count,
35 gl_shader_stage stage,
36 const char *entry_point_name,
37 const VkSpecializationInfo *spec_info)
38 {
39 /* TODO these are made-up */
40 const struct spirv_to_nir_options spirv_options = {
41 .lower_ubo_ssbo_access_to_offsets = true,
42 .caps = { false },
43 };
44 const nir_shader_compiler_options *nir_options =
45 ir3_get_compiler_options(compiler);
46
47 /* convert VkSpecializationInfo */
48 struct nir_spirv_specialization *spec = NULL;
49 uint32_t num_spec = 0;
50 if (spec_info && spec_info->mapEntryCount) {
51 spec = malloc(sizeof(*spec) * spec_info->mapEntryCount);
52 if (!spec)
53 return NULL;
54
55 for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
56 const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
57 const void *data = spec_info->pData + entry->offset;
58 assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
59 spec[i].id = entry->constantID;
60 if (entry->size == 8)
61 spec[i].data64 = *(const uint64_t *) data;
62 else
63 spec[i].data32 = *(const uint32_t *) data;
64 spec[i].defined_on_module = false;
65 }
66
67 num_spec = spec_info->mapEntryCount;
68 }
69
70 nir_shader *nir =
71 spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
72 &spirv_options, nir_options);
73
74 free(spec);
75
76 assert(nir->info.stage == stage);
77 nir_validate_shader(nir, "after spirv_to_nir");
78
79 return nir;
80 }
81
82 static void
83 tu_sort_variables_by_location(struct exec_list *variables)
84 {
85 struct exec_list sorted;
86 exec_list_make_empty(&sorted);
87
88 nir_foreach_variable_safe(var, variables)
89 {
90 exec_node_remove(&var->node);
91
92 /* insert the variable into the sorted list */
93 nir_variable *next = NULL;
94 nir_foreach_variable(tmp, &sorted)
95 {
96 if (var->data.location < tmp->data.location) {
97 next = tmp;
98 break;
99 }
100 }
101 if (next)
102 exec_node_insert_node_before(&next->node, &var->node);
103 else
104 exec_list_push_tail(&sorted, &var->node);
105 }
106
107 exec_list_move_nodes_to(&sorted, variables);
108 }
109
110 struct tu_shader *
111 tu_shader_create(struct tu_device *dev,
112 gl_shader_stage stage,
113 const VkPipelineShaderStageCreateInfo *stage_info,
114 const VkAllocationCallbacks *alloc)
115 {
116 const struct tu_shader_module *module =
117 tu_shader_module_from_handle(stage_info->module);
118 struct tu_shader *shader;
119
120 const uint32_t max_variant_count = (stage == MESA_SHADER_VERTEX) ? 2 : 1;
121 shader = vk_zalloc2(
122 &dev->alloc, alloc,
123 sizeof(*shader) + sizeof(struct ir3_shader_variant) * max_variant_count,
124 8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
125 if (!shader)
126 return NULL;
127
128 /* translate SPIR-V to NIR */
129 assert(module->code_size % 4 == 0);
130 nir_shader *nir = tu_spirv_to_nir(
131 dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
132 stage, stage_info->pName, stage_info->pSpecializationInfo);
133 if (!nir) {
134 vk_free2(&dev->alloc, alloc, shader);
135 return NULL;
136 }
137
138 if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
139 fprintf(stderr, "translated nir:\n");
140 nir_print_shader(nir, stderr);
141 }
142
143 /* TODO what needs to happen? */
144
145 switch (stage) {
146 case MESA_SHADER_VERTEX:
147 tu_sort_variables_by_location(&nir->outputs);
148 break;
149 case MESA_SHADER_TESS_CTRL:
150 case MESA_SHADER_TESS_EVAL:
151 case MESA_SHADER_GEOMETRY:
152 tu_sort_variables_by_location(&nir->inputs);
153 tu_sort_variables_by_location(&nir->outputs);
154 break;
155 case MESA_SHADER_FRAGMENT:
156 tu_sort_variables_by_location(&nir->inputs);
157 break;
158 case MESA_SHADER_COMPUTE:
159 break;
160 default:
161 unreachable("invalid gl_shader_stage");
162 break;
163 }
164
165 nir_assign_var_locations(&nir->inputs, &nir->num_inputs,
166 ir3_glsl_type_size);
167 nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
168 ir3_glsl_type_size);
169 nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
170 ir3_glsl_type_size);
171
172 NIR_PASS_V(nir, nir_lower_system_values);
173 NIR_PASS_V(nir, nir_lower_frexp);
174 NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size, 0);
175
176 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
177
178 shader->ir3_shader.compiler = dev->compiler;
179 shader->ir3_shader.type = stage;
180 shader->ir3_shader.nir = nir;
181
182 return shader;
183 }
184
185 void
186 tu_shader_destroy(struct tu_device *dev,
187 struct tu_shader *shader,
188 const VkAllocationCallbacks *alloc)
189 {
190 if (shader->ir3_shader.nir)
191 ralloc_free(shader->ir3_shader.nir);
192
193 for (uint32_t i = 0; i < 1 + shader->has_binning_pass; i++) {
194 if (shader->variants[i].ir)
195 ir3_destroy(shader->variants[i].ir);
196 }
197
198 if (shader->ir3_shader.const_state.immediates)
199 free(shader->ir3_shader.const_state.immediates);
200 if (shader->binary)
201 free(shader->binary);
202 if (shader->binning_binary)
203 free(shader->binning_binary);
204
205 vk_free2(&dev->alloc, alloc, shader);
206 }
207
208 void
209 tu_shader_compile_options_init(
210 struct tu_shader_compile_options *options,
211 const VkGraphicsPipelineCreateInfo *pipeline_info)
212 {
213 *options = (struct tu_shader_compile_options) {
214 /* TODO ir3_key */
215
216 .optimize = !(pipeline_info->flags &
217 VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT),
218 .include_binning_pass = true,
219 };
220 }
221
222 static uint32_t *
223 tu_compile_shader_variant(struct ir3_shader *shader,
224 const struct ir3_shader_key *key,
225 struct ir3_shader_variant *nonbinning,
226 struct ir3_shader_variant *variant)
227 {
228 variant->shader = shader;
229 variant->type = shader->type;
230 variant->key = *key;
231 variant->binning_pass = !!nonbinning;
232 variant->nonbinning = nonbinning;
233
234 int ret = ir3_compile_shader_nir(shader->compiler, variant);
235 if (ret)
236 return NULL;
237
238 /* when assemble fails, we rely on tu_shader_destroy to clean up the
239 * variant
240 */
241 return ir3_shader_assemble(variant, shader->compiler->gpu_id);
242 }
243
244 VkResult
245 tu_shader_compile(struct tu_device *dev,
246 struct tu_shader *shader,
247 const struct tu_shader *next_stage,
248 const struct tu_shader_compile_options *options,
249 const VkAllocationCallbacks *alloc)
250 {
251 if (options->optimize) {
252 /* ignore the key for the first pass of optimization */
253 ir3_optimize_nir(&shader->ir3_shader, shader->ir3_shader.nir, NULL);
254
255 if (unlikely(dev->physical_device->instance->debug_flags &
256 TU_DEBUG_NIR)) {
257 fprintf(stderr, "optimized nir:\n");
258 nir_print_shader(shader->ir3_shader.nir, stderr);
259 }
260 }
261
262 shader->binary = tu_compile_shader_variant(
263 &shader->ir3_shader, &options->key, NULL, &shader->variants[0]);
264 if (!shader->binary)
265 return VK_ERROR_OUT_OF_HOST_MEMORY;
266
267 /* compile another variant for the binning pass */
268 if (options->include_binning_pass &&
269 shader->ir3_shader.type == MESA_SHADER_VERTEX) {
270 shader->binning_binary = tu_compile_shader_variant(
271 &shader->ir3_shader, &options->key, &shader->variants[0],
272 &shader->variants[1]);
273 if (!shader->binning_binary)
274 return VK_ERROR_OUT_OF_HOST_MEMORY;
275
276 shader->has_binning_pass = true;
277 }
278
279 if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_IR3)) {
280 fprintf(stderr, "disassembled ir3:\n");
281 fprintf(stderr, "shader: %s\n",
282 gl_shader_stage_name(shader->ir3_shader.type));
283 ir3_shader_disasm(&shader->variants[0], shader->binary, stderr);
284
285 if (shader->has_binning_pass) {
286 fprintf(stderr, "disassembled ir3:\n");
287 fprintf(stderr, "shader: %s (binning)\n",
288 gl_shader_stage_name(shader->ir3_shader.type));
289 ir3_shader_disasm(&shader->variants[1], shader->binning_binary,
290 stderr);
291 }
292 }
293
294 return VK_SUCCESS;
295 }
296
297 VkResult
298 tu_CreateShaderModule(VkDevice _device,
299 const VkShaderModuleCreateInfo *pCreateInfo,
300 const VkAllocationCallbacks *pAllocator,
301 VkShaderModule *pShaderModule)
302 {
303 TU_FROM_HANDLE(tu_device, device, _device);
304 struct tu_shader_module *module;
305
306 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
307 assert(pCreateInfo->flags == 0);
308 assert(pCreateInfo->codeSize % 4 == 0);
309
310 module = vk_alloc2(&device->alloc, pAllocator,
311 sizeof(*module) + pCreateInfo->codeSize, 8,
312 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
313 if (module == NULL)
314 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
315
316 module->code_size = pCreateInfo->codeSize;
317 memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
318
319 _mesa_sha1_compute(module->code, module->code_size, module->sha1);
320
321 *pShaderModule = tu_shader_module_to_handle(module);
322
323 return VK_SUCCESS;
324 }
325
326 void
327 tu_DestroyShaderModule(VkDevice _device,
328 VkShaderModule _module,
329 const VkAllocationCallbacks *pAllocator)
330 {
331 TU_FROM_HANDLE(tu_device, device, _device);
332 TU_FROM_HANDLE(tu_shader_module, module, _module);
333
334 if (!module)
335 return;
336
337 vk_free2(&device->alloc, pAllocator, module);
338 }