src/freedreno/vulkan/tu_shader.c

   1 /*
   2  * Copyright © 2019 Google LLC
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "tu_private.h"
  25
  26 #include "spirv/nir_spirv.h"
  27 #include "util/mesa-sha1.h"
  28 #include "nir/nir_xfb_info.h"
  29 #include "nir/nir_vulkan.h"
  30 #include "vk_util.h"
  31
  32 #include "ir3/ir3_nir.h"
  33
  34 static nir_shader *
  35 tu_spirv_to_nir(struct ir3_compiler *compiler,
  36                 const uint32_t *words,
  37                 size_t word_count,
  38                 gl_shader_stage stage,
  39                 const char *entry_point_name,
  40                 const VkSpecializationInfo *spec_info)
  41 {
  42    /* TODO these are made-up */
  43    const struct spirv_to_nir_options spirv_options = {
  44       .frag_coord_is_sysval = true,
  45       .lower_ubo_ssbo_access_to_offsets = true,
  46       .caps = {
  47          .transform_feedback = compiler->gpu_id >= 600,
  48       },
  49    };
  50    const nir_shader_compiler_options *nir_options =
  51       ir3_get_compiler_options(compiler);
  52
  53    /* convert VkSpecializationInfo */
  54    struct nir_spirv_specialization *spec = NULL;
  55    uint32_t num_spec = 0;
  56    if (spec_info && spec_info->mapEntryCount) {
  57       spec = calloc(spec_info->mapEntryCount, sizeof(*spec));
  58       if (!spec)
  59          return NULL;
  60
  61       for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
  62          const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
  63          const void *data = spec_info->pData + entry->offset;
  64          assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
  65          spec[i].id = entry->constantID;
  66          switch (entry->size) {
  67          case 8:
  68             spec[i].value.u64 = *(const uint64_t *)data;
  69             break;
  70          case 4:
  71             spec[i].value.u32 = *(const uint32_t *)data;
  72             break;
  73          case 2:
  74             spec[i].value.u16 = *(const uint16_t *)data;
  75             break;
  76          case 1:
  77             spec[i].value.u8 = *(const uint8_t *)data;
  78             break;
  79          default:
  80             assert(!"Invalid spec constant size");
  81             break;
  82          }
  83          spec[i].defined_on_module = false;
  84       }
  85
  86       num_spec = spec_info->mapEntryCount;
  87    }
  88
  89    nir_shader *nir =
  90       spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
  91                    &spirv_options, nir_options);
  92
  93    free(spec);
  94
  95    assert(nir->info.stage == stage);
  96    nir_validate_shader(nir, "after spirv_to_nir");
  97
  98    return nir;
  99 }
 100
 101 static void
 102 lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr,
 103                          struct tu_shader *shader)
 104 {
 105    nir_intrinsic_instr *load =
 106       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
 107    load->num_components = instr->num_components;
 108    uint32_t base = nir_intrinsic_base(instr);
 109    assert(base % 4 == 0);
 110    assert(base >= shader->push_consts.lo * 16);
 111    base -= shader->push_consts.lo * 16;
 112    nir_intrinsic_set_base(load, base / 4);
 113    load->src[0] =
 114       nir_src_for_ssa(nir_ushr(b, instr->src[0].ssa, nir_imm_int(b, 2)));
 115    nir_ssa_dest_init(&load->instr, &load->dest,
 116                      load->num_components, instr->dest.ssa.bit_size,
 117                      instr->dest.ssa.name);
 118    nir_builder_instr_insert(b, &load->instr);
 119    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(&load->dest.ssa));
 120
 121    nir_instr_remove(&instr->instr);
 122 }
 123
 124 static void
 125 lower_vulkan_resource_index(nir_builder *b, nir_intrinsic_instr *instr,
 126                             struct tu_shader *shader,
 127                             const struct tu_pipeline_layout *layout)
 128 {
 129    nir_ssa_def *vulkan_idx = instr->src[0].ssa;
 130
 131    unsigned set = nir_intrinsic_desc_set(instr);
 132    unsigned binding = nir_intrinsic_binding(instr);
 133    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 134    struct tu_descriptor_set_binding_layout *binding_layout =
 135       &set_layout->binding[binding];
 136    uint32_t base;
 137
 138    shader->active_desc_sets |= 1u << set;
 139
 140    switch (binding_layout->type) {
 141    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 142    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 143       base = layout->set[set].dynamic_offset_start +
 144          binding_layout->dynamic_offset_offset +
 145          layout->input_attachment_count;
 146       set = MAX_SETS;
 147       break;
 148    default:
 149       base = binding_layout->offset / (4 * A6XX_TEX_CONST_DWORDS);
 150       break;
 151    }
 152
 153    nir_intrinsic_instr *bindless =
 154       nir_intrinsic_instr_create(b->shader,
 155                                  nir_intrinsic_bindless_resource_ir3);
 156    bindless->num_components = 1;
 157    nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 158                      1, 32, NULL);
 159    nir_intrinsic_set_desc_set(bindless, set);
 160    bindless->src[0] = nir_src_for_ssa(nir_iadd(b, nir_imm_int(b, base), vulkan_idx));
 161    nir_builder_instr_insert(b, &bindless->instr);
 162
 163    nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 164                             nir_src_for_ssa(&bindless->dest.ssa));
 165    nir_instr_remove(&instr->instr);
 166 }
 167
 168 static nir_ssa_def *
 169 build_bindless(nir_builder *b, nir_deref_instr *deref, bool is_sampler,
 170                struct tu_shader *shader,
 171                const struct tu_pipeline_layout *layout)
 172 {
 173    nir_variable *var = nir_deref_instr_get_variable(deref);
 174
 175    unsigned set = var->data.descriptor_set;
 176    unsigned binding = var->data.binding;
 177    const struct tu_descriptor_set_binding_layout *bind_layout =
 178       &layout->set[set].layout->binding[binding];
 179
 180    shader->active_desc_sets |= 1u << set;
 181
 182    nir_ssa_def *desc_offset;
 183    unsigned descriptor_stride;
 184    if (bind_layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
 185       unsigned offset =
 186          layout->set[set].input_attachment_start +
 187          bind_layout->input_attachment_offset;
 188       desc_offset = nir_imm_int(b, offset);
 189       set = MAX_SETS;
 190       descriptor_stride = 1;
 191    } else {
 192       unsigned offset = 0;
 193       /* Samplers come second in combined image/sampler descriptors, see
 194        * write_combined_image_sampler_descriptor().
 195        */
 196       if (is_sampler && bind_layout->type ==
 197           VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
 198          offset = 1;
 199       }
 200       desc_offset =
 201          nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) +
 202                      offset);
 203       descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS);
 204    }
 205
 206    if (deref->deref_type != nir_deref_type_var) {
 207       assert(deref->deref_type == nir_deref_type_array);
 208
 209       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 210       desc_offset = nir_iadd(b, desc_offset,
 211                              nir_imul_imm(b, arr_index, descriptor_stride));
 212    }
 213
 214    nir_intrinsic_instr *bindless =
 215       nir_intrinsic_instr_create(b->shader,
 216                                  nir_intrinsic_bindless_resource_ir3);
 217    bindless->num_components = 1;
 218    nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 219                      1, 32, NULL);
 220    nir_intrinsic_set_desc_set(bindless, set);
 221    bindless->src[0] = nir_src_for_ssa(desc_offset);
 222    nir_builder_instr_insert(b, &bindless->instr);
 223
 224    return &bindless->dest.ssa;
 225 }
 226
 227 static void
 228 lower_image_deref(nir_builder *b,
 229                   nir_intrinsic_instr *instr, struct tu_shader *shader,
 230                   const struct tu_pipeline_layout *layout)
 231 {
 232    nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
 233    nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 234    nir_rewrite_image_intrinsic(instr, bindless, true);
 235 }
 236
 237 static bool
 238 lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
 239                 struct tu_shader *shader,
 240                 const struct tu_pipeline_layout *layout)
 241 {
 242    switch (instr->intrinsic) {
 243    case nir_intrinsic_load_layer_id:
 244       /* TODO: remove this when layered rendering is implemented */
 245       nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 246                                nir_src_for_ssa(nir_imm_int(b, 0)));
 247       nir_instr_remove(&instr->instr);
 248       return true;
 249
 250    case nir_intrinsic_load_push_constant:
 251       lower_load_push_constant(b, instr, shader);
 252       return true;
 253
 254    case nir_intrinsic_vulkan_resource_index:
 255       lower_vulkan_resource_index(b, instr, shader, layout);
 256       return true;
 257
 258    case nir_intrinsic_image_deref_load:
 259    case nir_intrinsic_image_deref_store:
 260    case nir_intrinsic_image_deref_atomic_add:
 261    case nir_intrinsic_image_deref_atomic_imin:
 262    case nir_intrinsic_image_deref_atomic_umin:
 263    case nir_intrinsic_image_deref_atomic_imax:
 264    case nir_intrinsic_image_deref_atomic_umax:
 265    case nir_intrinsic_image_deref_atomic_and:
 266    case nir_intrinsic_image_deref_atomic_or:
 267    case nir_intrinsic_image_deref_atomic_xor:
 268    case nir_intrinsic_image_deref_atomic_exchange:
 269    case nir_intrinsic_image_deref_atomic_comp_swap:
 270    case nir_intrinsic_image_deref_size:
 271    case nir_intrinsic_image_deref_samples:
 272       lower_image_deref(b, instr, shader, layout);
 273       return true;
 274
 275    default:
 276       return false;
 277    }
 278 }
 279
 280 static void
 281 lower_tex_ycbcr(const struct tu_pipeline_layout *layout,
 282                 nir_builder *builder,
 283                 nir_tex_instr *tex)
 284 {
 285    int deref_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 286    assert(deref_src_idx >= 0);
 287    nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);
 288
 289    nir_variable *var = nir_deref_instr_get_variable(deref);
 290    const struct tu_descriptor_set_layout *set_layout =
 291       layout->set[var->data.descriptor_set].layout;
 292    const struct tu_descriptor_set_binding_layout *binding =
 293       &set_layout->binding[var->data.binding];
 294    const struct tu_sampler_ycbcr_conversion *ycbcr_samplers =
 295       tu_immutable_ycbcr_samplers(set_layout, binding);
 296
 297    if (!ycbcr_samplers)
 298       return;
 299
 300    /* For the following instructions, we don't apply any change */
 301    if (tex->op == nir_texop_txs ||
 302        tex->op == nir_texop_query_levels ||
 303        tex->op == nir_texop_lod)
 304       return;
 305
 306    assert(tex->texture_index == 0);
 307    unsigned array_index = 0;
 308    if (deref->deref_type != nir_deref_type_var) {
 309       assert(deref->deref_type == nir_deref_type_array);
 310       if (!nir_src_is_const(deref->arr.index))
 311          return;
 312       array_index = nir_src_as_uint(deref->arr.index);
 313       array_index = MIN2(array_index, binding->array_size - 1);
 314    }
 315    const struct tu_sampler_ycbcr_conversion *ycbcr_sampler = ycbcr_samplers + array_index;
 316
 317    if (ycbcr_sampler->ycbcr_model == VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY)
 318       return;
 319
 320    builder->cursor = nir_after_instr(&tex->instr);
 321
 322    uint8_t bits = vk_format_get_component_bits(ycbcr_sampler->format,
 323                                                UTIL_FORMAT_COLORSPACE_RGB,
 324                                                PIPE_SWIZZLE_X);
 325    uint32_t bpcs[3] = {bits, bits, bits}; /* TODO: use right bpc for each channel ? */
 326    nir_ssa_def *result = nir_convert_ycbcr_to_rgb(builder,
 327                                                   ycbcr_sampler->ycbcr_model,
 328                                                   ycbcr_sampler->ycbcr_range,
 329                                                   &tex->dest.ssa,
 330                                                   bpcs);
 331    nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, nir_src_for_ssa(result),
 332                                   result->parent_instr);
 333
 334    builder->cursor = nir_before_instr(&tex->instr);
 335 }
 336
 337 static bool
 338 lower_tex(nir_builder *b, nir_tex_instr *tex,
 339           struct tu_shader *shader, const struct tu_pipeline_layout *layout)
 340 {
 341    lower_tex_ycbcr(layout, b, tex);
 342
 343    int sampler_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_deref);
 344    if (sampler_src_idx >= 0) {
 345       nir_deref_instr *deref = nir_src_as_deref(tex->src[sampler_src_idx].src);
 346       nir_ssa_def *bindless = build_bindless(b, deref, true, shader, layout);
 347       nir_instr_rewrite_src(&tex->instr, &tex->src[sampler_src_idx].src,
 348                             nir_src_for_ssa(bindless));
 349       tex->src[sampler_src_idx].src_type = nir_tex_src_sampler_handle;
 350    }
 351
 352    int tex_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 353    if (tex_src_idx >= 0) {
 354       nir_deref_instr *deref = nir_src_as_deref(tex->src[tex_src_idx].src);
 355       nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 356       nir_instr_rewrite_src(&tex->instr, &tex->src[tex_src_idx].src,
 357                             nir_src_for_ssa(bindless));
 358       tex->src[tex_src_idx].src_type = nir_tex_src_texture_handle;
 359    }
 360
 361    return true;
 362 }
 363
 364 static bool
 365 lower_impl(nir_function_impl *impl, struct tu_shader *shader,
 366             const struct tu_pipeline_layout *layout)
 367 {
 368    nir_builder b;
 369    nir_builder_init(&b, impl);
 370    bool progress = false;
 371
 372    nir_foreach_block(block, impl) {
 373       nir_foreach_instr_safe(instr, block) {
 374          b.cursor = nir_before_instr(instr);
 375          switch (instr->type) {
 376          case nir_instr_type_tex:
 377             progress |= lower_tex(&b, nir_instr_as_tex(instr), shader, layout);
 378             break;
 379          case nir_instr_type_intrinsic:
 380             progress |= lower_intrinsic(&b, nir_instr_as_intrinsic(instr), shader, layout);
 381             break;
 382          default:
 383             break;
 384          }
 385       }
 386    }
 387
 388    return progress;
 389 }
 390
 391
 392 /* Figure out the range of push constants that we're actually going to push to
 393  * the shader, and tell the backend to reserve this range when pushing UBO
 394  * constants.
 395  */
 396
 397 static void
 398 gather_push_constants(nir_shader *shader, struct tu_shader *tu_shader)
 399 {
 400    uint32_t min = UINT32_MAX, max = 0;
 401    nir_foreach_function(function, shader) {
 402       if (!function->impl)
 403          continue;
 404
 405       nir_foreach_block(block, function->impl) {
 406          nir_foreach_instr_safe(instr, block) {
 407             if (instr->type != nir_instr_type_intrinsic)
 408                continue;
 409
 410             nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 411             if (intrin->intrinsic != nir_intrinsic_load_push_constant)
 412                continue;
 413
 414             uint32_t base = nir_intrinsic_base(intrin);
 415             uint32_t range = nir_intrinsic_range(intrin);
 416             min = MIN2(min, base);
 417             max = MAX2(max, base + range);
 418             break;
 419          }
 420       }
 421    }
 422
 423    if (min >= max) {
 424       tu_shader->push_consts.lo = 0;
 425       tu_shader->push_consts.count = 0;
 426       tu_shader->ir3_shader.const_state.num_reserved_user_consts = 0;
 427       return;
 428    }
 429
 430    /* CP_LOAD_STATE OFFSET and NUM_UNIT are in units of vec4 (4 dwords),
 431     * however there's an alignment requirement of 4 on OFFSET. Expand the
 432     * range and change units accordingly.
 433     */
 434    tu_shader->push_consts.lo = (min / 16) / 4 * 4;
 435    tu_shader->push_consts.count =
 436       align(max, 16) / 16 - tu_shader->push_consts.lo;
 437    tu_shader->ir3_shader.const_state.num_reserved_user_consts =
 438       align(tu_shader->push_consts.count, 4);
 439 }
 440
 441 /* Gather the InputAttachmentIndex for each input attachment from the NIR
 442  * shader and organize the info in a way so that draw-time patching is easy.
 443  */
 444 static void
 445 gather_input_attachments(nir_shader *shader, struct tu_shader *tu_shader,
 446                          const struct tu_pipeline_layout *layout)
 447 {
 448    nir_foreach_variable(var, &shader->uniforms) {
 449       const struct glsl_type *glsl_type = glsl_without_array(var->type);
 450
 451       if (!glsl_type_is_image(glsl_type))
 452          continue;
 453
 454       enum glsl_sampler_dim dim = glsl_get_sampler_dim(glsl_type);
 455
 456       const uint32_t set = var->data.descriptor_set;
 457       const uint32_t binding = var->data.binding;
 458       const struct tu_descriptor_set_binding_layout *bind_layout =
 459             &layout->set[set].layout->binding[binding];
 460       const uint32_t array_size = bind_layout->array_size;
 461
 462       if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
 463           dim == GLSL_SAMPLER_DIM_SUBPASS_MS) {
 464          unsigned offset =
 465             layout->set[set].input_attachment_start +
 466             bind_layout->input_attachment_offset;
 467          for (unsigned i = 0; i < array_size; i++)
 468             tu_shader->attachment_idx[offset + i] = var->data.index + i;
 469       }
 470    }
 471 }
 472
 473 static bool
 474 tu_lower_io(nir_shader *shader, struct tu_shader *tu_shader,
 475             const struct tu_pipeline_layout *layout)
 476 {
 477    bool progress = false;
 478
 479    gather_push_constants(shader, tu_shader);
 480    gather_input_attachments(shader, tu_shader, layout);
 481
 482    nir_foreach_function(function, shader) {
 483       if (function->impl)
 484          progress |= lower_impl(function->impl, tu_shader, layout);
 485    }
 486
 487    return progress;
 488 }
 489
 490 static void
 491 tu_gather_xfb_info(nir_shader *nir, struct tu_shader *shader)
 492 {
 493    struct ir3_stream_output_info *info = &shader->ir3_shader.stream_output;
 494    nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
 495
 496    if (!xfb)
 497       return;
 498
 499    /* creating a map from VARYING_SLOT_* enums to consecutive index */
 500    uint8_t num_outputs = 0;
 501    uint64_t outputs_written = 0;
 502    for (int i = 0; i < xfb->output_count; i++)
 503       outputs_written |= BITFIELD64_BIT(xfb->outputs[i].location);
 504
 505    uint8_t output_map[VARYING_SLOT_TESS_MAX];
 506    memset(output_map, 0, sizeof(output_map));
 507
 508    for (unsigned attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 509       if (outputs_written & BITFIELD64_BIT(attr))
 510          output_map[attr] = num_outputs++;
 511    }
 512
 513    assert(xfb->output_count < IR3_MAX_SO_OUTPUTS);
 514    info->num_outputs = xfb->output_count;
 515
 516    for (int i = 0; i < IR3_MAX_SO_BUFFERS; i++)
 517       info->stride[i] = xfb->buffers[i].stride / 4;
 518
 519    for (int i = 0; i < xfb->output_count; i++) {
 520       info->output[i].register_index = output_map[xfb->outputs[i].location];
 521       info->output[i].start_component = xfb->outputs[i].component_offset;
 522       info->output[i].num_components =
 523                            util_bitcount(xfb->outputs[i].component_mask);
 524       info->output[i].output_buffer  = xfb->outputs[i].buffer;
 525       info->output[i].dst_offset = xfb->outputs[i].offset / 4;
 526       info->output[i].stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
 527    }
 528
 529    ralloc_free(xfb);
 530 }
 531
 532 struct tu_shader *
 533 tu_shader_create(struct tu_device *dev,
 534                  gl_shader_stage stage,
 535                  const VkPipelineShaderStageCreateInfo *stage_info,
 536                  struct tu_pipeline_layout *layout,
 537                  const VkAllocationCallbacks *alloc)
 538 {
 539    struct tu_shader *shader;
 540
 541    const uint32_t max_variant_count = (stage == MESA_SHADER_VERTEX) ? 2 : 1;
 542    shader = vk_zalloc2(
 543       &dev->alloc, alloc,
 544       sizeof(*shader) + sizeof(struct ir3_shader_variant) * max_variant_count,
 545       8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
 546    if (!shader)
 547       return NULL;
 548
 549    nir_shader *nir;
 550    if (stage_info) {
 551       /* translate SPIR-V to NIR */
 552       const struct tu_shader_module *module =
 553          tu_shader_module_from_handle(stage_info->module);
 554       assert(module->code_size % 4 == 0);
 555       nir = tu_spirv_to_nir(
 556          dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
 557          stage, stage_info->pName, stage_info->pSpecializationInfo);
 558    } else {
 559       assert(stage == MESA_SHADER_FRAGMENT);
 560       nir_builder fs_b;
 561       const nir_shader_compiler_options *nir_options =
 562          ir3_get_compiler_options(dev->compiler);
 563       nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, nir_options);
 564       fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
 565       nir = fs_b.shader;
 566    }
 567
 568    if (!nir) {
 569       vk_free2(&dev->alloc, alloc, shader);
 570       return NULL;
 571    }
 572
 573    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
 574       fprintf(stderr, "translated nir:\n");
 575       nir_print_shader(nir, stderr);
 576    }
 577
 578    /* multi step inlining procedure */
 579    NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
 580    NIR_PASS_V(nir, nir_lower_returns);
 581    NIR_PASS_V(nir, nir_inline_functions);
 582    NIR_PASS_V(nir, nir_opt_deref);
 583    foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 584       if (!func->is_entrypoint)
 585          exec_node_remove(&func->node);
 586    }
 587    assert(exec_list_length(&nir->functions) == 1);
 588    NIR_PASS_V(nir, nir_lower_variable_initializers, ~nir_var_function_temp);
 589
 590    /* Split member structs.  We do this before lower_io_to_temporaries so that
 591     * it doesn't lower system values to temporaries by accident.
 592     */
 593    NIR_PASS_V(nir, nir_split_var_copies);
 594    NIR_PASS_V(nir, nir_split_per_member_structs);
 595
 596    NIR_PASS_V(nir, nir_remove_dead_variables,
 597               nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
 598               NULL);
 599
 600    /* Gather information for transform feedback.
 601     * This should be called after nir_split_per_member_structs.
 602     * Also needs to be called after nir_remove_dead_variables with varyings,
 603     * so that we could align stream outputs correctly.
 604     */
 605    if (nir->info.stage == MESA_SHADER_VERTEX ||
 606          nir->info.stage == MESA_SHADER_TESS_EVAL ||
 607          nir->info.stage == MESA_SHADER_GEOMETRY)
 608       tu_gather_xfb_info(nir, shader);
 609
 610    NIR_PASS_V(nir, nir_propagate_invariant);
 611
 612    NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true);
 613
 614    NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 615    NIR_PASS_V(nir, nir_split_var_copies);
 616    NIR_PASS_V(nir, nir_lower_var_copies);
 617
 618    NIR_PASS_V(nir, nir_opt_copy_prop_vars);
 619    NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all);
 620
 621    /* ir3 doesn't support indirect input/output */
 622    NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
 623
 624    NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 625
 626    nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs, stage);
 627    nir_assign_io_var_locations(&nir->outputs, &nir->num_outputs, stage);
 628
 629    NIR_PASS_V(nir, nir_lower_system_values);
 630    NIR_PASS_V(nir, nir_lower_frexp);
 631
 632    if (stage == MESA_SHADER_FRAGMENT)
 633       NIR_PASS_V(nir, nir_lower_input_attachments, true);
 634
 635    if (stage == MESA_SHADER_GEOMETRY)
 636       NIR_PASS_V(nir, ir3_nir_lower_gs);
 637
 638    NIR_PASS_V(nir, tu_lower_io, shader, layout);
 639
 640    NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size, 0);
 641
 642    if (stage == MESA_SHADER_FRAGMENT) {
 643       /* NOTE: lower load_barycentric_at_sample first, since it
 644        * produces load_barycentric_at_offset:
 645        */
 646       NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
 647       NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
 648
 649       NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
 650    }
 651
 652    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 653
 654    /* num_uniforms only used by ir3 for size of ubo 0 (push constants) */
 655    nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE / 16;
 656
 657    shader->ir3_shader.compiler = dev->compiler;
 658    shader->ir3_shader.type = stage;
 659    shader->ir3_shader.nir = nir;
 660
 661    return shader;
 662 }
 663
 664 void
 665 tu_shader_destroy(struct tu_device *dev,
 666                   struct tu_shader *shader,
 667                   const VkAllocationCallbacks *alloc)
 668 {
 669    if (shader->ir3_shader.nir)
 670       ralloc_free(shader->ir3_shader.nir);
 671
 672    for (uint32_t i = 0; i < 1 + shader->has_binning_pass; i++) {
 673       if (shader->variants[i].ir)
 674          ir3_destroy(shader->variants[i].ir);
 675    }
 676
 677    if (shader->ir3_shader.const_state.immediates)
 678            free(shader->ir3_shader.const_state.immediates);
 679    if (shader->binary)
 680       free(shader->binary);
 681    if (shader->binning_binary)
 682       free(shader->binning_binary);
 683
 684    vk_free2(&dev->alloc, alloc, shader);
 685 }
 686
 687 void
 688 tu_shader_compile_options_init(
 689    struct tu_shader_compile_options *options,
 690    const VkGraphicsPipelineCreateInfo *pipeline_info)
 691 {
 692    bool has_gs = false;
 693    bool msaa = false;
 694    if (pipeline_info) {
 695       for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
 696          if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
 697             has_gs = true;
 698             break;
 699          }
 700       }
 701
 702       const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
 703       const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
 704          vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
 705       if (!pipeline_info->pRasterizationState->rasterizerDiscardEnable &&
 706           (msaa_info->rasterizationSamples > 1 ||
 707           /* also set msaa key when sample location is not the default
 708            * since this affects varying interpolation */
 709            (sample_locations && sample_locations->sampleLocationsEnable))) {
 710          msaa = true;
 711       }
 712    }
 713
 714    *options = (struct tu_shader_compile_options) {
 715       /* TODO: Populate the remaining fields of ir3_shader_key. */
 716       .key = {
 717          .has_gs = has_gs,
 718          .msaa = msaa,
 719       },
 720       /* TODO: VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
 721        * some optimizations need to happen otherwise shader might not compile
 722        */
 723       .optimize = true,
 724       .include_binning_pass = true,
 725    };
 726 }
 727
 728 static uint32_t *
 729 tu_compile_shader_variant(struct ir3_shader *shader,
 730                           const struct ir3_shader_key *key,
 731                           struct ir3_shader_variant *nonbinning,
 732                           struct ir3_shader_variant *variant)
 733 {
 734    variant->shader = shader;
 735    variant->type = shader->type;
 736    variant->key = *key;
 737    variant->binning_pass = !!nonbinning;
 738    variant->nonbinning = nonbinning;
 739
 740    int ret = ir3_compile_shader_nir(shader->compiler, variant);
 741    if (ret)
 742       return NULL;
 743
 744    /* when assemble fails, we rely on tu_shader_destroy to clean up the
 745     * variant
 746     */
 747    return ir3_shader_assemble(variant, shader->compiler->gpu_id);
 748 }
 749
 750 VkResult
 751 tu_shader_compile(struct tu_device *dev,
 752                   struct tu_shader *shader,
 753                   const struct tu_shader *next_stage,
 754                   const struct tu_shader_compile_options *options,
 755                   const VkAllocationCallbacks *alloc)
 756 {
 757    if (options->optimize) {
 758       /* ignore the key for the first pass of optimization */
 759       ir3_optimize_nir(&shader->ir3_shader, shader->ir3_shader.nir, NULL);
 760
 761       if (unlikely(dev->physical_device->instance->debug_flags &
 762                    TU_DEBUG_NIR)) {
 763          fprintf(stderr, "optimized nir:\n");
 764          nir_print_shader(shader->ir3_shader.nir, stderr);
 765       }
 766    }
 767
 768    shader->binary = tu_compile_shader_variant(
 769       &shader->ir3_shader, &options->key, NULL, &shader->variants[0]);
 770    if (!shader->binary)
 771       return VK_ERROR_OUT_OF_HOST_MEMORY;
 772
 773    if (shader_debug_enabled(shader->ir3_shader.type)) {
 774       fprintf(stdout, "Native code for unnamed %s shader %s:\n",
 775               ir3_shader_stage(&shader->variants[0]), shader->ir3_shader.nir->info.name);
 776        if (shader->ir3_shader.type == MESA_SHADER_FRAGMENT)
 777                fprintf(stdout, "SIMD0\n");
 778        ir3_shader_disasm(&shader->variants[0], shader->binary, stdout);
 779    }
 780
 781    /* compile another variant for the binning pass */
 782    if (options->include_binning_pass &&
 783        shader->ir3_shader.type == MESA_SHADER_VERTEX) {
 784       shader->binning_binary = tu_compile_shader_variant(
 785          &shader->ir3_shader, &options->key, &shader->variants[0],
 786          &shader->variants[1]);
 787       if (!shader->binning_binary)
 788          return VK_ERROR_OUT_OF_HOST_MEMORY;
 789
 790       shader->has_binning_pass = true;
 791
 792       if (shader_debug_enabled(MESA_SHADER_VERTEX)) {
 793          fprintf(stdout, "Native code for unnamed binning shader %s:\n",
 794                  shader->ir3_shader.nir->info.name);
 795           ir3_shader_disasm(&shader->variants[1], shader->binary, stdout);
 796       }
 797    }
 798
 799    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_IR3)) {
 800       fprintf(stderr, "disassembled ir3:\n");
 801       fprintf(stderr, "shader: %s\n",
 802               gl_shader_stage_name(shader->ir3_shader.type));
 803       ir3_shader_disasm(&shader->variants[0], shader->binary, stderr);
 804
 805       if (shader->has_binning_pass) {
 806          fprintf(stderr, "disassembled ir3:\n");
 807          fprintf(stderr, "shader: %s (binning)\n",
 808                  gl_shader_stage_name(shader->ir3_shader.type));
 809          ir3_shader_disasm(&shader->variants[1], shader->binning_binary,
 810                            stderr);
 811       }
 812    }
 813
 814    return VK_SUCCESS;
 815 }
 816
 817 VkResult
 818 tu_CreateShaderModule(VkDevice _device,
 819                       const VkShaderModuleCreateInfo *pCreateInfo,
 820                       const VkAllocationCallbacks *pAllocator,
 821                       VkShaderModule *pShaderModule)
 822 {
 823    TU_FROM_HANDLE(tu_device, device, _device);
 824    struct tu_shader_module *module;
 825
 826    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
 827    assert(pCreateInfo->flags == 0);
 828    assert(pCreateInfo->codeSize % 4 == 0);
 829
 830    module = vk_alloc2(&device->alloc, pAllocator,
 831                       sizeof(*module) + pCreateInfo->codeSize, 8,
 832                       VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 833    if (module == NULL)
 834       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 835
 836    module->code_size = pCreateInfo->codeSize;
 837    memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
 838
 839    _mesa_sha1_compute(module->code, module->code_size, module->sha1);
 840
 841    *pShaderModule = tu_shader_module_to_handle(module);
 842
 843    return VK_SUCCESS;
 844 }
 845
 846 void
 847 tu_DestroyShaderModule(VkDevice _device,
 848                        VkShaderModule _module,
 849                        const VkAllocationCallbacks *pAllocator)
 850 {
 851    TU_FROM_HANDLE(tu_device, device, _device);
 852    TU_FROM_HANDLE(tu_shader_module, module, _module);
 853
 854    if (!module)
 855       return;
 856
 857    vk_free2(&device->alloc, pAllocator, module);
 858 }