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tgsi_to_nir: Remove dependency on libglsl.
[mesa.git] / src / gallium / auxiliary / nir / tgsi_to_nir.c
1 /*
2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/ralloc.h"
26 #include "pipe/p_screen.h"
27
28 #include "compiler/nir/nir.h"
29 #include "compiler/nir/nir_control_flow.h"
30 #include "compiler/nir/nir_builder.h"
31 #include "compiler/shader_enums.h"
32
33 #include "tgsi_to_nir.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "tgsi/tgsi_info.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_from_mesa.h"
39
40 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
41 TGSI_SWIZZLE_##X, \
42 TGSI_SWIZZLE_##Y, \
43 TGSI_SWIZZLE_##Z, \
44 TGSI_SWIZZLE_##W, \
45 }
46
47 struct ttn_reg_info {
48 /** nir register containing this TGSI index. */
49 nir_register *reg;
50 nir_variable *var;
51 /** Offset (in vec4s) from the start of var for this TGSI index. */
52 int offset;
53 };
54
55 struct ttn_compile {
56 union tgsi_full_token *token;
57 nir_builder build;
58 struct tgsi_shader_info *scan;
59
60 struct ttn_reg_info *output_regs;
61 struct ttn_reg_info *temp_regs;
62 nir_ssa_def **imm_defs;
63
64 unsigned num_samp_types;
65 nir_alu_type *samp_types;
66
67 nir_register *addr_reg;
68
69 nir_variable **inputs;
70 nir_variable **outputs;
71 nir_variable *samplers[PIPE_MAX_SAMPLERS];
72 nir_variable *images[PIPE_MAX_SHADER_IMAGES];
73 nir_variable *ssbo[PIPE_MAX_SHADER_BUFFERS];
74
75 nir_variable *input_var_face;
76 nir_variable *input_var_position;
77 nir_variable *input_var_point;
78
79 /**
80 * Stack of nir_cursors where instructions should be pushed as we pop
81 * back out of the control flow stack.
82 *
83 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
84 * instructions should be placed, and if_stack[if_stack_pos - 1] has where
85 * the next instructions outside of the if/then/else block go.
86 */
87 nir_cursor *if_stack;
88 unsigned if_stack_pos;
89
90 /**
91 * Stack of nir_cursors where instructions should be pushed as we pop
92 * back out of the control flow stack.
93 *
94 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
95 * of the loop.
96 */
97 nir_cursor *loop_stack;
98 unsigned loop_stack_pos;
99
100 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
101 unsigned next_imm;
102
103 bool cap_scalar;
104 bool cap_face_is_sysval;
105 bool cap_position_is_sysval;
106 bool cap_point_is_sysval;
107 bool cap_packed_uniforms;
108 bool cap_samplers_as_deref;
109 };
110
111 #define ttn_swizzle(b, src, x, y, z, w) \
112 nir_swizzle(b, src, SWIZ(x, y, z, w), 4)
113 #define ttn_channel(b, src, swiz) \
114 nir_channel(b, src, TGSI_SWIZZLE_##swiz)
115
116 static gl_varying_slot
117 tgsi_varying_semantic_to_slot(unsigned semantic, unsigned index)
118 {
119 switch (semantic) {
120 case TGSI_SEMANTIC_POSITION:
121 return VARYING_SLOT_POS;
122 case TGSI_SEMANTIC_COLOR:
123 if (index == 0)
124 return VARYING_SLOT_COL0;
125 else
126 return VARYING_SLOT_COL1;
127 case TGSI_SEMANTIC_BCOLOR:
128 if (index == 0)
129 return VARYING_SLOT_BFC0;
130 else
131 return VARYING_SLOT_BFC1;
132 case TGSI_SEMANTIC_FOG:
133 return VARYING_SLOT_FOGC;
134 case TGSI_SEMANTIC_PSIZE:
135 return VARYING_SLOT_PSIZ;
136 case TGSI_SEMANTIC_GENERIC:
137 assert(index < 32);
138 return VARYING_SLOT_VAR0 + index;
139 case TGSI_SEMANTIC_FACE:
140 return VARYING_SLOT_FACE;
141 case TGSI_SEMANTIC_EDGEFLAG:
142 return VARYING_SLOT_EDGE;
143 case TGSI_SEMANTIC_PRIMID:
144 return VARYING_SLOT_PRIMITIVE_ID;
145 case TGSI_SEMANTIC_CLIPDIST:
146 if (index == 0)
147 return VARYING_SLOT_CLIP_DIST0;
148 else
149 return VARYING_SLOT_CLIP_DIST1;
150 case TGSI_SEMANTIC_CLIPVERTEX:
151 return VARYING_SLOT_CLIP_VERTEX;
152 case TGSI_SEMANTIC_TEXCOORD:
153 assert(index < 8);
154 return VARYING_SLOT_TEX0 + index;
155 case TGSI_SEMANTIC_PCOORD:
156 return VARYING_SLOT_PNTC;
157 case TGSI_SEMANTIC_VIEWPORT_INDEX:
158 return VARYING_SLOT_VIEWPORT;
159 case TGSI_SEMANTIC_LAYER:
160 return VARYING_SLOT_LAYER;
161 case TGSI_SEMANTIC_TESSINNER:
162 return VARYING_SLOT_TESS_LEVEL_INNER;
163 case TGSI_SEMANTIC_TESSOUTER:
164 return VARYING_SLOT_TESS_LEVEL_OUTER;
165 default:
166 fprintf(stderr, "Bad TGSI semantic: %d/%d\n", semantic, index);
167 abort();
168 }
169 }
170
171 static enum gl_frag_depth_layout
172 ttn_get_depth_layout(unsigned tgsi_fs_depth_layout)
173 {
174 switch (tgsi_fs_depth_layout) {
175 case TGSI_FS_DEPTH_LAYOUT_NONE:
176 return FRAG_DEPTH_LAYOUT_NONE;
177 case TGSI_FS_DEPTH_LAYOUT_ANY:
178 return FRAG_DEPTH_LAYOUT_ANY;
179 case TGSI_FS_DEPTH_LAYOUT_GREATER:
180 return FRAG_DEPTH_LAYOUT_GREATER;
181 case TGSI_FS_DEPTH_LAYOUT_LESS:
182 return FRAG_DEPTH_LAYOUT_LESS;
183 case TGSI_FS_DEPTH_LAYOUT_UNCHANGED:
184 return FRAG_DEPTH_LAYOUT_UNCHANGED;
185 default:
186 unreachable("bad TGSI FS depth layout");
187 }
188 }
189
190 static nir_ssa_def *
191 ttn_src_for_dest(nir_builder *b, nir_alu_dest *dest)
192 {
193 nir_alu_src src;
194 memset(&src, 0, sizeof(src));
195
196 if (dest->dest.is_ssa)
197 src.src = nir_src_for_ssa(&dest->dest.ssa);
198 else {
199 assert(!dest->dest.reg.indirect);
200 src.src = nir_src_for_reg(dest->dest.reg.reg);
201 src.src.reg.base_offset = dest->dest.reg.base_offset;
202 }
203
204 for (int i = 0; i < 4; i++)
205 src.swizzle[i] = i;
206
207 return nir_mov_alu(b, src, 4);
208 }
209
210 static enum glsl_interp_mode
211 ttn_translate_interp_mode(unsigned tgsi_interp)
212 {
213 switch (tgsi_interp) {
214 case TGSI_INTERPOLATE_CONSTANT:
215 return INTERP_MODE_FLAT;
216 case TGSI_INTERPOLATE_LINEAR:
217 return INTERP_MODE_NOPERSPECTIVE;
218 case TGSI_INTERPOLATE_PERSPECTIVE:
219 return INTERP_MODE_SMOOTH;
220 case TGSI_INTERPOLATE_COLOR:
221 return INTERP_MODE_SMOOTH;
222 default:
223 unreachable("bad TGSI interpolation mode");
224 }
225 }
226
227 static void
228 ttn_emit_declaration(struct ttn_compile *c)
229 {
230 nir_builder *b = &c->build;
231 struct tgsi_full_declaration *decl = &c->token->FullDeclaration;
232 unsigned array_size = decl->Range.Last - decl->Range.First + 1;
233 unsigned file = decl->Declaration.File;
234 unsigned i;
235
236 if (file == TGSI_FILE_TEMPORARY) {
237 if (decl->Declaration.Array) {
238 /* for arrays, we create variables instead of registers: */
239 nir_variable *var = rzalloc(b->shader, nir_variable);
240
241 var->type = glsl_array_type(glsl_vec4_type(), array_size, 0);
242 var->data.mode = nir_var_shader_temp;
243 var->name = ralloc_asprintf(var, "arr_%d", decl->Array.ArrayID);
244
245 exec_list_push_tail(&b->shader->globals, &var->node);
246
247 for (i = 0; i < array_size; i++) {
248 /* point all the matching slots to the same var,
249 * with appropriate offset set, mostly just so
250 * we know what to do when tgsi does a non-indirect
251 * access
252 */
253 c->temp_regs[decl->Range.First + i].reg = NULL;
254 c->temp_regs[decl->Range.First + i].var = var;
255 c->temp_regs[decl->Range.First + i].offset = i;
256 }
257 } else {
258 for (i = 0; i < array_size; i++) {
259 nir_register *reg = nir_local_reg_create(b->impl);
260 reg->num_components = 4;
261 c->temp_regs[decl->Range.First + i].reg = reg;
262 c->temp_regs[decl->Range.First + i].var = NULL;
263 c->temp_regs[decl->Range.First + i].offset = 0;
264 }
265 }
266 } else if (file == TGSI_FILE_ADDRESS) {
267 c->addr_reg = nir_local_reg_create(b->impl);
268 c->addr_reg->num_components = 4;
269 } else if (file == TGSI_FILE_SYSTEM_VALUE) {
270 /* Nothing to record for system values. */
271 } else if (file == TGSI_FILE_BUFFER) {
272 /* Nothing to record for buffers. */
273 } else if (file == TGSI_FILE_IMAGE) {
274 /* Nothing to record for images. */
275 } else if (file == TGSI_FILE_SAMPLER) {
276 /* Nothing to record for samplers. */
277 } else if (file == TGSI_FILE_SAMPLER_VIEW) {
278 struct tgsi_declaration_sampler_view *sview = &decl->SamplerView;
279 nir_alu_type type;
280
281 assert((sview->ReturnTypeX == sview->ReturnTypeY) &&
282 (sview->ReturnTypeX == sview->ReturnTypeZ) &&
283 (sview->ReturnTypeX == sview->ReturnTypeW));
284
285 switch (sview->ReturnTypeX) {
286 case TGSI_RETURN_TYPE_SINT:
287 type = nir_type_int;
288 break;
289 case TGSI_RETURN_TYPE_UINT:
290 type = nir_type_uint;
291 break;
292 case TGSI_RETURN_TYPE_FLOAT:
293 default:
294 type = nir_type_float;
295 break;
296 }
297
298 for (i = 0; i < array_size; i++) {
299 c->samp_types[decl->Range.First + i] = type;
300 }
301 } else {
302 bool is_array = (array_size > 1);
303
304 assert(file == TGSI_FILE_INPUT ||
305 file == TGSI_FILE_OUTPUT ||
306 file == TGSI_FILE_CONSTANT);
307
308 /* nothing to do for UBOs: */
309 if ((file == TGSI_FILE_CONSTANT) && decl->Declaration.Dimension &&
310 decl->Dim.Index2D != 0) {
311 b->shader->info.num_ubos =
312 MAX2(b->shader->info.num_ubos, decl->Dim.Index2D);
313 return;
314 }
315
316 if ((file == TGSI_FILE_INPUT) || (file == TGSI_FILE_OUTPUT)) {
317 is_array = (is_array && decl->Declaration.Array &&
318 (decl->Array.ArrayID != 0));
319 }
320
321 for (i = 0; i < array_size; i++) {
322 unsigned idx = decl->Range.First + i;
323 nir_variable *var = rzalloc(b->shader, nir_variable);
324
325 var->data.driver_location = idx;
326
327 var->type = glsl_vec4_type();
328 if (is_array)
329 var->type = glsl_array_type(var->type, array_size, 0);
330
331 switch (file) {
332 case TGSI_FILE_INPUT:
333 var->data.read_only = true;
334 var->data.mode = nir_var_shader_in;
335 var->name = ralloc_asprintf(var, "in_%d", idx);
336
337 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
338 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
339 var->type = glsl_bool_type();
340 if (c->cap_face_is_sysval) {
341 var->data.mode = nir_var_system_value;
342 var->data.location = SYSTEM_VALUE_FRONT_FACE;
343 } else {
344 var->data.location = VARYING_SLOT_FACE;
345 }
346 c->input_var_face = var;
347 } else if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
348 if (c->cap_position_is_sysval) {
349 var->data.mode = nir_var_system_value;
350 var->data.location = SYSTEM_VALUE_FRAG_COORD;
351 } else {
352 var->data.location = VARYING_SLOT_POS;
353 }
354 c->input_var_position = var;
355 } else if (decl->Semantic.Name == TGSI_SEMANTIC_PCOORD) {
356 if (c->cap_point_is_sysval) {
357 var->data.mode = nir_var_system_value;
358 var->data.location = SYSTEM_VALUE_POINT_COORD;
359 } else {
360 var->data.location = VARYING_SLOT_PNTC;
361 }
362 c->input_var_point = var;
363 } else {
364 var->data.location =
365 tgsi_varying_semantic_to_slot(decl->Semantic.Name,
366 decl->Semantic.Index);
367 }
368 } else {
369 assert(!decl->Declaration.Semantic);
370 var->data.location = VERT_ATTRIB_GENERIC0 + idx;
371 }
372 var->data.index = 0;
373 var->data.interpolation =
374 ttn_translate_interp_mode(decl->Interp.Interpolate);
375
376 exec_list_push_tail(&b->shader->inputs, &var->node);
377 c->inputs[idx] = var;
378
379 for (int i = 0; i < array_size; i++)
380 b->shader->info.inputs_read |= 1 << (var->data.location + i);
381
382 break;
383 case TGSI_FILE_OUTPUT: {
384 int semantic_name = decl->Semantic.Name;
385 int semantic_index = decl->Semantic.Index;
386 /* Since we can't load from outputs in the IR, we make temporaries
387 * for the outputs and emit stores to the real outputs at the end of
388 * the shader.
389 */
390 nir_register *reg = nir_local_reg_create(b->impl);
391 reg->num_components = 4;
392 if (is_array)
393 reg->num_array_elems = array_size;
394
395 var->data.mode = nir_var_shader_out;
396 var->name = ralloc_asprintf(var, "out_%d", idx);
397 var->data.index = 0;
398 var->data.interpolation =
399 ttn_translate_interp_mode(decl->Interp.Interpolate);
400 var->data.patch = semantic_name == TGSI_SEMANTIC_TESSINNER ||
401 semantic_name == TGSI_SEMANTIC_TESSOUTER ||
402 semantic_name == TGSI_SEMANTIC_PATCH;
403
404 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
405 switch (semantic_name) {
406 case TGSI_SEMANTIC_COLOR: {
407 /* TODO tgsi loses some information, so we cannot
408 * actually differentiate here between DSB and MRT
409 * at this point. But so far no drivers using tgsi-
410 * to-nir support dual source blend:
411 */
412 bool dual_src_blend = false;
413 if (dual_src_blend && (semantic_index == 1)) {
414 var->data.location = FRAG_RESULT_DATA0;
415 var->data.index = 1;
416 } else {
417 if (c->scan->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
418 var->data.location = FRAG_RESULT_COLOR;
419 else
420 var->data.location = FRAG_RESULT_DATA0 + semantic_index;
421 }
422 break;
423 }
424 case TGSI_SEMANTIC_POSITION:
425 var->data.location = FRAG_RESULT_DEPTH;
426 var->type = glsl_float_type();
427 break;
428 case TGSI_SEMANTIC_STENCIL:
429 var->data.location = FRAG_RESULT_STENCIL;
430 var->type = glsl_int_type();
431 break;
432 default:
433 fprintf(stderr, "Bad TGSI semantic: %d/%d\n",
434 decl->Semantic.Name, decl->Semantic.Index);
435 abort();
436 }
437 } else {
438 var->data.location =
439 tgsi_varying_semantic_to_slot(semantic_name, semantic_index);
440 }
441
442 if (is_array) {
443 unsigned j;
444 for (j = 0; j < array_size; j++) {
445 c->output_regs[idx + j].offset = i + j;
446 c->output_regs[idx + j].reg = reg;
447 }
448 } else {
449 c->output_regs[idx].offset = i;
450 c->output_regs[idx].reg = reg;
451 }
452
453 exec_list_push_tail(&b->shader->outputs, &var->node);
454 c->outputs[idx] = var;
455
456 for (int i = 0; i < array_size; i++)
457 b->shader->info.outputs_written |= 1ull << (var->data.location + i);
458 }
459 break;
460 case TGSI_FILE_CONSTANT:
461 var->data.mode = nir_var_uniform;
462 var->name = ralloc_asprintf(var, "uniform_%d", idx);
463 var->data.location = idx;
464
465 exec_list_push_tail(&b->shader->uniforms, &var->node);
466 break;
467 default:
468 unreachable("bad declaration file");
469 return;
470 }
471
472 if (is_array)
473 break;
474 }
475
476 }
477 }
478
479 static void
480 ttn_emit_immediate(struct ttn_compile *c)
481 {
482 nir_builder *b = &c->build;
483 struct tgsi_full_immediate *tgsi_imm = &c->token->FullImmediate;
484 nir_load_const_instr *load_const;
485 int i;
486
487 load_const = nir_load_const_instr_create(b->shader, 4, 32);
488 c->imm_defs[c->next_imm] = &load_const->def;
489 c->next_imm++;
490
491 for (i = 0; i < load_const->def.num_components; i++)
492 load_const->value[i].u32 = tgsi_imm->u[i].Uint;
493
494 nir_builder_instr_insert(b, &load_const->instr);
495 }
496
497 static nir_ssa_def *
498 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect);
499
500 /* generate either a constant or indirect deref chain for accessing an
501 * array variable.
502 */
503 static nir_deref_instr *
504 ttn_array_deref(struct ttn_compile *c, nir_variable *var, unsigned offset,
505 struct tgsi_ind_register *indirect)
506 {
507 nir_deref_instr *deref = nir_build_deref_var(&c->build, var);
508 nir_ssa_def *index = nir_imm_int(&c->build, offset);
509 if (indirect)
510 index = nir_iadd(&c->build, index, ttn_src_for_indirect(c, indirect));
511 return nir_build_deref_array(&c->build, deref, index);
512 }
513
514 /* Special case: Turn the frontface varying into a load of the
515 * frontface variable, and create the vector as required by TGSI.
516 */
517 static nir_ssa_def *
518 ttn_emulate_tgsi_front_face(struct ttn_compile *c)
519 {
520 nir_ssa_def *tgsi_frontface[4];
521
522 if (c->cap_face_is_sysval) {
523 /* When it's a system value, it should be an integer vector: (F, 0, 0, 1)
524 * F is 0xffffffff if front-facing, 0 if not.
525 */
526
527 nir_ssa_def *frontface = nir_load_front_face(&c->build, 1);
528
529 tgsi_frontface[0] = nir_bcsel(&c->build,
530 frontface,
531 nir_imm_int(&c->build, 0xffffffff),
532 nir_imm_int(&c->build, 0));
533 tgsi_frontface[1] = nir_imm_int(&c->build, 0);
534 tgsi_frontface[2] = nir_imm_int(&c->build, 0);
535 tgsi_frontface[3] = nir_imm_int(&c->build, 1);
536 } else {
537 /* When it's an input, it should be a float vector: (F, 0.0, 0.0, 1.0)
538 * F is positive if front-facing, negative if not.
539 */
540
541 assert(c->input_var_face);
542 nir_ssa_def *frontface = nir_load_var(&c->build, c->input_var_face);
543
544 tgsi_frontface[0] = nir_bcsel(&c->build,
545 frontface,
546 nir_imm_float(&c->build, 1.0),
547 nir_imm_float(&c->build, -1.0));
548 tgsi_frontface[1] = nir_imm_float(&c->build, 0.0);
549 tgsi_frontface[2] = nir_imm_float(&c->build, 0.0);
550 tgsi_frontface[3] = nir_imm_float(&c->build, 1.0);
551 }
552
553 return nir_vec(&c->build, tgsi_frontface, 4);
554 }
555
556 static nir_src
557 ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
558 struct tgsi_ind_register *indirect,
559 struct tgsi_dimension *dim,
560 struct tgsi_ind_register *dimind,
561 bool src_is_float)
562 {
563 nir_builder *b = &c->build;
564 nir_src src;
565
566 memset(&src, 0, sizeof(src));
567
568 switch (file) {
569 case TGSI_FILE_TEMPORARY:
570 if (c->temp_regs[index].var) {
571 unsigned offset = c->temp_regs[index].offset;
572 nir_variable *var = c->temp_regs[index].var;
573 nir_ssa_def *load = nir_load_deref(&c->build,
574 ttn_array_deref(c, var, offset, indirect));
575
576 src = nir_src_for_ssa(load);
577 } else {
578 assert(!indirect);
579 src.reg.reg = c->temp_regs[index].reg;
580 }
581 assert(!dim);
582 break;
583
584 case TGSI_FILE_ADDRESS:
585 src.reg.reg = c->addr_reg;
586 assert(!dim);
587 break;
588
589 case TGSI_FILE_IMMEDIATE:
590 src = nir_src_for_ssa(c->imm_defs[index]);
591 assert(!indirect);
592 assert(!dim);
593 break;
594
595 case TGSI_FILE_SYSTEM_VALUE: {
596 nir_intrinsic_op op;
597 nir_ssa_def *load;
598
599 assert(!indirect);
600 assert(!dim);
601
602 switch (c->scan->system_value_semantic_name[index]) {
603 case TGSI_SEMANTIC_VERTEXID_NOBASE:
604 op = nir_intrinsic_load_vertex_id_zero_base;
605 load = nir_load_vertex_id_zero_base(b);
606 break;
607 case TGSI_SEMANTIC_VERTEXID:
608 op = nir_intrinsic_load_vertex_id;
609 load = nir_load_vertex_id(b);
610 break;
611 case TGSI_SEMANTIC_BASEVERTEX:
612 op = nir_intrinsic_load_base_vertex;
613 load = nir_load_base_vertex(b);
614 break;
615 case TGSI_SEMANTIC_INSTANCEID:
616 op = nir_intrinsic_load_instance_id;
617 load = nir_load_instance_id(b);
618 break;
619 case TGSI_SEMANTIC_FACE:
620 assert(c->cap_face_is_sysval);
621 op = nir_intrinsic_load_front_face;
622 load = ttn_emulate_tgsi_front_face(c);
623 break;
624 case TGSI_SEMANTIC_POSITION:
625 assert(c->cap_position_is_sysval);
626 op = nir_intrinsic_load_frag_coord;
627 load = nir_load_frag_coord(b);
628 break;
629 case TGSI_SEMANTIC_PCOORD:
630 assert(c->cap_point_is_sysval);
631 op = nir_intrinsic_load_point_coord;
632 load = nir_load_point_coord(b);
633 break;
634 case TGSI_SEMANTIC_THREAD_ID:
635 op = nir_intrinsic_load_local_invocation_id;
636 load = nir_load_local_invocation_id(b);
637 break;
638 case TGSI_SEMANTIC_BLOCK_ID:
639 op = nir_intrinsic_load_work_group_id;
640 load = nir_load_work_group_id(b);
641 break;
642 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
643 op = nir_intrinsic_load_user_data_amd;
644 load = nir_load_user_data_amd(b);
645 break;
646 case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL:
647 op = nir_intrinsic_load_tess_level_inner_default;
648 load = nir_load_tess_level_inner_default(b);
649 break;
650 case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL:
651 op = nir_intrinsic_load_tess_level_outer_default;
652 load = nir_load_tess_level_outer_default(b);
653 break;
654 default:
655 unreachable("bad system value");
656 }
657
658 if (load->num_components == 3)
659 load = nir_swizzle(b, load, SWIZ(X, Y, Z, Z), 4);
660
661 src = nir_src_for_ssa(load);
662 b->shader->info.system_values_read |=
663 (1ull << nir_system_value_from_intrinsic(op));
664
665 break;
666 }
667
668 case TGSI_FILE_INPUT:
669 if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
670 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_FACE) {
671 assert(!c->cap_face_is_sysval && c->input_var_face);
672 return nir_src_for_ssa(ttn_emulate_tgsi_front_face(c));
673 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
674 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_POSITION) {
675 assert(!c->cap_position_is_sysval && c->input_var_position);
676 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_position));
677 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
678 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_PCOORD) {
679 assert(!c->cap_point_is_sysval && c->input_var_point);
680 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_point));
681 } else {
682 /* Indirection on input arrays isn't supported by TTN. */
683 assert(!dim);
684 nir_deref_instr *deref = nir_build_deref_var(&c->build,
685 c->inputs[index]);
686 return nir_src_for_ssa(nir_load_deref(&c->build, deref));
687 }
688 break;
689
690 case TGSI_FILE_CONSTANT: {
691 nir_intrinsic_instr *load;
692 nir_intrinsic_op op;
693 unsigned srcn = 0;
694
695 if (dim && (dim->Index > 0 || dim->Indirect)) {
696 op = nir_intrinsic_load_ubo;
697 } else {
698 op = nir_intrinsic_load_uniform;
699 }
700
701 load = nir_intrinsic_instr_create(b->shader, op);
702 if (op == nir_intrinsic_load_uniform) {
703 nir_intrinsic_set_type(load, src_is_float ? nir_type_float :
704 nir_type_int);
705 }
706
707 load->num_components = 4;
708 if (dim && (dim->Index > 0 || dim->Indirect)) {
709 if (dimind) {
710 load->src[srcn] =
711 ttn_src_for_file_and_index(c, dimind->File, dimind->Index,
712 NULL, NULL, NULL, false);
713 } else {
714 /* UBOs start at index 1 in TGSI: */
715 load->src[srcn] =
716 nir_src_for_ssa(nir_imm_int(b, dim->Index - 1));
717 }
718 srcn++;
719 }
720
721 nir_ssa_def *offset;
722 if (op == nir_intrinsic_load_ubo) {
723 /* UBO loads don't have a base offset. */
724 offset = nir_imm_int(b, index);
725 if (indirect) {
726 offset = nir_iadd(b, offset, ttn_src_for_indirect(c, indirect));
727 }
728 /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */
729 offset = nir_ishl(b, offset, nir_imm_int(b, 4));
730 } else {
731 nir_intrinsic_set_base(load, index);
732 if (indirect) {
733 offset = ttn_src_for_indirect(c, indirect);
734 } else {
735 offset = nir_imm_int(b, 0);
736 }
737 }
738 load->src[srcn++] = nir_src_for_ssa(offset);
739
740 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
741 nir_builder_instr_insert(b, &load->instr);
742
743 src = nir_src_for_ssa(&load->dest.ssa);
744 break;
745 }
746
747 default:
748 unreachable("bad src file");
749 }
750
751
752 return src;
753 }
754
755 static nir_ssa_def *
756 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect)
757 {
758 nir_builder *b = &c->build;
759 nir_alu_src src;
760 memset(&src, 0, sizeof(src));
761 for (int i = 0; i < 4; i++)
762 src.swizzle[i] = indirect->Swizzle;
763 src.src = ttn_src_for_file_and_index(c,
764 indirect->File,
765 indirect->Index,
766 NULL, NULL, NULL,
767 false);
768 return nir_mov_alu(b, src, 1);
769 }
770
771 static nir_alu_dest
772 ttn_get_dest(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
773 {
774 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
775 nir_alu_dest dest;
776 unsigned index = tgsi_dst->Index;
777
778 memset(&dest, 0, sizeof(dest));
779
780 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
781 if (c->temp_regs[index].var) {
782 nir_register *reg;
783
784 /* this works, because TGSI will give us a base offset
785 * (in case of indirect index) that points back into
786 * the array. Access can be direct or indirect, we
787 * don't really care. Just create a one-shot dst reg
788 * that will get store_var'd back into the array var
789 * at the end of ttn_emit_instruction()
790 */
791 reg = nir_local_reg_create(c->build.impl);
792 reg->num_components = 4;
793 dest.dest.reg.reg = reg;
794 dest.dest.reg.base_offset = 0;
795 } else {
796 assert(!tgsi_dst->Indirect);
797 dest.dest.reg.reg = c->temp_regs[index].reg;
798 dest.dest.reg.base_offset = c->temp_regs[index].offset;
799 }
800 } else if (tgsi_dst->File == TGSI_FILE_OUTPUT) {
801 dest.dest.reg.reg = c->output_regs[index].reg;
802 dest.dest.reg.base_offset = c->output_regs[index].offset;
803 } else if (tgsi_dst->File == TGSI_FILE_ADDRESS) {
804 assert(index == 0);
805 dest.dest.reg.reg = c->addr_reg;
806 }
807
808 dest.write_mask = tgsi_dst->WriteMask;
809 dest.saturate = false;
810
811 if (tgsi_dst->Indirect && (tgsi_dst->File != TGSI_FILE_TEMPORARY)) {
812 nir_src *indirect = ralloc(c->build.shader, nir_src);
813 *indirect = nir_src_for_ssa(ttn_src_for_indirect(c, &tgsi_fdst->Indirect));
814 dest.dest.reg.indirect = indirect;
815 }
816
817 return dest;
818 }
819
820 static nir_variable *
821 ttn_get_var(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
822 {
823 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
824 unsigned index = tgsi_dst->Index;
825
826 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
827 /* we should not have an indirect when there is no var! */
828 if (!c->temp_regs[index].var)
829 assert(!tgsi_dst->Indirect);
830 return c->temp_regs[index].var;
831 }
832
833 return NULL;
834 }
835
836 static nir_ssa_def *
837 ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc,
838 int src_idx)
839 {
840 nir_builder *b = &c->build;
841 struct tgsi_src_register *tgsi_src = &tgsi_fsrc->Register;
842 enum tgsi_opcode opcode = c->token->FullInstruction.Instruction.Opcode;
843 unsigned tgsi_src_type = tgsi_opcode_infer_src_type(opcode, src_idx);
844 bool src_is_float = (tgsi_src_type == TGSI_TYPE_FLOAT ||
845 tgsi_src_type == TGSI_TYPE_DOUBLE ||
846 tgsi_src_type == TGSI_TYPE_UNTYPED);
847 nir_alu_src src;
848
849 memset(&src, 0, sizeof(src));
850
851 if (tgsi_src->File == TGSI_FILE_NULL) {
852 return nir_imm_float(b, 0.0);
853 } else if (tgsi_src->File == TGSI_FILE_SAMPLER ||
854 tgsi_src->File == TGSI_FILE_IMAGE ||
855 tgsi_src->File == TGSI_FILE_BUFFER) {
856 /* Only the index of the resource gets used in texturing, and it will
857 * handle looking that up on its own instead of using the nir_alu_src.
858 */
859 assert(!tgsi_src->Indirect);
860 return NULL;
861 } else {
862 struct tgsi_ind_register *ind = NULL;
863 struct tgsi_dimension *dim = NULL;
864 struct tgsi_ind_register *dimind = NULL;
865 if (tgsi_src->Indirect)
866 ind = &tgsi_fsrc->Indirect;
867 if (tgsi_src->Dimension) {
868 dim = &tgsi_fsrc->Dimension;
869 if (dim->Indirect)
870 dimind = &tgsi_fsrc->DimIndirect;
871 }
872 src.src = ttn_src_for_file_and_index(c,
873 tgsi_src->File,
874 tgsi_src->Index,
875 ind, dim, dimind,
876 src_is_float);
877 }
878
879 src.swizzle[0] = tgsi_src->SwizzleX;
880 src.swizzle[1] = tgsi_src->SwizzleY;
881 src.swizzle[2] = tgsi_src->SwizzleZ;
882 src.swizzle[3] = tgsi_src->SwizzleW;
883
884 nir_ssa_def *def = nir_mov_alu(b, src, 4);
885
886 if (tgsi_type_is_64bit(tgsi_src_type))
887 def = nir_bitcast_vector(b, def, 64);
888
889 if (tgsi_src->Absolute) {
890 if (src_is_float)
891 def = nir_fabs(b, def);
892 else
893 def = nir_iabs(b, def);
894 }
895
896 if (tgsi_src->Negate) {
897 if (src_is_float)
898 def = nir_fneg(b, def);
899 else
900 def = nir_ineg(b, def);
901 }
902
903 return def;
904 }
905
906 static void
907 ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
908 nir_ssa_def *def, unsigned write_mask)
909 {
910 if (!(dest.write_mask & write_mask))
911 return;
912
913 nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
914 mov->dest = dest;
915 mov->dest.write_mask &= write_mask;
916 mov->src[0].src = nir_src_for_ssa(def);
917 for (unsigned i = def->num_components; i < 4; i++)
918 mov->src[0].swizzle[i] = def->num_components - 1;
919 nir_builder_instr_insert(b, &mov->instr);
920 }
921
922 static void
923 ttn_move_dest(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def)
924 {
925 ttn_move_dest_masked(b, dest, def, TGSI_WRITEMASK_XYZW);
926 }
927
928 static void
929 ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, unsigned dest_bitsize,
930 nir_ssa_def **src)
931 {
932 nir_ssa_def *def = nir_build_alu_src_arr(b, op, src);
933 if (def->bit_size == 1)
934 def = nir_ineg(b, nir_b2i(b, def, dest_bitsize));
935 assert(def->bit_size == dest_bitsize);
936 if (dest_bitsize == 64) {
937 if (def->num_components > 2) {
938 /* 32 -> 64 bit conversion ops are supposed to only convert the first
939 * two components, and we need to truncate here to avoid creating a
940 * vec8 after bitcasting the destination.
941 */
942 def = nir_channels(b, def, 0x3);
943 }
944 def = nir_bitcast_vector(b, def, 32);
945 }
946 ttn_move_dest(b, dest, def);
947 }
948
949 static void
950 ttn_arl(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
951 {
952 ttn_move_dest(b, dest, nir_f2i32(b, nir_ffloor(b, src[0])));
953 }
954
955 /* EXP - Approximate Exponential Base 2
956 * dst.x = 2^{\lfloor src.x\rfloor}
957 * dst.y = src.x - \lfloor src.x\rfloor
958 * dst.z = 2^{src.x}
959 * dst.w = 1.0
960 */
961 static void
962 ttn_exp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
963 {
964 nir_ssa_def *srcx = ttn_channel(b, src[0], X);
965
966 ttn_move_dest_masked(b, dest, nir_fexp2(b, nir_ffloor(b, srcx)),
967 TGSI_WRITEMASK_X);
968 ttn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)),
969 TGSI_WRITEMASK_Y);
970 ttn_move_dest_masked(b, dest, nir_fexp2(b, srcx), TGSI_WRITEMASK_Z);
971 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
972 }
973
974 /* LOG - Approximate Logarithm Base 2
975 * dst.x = \lfloor\log_2{|src.x|}\rfloor
976 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
977 * dst.z = \log_2{|src.x|}
978 * dst.w = 1.0
979 */
980 static void
981 ttn_log(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
982 {
983 nir_ssa_def *abs_srcx = nir_fabs(b, ttn_channel(b, src[0], X));
984 nir_ssa_def *log2 = nir_flog2(b, abs_srcx);
985
986 ttn_move_dest_masked(b, dest, nir_ffloor(b, log2), TGSI_WRITEMASK_X);
987 ttn_move_dest_masked(b, dest,
988 nir_fdiv(b, abs_srcx, nir_fexp2(b, nir_ffloor(b, log2))),
989 TGSI_WRITEMASK_Y);
990 ttn_move_dest_masked(b, dest, nir_flog2(b, abs_srcx), TGSI_WRITEMASK_Z);
991 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
992 }
993
994 /* DST - Distance Vector
995 * dst.x = 1.0
996 * dst.y = src0.y \times src1.y
997 * dst.z = src0.z
998 * dst.w = src1.w
999 */
1000 static void
1001 ttn_dst(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1002 {
1003 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_X);
1004 ttn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), TGSI_WRITEMASK_Y);
1005 ttn_move_dest_masked(b, dest, nir_mov(b, src[0]), TGSI_WRITEMASK_Z);
1006 ttn_move_dest_masked(b, dest, nir_mov(b, src[1]), TGSI_WRITEMASK_W);
1007 }
1008
1009 /* LIT - Light Coefficients
1010 * dst.x = 1.0
1011 * dst.y = max(src.x, 0.0)
1012 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
1013 * dst.w = 1.0
1014 */
1015 static void
1016 ttn_lit(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1017 {
1018 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_XW);
1019
1020 ttn_move_dest_masked(b, dest, nir_fmax(b, ttn_channel(b, src[0], X),
1021 nir_imm_float(b, 0.0)), TGSI_WRITEMASK_Y);
1022
1023 if (dest.write_mask & TGSI_WRITEMASK_Z) {
1024 nir_ssa_def *src0_y = ttn_channel(b, src[0], Y);
1025 nir_ssa_def *wclamp = nir_fmax(b, nir_fmin(b, ttn_channel(b, src[0], W),
1026 nir_imm_float(b, 128.0)),
1027 nir_imm_float(b, -128.0));
1028 nir_ssa_def *pow = nir_fpow(b, nir_fmax(b, src0_y, nir_imm_float(b, 0.0)),
1029 wclamp);
1030
1031 ttn_move_dest_masked(b, dest,
1032 nir_bcsel(b,
1033 nir_flt(b,
1034 ttn_channel(b, src[0], X),
1035 nir_imm_float(b, 0.0)),
1036 nir_imm_float(b, 0.0),
1037 pow),
1038 TGSI_WRITEMASK_Z);
1039 }
1040 }
1041
1042 static void
1043 ttn_sle(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1044 {
1045 ttn_move_dest(b, dest, nir_sge(b, src[1], src[0]));
1046 }
1047
1048 static void
1049 ttn_sgt(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1050 {
1051 ttn_move_dest(b, dest, nir_slt(b, src[1], src[0]));
1052 }
1053
1054 static void
1055 ttn_dp2(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1056 {
1057 ttn_move_dest(b, dest, nir_fdot2(b, src[0], src[1]));
1058 }
1059
1060 static void
1061 ttn_dp3(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1062 {
1063 ttn_move_dest(b, dest, nir_fdot3(b, src[0], src[1]));
1064 }
1065
1066 static void
1067 ttn_dp4(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1068 {
1069 ttn_move_dest(b, dest, nir_fdot4(b, src[0], src[1]));
1070 }
1071
1072 static void
1073 ttn_umad(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1074 {
1075 ttn_move_dest(b, dest, nir_iadd(b, nir_imul(b, src[0], src[1]), src[2]));
1076 }
1077
1078 static void
1079 ttn_arr(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1080 {
1081 ttn_move_dest(b, dest, nir_f2i32(b, nir_fround_even(b, src[0])));
1082 }
1083
1084 static void
1085 ttn_cmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1086 {
1087 ttn_move_dest(b, dest, nir_bcsel(b,
1088 nir_flt(b, src[0], nir_imm_float(b, 0.0)),
1089 src[1], src[2]));
1090 }
1091
1092 static void
1093 ttn_ucmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1094 {
1095 ttn_move_dest(b, dest, nir_bcsel(b,
1096 nir_ine(b, src[0], nir_imm_int(b, 0)),
1097 src[1], src[2]));
1098 }
1099
1100 static void
1101 ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1102 {
1103 nir_intrinsic_instr *discard =
1104 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard);
1105 nir_builder_instr_insert(b, &discard->instr);
1106 b->shader->info.fs.uses_discard = true;
1107 }
1108
1109 static void
1110 ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1111 {
1112 nir_ssa_def *cmp = nir_bany(b, nir_flt(b, src[0], nir_imm_float(b, 0.0)));
1113 nir_intrinsic_instr *discard =
1114 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard_if);
1115 discard->src[0] = nir_src_for_ssa(cmp);
1116 nir_builder_instr_insert(b, &discard->instr);
1117 b->shader->info.fs.uses_discard = true;
1118 }
1119
1120 static void
1121 ttn_if(struct ttn_compile *c, nir_ssa_def *src, bool is_uint)
1122 {
1123 nir_builder *b = &c->build;
1124 nir_ssa_def *src_x = ttn_channel(b, src, X);
1125
1126 nir_if *if_stmt = nir_if_create(b->shader);
1127 if (is_uint) {
1128 /* equivalent to TGSI UIF, src is interpreted as integer */
1129 if_stmt->condition = nir_src_for_ssa(nir_ine(b, src_x, nir_imm_int(b, 0)));
1130 } else {
1131 /* equivalent to TGSI IF, src is interpreted as float */
1132 if_stmt->condition = nir_src_for_ssa(nir_fne(b, src_x, nir_imm_float(b, 0.0)));
1133 }
1134 nir_builder_cf_insert(b, &if_stmt->cf_node);
1135
1136 c->if_stack[c->if_stack_pos] = nir_after_cf_node(&if_stmt->cf_node);
1137 c->if_stack_pos++;
1138
1139 b->cursor = nir_after_cf_list(&if_stmt->then_list);
1140
1141 c->if_stack[c->if_stack_pos] = nir_after_cf_list(&if_stmt->else_list);
1142 c->if_stack_pos++;
1143 }
1144
1145 static void
1146 ttn_else(struct ttn_compile *c)
1147 {
1148 nir_builder *b = &c->build;
1149
1150 b->cursor = c->if_stack[c->if_stack_pos - 1];
1151 }
1152
1153 static void
1154 ttn_endif(struct ttn_compile *c)
1155 {
1156 nir_builder *b = &c->build;
1157
1158 c->if_stack_pos -= 2;
1159 b->cursor = c->if_stack[c->if_stack_pos];
1160 }
1161
1162 static void
1163 ttn_bgnloop(struct ttn_compile *c)
1164 {
1165 nir_builder *b = &c->build;
1166
1167 nir_loop *loop = nir_loop_create(b->shader);
1168 nir_builder_cf_insert(b, &loop->cf_node);
1169
1170 c->loop_stack[c->loop_stack_pos] = nir_after_cf_node(&loop->cf_node);
1171 c->loop_stack_pos++;
1172
1173 b->cursor = nir_after_cf_list(&loop->body);
1174 }
1175
1176 static void
1177 ttn_cont(nir_builder *b)
1178 {
1179 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_continue);
1180 nir_builder_instr_insert(b, &instr->instr);
1181 }
1182
1183 static void
1184 ttn_brk(nir_builder *b)
1185 {
1186 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
1187 nir_builder_instr_insert(b, &instr->instr);
1188 }
1189
1190 static void
1191 ttn_endloop(struct ttn_compile *c)
1192 {
1193 nir_builder *b = &c->build;
1194
1195 c->loop_stack_pos--;
1196 b->cursor = c->loop_stack[c->loop_stack_pos];
1197 }
1198
1199 static void
1200 get_texture_info(unsigned texture,
1201 enum glsl_sampler_dim *dim,
1202 bool *is_shadow,
1203 bool *is_array)
1204 {
1205 assert(is_array);
1206 *is_array = false;
1207
1208 if (is_shadow)
1209 *is_shadow = false;
1210
1211 switch (texture) {
1212 case TGSI_TEXTURE_BUFFER:
1213 *dim = GLSL_SAMPLER_DIM_BUF;
1214 break;
1215 case TGSI_TEXTURE_1D:
1216 *dim = GLSL_SAMPLER_DIM_1D;
1217 break;
1218 case TGSI_TEXTURE_1D_ARRAY:
1219 *dim = GLSL_SAMPLER_DIM_1D;
1220 *is_array = true;
1221 break;
1222 case TGSI_TEXTURE_SHADOW1D:
1223 *dim = GLSL_SAMPLER_DIM_1D;
1224 *is_shadow = true;
1225 break;
1226 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1227 *dim = GLSL_SAMPLER_DIM_1D;
1228 *is_shadow = true;
1229 *is_array = true;
1230 break;
1231 case TGSI_TEXTURE_2D:
1232 *dim = GLSL_SAMPLER_DIM_2D;
1233 break;
1234 case TGSI_TEXTURE_2D_ARRAY:
1235 *dim = GLSL_SAMPLER_DIM_2D;
1236 *is_array = true;
1237 break;
1238 case TGSI_TEXTURE_2D_MSAA:
1239 *dim = GLSL_SAMPLER_DIM_MS;
1240 break;
1241 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1242 *dim = GLSL_SAMPLER_DIM_MS;
1243 *is_array = true;
1244 break;
1245 case TGSI_TEXTURE_SHADOW2D:
1246 *dim = GLSL_SAMPLER_DIM_2D;
1247 *is_shadow = true;
1248 break;
1249 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1250 *dim = GLSL_SAMPLER_DIM_2D;
1251 *is_shadow = true;
1252 *is_array = true;
1253 break;
1254 case TGSI_TEXTURE_3D:
1255 *dim = GLSL_SAMPLER_DIM_3D;
1256 break;
1257 case TGSI_TEXTURE_CUBE:
1258 *dim = GLSL_SAMPLER_DIM_CUBE;
1259 break;
1260 case TGSI_TEXTURE_CUBE_ARRAY:
1261 *dim = GLSL_SAMPLER_DIM_CUBE;
1262 *is_array = true;
1263 break;
1264 case TGSI_TEXTURE_SHADOWCUBE:
1265 *dim = GLSL_SAMPLER_DIM_CUBE;
1266 *is_shadow = true;
1267 break;
1268 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1269 *dim = GLSL_SAMPLER_DIM_CUBE;
1270 *is_shadow = true;
1271 *is_array = true;
1272 break;
1273 case TGSI_TEXTURE_RECT:
1274 *dim = GLSL_SAMPLER_DIM_RECT;
1275 break;
1276 case TGSI_TEXTURE_SHADOWRECT:
1277 *dim = GLSL_SAMPLER_DIM_RECT;
1278 *is_shadow = true;
1279 break;
1280 default:
1281 fprintf(stderr, "Unknown TGSI texture target %d\n", texture);
1282 abort();
1283 }
1284 }
1285
1286 static enum glsl_base_type
1287 base_type_for_alu_type(nir_alu_type type)
1288 {
1289 type = nir_alu_type_get_base_type(type);
1290
1291 switch (type) {
1292 case nir_type_float:
1293 return GLSL_TYPE_FLOAT;
1294 case nir_type_int:
1295 return GLSL_TYPE_INT;
1296 case nir_type_uint:
1297 return GLSL_TYPE_UINT;
1298 default:
1299 unreachable("invalid type");
1300 }
1301 }
1302
1303 static nir_variable *
1304 get_sampler_var(struct ttn_compile *c, int binding,
1305 enum glsl_sampler_dim dim,
1306 bool is_shadow,
1307 bool is_array,
1308 enum glsl_base_type base_type,
1309 nir_texop op)
1310 {
1311 nir_variable *var = c->samplers[binding];
1312 if (!var) {
1313 const struct glsl_type *type =
1314 glsl_sampler_type(dim, is_shadow, is_array, base_type);
1315 var = nir_variable_create(c->build.shader, nir_var_uniform, type,
1316 "sampler");
1317 var->data.binding = binding;
1318 var->data.explicit_binding = true;
1319 c->samplers[binding] = var;
1320
1321 /* Record textures used */
1322 unsigned mask = 1 << binding;
1323 c->build.shader->info.textures_used |= mask;
1324 if (op == nir_texop_txf ||
1325 op == nir_texop_txf_ms ||
1326 op == nir_texop_txf_ms_mcs)
1327 c->build.shader->info.textures_used_by_txf |= mask;
1328 }
1329
1330 return var;
1331 }
1332
1333 static nir_variable *
1334 get_image_var(struct ttn_compile *c, int binding,
1335 enum glsl_sampler_dim dim,
1336 bool is_array,
1337 enum glsl_base_type base_type,
1338 enum gl_access_qualifier access,
1339 GLenum format)
1340 {
1341 nir_variable *var = c->images[binding];
1342
1343 if (!var) {
1344 const struct glsl_type *type = glsl_image_type(dim, is_array, base_type);
1345
1346 var = nir_variable_create(c->build.shader, nir_var_uniform, type, "image");
1347 var->data.binding = binding;
1348 var->data.explicit_binding = true;
1349 var->data.image.access = access;
1350 var->data.image.format = format;
1351 c->images[binding] = var;
1352 }
1353
1354 return var;
1355 }
1356
1357 static void
1358 add_ssbo_var(struct ttn_compile *c, int binding)
1359 {
1360 nir_variable *var = c->ssbo[binding];
1361
1362 if (!var) {
1363 /* A length of 0 is used to denote unsized arrays */
1364 const struct glsl_type *type = glsl_array_type(glsl_uint_type(), 0, 0);
1365
1366 struct glsl_struct_field field = {
1367 .type = type,
1368 .name = "data",
1369 .location = -1,
1370 };
1371
1372 var = nir_variable_create(c->build.shader, nir_var_mem_ssbo, type, "ssbo");
1373 var->data.binding = binding;
1374 var->interface_type =
1375 glsl_interface_type(&field, 1, GLSL_INTERFACE_PACKING_STD430,
1376 false, "data");
1377 c->ssbo[binding] = var;
1378 }
1379 }
1380
1381 static void
1382 ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1383 {
1384 nir_builder *b = &c->build;
1385 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1386 nir_tex_instr *instr;
1387 nir_texop op;
1388 unsigned num_srcs, samp = 1, sview, i;
1389
1390 switch (tgsi_inst->Instruction.Opcode) {
1391 case TGSI_OPCODE_TEX:
1392 op = nir_texop_tex;
1393 num_srcs = 1;
1394 break;
1395 case TGSI_OPCODE_TEX2:
1396 op = nir_texop_tex;
1397 num_srcs = 1;
1398 samp = 2;
1399 break;
1400 case TGSI_OPCODE_TXP:
1401 op = nir_texop_tex;
1402 num_srcs = 2;
1403 break;
1404 case TGSI_OPCODE_TXB:
1405 op = nir_texop_txb;
1406 num_srcs = 2;
1407 break;
1408 case TGSI_OPCODE_TXB2:
1409 op = nir_texop_txb;
1410 num_srcs = 2;
1411 samp = 2;
1412 break;
1413 case TGSI_OPCODE_TXL:
1414 case TGSI_OPCODE_TEX_LZ:
1415 op = nir_texop_txl;
1416 num_srcs = 2;
1417 break;
1418 case TGSI_OPCODE_TXL2:
1419 op = nir_texop_txl;
1420 num_srcs = 2;
1421 samp = 2;
1422 break;
1423 case TGSI_OPCODE_TXF:
1424 case TGSI_OPCODE_TXF_LZ:
1425 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
1426 tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1427 op = nir_texop_txf_ms;
1428 } else {
1429 op = nir_texop_txf;
1430 }
1431 num_srcs = 2;
1432 break;
1433 case TGSI_OPCODE_TXD:
1434 op = nir_texop_txd;
1435 num_srcs = 3;
1436 samp = 3;
1437 break;
1438 case TGSI_OPCODE_LODQ:
1439 op = nir_texop_lod;
1440 num_srcs = 1;
1441 break;
1442
1443 default:
1444 fprintf(stderr, "unknown TGSI tex op %d\n", tgsi_inst->Instruction.Opcode);
1445 abort();
1446 }
1447
1448 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
1449 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1450 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
1451 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1452 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
1453 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
1454 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1455 num_srcs++;
1456 }
1457
1458 /* Deref sources */
1459 num_srcs += 2;
1460
1461 num_srcs += tgsi_inst->Texture.NumOffsets;
1462
1463 instr = nir_tex_instr_create(b->shader, num_srcs);
1464 instr->op = op;
1465
1466 get_texture_info(tgsi_inst->Texture.Texture,
1467 &instr->sampler_dim, &instr->is_shadow, &instr->is_array);
1468
1469 switch (instr->sampler_dim) {
1470 case GLSL_SAMPLER_DIM_1D:
1471 case GLSL_SAMPLER_DIM_BUF:
1472 instr->coord_components = 1;
1473 break;
1474 case GLSL_SAMPLER_DIM_2D:
1475 case GLSL_SAMPLER_DIM_RECT:
1476 case GLSL_SAMPLER_DIM_EXTERNAL:
1477 case GLSL_SAMPLER_DIM_MS:
1478 instr->coord_components = 2;
1479 break;
1480 case GLSL_SAMPLER_DIM_3D:
1481 case GLSL_SAMPLER_DIM_CUBE:
1482 instr->coord_components = 3;
1483 break;
1484 case GLSL_SAMPLER_DIM_SUBPASS:
1485 case GLSL_SAMPLER_DIM_SUBPASS_MS:
1486 unreachable("invalid sampler_dim");
1487 }
1488
1489 if (instr->is_array)
1490 instr->coord_components++;
1491
1492 assert(tgsi_inst->Src[samp].Register.File == TGSI_FILE_SAMPLER);
1493
1494 /* TODO if we supported any opc's which take an explicit SVIEW
1495 * src, we would use that here instead. But for the "legacy"
1496 * texture opc's the SVIEW index is same as SAMP index:
1497 */
1498 sview = tgsi_inst->Src[samp].Register.Index;
1499
1500 if (op == nir_texop_lod) {
1501 instr->dest_type = nir_type_float;
1502 } else if (sview < c->num_samp_types) {
1503 instr->dest_type = c->samp_types[sview];
1504 } else {
1505 instr->dest_type = nir_type_float;
1506 }
1507
1508 nir_variable *var =
1509 get_sampler_var(c, sview, instr->sampler_dim,
1510 instr->is_shadow,
1511 instr->is_array,
1512 base_type_for_alu_type(instr->dest_type),
1513 op);
1514
1515 nir_deref_instr *deref = nir_build_deref_var(b, var);
1516
1517 unsigned src_number = 0;
1518
1519 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1520 instr->src[src_number].src_type = nir_tex_src_texture_deref;
1521 src_number++;
1522 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1523 instr->src[src_number].src_type = nir_tex_src_sampler_deref;
1524 src_number++;
1525
1526 instr->src[src_number].src =
1527 nir_src_for_ssa(nir_swizzle(b, src[0], SWIZ(X, Y, Z, W),
1528 instr->coord_components));
1529 instr->src[src_number].src_type = nir_tex_src_coord;
1530 src_number++;
1531
1532 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1533 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1534 instr->src[src_number].src_type = nir_tex_src_projector;
1535 src_number++;
1536 }
1537
1538 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
1539 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1540 instr->src[src_number].src_type = nir_tex_src_bias;
1541 src_number++;
1542 }
1543
1544 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
1545 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1546 instr->src[src_number].src_type = nir_tex_src_bias;
1547 src_number++;
1548 }
1549
1550 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
1551 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ) {
1552 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ)
1553 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1554 else
1555 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1556 instr->src[src_number].src_type = nir_tex_src_lod;
1557 src_number++;
1558 }
1559
1560 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
1561 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1562 instr->src[src_number].src_type = nir_tex_src_lod;
1563 src_number++;
1564 }
1565
1566 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF ||
1567 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ) {
1568 if (op == nir_texop_txf_ms) {
1569 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1570 instr->src[src_number].src_type = nir_tex_src_ms_index;
1571 } else {
1572 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ)
1573 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1574 else
1575 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1576 instr->src[src_number].src_type = nir_tex_src_lod;
1577 }
1578 src_number++;
1579 }
1580
1581 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
1582 instr->src[src_number].src_type = nir_tex_src_ddx;
1583 instr->src[src_number].src =
1584 nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1585 nir_tex_instr_src_size(instr, src_number)));
1586 src_number++;
1587 instr->src[src_number].src_type = nir_tex_src_ddy;
1588 instr->src[src_number].src =
1589 nir_src_for_ssa(nir_swizzle(b, src[2], SWIZ(X, Y, Z, W),
1590 nir_tex_instr_src_size(instr, src_number)));
1591 src_number++;
1592 }
1593
1594 if (instr->is_shadow) {
1595 if (instr->coord_components == 4)
1596 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1597 else if (instr->coord_components == 3)
1598 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1599 else
1600 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], Z));
1601
1602 instr->src[src_number].src_type = nir_tex_src_comparator;
1603 src_number++;
1604 }
1605
1606 for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
1607 struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
1608 /* since TexOffset ins't using tgsi_full_src_register we get to
1609 * do some extra gymnastics:
1610 */
1611 nir_alu_src src;
1612
1613 memset(&src, 0, sizeof(src));
1614
1615 src.src = ttn_src_for_file_and_index(c,
1616 tex_offset->File,
1617 tex_offset->Index,
1618 NULL, NULL, NULL,
1619 true);
1620
1621 src.swizzle[0] = tex_offset->SwizzleX;
1622 src.swizzle[1] = tex_offset->SwizzleY;
1623 src.swizzle[2] = tex_offset->SwizzleZ;
1624 src.swizzle[3] = TGSI_SWIZZLE_W;
1625
1626 instr->src[src_number].src_type = nir_tex_src_offset;
1627 instr->src[src_number].src = nir_src_for_ssa(
1628 nir_mov_alu(b, src, nir_tex_instr_src_size(instr, src_number)));
1629 src_number++;
1630 }
1631
1632 assert(src_number == num_srcs);
1633 assert(src_number == instr->num_srcs);
1634
1635 nir_ssa_dest_init(&instr->instr, &instr->dest,
1636 nir_tex_instr_dest_size(instr),
1637 32, NULL);
1638 nir_builder_instr_insert(b, &instr->instr);
1639
1640 /* Resolve the writemask on the texture op. */
1641 ttn_move_dest(b, dest, &instr->dest.ssa);
1642 }
1643
1644 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1645 *
1646 * dst.x = texture\_width(unit, lod)
1647 * dst.y = texture\_height(unit, lod)
1648 * dst.z = texture\_depth(unit, lod)
1649 * dst.w = texture\_levels(unit)
1650 *
1651 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1652 */
1653 static void
1654 ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1655 {
1656 nir_builder *b = &c->build;
1657 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1658 nir_tex_instr *txs, *qlv;
1659
1660 txs = nir_tex_instr_create(b->shader, 2);
1661 txs->op = nir_texop_txs;
1662 get_texture_info(tgsi_inst->Texture.Texture,
1663 &txs->sampler_dim, &txs->is_shadow, &txs->is_array);
1664
1665 qlv = nir_tex_instr_create(b->shader, 1);
1666 qlv->op = nir_texop_query_levels;
1667 get_texture_info(tgsi_inst->Texture.Texture,
1668 &qlv->sampler_dim, &qlv->is_shadow, &qlv->is_array);
1669
1670 assert(tgsi_inst->Src[1].Register.File == TGSI_FILE_SAMPLER);
1671 int tex_index = tgsi_inst->Src[1].Register.Index;
1672
1673 nir_variable *var =
1674 get_sampler_var(c, tex_index, txs->sampler_dim,
1675 txs->is_shadow,
1676 txs->is_array,
1677 base_type_for_alu_type(txs->dest_type),
1678 nir_texop_txs);
1679
1680 nir_deref_instr *deref = nir_build_deref_var(b, var);
1681
1682 txs->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1683 txs->src[0].src_type = nir_tex_src_texture_deref;
1684
1685 qlv->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1686 qlv->src[0].src_type = nir_tex_src_texture_deref;
1687
1688 /* lod: */
1689 txs->src[1].src = nir_src_for_ssa(ttn_channel(b, src[0], X));
1690 txs->src[1].src_type = nir_tex_src_lod;
1691
1692 nir_ssa_dest_init(&txs->instr, &txs->dest,
1693 nir_tex_instr_dest_size(txs), 32, NULL);
1694 nir_builder_instr_insert(b, &txs->instr);
1695
1696 nir_ssa_dest_init(&qlv->instr, &qlv->dest, 1, 32, NULL);
1697 nir_builder_instr_insert(b, &qlv->instr);
1698
1699 ttn_move_dest_masked(b, dest, &txs->dest.ssa, TGSI_WRITEMASK_XYZ);
1700 ttn_move_dest_masked(b, dest, &qlv->dest.ssa, TGSI_WRITEMASK_W);
1701 }
1702
1703 static enum glsl_base_type
1704 get_image_base_type(struct tgsi_full_instruction *tgsi_inst)
1705 {
1706 const struct util_format_description *desc =
1707 util_format_description(tgsi_inst->Memory.Format);
1708
1709 if (desc->channel[0].pure_integer) {
1710 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED)
1711 return GLSL_TYPE_INT;
1712 else
1713 return GLSL_TYPE_UINT;
1714 }
1715 return GLSL_TYPE_FLOAT;
1716 }
1717
1718 static enum gl_access_qualifier
1719 get_mem_qualifier(struct tgsi_full_instruction *tgsi_inst)
1720 {
1721 enum gl_access_qualifier access = 0;
1722
1723 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_COHERENT)
1724 access |= ACCESS_COHERENT;
1725 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT)
1726 access |= ACCESS_RESTRICT;
1727 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
1728 access |= ACCESS_VOLATILE;
1729 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
1730 access |= ACCESS_STREAM_CACHE_POLICY;
1731
1732 return access;
1733 }
1734
1735 static GLenum
1736 get_image_format(struct tgsi_full_instruction *tgsi_inst)
1737 {
1738 switch (tgsi_inst->Memory.Format) {
1739 case PIPE_FORMAT_R8_UNORM:
1740 return GL_R8;
1741 case PIPE_FORMAT_R8G8_UNORM:
1742 return GL_RG8;
1743 case PIPE_FORMAT_R8G8B8A8_UNORM:
1744 return GL_RGBA8;
1745 case PIPE_FORMAT_R16_UNORM:
1746 return GL_R16;
1747 case PIPE_FORMAT_R16G16_UNORM:
1748 return GL_RG16;
1749 case PIPE_FORMAT_R16G16B16A16_UNORM:
1750 return GL_RGBA16;
1751
1752 case PIPE_FORMAT_R8_SNORM:
1753 return GL_R8_SNORM;
1754 case PIPE_FORMAT_R8G8_SNORM:
1755 return GL_RG8_SNORM;
1756 case PIPE_FORMAT_R8G8B8A8_SNORM:
1757 return GL_RGBA8_SNORM;
1758 case PIPE_FORMAT_R16_SNORM:
1759 return GL_R16_SNORM;
1760 case PIPE_FORMAT_R16G16_SNORM:
1761 return GL_RG16_SNORM;
1762 case PIPE_FORMAT_R16G16B16A16_SNORM:
1763 return GL_RGBA16_SNORM;
1764
1765 case PIPE_FORMAT_R8_UINT:
1766 return GL_R8UI;
1767 case PIPE_FORMAT_R8G8_UINT:
1768 return GL_RG8UI;
1769 case PIPE_FORMAT_R8G8B8A8_UINT:
1770 return GL_RGBA8UI;
1771 case PIPE_FORMAT_R16_UINT:
1772 return GL_R16UI;
1773 case PIPE_FORMAT_R16G16_UINT:
1774 return GL_RG16UI;
1775 case PIPE_FORMAT_R16G16B16A16_UINT:
1776 return GL_RGBA16UI;
1777 case PIPE_FORMAT_R32_UINT:
1778 return GL_R32UI;
1779 case PIPE_FORMAT_R32G32_UINT:
1780 return GL_RG32UI;
1781 case PIPE_FORMAT_R32G32B32A32_UINT:
1782 return GL_RGBA32UI;
1783
1784 case PIPE_FORMAT_R8_SINT:
1785 return GL_R8I;
1786 case PIPE_FORMAT_R8G8_SINT:
1787 return GL_RG8I;
1788 case PIPE_FORMAT_R8G8B8A8_SINT:
1789 return GL_RGBA8I;
1790 case PIPE_FORMAT_R16_SINT:
1791 return GL_R16I;
1792 case PIPE_FORMAT_R16G16_SINT:
1793 return GL_RG16I;
1794 case PIPE_FORMAT_R16G16B16A16_SINT:
1795 return GL_RGBA16I;
1796 case PIPE_FORMAT_R32_SINT:
1797 return GL_R32I;
1798 case PIPE_FORMAT_R32G32_SINT:
1799 return GL_RG32I;
1800 case PIPE_FORMAT_R32G32B32A32_SINT:
1801 return GL_RGBA32I;
1802
1803 case PIPE_FORMAT_R16_FLOAT:
1804 return GL_R16F;
1805 case PIPE_FORMAT_R16G16_FLOAT:
1806 return GL_RG16F;
1807 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1808 return GL_RGBA16F;
1809 case PIPE_FORMAT_R32_FLOAT:
1810 return GL_R32F;
1811 case PIPE_FORMAT_R32G32_FLOAT:
1812 return GL_RG32F;
1813 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1814 return GL_RGBA32F;
1815
1816 case PIPE_FORMAT_R11G11B10_FLOAT:
1817 return GL_R11F_G11F_B10F;
1818 case PIPE_FORMAT_R10G10B10A2_UINT:
1819 return GL_RGB10_A2UI;
1820 case PIPE_FORMAT_R10G10B10A2_UNORM:
1821 return GL_RGB10_A2;
1822
1823 default:
1824 unreachable("unhandled image format");
1825 }
1826 }
1827
1828 static void
1829 ttn_mem(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1830 {
1831 nir_builder *b = &c->build;
1832 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1833 nir_intrinsic_instr *instr = NULL;
1834 unsigned resource_index, addr_src_index, file;
1835
1836 switch (tgsi_inst->Instruction.Opcode) {
1837 case TGSI_OPCODE_LOAD:
1838 assert(!tgsi_inst->Src[0].Register.Indirect);
1839 resource_index = tgsi_inst->Src[0].Register.Index;
1840 file = tgsi_inst->Src[0].Register.File;
1841 addr_src_index = 1;
1842 break;
1843 case TGSI_OPCODE_STORE:
1844 assert(!tgsi_inst->Dst[0].Register.Indirect);
1845 resource_index = tgsi_inst->Dst[0].Register.Index;
1846 file = tgsi_inst->Dst[0].Register.File;
1847 addr_src_index = 0;
1848 break;
1849 default:
1850 unreachable("unexpected memory opcode");
1851 }
1852
1853 if (file == TGSI_FILE_BUFFER) {
1854 nir_intrinsic_op op;
1855
1856 switch (tgsi_inst->Instruction.Opcode) {
1857 case TGSI_OPCODE_LOAD:
1858 op = nir_intrinsic_load_ssbo;
1859 break;
1860 case TGSI_OPCODE_STORE:
1861 op = nir_intrinsic_store_ssbo;
1862 break;
1863 }
1864
1865 add_ssbo_var(c, resource_index);
1866
1867 instr = nir_intrinsic_instr_create(b->shader, op);
1868 instr->num_components = util_last_bit(tgsi_inst->Dst[0].Register.WriteMask);
1869 nir_intrinsic_set_access(instr, get_mem_qualifier(tgsi_inst));
1870 nir_intrinsic_set_align(instr, 4, 0);
1871
1872 unsigned i = 0;
1873 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1874 instr->src[i++] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1875 instr->num_components));
1876 instr->src[i++] = nir_src_for_ssa(nir_imm_int(b, resource_index));
1877 instr->src[i++] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], X));
1878
1879 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1880 nir_intrinsic_set_write_mask(instr, tgsi_inst->Dst[0].Register.WriteMask);
1881
1882 } else if (file == TGSI_FILE_IMAGE) {
1883 nir_intrinsic_op op;
1884
1885 switch (tgsi_inst->Instruction.Opcode) {
1886 case TGSI_OPCODE_LOAD:
1887 op = nir_intrinsic_image_deref_load;
1888 break;
1889 case TGSI_OPCODE_STORE:
1890 op = nir_intrinsic_image_deref_store;
1891 break;
1892 }
1893
1894 instr = nir_intrinsic_instr_create(b->shader, op);
1895
1896 /* Set the image variable dereference. */
1897 enum glsl_sampler_dim dim;
1898 bool is_array;
1899 get_texture_info(tgsi_inst->Memory.Texture, &dim, NULL, &is_array);
1900
1901 enum glsl_base_type base_type = get_image_base_type(tgsi_inst);
1902 enum gl_access_qualifier access = get_mem_qualifier(tgsi_inst);
1903 GLenum format = get_image_format(tgsi_inst);
1904
1905 nir_variable *image =
1906 get_image_var(c, resource_index,
1907 dim, is_array, base_type, access, format);
1908 nir_deref_instr *image_deref = nir_build_deref_var(b, image);
1909 const struct glsl_type *type = image_deref->type;
1910
1911 nir_intrinsic_set_access(instr, image_deref->var->data.image.access);
1912
1913 instr->src[0] = nir_src_for_ssa(&image_deref->dest.ssa);
1914 instr->src[1] = nir_src_for_ssa(src[addr_src_index]);
1915
1916 /* Set the sample argument, which is undefined for single-sample images. */
1917 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_MS) {
1918 instr->src[2] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], W));
1919 } else {
1920 instr->src[2] = nir_src_for_ssa(nir_ssa_undef(b, 1, 32));
1921 }
1922
1923 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
1924 instr->src[3] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W), 4));
1925 }
1926
1927 instr->num_components = 4;
1928 } else {
1929 unreachable("unexpected file");
1930 }
1931
1932
1933 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
1934 nir_ssa_dest_init(&instr->instr, &instr->dest,
1935 util_last_bit(tgsi_inst->Dst[0].Register.WriteMask),
1936 32, NULL);
1937 nir_builder_instr_insert(b, &instr->instr);
1938 ttn_move_dest(b, dest, &instr->dest.ssa);
1939 } else {
1940 nir_builder_instr_insert(b, &instr->instr);
1941 }
1942 }
1943
1944 static const nir_op op_trans[TGSI_OPCODE_LAST] = {
1945 [TGSI_OPCODE_ARL] = 0,
1946 [TGSI_OPCODE_MOV] = nir_op_mov,
1947 [TGSI_OPCODE_LIT] = 0,
1948 [TGSI_OPCODE_RCP] = nir_op_frcp,
1949 [TGSI_OPCODE_RSQ] = nir_op_frsq,
1950 [TGSI_OPCODE_EXP] = 0,
1951 [TGSI_OPCODE_LOG] = 0,
1952 [TGSI_OPCODE_MUL] = nir_op_fmul,
1953 [TGSI_OPCODE_ADD] = nir_op_fadd,
1954 [TGSI_OPCODE_DP3] = 0,
1955 [TGSI_OPCODE_DP4] = 0,
1956 [TGSI_OPCODE_DST] = 0,
1957 [TGSI_OPCODE_MIN] = nir_op_fmin,
1958 [TGSI_OPCODE_MAX] = nir_op_fmax,
1959 [TGSI_OPCODE_SLT] = nir_op_slt,
1960 [TGSI_OPCODE_SGE] = nir_op_sge,
1961 [TGSI_OPCODE_MAD] = nir_op_ffma,
1962 [TGSI_OPCODE_TEX_LZ] = 0,
1963 [TGSI_OPCODE_LRP] = 0,
1964 [TGSI_OPCODE_SQRT] = nir_op_fsqrt,
1965 [TGSI_OPCODE_FRC] = nir_op_ffract,
1966 [TGSI_OPCODE_TXF_LZ] = 0,
1967 [TGSI_OPCODE_FLR] = nir_op_ffloor,
1968 [TGSI_OPCODE_ROUND] = nir_op_fround_even,
1969 [TGSI_OPCODE_EX2] = nir_op_fexp2,
1970 [TGSI_OPCODE_LG2] = nir_op_flog2,
1971 [TGSI_OPCODE_POW] = nir_op_fpow,
1972 [TGSI_OPCODE_COS] = nir_op_fcos,
1973 [TGSI_OPCODE_DDX] = nir_op_fddx,
1974 [TGSI_OPCODE_DDY] = nir_op_fddy,
1975 [TGSI_OPCODE_KILL] = 0,
1976 [TGSI_OPCODE_PK2H] = 0, /* XXX */
1977 [TGSI_OPCODE_PK2US] = 0, /* XXX */
1978 [TGSI_OPCODE_PK4B] = 0, /* XXX */
1979 [TGSI_OPCODE_PK4UB] = 0, /* XXX */
1980 [TGSI_OPCODE_SEQ] = nir_op_seq,
1981 [TGSI_OPCODE_SGT] = 0,
1982 [TGSI_OPCODE_SIN] = nir_op_fsin,
1983 [TGSI_OPCODE_SNE] = nir_op_sne,
1984 [TGSI_OPCODE_SLE] = 0,
1985 [TGSI_OPCODE_TEX] = 0,
1986 [TGSI_OPCODE_TXD] = 0,
1987 [TGSI_OPCODE_TXP] = 0,
1988 [TGSI_OPCODE_UP2H] = 0, /* XXX */
1989 [TGSI_OPCODE_UP2US] = 0, /* XXX */
1990 [TGSI_OPCODE_UP4B] = 0, /* XXX */
1991 [TGSI_OPCODE_UP4UB] = 0, /* XXX */
1992 [TGSI_OPCODE_ARR] = 0,
1993
1994 /* No function calls, yet. */
1995 [TGSI_OPCODE_CAL] = 0, /* XXX */
1996 [TGSI_OPCODE_RET] = 0, /* XXX */
1997
1998 [TGSI_OPCODE_SSG] = nir_op_fsign,
1999 [TGSI_OPCODE_CMP] = 0,
2000 [TGSI_OPCODE_TXB] = 0,
2001 [TGSI_OPCODE_DIV] = nir_op_fdiv,
2002 [TGSI_OPCODE_DP2] = 0,
2003 [TGSI_OPCODE_TXL] = 0,
2004
2005 [TGSI_OPCODE_BRK] = 0,
2006 [TGSI_OPCODE_IF] = 0,
2007 [TGSI_OPCODE_UIF] = 0,
2008 [TGSI_OPCODE_ELSE] = 0,
2009 [TGSI_OPCODE_ENDIF] = 0,
2010
2011 [TGSI_OPCODE_DDX_FINE] = nir_op_fddx_fine,
2012 [TGSI_OPCODE_DDY_FINE] = nir_op_fddy_fine,
2013
2014 [TGSI_OPCODE_CEIL] = nir_op_fceil,
2015 [TGSI_OPCODE_I2F] = nir_op_i2f32,
2016 [TGSI_OPCODE_NOT] = nir_op_inot,
2017 [TGSI_OPCODE_TRUNC] = nir_op_ftrunc,
2018 [TGSI_OPCODE_SHL] = nir_op_ishl,
2019 [TGSI_OPCODE_AND] = nir_op_iand,
2020 [TGSI_OPCODE_OR] = nir_op_ior,
2021 [TGSI_OPCODE_MOD] = nir_op_umod,
2022 [TGSI_OPCODE_XOR] = nir_op_ixor,
2023 [TGSI_OPCODE_TXF] = 0,
2024 [TGSI_OPCODE_TXQ] = 0,
2025
2026 [TGSI_OPCODE_CONT] = 0,
2027
2028 [TGSI_OPCODE_EMIT] = 0, /* XXX */
2029 [TGSI_OPCODE_ENDPRIM] = 0, /* XXX */
2030
2031 [TGSI_OPCODE_BGNLOOP] = 0,
2032 [TGSI_OPCODE_BGNSUB] = 0, /* XXX: no function calls */
2033 [TGSI_OPCODE_ENDLOOP] = 0,
2034 [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */
2035
2036 [TGSI_OPCODE_NOP] = 0,
2037 [TGSI_OPCODE_FSEQ] = nir_op_feq,
2038 [TGSI_OPCODE_FSGE] = nir_op_fge,
2039 [TGSI_OPCODE_FSLT] = nir_op_flt,
2040 [TGSI_OPCODE_FSNE] = nir_op_fne,
2041
2042 [TGSI_OPCODE_KILL_IF] = 0,
2043
2044 [TGSI_OPCODE_END] = 0,
2045
2046 [TGSI_OPCODE_F2I] = nir_op_f2i32,
2047 [TGSI_OPCODE_IDIV] = nir_op_idiv,
2048 [TGSI_OPCODE_IMAX] = nir_op_imax,
2049 [TGSI_OPCODE_IMIN] = nir_op_imin,
2050 [TGSI_OPCODE_INEG] = nir_op_ineg,
2051 [TGSI_OPCODE_ISGE] = nir_op_ige,
2052 [TGSI_OPCODE_ISHR] = nir_op_ishr,
2053 [TGSI_OPCODE_ISLT] = nir_op_ilt,
2054 [TGSI_OPCODE_F2U] = nir_op_f2u32,
2055 [TGSI_OPCODE_U2F] = nir_op_u2f32,
2056 [TGSI_OPCODE_UADD] = nir_op_iadd,
2057 [TGSI_OPCODE_UDIV] = nir_op_udiv,
2058 [TGSI_OPCODE_UMAD] = 0,
2059 [TGSI_OPCODE_UMAX] = nir_op_umax,
2060 [TGSI_OPCODE_UMIN] = nir_op_umin,
2061 [TGSI_OPCODE_UMOD] = nir_op_umod,
2062 [TGSI_OPCODE_UMUL] = nir_op_imul,
2063 [TGSI_OPCODE_USEQ] = nir_op_ieq,
2064 [TGSI_OPCODE_USGE] = nir_op_uge,
2065 [TGSI_OPCODE_USHR] = nir_op_ushr,
2066 [TGSI_OPCODE_USLT] = nir_op_ult,
2067 [TGSI_OPCODE_USNE] = nir_op_ine,
2068
2069 [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
2070 [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */
2071 [TGSI_OPCODE_DEFAULT] = 0, /* not emitted by glsl_to_tgsi.cpp */
2072 [TGSI_OPCODE_ENDSWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
2073
2074 /* XXX: SAMPLE opcodes */
2075
2076 [TGSI_OPCODE_UARL] = nir_op_mov,
2077 [TGSI_OPCODE_UCMP] = 0,
2078 [TGSI_OPCODE_IABS] = nir_op_iabs,
2079 [TGSI_OPCODE_ISSG] = nir_op_isign,
2080
2081 [TGSI_OPCODE_LOAD] = 0,
2082 [TGSI_OPCODE_STORE] = 0,
2083
2084 /* XXX: atomics */
2085
2086 [TGSI_OPCODE_TEX2] = 0,
2087 [TGSI_OPCODE_TXB2] = 0,
2088 [TGSI_OPCODE_TXL2] = 0,
2089
2090 [TGSI_OPCODE_IMUL_HI] = nir_op_imul_high,
2091 [TGSI_OPCODE_UMUL_HI] = nir_op_umul_high,
2092
2093 [TGSI_OPCODE_TG4] = 0,
2094 [TGSI_OPCODE_LODQ] = 0,
2095
2096 [TGSI_OPCODE_IBFE] = nir_op_ibitfield_extract,
2097 [TGSI_OPCODE_UBFE] = nir_op_ubitfield_extract,
2098 [TGSI_OPCODE_BFI] = nir_op_bitfield_insert,
2099 [TGSI_OPCODE_BREV] = nir_op_bitfield_reverse,
2100 [TGSI_OPCODE_POPC] = nir_op_bit_count,
2101 [TGSI_OPCODE_LSB] = nir_op_find_lsb,
2102 [TGSI_OPCODE_IMSB] = nir_op_ifind_msb,
2103 [TGSI_OPCODE_UMSB] = nir_op_ufind_msb,
2104
2105 [TGSI_OPCODE_INTERP_CENTROID] = 0, /* XXX */
2106 [TGSI_OPCODE_INTERP_SAMPLE] = 0, /* XXX */
2107 [TGSI_OPCODE_INTERP_OFFSET] = 0, /* XXX */
2108
2109 [TGSI_OPCODE_F2D] = nir_op_f2f64,
2110 [TGSI_OPCODE_D2F] = nir_op_f2f32,
2111 [TGSI_OPCODE_DMUL] = nir_op_fmul,
2112 [TGSI_OPCODE_D2U] = nir_op_f2u32,
2113 [TGSI_OPCODE_U2D] = nir_op_u2f64,
2114
2115 [TGSI_OPCODE_U64ADD] = nir_op_iadd,
2116 [TGSI_OPCODE_U64MUL] = nir_op_imul,
2117 [TGSI_OPCODE_U64DIV] = nir_op_udiv,
2118 [TGSI_OPCODE_U64SNE] = nir_op_ine,
2119 };
2120
2121 static void
2122 ttn_emit_instruction(struct ttn_compile *c)
2123 {
2124 nir_builder *b = &c->build;
2125 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
2126 unsigned i;
2127 unsigned tgsi_op = tgsi_inst->Instruction.Opcode;
2128 struct tgsi_full_dst_register *tgsi_dst = &tgsi_inst->Dst[0];
2129
2130 if (tgsi_op == TGSI_OPCODE_END)
2131 return;
2132
2133 nir_ssa_def *src[TGSI_FULL_MAX_SRC_REGISTERS];
2134 for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
2135 src[i] = ttn_get_src(c, &tgsi_inst->Src[i], i);
2136 }
2137 nir_alu_dest dest = ttn_get_dest(c, tgsi_dst);
2138
2139 unsigned tgsi_dst_type = tgsi_opcode_infer_dst_type(tgsi_op, 0);
2140
2141 /* The destination bitsize of the NIR opcode (not TGSI, where it's always
2142 * 32 bits). This needs to be passed into ttn_alu() because it can't be
2143 * inferred for comparison opcodes.
2144 */
2145 unsigned dst_bitsize = tgsi_type_is_64bit(tgsi_dst_type) ? 64 : 32;
2146
2147 switch (tgsi_op) {
2148 case TGSI_OPCODE_RSQ:
2149 ttn_move_dest(b, dest, nir_frsq(b, ttn_channel(b, src[0], X)));
2150 break;
2151
2152 case TGSI_OPCODE_SQRT:
2153 ttn_move_dest(b, dest, nir_fsqrt(b, ttn_channel(b, src[0], X)));
2154 break;
2155
2156 case TGSI_OPCODE_RCP:
2157 ttn_move_dest(b, dest, nir_frcp(b, ttn_channel(b, src[0], X)));
2158 break;
2159
2160 case TGSI_OPCODE_EX2:
2161 ttn_move_dest(b, dest, nir_fexp2(b, ttn_channel(b, src[0], X)));
2162 break;
2163
2164 case TGSI_OPCODE_LG2:
2165 ttn_move_dest(b, dest, nir_flog2(b, ttn_channel(b, src[0], X)));
2166 break;
2167
2168 case TGSI_OPCODE_POW:
2169 ttn_move_dest(b, dest, nir_fpow(b,
2170 ttn_channel(b, src[0], X),
2171 ttn_channel(b, src[1], X)));
2172 break;
2173
2174 case TGSI_OPCODE_COS:
2175 ttn_move_dest(b, dest, nir_fcos(b, ttn_channel(b, src[0], X)));
2176 break;
2177
2178 case TGSI_OPCODE_SIN:
2179 ttn_move_dest(b, dest, nir_fsin(b, ttn_channel(b, src[0], X)));
2180 break;
2181
2182 case TGSI_OPCODE_ARL:
2183 ttn_arl(b, op_trans[tgsi_op], dest, src);
2184 break;
2185
2186 case TGSI_OPCODE_EXP:
2187 ttn_exp(b, op_trans[tgsi_op], dest, src);
2188 break;
2189
2190 case TGSI_OPCODE_LOG:
2191 ttn_log(b, op_trans[tgsi_op], dest, src);
2192 break;
2193
2194 case TGSI_OPCODE_DST:
2195 ttn_dst(b, op_trans[tgsi_op], dest, src);
2196 break;
2197
2198 case TGSI_OPCODE_LIT:
2199 ttn_lit(b, op_trans[tgsi_op], dest, src);
2200 break;
2201
2202 case TGSI_OPCODE_DP2:
2203 ttn_dp2(b, op_trans[tgsi_op], dest, src);
2204 break;
2205
2206 case TGSI_OPCODE_DP3:
2207 ttn_dp3(b, op_trans[tgsi_op], dest, src);
2208 break;
2209
2210 case TGSI_OPCODE_DP4:
2211 ttn_dp4(b, op_trans[tgsi_op], dest, src);
2212 break;
2213
2214 case TGSI_OPCODE_UMAD:
2215 ttn_umad(b, op_trans[tgsi_op], dest, src);
2216 break;
2217
2218 case TGSI_OPCODE_LRP:
2219 ttn_move_dest(b, dest, nir_flrp(b, src[2], src[1], src[0]));
2220 break;
2221
2222 case TGSI_OPCODE_KILL:
2223 ttn_kill(b, op_trans[tgsi_op], dest, src);
2224 break;
2225
2226 case TGSI_OPCODE_ARR:
2227 ttn_arr(b, op_trans[tgsi_op], dest, src);
2228 break;
2229
2230 case TGSI_OPCODE_CMP:
2231 ttn_cmp(b, op_trans[tgsi_op], dest, src);
2232 break;
2233
2234 case TGSI_OPCODE_UCMP:
2235 ttn_ucmp(b, op_trans[tgsi_op], dest, src);
2236 break;
2237
2238 case TGSI_OPCODE_SGT:
2239 ttn_sgt(b, op_trans[tgsi_op], dest, src);
2240 break;
2241
2242 case TGSI_OPCODE_SLE:
2243 ttn_sle(b, op_trans[tgsi_op], dest, src);
2244 break;
2245
2246 case TGSI_OPCODE_KILL_IF:
2247 ttn_kill_if(b, op_trans[tgsi_op], dest, src);
2248 break;
2249
2250 case TGSI_OPCODE_TEX:
2251 case TGSI_OPCODE_TEX_LZ:
2252 case TGSI_OPCODE_TXP:
2253 case TGSI_OPCODE_TXL:
2254 case TGSI_OPCODE_TXB:
2255 case TGSI_OPCODE_TXD:
2256 case TGSI_OPCODE_TEX2:
2257 case TGSI_OPCODE_TXL2:
2258 case TGSI_OPCODE_TXB2:
2259 case TGSI_OPCODE_TXF:
2260 case TGSI_OPCODE_TXF_LZ:
2261 case TGSI_OPCODE_TG4:
2262 case TGSI_OPCODE_LODQ:
2263 ttn_tex(c, dest, src);
2264 break;
2265
2266 case TGSI_OPCODE_TXQ:
2267 ttn_txq(c, dest, src);
2268 break;
2269
2270 case TGSI_OPCODE_LOAD:
2271 case TGSI_OPCODE_STORE:
2272 ttn_mem(c, dest, src);
2273 break;
2274
2275 case TGSI_OPCODE_NOP:
2276 break;
2277
2278 case TGSI_OPCODE_IF:
2279 ttn_if(c, src[0], false);
2280 break;
2281
2282 case TGSI_OPCODE_UIF:
2283 ttn_if(c, src[0], true);
2284 break;
2285
2286 case TGSI_OPCODE_ELSE:
2287 ttn_else(c);
2288 break;
2289
2290 case TGSI_OPCODE_ENDIF:
2291 ttn_endif(c);
2292 break;
2293
2294 case TGSI_OPCODE_BGNLOOP:
2295 ttn_bgnloop(c);
2296 break;
2297
2298 case TGSI_OPCODE_BRK:
2299 ttn_brk(b);
2300 break;
2301
2302 case TGSI_OPCODE_CONT:
2303 ttn_cont(b);
2304 break;
2305
2306 case TGSI_OPCODE_ENDLOOP:
2307 ttn_endloop(c);
2308 break;
2309
2310 default:
2311 if (op_trans[tgsi_op] != 0 || tgsi_op == TGSI_OPCODE_MOV) {
2312 ttn_alu(b, op_trans[tgsi_op], dest, dst_bitsize, src);
2313 } else {
2314 fprintf(stderr, "unknown TGSI opcode: %s\n",
2315 tgsi_get_opcode_name(tgsi_op));
2316 abort();
2317 }
2318 break;
2319 }
2320
2321 if (tgsi_inst->Instruction.Saturate) {
2322 assert(!dest.dest.is_ssa);
2323 ttn_move_dest(b, dest, nir_fsat(b, ttn_src_for_dest(b, &dest)));
2324 }
2325
2326 /* if the dst has a matching var, append store_var to move
2327 * output from reg to var
2328 */
2329 nir_variable *var = ttn_get_var(c, tgsi_dst);
2330 if (var) {
2331 unsigned index = tgsi_dst->Register.Index;
2332 unsigned offset = c->temp_regs[index].offset;
2333 struct tgsi_ind_register *indirect = tgsi_dst->Register.Indirect ?
2334 &tgsi_dst->Indirect : NULL;
2335 nir_src val = nir_src_for_reg(dest.dest.reg.reg);
2336 nir_store_deref(b, ttn_array_deref(c, var, offset, indirect),
2337 nir_ssa_for_src(b, val, 4), dest.write_mask);
2338 }
2339 }
2340
2341 /**
2342 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
2343 * variables at the end of the shader.
2344 *
2345 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
2346 * written, because there's no output load intrinsic, which means we couldn't
2347 * handle writemasks.
2348 */
2349 static void
2350 ttn_add_output_stores(struct ttn_compile *c)
2351 {
2352 nir_builder *b = &c->build;
2353
2354 for (int i = 0; i < c->build.shader->num_outputs; i++) {
2355 nir_variable *var = c->outputs[i];
2356 if (!var)
2357 continue;
2358
2359 nir_src src = nir_src_for_reg(c->output_regs[i].reg);
2360 src.reg.base_offset = c->output_regs[i].offset;
2361
2362 nir_ssa_def *store_value = nir_ssa_for_src(b, src, 4);
2363 if (c->build.shader->info.stage == MESA_SHADER_FRAGMENT) {
2364 /* TGSI uses TGSI_SEMANTIC_POSITION.z for the depth output
2365 * and TGSI_SEMANTIC_STENCIL.y for the stencil output,
2366 * while NIR uses a single-component output.
2367 */
2368 if (var->data.location == FRAG_RESULT_DEPTH)
2369 store_value = nir_channel(b, store_value, 2);
2370 else if (var->data.location == FRAG_RESULT_STENCIL)
2371 store_value = nir_channel(b, store_value, 1);
2372 }
2373
2374 nir_store_deref(b, nir_build_deref_var(b, var), store_value,
2375 (1 << store_value->num_components) - 1);
2376 }
2377 }
2378
2379 /**
2380 * Parses the given TGSI tokens.
2381 */
2382 static void
2383 ttn_parse_tgsi(struct ttn_compile *c, const void *tgsi_tokens)
2384 {
2385 struct tgsi_parse_context parser;
2386 int ret;
2387
2388 ret = tgsi_parse_init(&parser, tgsi_tokens);
2389 assert(ret == TGSI_PARSE_OK);
2390
2391 while (!tgsi_parse_end_of_tokens(&parser)) {
2392 tgsi_parse_token(&parser);
2393 c->token = &parser.FullToken;
2394
2395 switch (parser.FullToken.Token.Type) {
2396 case TGSI_TOKEN_TYPE_DECLARATION:
2397 ttn_emit_declaration(c);
2398 break;
2399
2400 case TGSI_TOKEN_TYPE_INSTRUCTION:
2401 ttn_emit_instruction(c);
2402 break;
2403
2404 case TGSI_TOKEN_TYPE_IMMEDIATE:
2405 ttn_emit_immediate(c);
2406 break;
2407 }
2408 }
2409
2410 tgsi_parse_free(&parser);
2411 }
2412
2413 static void
2414 ttn_read_pipe_caps(struct ttn_compile *c,
2415 struct pipe_screen *screen)
2416 {
2417 c->cap_scalar = screen->get_shader_param(screen, c->scan->processor, PIPE_SHADER_CAP_SCALAR_ISA);
2418 c->cap_packed_uniforms = screen->get_param(screen, PIPE_CAP_PACKED_UNIFORMS);
2419 c->cap_samplers_as_deref = screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF);
2420 c->cap_face_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
2421 c->cap_position_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL);
2422 c->cap_point_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL);
2423 }
2424
2425 /**
2426 * Initializes a TGSI-to-NIR compiler.
2427 */
2428 static struct ttn_compile *
2429 ttn_compile_init(const void *tgsi_tokens,
2430 const nir_shader_compiler_options *options,
2431 struct pipe_screen *screen)
2432 {
2433 struct ttn_compile *c;
2434 struct nir_shader *s;
2435 struct tgsi_shader_info scan;
2436
2437 assert(options || screen);
2438 c = rzalloc(NULL, struct ttn_compile);
2439
2440 tgsi_scan_shader(tgsi_tokens, &scan);
2441 c->scan = &scan;
2442
2443 if (!options) {
2444 options =
2445 screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR, scan.processor);
2446 }
2447
2448 nir_builder_init_simple_shader(&c->build, NULL,
2449 tgsi_processor_to_shader_stage(scan.processor),
2450 options);
2451
2452 s = c->build.shader;
2453
2454 if (screen) {
2455 ttn_read_pipe_caps(c, screen);
2456 } else {
2457 /* TTN used to be hard coded to always make FACE a sysval,
2458 * so it makes sense to preserve that behavior so users don't break. */
2459 c->cap_face_is_sysval = true;
2460 }
2461
2462 if (s->info.stage == MESA_SHADER_FRAGMENT)
2463 s->info.fs.untyped_color_outputs = true;
2464
2465 s->num_inputs = scan.file_max[TGSI_FILE_INPUT] + 1;
2466 s->num_uniforms = scan.const_file_max[0] + 1;
2467 s->num_outputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
2468 s->info.num_ssbos = util_last_bit(scan.shader_buffers_declared);
2469 s->info.num_ubos = util_last_bit(scan.const_buffers_declared >> 1);
2470 s->info.num_images = util_last_bit(scan.images_declared);
2471 s->info.num_textures = util_last_bit(scan.samplers_declared);
2472
2473 for (unsigned i = 0; i < TGSI_PROPERTY_COUNT; i++) {
2474 unsigned value = scan.properties[i];
2475
2476 switch (i) {
2477 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
2478 break; /* handled in ttn_emit_declaration */
2479 case TGSI_PROPERTY_FS_COORD_ORIGIN:
2480 if (s->info.stage == MESA_SHADER_FRAGMENT)
2481 s->info.fs.origin_upper_left = value == TGSI_FS_COORD_ORIGIN_UPPER_LEFT;
2482 break;
2483 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
2484 if (s->info.stage == MESA_SHADER_FRAGMENT)
2485 s->info.fs.pixel_center_integer = value == TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
2486 break;
2487 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
2488 if (s->info.stage == MESA_SHADER_FRAGMENT)
2489 s->info.fs.depth_layout = ttn_get_depth_layout(value);
2490 break;
2491 case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION:
2492 if (s->info.stage == MESA_SHADER_VERTEX)
2493 s->info.vs.window_space_position = value;
2494 break;
2495 case TGSI_PROPERTY_NEXT_SHADER:
2496 s->info.next_stage = tgsi_processor_to_shader_stage(value);
2497 break;
2498 case TGSI_PROPERTY_VS_BLIT_SGPRS_AMD:
2499 if (s->info.stage == MESA_SHADER_VERTEX)
2500 s->info.vs.blit_sgprs_amd = value;
2501 break;
2502 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
2503 if (s->info.stage == MESA_SHADER_COMPUTE)
2504 s->info.cs.local_size[0] = value;
2505 break;
2506 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
2507 if (s->info.stage == MESA_SHADER_COMPUTE)
2508 s->info.cs.local_size[1] = value;
2509 break;
2510 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
2511 if (s->info.stage == MESA_SHADER_COMPUTE)
2512 s->info.cs.local_size[2] = value;
2513 break;
2514 case TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD:
2515 if (s->info.stage == MESA_SHADER_COMPUTE)
2516 s->info.cs.user_data_components_amd = value;
2517 break;
2518 default:
2519 if (value) {
2520 fprintf(stderr, "tgsi_to_nir: unhandled TGSI property %u = %u\n",
2521 i, value);
2522 unreachable("unhandled TGSI property");
2523 }
2524 }
2525 }
2526
2527 if (s->info.stage == MESA_SHADER_COMPUTE &&
2528 (!s->info.cs.local_size[0] ||
2529 !s->info.cs.local_size[1] ||
2530 !s->info.cs.local_size[2]))
2531 s->info.cs.local_size_variable = true;
2532
2533 c->inputs = rzalloc_array(c, struct nir_variable *, s->num_inputs);
2534 c->outputs = rzalloc_array(c, struct nir_variable *, s->num_outputs);
2535
2536 c->output_regs = rzalloc_array(c, struct ttn_reg_info,
2537 scan.file_max[TGSI_FILE_OUTPUT] + 1);
2538 c->temp_regs = rzalloc_array(c, struct ttn_reg_info,
2539 scan.file_max[TGSI_FILE_TEMPORARY] + 1);
2540 c->imm_defs = rzalloc_array(c, nir_ssa_def *,
2541 scan.file_max[TGSI_FILE_IMMEDIATE] + 1);
2542
2543 c->num_samp_types = scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1;
2544 c->samp_types = rzalloc_array(c, nir_alu_type, c->num_samp_types);
2545
2546 c->if_stack = rzalloc_array(c, nir_cursor,
2547 (scan.opcode_count[TGSI_OPCODE_IF] +
2548 scan.opcode_count[TGSI_OPCODE_UIF]) * 2);
2549 c->loop_stack = rzalloc_array(c, nir_cursor,
2550 scan.opcode_count[TGSI_OPCODE_BGNLOOP]);
2551
2552
2553 ttn_parse_tgsi(c, tgsi_tokens);
2554 ttn_add_output_stores(c);
2555
2556 nir_validate_shader(c->build.shader, "TTN: after parsing TGSI and creating the NIR shader");
2557
2558 return c;
2559 }
2560
2561 static void
2562 ttn_optimize_nir(nir_shader *nir, bool scalar)
2563 {
2564 bool progress;
2565 do {
2566 progress = false;
2567
2568 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2569
2570 if (scalar) {
2571 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
2572 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
2573 }
2574
2575 NIR_PASS_V(nir, nir_lower_alu);
2576 NIR_PASS_V(nir, nir_lower_pack);
2577 NIR_PASS(progress, nir, nir_copy_prop);
2578 NIR_PASS(progress, nir, nir_opt_remove_phis);
2579 NIR_PASS(progress, nir, nir_opt_dce);
2580
2581 if (nir_opt_trivial_continues(nir)) {
2582 progress = true;
2583 NIR_PASS(progress, nir, nir_copy_prop);
2584 NIR_PASS(progress, nir, nir_opt_dce);
2585 }
2586
2587 NIR_PASS(progress, nir, nir_opt_if, false);
2588 NIR_PASS(progress, nir, nir_opt_dead_cf);
2589 NIR_PASS(progress, nir, nir_opt_cse);
2590 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
2591
2592 NIR_PASS(progress, nir, nir_opt_algebraic);
2593 NIR_PASS(progress, nir, nir_opt_constant_folding);
2594
2595 NIR_PASS(progress, nir, nir_opt_undef);
2596 NIR_PASS(progress, nir, nir_opt_conditional_discard);
2597
2598 if (nir->options->max_unroll_iterations) {
2599 NIR_PASS(progress, nir, nir_opt_loop_unroll, (nir_variable_mode)0);
2600 }
2601
2602 } while (progress);
2603
2604 }
2605
2606 /**
2607 * Finalizes the NIR in a similar way as st_glsl_to_nir does.
2608 *
2609 * Drivers expect that these passes are already performed,
2610 * so we have to do it here too.
2611 */
2612 static void
2613 ttn_finalize_nir(struct ttn_compile *c)
2614 {
2615 struct nir_shader *nir = c->build.shader;
2616
2617 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2618 NIR_PASS_V(nir, nir_lower_regs_to_ssa);
2619
2620 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2621 NIR_PASS_V(nir, nir_split_var_copies);
2622 NIR_PASS_V(nir, nir_lower_var_copies);
2623 NIR_PASS_V(nir, nir_lower_system_values);
2624
2625 if (c->cap_packed_uniforms)
2626 NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, 16);
2627
2628 if (!c->cap_samplers_as_deref)
2629 NIR_PASS_V(nir, nir_lower_samplers);
2630
2631 ttn_optimize_nir(nir, c->cap_scalar);
2632 nir_shader_gather_info(nir, c->build.impl);
2633 nir_validate_shader(nir, "TTN: after all optimizations");
2634 }
2635
2636 struct nir_shader *
2637 tgsi_to_nir(const void *tgsi_tokens,
2638 struct pipe_screen *screen)
2639 {
2640 struct ttn_compile *c;
2641 struct nir_shader *s;
2642
2643 c = ttn_compile_init(tgsi_tokens, NULL, screen);
2644 s = c->build.shader;
2645 ttn_finalize_nir(c);
2646 ralloc_free(c);
2647
2648 return s;
2649 }
2650
2651 struct nir_shader *
2652 tgsi_to_nir_noscreen(const void *tgsi_tokens,
2653 const nir_shader_compiler_options *options)
2654 {
2655 struct ttn_compile *c;
2656 struct nir_shader *s;
2657
2658 c = ttn_compile_init(tgsi_tokens, options, NULL);
2659 s = c->build.shader;
2660 ralloc_free(c);
2661
2662 return s;
2663 }
2664