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[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define DEBUG_EXECUTION 0
66
67
68 #define FAST_MATH 0
69
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
74
75 static void
76 micro_abs(union tgsi_exec_channel *dst,
77 const union tgsi_exec_channel *src)
78 {
79 dst->f[0] = fabsf(src->f[0]);
80 dst->f[1] = fabsf(src->f[1]);
81 dst->f[2] = fabsf(src->f[2]);
82 dst->f[3] = fabsf(src->f[3]);
83 }
84
85 static void
86 micro_arl(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
88 {
89 dst->i[0] = (int)floorf(src->f[0]);
90 dst->i[1] = (int)floorf(src->f[1]);
91 dst->i[2] = (int)floorf(src->f[2]);
92 dst->i[3] = (int)floorf(src->f[3]);
93 }
94
95 static void
96 micro_arr(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
98 {
99 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
100 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
101 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
102 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
103 }
104
105 static void
106 micro_ceil(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
108 {
109 dst->f[0] = ceilf(src->f[0]);
110 dst->f[1] = ceilf(src->f[1]);
111 dst->f[2] = ceilf(src->f[2]);
112 dst->f[3] = ceilf(src->f[3]);
113 }
114
115 static void
116 micro_clamp(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src0,
118 const union tgsi_exec_channel *src1,
119 const union tgsi_exec_channel *src2)
120 {
121 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
122 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
123 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
124 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
125 }
126
127 static void
128 micro_cmp(union tgsi_exec_channel *dst,
129 const union tgsi_exec_channel *src0,
130 const union tgsi_exec_channel *src1,
131 const union tgsi_exec_channel *src2)
132 {
133 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
134 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
135 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
136 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
137 }
138
139 static void
140 micro_cnd(union tgsi_exec_channel *dst,
141 const union tgsi_exec_channel *src0,
142 const union tgsi_exec_channel *src1,
143 const union tgsi_exec_channel *src2)
144 {
145 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
146 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
147 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
148 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
149 }
150
151 static void
152 micro_cos(union tgsi_exec_channel *dst,
153 const union tgsi_exec_channel *src)
154 {
155 dst->f[0] = cosf(src->f[0]);
156 dst->f[1] = cosf(src->f[1]);
157 dst->f[2] = cosf(src->f[2]);
158 dst->f[3] = cosf(src->f[3]);
159 }
160
161 static void
162 micro_ddx(union tgsi_exec_channel *dst,
163 const union tgsi_exec_channel *src)
164 {
165 dst->f[0] =
166 dst->f[1] =
167 dst->f[2] =
168 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
169 }
170
171 static void
172 micro_ddy(union tgsi_exec_channel *dst,
173 const union tgsi_exec_channel *src)
174 {
175 dst->f[0] =
176 dst->f[1] =
177 dst->f[2] =
178 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
179 }
180
181 static void
182 micro_exp2(union tgsi_exec_channel *dst,
183 const union tgsi_exec_channel *src)
184 {
185 #if FAST_MATH
186 dst->f[0] = util_fast_exp2(src->f[0]);
187 dst->f[1] = util_fast_exp2(src->f[1]);
188 dst->f[2] = util_fast_exp2(src->f[2]);
189 dst->f[3] = util_fast_exp2(src->f[3]);
190 #else
191 #if DEBUG
192 /* Inf is okay for this instruction, so clamp it to silence assertions. */
193 uint i;
194 union tgsi_exec_channel clamped;
195
196 for (i = 0; i < 4; i++) {
197 if (src->f[i] > 127.99999f) {
198 clamped.f[i] = 127.99999f;
199 } else if (src->f[i] < -126.99999f) {
200 clamped.f[i] = -126.99999f;
201 } else {
202 clamped.f[i] = src->f[i];
203 }
204 }
205 src = &clamped;
206 #endif /* DEBUG */
207
208 dst->f[0] = powf(2.0f, src->f[0]);
209 dst->f[1] = powf(2.0f, src->f[1]);
210 dst->f[2] = powf(2.0f, src->f[2]);
211 dst->f[3] = powf(2.0f, src->f[3]);
212 #endif /* FAST_MATH */
213 }
214
215 static void
216 micro_flr(union tgsi_exec_channel *dst,
217 const union tgsi_exec_channel *src)
218 {
219 dst->f[0] = floorf(src->f[0]);
220 dst->f[1] = floorf(src->f[1]);
221 dst->f[2] = floorf(src->f[2]);
222 dst->f[3] = floorf(src->f[3]);
223 }
224
225 static void
226 micro_frc(union tgsi_exec_channel *dst,
227 const union tgsi_exec_channel *src)
228 {
229 dst->f[0] = src->f[0] - floorf(src->f[0]);
230 dst->f[1] = src->f[1] - floorf(src->f[1]);
231 dst->f[2] = src->f[2] - floorf(src->f[2]);
232 dst->f[3] = src->f[3] - floorf(src->f[3]);
233 }
234
235 static void
236 micro_iabs(union tgsi_exec_channel *dst,
237 const union tgsi_exec_channel *src)
238 {
239 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
240 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
241 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
242 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
243 }
244
245 static void
246 micro_ineg(union tgsi_exec_channel *dst,
247 const union tgsi_exec_channel *src)
248 {
249 dst->i[0] = -src->i[0];
250 dst->i[1] = -src->i[1];
251 dst->i[2] = -src->i[2];
252 dst->i[3] = -src->i[3];
253 }
254
255 static void
256 micro_lg2(union tgsi_exec_channel *dst,
257 const union tgsi_exec_channel *src)
258 {
259 #if FAST_MATH
260 dst->f[0] = util_fast_log2(src->f[0]);
261 dst->f[1] = util_fast_log2(src->f[1]);
262 dst->f[2] = util_fast_log2(src->f[2]);
263 dst->f[3] = util_fast_log2(src->f[3]);
264 #else
265 dst->f[0] = logf(src->f[0]) * 1.442695f;
266 dst->f[1] = logf(src->f[1]) * 1.442695f;
267 dst->f[2] = logf(src->f[2]) * 1.442695f;
268 dst->f[3] = logf(src->f[3]) * 1.442695f;
269 #endif
270 }
271
272 static void
273 micro_lrp(union tgsi_exec_channel *dst,
274 const union tgsi_exec_channel *src0,
275 const union tgsi_exec_channel *src1,
276 const union tgsi_exec_channel *src2)
277 {
278 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
279 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
280 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
281 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
282 }
283
284 static void
285 micro_mad(union tgsi_exec_channel *dst,
286 const union tgsi_exec_channel *src0,
287 const union tgsi_exec_channel *src1,
288 const union tgsi_exec_channel *src2)
289 {
290 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
291 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
292 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
293 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
294 }
295
296 static void
297 micro_mov(union tgsi_exec_channel *dst,
298 const union tgsi_exec_channel *src)
299 {
300 dst->u[0] = src->u[0];
301 dst->u[1] = src->u[1];
302 dst->u[2] = src->u[2];
303 dst->u[3] = src->u[3];
304 }
305
306 static void
307 micro_rcp(union tgsi_exec_channel *dst,
308 const union tgsi_exec_channel *src)
309 {
310 #if 0 /* for debugging */
311 assert(src->f[0] != 0.0f);
312 assert(src->f[1] != 0.0f);
313 assert(src->f[2] != 0.0f);
314 assert(src->f[3] != 0.0f);
315 #endif
316 dst->f[0] = 1.0f / src->f[0];
317 dst->f[1] = 1.0f / src->f[1];
318 dst->f[2] = 1.0f / src->f[2];
319 dst->f[3] = 1.0f / src->f[3];
320 }
321
322 static void
323 micro_rnd(union tgsi_exec_channel *dst,
324 const union tgsi_exec_channel *src)
325 {
326 dst->f[0] = floorf(src->f[0] + 0.5f);
327 dst->f[1] = floorf(src->f[1] + 0.5f);
328 dst->f[2] = floorf(src->f[2] + 0.5f);
329 dst->f[3] = floorf(src->f[3] + 0.5f);
330 }
331
332 static void
333 micro_rsq(union tgsi_exec_channel *dst,
334 const union tgsi_exec_channel *src)
335 {
336 #if 0 /* for debugging */
337 assert(src->f[0] != 0.0f);
338 assert(src->f[1] != 0.0f);
339 assert(src->f[2] != 0.0f);
340 assert(src->f[3] != 0.0f);
341 #endif
342 dst->f[0] = 1.0f / sqrtf(src->f[0]);
343 dst->f[1] = 1.0f / sqrtf(src->f[1]);
344 dst->f[2] = 1.0f / sqrtf(src->f[2]);
345 dst->f[3] = 1.0f / sqrtf(src->f[3]);
346 }
347
348 static void
349 micro_sqrt(union tgsi_exec_channel *dst,
350 const union tgsi_exec_channel *src)
351 {
352 dst->f[0] = sqrtf(src->f[0]);
353 dst->f[1] = sqrtf(src->f[1]);
354 dst->f[2] = sqrtf(src->f[2]);
355 dst->f[3] = sqrtf(src->f[3]);
356 }
357
358 static void
359 micro_seq(union tgsi_exec_channel *dst,
360 const union tgsi_exec_channel *src0,
361 const union tgsi_exec_channel *src1)
362 {
363 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
364 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
365 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
366 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
367 }
368
369 static void
370 micro_sge(union tgsi_exec_channel *dst,
371 const union tgsi_exec_channel *src0,
372 const union tgsi_exec_channel *src1)
373 {
374 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
375 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
376 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
377 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
378 }
379
380 static void
381 micro_sgn(union tgsi_exec_channel *dst,
382 const union tgsi_exec_channel *src)
383 {
384 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
385 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
386 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
387 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
388 }
389
390 static void
391 micro_isgn(union tgsi_exec_channel *dst,
392 const union tgsi_exec_channel *src)
393 {
394 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
395 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
396 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
397 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
398 }
399
400 static void
401 micro_sgt(union tgsi_exec_channel *dst,
402 const union tgsi_exec_channel *src0,
403 const union tgsi_exec_channel *src1)
404 {
405 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
406 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
407 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
408 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
409 }
410
411 static void
412 micro_sin(union tgsi_exec_channel *dst,
413 const union tgsi_exec_channel *src)
414 {
415 dst->f[0] = sinf(src->f[0]);
416 dst->f[1] = sinf(src->f[1]);
417 dst->f[2] = sinf(src->f[2]);
418 dst->f[3] = sinf(src->f[3]);
419 }
420
421 static void
422 micro_sle(union tgsi_exec_channel *dst,
423 const union tgsi_exec_channel *src0,
424 const union tgsi_exec_channel *src1)
425 {
426 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
427 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
428 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
429 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
430 }
431
432 static void
433 micro_slt(union tgsi_exec_channel *dst,
434 const union tgsi_exec_channel *src0,
435 const union tgsi_exec_channel *src1)
436 {
437 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
438 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
439 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
440 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
441 }
442
443 static void
444 micro_sne(union tgsi_exec_channel *dst,
445 const union tgsi_exec_channel *src0,
446 const union tgsi_exec_channel *src1)
447 {
448 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
449 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
450 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
451 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
452 }
453
454 static void
455 micro_sfl(union tgsi_exec_channel *dst)
456 {
457 dst->f[0] = 0.0f;
458 dst->f[1] = 0.0f;
459 dst->f[2] = 0.0f;
460 dst->f[3] = 0.0f;
461 }
462
463 static void
464 micro_str(union tgsi_exec_channel *dst)
465 {
466 dst->f[0] = 1.0f;
467 dst->f[1] = 1.0f;
468 dst->f[2] = 1.0f;
469 dst->f[3] = 1.0f;
470 }
471
472 static void
473 micro_trunc(union tgsi_exec_channel *dst,
474 const union tgsi_exec_channel *src)
475 {
476 dst->f[0] = (float)(int)src->f[0];
477 dst->f[1] = (float)(int)src->f[1];
478 dst->f[2] = (float)(int)src->f[2];
479 dst->f[3] = (float)(int)src->f[3];
480 }
481
482
483 enum tgsi_exec_datatype {
484 TGSI_EXEC_DATA_FLOAT,
485 TGSI_EXEC_DATA_INT,
486 TGSI_EXEC_DATA_UINT
487 };
488
489 /*
490 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
491 */
492 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
493 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
494 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
495 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
496 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
497 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
498
499
500 /** The execution mask depends on the conditional mask and the loop mask */
501 #define UPDATE_EXEC_MASK(MACH) \
502 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
503
504
505 static const union tgsi_exec_channel ZeroVec =
506 { { 0.0, 0.0, 0.0, 0.0 } };
507
508 static const union tgsi_exec_channel OneVec = {
509 {1.0f, 1.0f, 1.0f, 1.0f}
510 };
511
512 static const union tgsi_exec_channel P128Vec = {
513 {128.0f, 128.0f, 128.0f, 128.0f}
514 };
515
516 static const union tgsi_exec_channel M128Vec = {
517 {-128.0f, -128.0f, -128.0f, -128.0f}
518 };
519
520
521 /**
522 * Assert that none of the float values in 'chan' are infinite or NaN.
523 * NaN and Inf may occur normally during program execution and should
524 * not lead to crashes, etc. But when debugging, it's helpful to catch
525 * them.
526 */
527 static INLINE void
528 check_inf_or_nan(const union tgsi_exec_channel *chan)
529 {
530 assert(!util_is_inf_or_nan((chan)->f[0]));
531 assert(!util_is_inf_or_nan((chan)->f[1]));
532 assert(!util_is_inf_or_nan((chan)->f[2]));
533 assert(!util_is_inf_or_nan((chan)->f[3]));
534 }
535
536
537 #ifdef DEBUG
538 static void
539 print_chan(const char *msg, const union tgsi_exec_channel *chan)
540 {
541 debug_printf("%s = {%f, %f, %f, %f}\n",
542 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
543 }
544 #endif
545
546
547 #ifdef DEBUG
548 static void
549 print_temp(const struct tgsi_exec_machine *mach, uint index)
550 {
551 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
552 int i;
553 debug_printf("Temp[%u] =\n", index);
554 for (i = 0; i < 4; i++) {
555 debug_printf(" %c: { %f, %f, %f, %f }\n",
556 "XYZW"[i],
557 tmp->xyzw[i].f[0],
558 tmp->xyzw[i].f[1],
559 tmp->xyzw[i].f[2],
560 tmp->xyzw[i].f[3]);
561 }
562 }
563 #endif
564
565
566 void
567 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
568 unsigned num_bufs,
569 const void **bufs,
570 const unsigned *buf_sizes)
571 {
572 unsigned i;
573
574 for (i = 0; i < num_bufs; i++) {
575 mach->Consts[i] = bufs[i];
576 mach->ConstsSize[i] = buf_sizes[i];
577 }
578 }
579
580
581 /**
582 * Check if there's a potential src/dst register data dependency when
583 * using SOA execution.
584 * Example:
585 * MOV T, T.yxwz;
586 * This would expand into:
587 * MOV t0, t1;
588 * MOV t1, t0;
589 * MOV t2, t3;
590 * MOV t3, t2;
591 * The second instruction will have the wrong value for t0 if executed as-is.
592 */
593 boolean
594 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
595 {
596 uint i, chan;
597
598 uint writemask = inst->Dst[0].Register.WriteMask;
599 if (writemask == TGSI_WRITEMASK_X ||
600 writemask == TGSI_WRITEMASK_Y ||
601 writemask == TGSI_WRITEMASK_Z ||
602 writemask == TGSI_WRITEMASK_W ||
603 writemask == TGSI_WRITEMASK_NONE) {
604 /* no chance of data dependency */
605 return FALSE;
606 }
607
608 /* loop over src regs */
609 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
610 if ((inst->Src[i].Register.File ==
611 inst->Dst[0].Register.File) &&
612 ((inst->Src[i].Register.Index ==
613 inst->Dst[0].Register.Index) ||
614 inst->Src[i].Register.Indirect ||
615 inst->Dst[0].Register.Indirect)) {
616 /* loop over dest channels */
617 uint channelsWritten = 0x0;
618 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
619 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
620 /* check if we're reading a channel that's been written */
621 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
622 if (channelsWritten & (1 << swizzle)) {
623 return TRUE;
624 }
625
626 channelsWritten |= (1 << chan);
627 }
628 }
629 }
630 }
631 return FALSE;
632 }
633
634
635 /**
636 * Initialize machine state by expanding tokens to full instructions,
637 * allocating temporary storage, setting up constants, etc.
638 * After this, we can call tgsi_exec_machine_run() many times.
639 */
640 void
641 tgsi_exec_machine_bind_shader(
642 struct tgsi_exec_machine *mach,
643 const struct tgsi_token *tokens,
644 struct tgsi_sampler *sampler)
645 {
646 uint k;
647 struct tgsi_parse_context parse;
648 struct tgsi_full_instruction *instructions;
649 struct tgsi_full_declaration *declarations;
650 uint maxInstructions = 10, numInstructions = 0;
651 uint maxDeclarations = 10, numDeclarations = 0;
652
653 #if 0
654 tgsi_dump(tokens, 0);
655 #endif
656
657 util_init_math();
658
659
660 mach->Tokens = tokens;
661 mach->Sampler = sampler;
662
663 if (!tokens) {
664 /* unbind and free all */
665 FREE(mach->Declarations);
666 mach->Declarations = NULL;
667 mach->NumDeclarations = 0;
668
669 FREE(mach->Instructions);
670 mach->Instructions = NULL;
671 mach->NumInstructions = 0;
672
673 return;
674 }
675
676 k = tgsi_parse_init (&parse, mach->Tokens);
677 if (k != TGSI_PARSE_OK) {
678 debug_printf( "Problem parsing!\n" );
679 return;
680 }
681
682 mach->Processor = parse.FullHeader.Processor.Processor;
683 mach->ImmLimit = 0;
684 mach->NumOutputs = 0;
685
686 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
687 !mach->UsedGeometryShader) {
688 struct tgsi_exec_vector *inputs;
689 struct tgsi_exec_vector *outputs;
690
691 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
692 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS,
693 16);
694
695 if (!inputs)
696 return;
697
698 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
699 TGSI_MAX_TOTAL_VERTICES, 16);
700
701 if (!outputs) {
702 align_free(inputs);
703 return;
704 }
705
706 align_free(mach->Inputs);
707 align_free(mach->Outputs);
708
709 mach->Inputs = inputs;
710 mach->Outputs = outputs;
711 mach->UsedGeometryShader = TRUE;
712 }
713
714 declarations = (struct tgsi_full_declaration *)
715 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
716
717 if (!declarations) {
718 return;
719 }
720
721 instructions = (struct tgsi_full_instruction *)
722 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
723
724 if (!instructions) {
725 FREE( declarations );
726 return;
727 }
728
729 while( !tgsi_parse_end_of_tokens( &parse ) ) {
730 uint i;
731
732 tgsi_parse_token( &parse );
733 switch( parse.FullToken.Token.Type ) {
734 case TGSI_TOKEN_TYPE_DECLARATION:
735 /* save expanded declaration */
736 if (numDeclarations == maxDeclarations) {
737 declarations = REALLOC(declarations,
738 maxDeclarations
739 * sizeof(struct tgsi_full_declaration),
740 (maxDeclarations + 10)
741 * sizeof(struct tgsi_full_declaration));
742 maxDeclarations += 10;
743 }
744 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
745 unsigned reg;
746 for (reg = parse.FullToken.FullDeclaration.Range.First;
747 reg <= parse.FullToken.FullDeclaration.Range.Last;
748 ++reg) {
749 ++mach->NumOutputs;
750 }
751 }
752 memcpy(declarations + numDeclarations,
753 &parse.FullToken.FullDeclaration,
754 sizeof(declarations[0]));
755 numDeclarations++;
756 break;
757
758 case TGSI_TOKEN_TYPE_IMMEDIATE:
759 {
760 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
761 assert( size <= 4 );
762 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
763
764 for( i = 0; i < size; i++ ) {
765 mach->Imms[mach->ImmLimit][i] =
766 parse.FullToken.FullImmediate.u[i].Float;
767 }
768 mach->ImmLimit += 1;
769 }
770 break;
771
772 case TGSI_TOKEN_TYPE_INSTRUCTION:
773
774 /* save expanded instruction */
775 if (numInstructions == maxInstructions) {
776 instructions = REALLOC(instructions,
777 maxInstructions
778 * sizeof(struct tgsi_full_instruction),
779 (maxInstructions + 10)
780 * sizeof(struct tgsi_full_instruction));
781 maxInstructions += 10;
782 }
783
784 memcpy(instructions + numInstructions,
785 &parse.FullToken.FullInstruction,
786 sizeof(instructions[0]));
787
788 numInstructions++;
789 break;
790
791 case TGSI_TOKEN_TYPE_PROPERTY:
792 break;
793
794 default:
795 assert( 0 );
796 }
797 }
798 tgsi_parse_free (&parse);
799
800 FREE(mach->Declarations);
801 mach->Declarations = declarations;
802 mach->NumDeclarations = numDeclarations;
803
804 FREE(mach->Instructions);
805 mach->Instructions = instructions;
806 mach->NumInstructions = numInstructions;
807 }
808
809
810 struct tgsi_exec_machine *
811 tgsi_exec_machine_create( void )
812 {
813 struct tgsi_exec_machine *mach;
814 uint i;
815
816 mach = align_malloc( sizeof *mach, 16 );
817 if (!mach)
818 goto fail;
819
820 memset(mach, 0, sizeof(*mach));
821
822 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
823 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
824 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
825
826 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
827 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
828 if (!mach->Inputs || !mach->Outputs)
829 goto fail;
830
831 /* Setup constants needed by the SSE2 executor. */
832 for( i = 0; i < 4; i++ ) {
833 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
834 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
835 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
836 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
837 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
838 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
839 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
840 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
841 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
842 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
843 }
844
845 #ifdef DEBUG
846 /* silence warnings */
847 (void) print_chan;
848 (void) print_temp;
849 #endif
850
851 return mach;
852
853 fail:
854 if (mach) {
855 align_free(mach->Inputs);
856 align_free(mach->Outputs);
857 align_free(mach);
858 }
859 return NULL;
860 }
861
862
863 void
864 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
865 {
866 if (mach) {
867 FREE(mach->Instructions);
868 FREE(mach->Declarations);
869
870 align_free(mach->Inputs);
871 align_free(mach->Outputs);
872
873 align_free(mach);
874 }
875 }
876
877 static void
878 micro_add(union tgsi_exec_channel *dst,
879 const union tgsi_exec_channel *src0,
880 const union tgsi_exec_channel *src1)
881 {
882 dst->f[0] = src0->f[0] + src1->f[0];
883 dst->f[1] = src0->f[1] + src1->f[1];
884 dst->f[2] = src0->f[2] + src1->f[2];
885 dst->f[3] = src0->f[3] + src1->f[3];
886 }
887
888 static void
889 micro_div(
890 union tgsi_exec_channel *dst,
891 const union tgsi_exec_channel *src0,
892 const union tgsi_exec_channel *src1 )
893 {
894 if (src1->f[0] != 0) {
895 dst->f[0] = src0->f[0] / src1->f[0];
896 }
897 if (src1->f[1] != 0) {
898 dst->f[1] = src0->f[1] / src1->f[1];
899 }
900 if (src1->f[2] != 0) {
901 dst->f[2] = src0->f[2] / src1->f[2];
902 }
903 if (src1->f[3] != 0) {
904 dst->f[3] = src0->f[3] / src1->f[3];
905 }
906 }
907
908 static void
909 micro_rcc(union tgsi_exec_channel *dst,
910 const union tgsi_exec_channel *src)
911 {
912 uint i;
913
914 for (i = 0; i < 4; i++) {
915 float recip = 1.0f / src->f[i];
916
917 if (recip > 0.0f) {
918 if (recip > 1.884467e+019f) {
919 dst->f[i] = 1.884467e+019f;
920 }
921 else if (recip < 5.42101e-020f) {
922 dst->f[i] = 5.42101e-020f;
923 }
924 else {
925 dst->f[i] = recip;
926 }
927 }
928 else {
929 if (recip < -1.884467e+019f) {
930 dst->f[i] = -1.884467e+019f;
931 }
932 else if (recip > -5.42101e-020f) {
933 dst->f[i] = -5.42101e-020f;
934 }
935 else {
936 dst->f[i] = recip;
937 }
938 }
939 }
940 }
941
942 static void
943 micro_lt(
944 union tgsi_exec_channel *dst,
945 const union tgsi_exec_channel *src0,
946 const union tgsi_exec_channel *src1,
947 const union tgsi_exec_channel *src2,
948 const union tgsi_exec_channel *src3 )
949 {
950 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
951 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
952 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
953 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
954 }
955
956 static void
957 micro_max(union tgsi_exec_channel *dst,
958 const union tgsi_exec_channel *src0,
959 const union tgsi_exec_channel *src1)
960 {
961 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
962 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
963 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
964 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
965 }
966
967 static void
968 micro_min(union tgsi_exec_channel *dst,
969 const union tgsi_exec_channel *src0,
970 const union tgsi_exec_channel *src1)
971 {
972 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
973 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
974 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
975 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
976 }
977
978 static void
979 micro_mul(union tgsi_exec_channel *dst,
980 const union tgsi_exec_channel *src0,
981 const union tgsi_exec_channel *src1)
982 {
983 dst->f[0] = src0->f[0] * src1->f[0];
984 dst->f[1] = src0->f[1] * src1->f[1];
985 dst->f[2] = src0->f[2] * src1->f[2];
986 dst->f[3] = src0->f[3] * src1->f[3];
987 }
988
989 static void
990 micro_neg(
991 union tgsi_exec_channel *dst,
992 const union tgsi_exec_channel *src )
993 {
994 dst->f[0] = -src->f[0];
995 dst->f[1] = -src->f[1];
996 dst->f[2] = -src->f[2];
997 dst->f[3] = -src->f[3];
998 }
999
1000 static void
1001 micro_pow(
1002 union tgsi_exec_channel *dst,
1003 const union tgsi_exec_channel *src0,
1004 const union tgsi_exec_channel *src1 )
1005 {
1006 #if FAST_MATH
1007 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1008 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1009 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1010 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1011 #else
1012 dst->f[0] = powf( src0->f[0], src1->f[0] );
1013 dst->f[1] = powf( src0->f[1], src1->f[1] );
1014 dst->f[2] = powf( src0->f[2], src1->f[2] );
1015 dst->f[3] = powf( src0->f[3], src1->f[3] );
1016 #endif
1017 }
1018
1019 static void
1020 micro_sub(union tgsi_exec_channel *dst,
1021 const union tgsi_exec_channel *src0,
1022 const union tgsi_exec_channel *src1)
1023 {
1024 dst->f[0] = src0->f[0] - src1->f[0];
1025 dst->f[1] = src0->f[1] - src1->f[1];
1026 dst->f[2] = src0->f[2] - src1->f[2];
1027 dst->f[3] = src0->f[3] - src1->f[3];
1028 }
1029
1030 static void
1031 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1032 const uint chan_index,
1033 const uint file,
1034 const uint swizzle,
1035 const union tgsi_exec_channel *index,
1036 const union tgsi_exec_channel *index2D,
1037 union tgsi_exec_channel *chan)
1038 {
1039 uint i;
1040
1041 assert(swizzle < 4);
1042
1043 switch (file) {
1044 case TGSI_FILE_CONSTANT:
1045 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1046 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1047 assert(mach->Consts[index2D->i[i]]);
1048
1049 if (index->i[i] < 0) {
1050 chan->u[i] = 0;
1051 } else {
1052 /* NOTE: copying the const value as a uint instead of float */
1053 const uint constbuf = index2D->i[i];
1054 const uint *buf = (const uint *)mach->Consts[constbuf];
1055 const int pos = index->i[i] * 4 + swizzle;
1056 /* const buffer bounds check */
1057 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1058 if (0) {
1059 /* Debug: print warning */
1060 static int count = 0;
1061 if (count++ < 100)
1062 debug_printf("TGSI Exec: const buffer index %d"
1063 " out of bounds\n", pos);
1064 }
1065 chan->u[i] = 0;
1066 }
1067 else
1068 chan->u[i] = buf[pos];
1069 }
1070 }
1071 break;
1072
1073 case TGSI_FILE_INPUT:
1074 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1075 /*
1076 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1077 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1078 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1079 index2D->i[i], index->i[i]);
1080 }*/
1081 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1082 assert(pos >= 0);
1083 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1084 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1085 }
1086 break;
1087
1088 case TGSI_FILE_SYSTEM_VALUE:
1089 /* XXX no swizzling at this point. Will be needed if we put
1090 * gl_FragCoord, for example, in a sys value register.
1091 */
1092 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1093 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1094 }
1095 break;
1096
1097 case TGSI_FILE_TEMPORARY:
1098 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1099 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1100 assert(index2D->i[i] == 0);
1101
1102 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1103 }
1104 break;
1105
1106 case TGSI_FILE_IMMEDIATE:
1107 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1108 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1109 assert(index2D->i[i] == 0);
1110
1111 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1112 }
1113 break;
1114
1115 case TGSI_FILE_ADDRESS:
1116 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1117 assert(index->i[i] >= 0);
1118 assert(index2D->i[i] == 0);
1119
1120 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1121 }
1122 break;
1123
1124 case TGSI_FILE_PREDICATE:
1125 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1126 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1127 assert(index2D->i[i] == 0);
1128
1129 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1130 }
1131 break;
1132
1133 case TGSI_FILE_OUTPUT:
1134 /* vertex/fragment output vars can be read too */
1135 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1136 assert(index->i[i] >= 0);
1137 assert(index2D->i[i] == 0);
1138
1139 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1140 }
1141 break;
1142
1143 default:
1144 assert(0);
1145 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1146 chan->u[i] = 0;
1147 }
1148 }
1149 }
1150
1151 static void
1152 fetch_source(const struct tgsi_exec_machine *mach,
1153 union tgsi_exec_channel *chan,
1154 const struct tgsi_full_src_register *reg,
1155 const uint chan_index,
1156 enum tgsi_exec_datatype src_datatype)
1157 {
1158 union tgsi_exec_channel index;
1159 union tgsi_exec_channel index2D;
1160 uint swizzle;
1161
1162 /* We start with a direct index into a register file.
1163 *
1164 * file[1],
1165 * where:
1166 * file = Register.File
1167 * [1] = Register.Index
1168 */
1169 index.i[0] =
1170 index.i[1] =
1171 index.i[2] =
1172 index.i[3] = reg->Register.Index;
1173
1174 /* There is an extra source register that indirectly subscripts
1175 * a register file. The direct index now becomes an offset
1176 * that is being added to the indirect register.
1177 *
1178 * file[ind[2].x+1],
1179 * where:
1180 * ind = Indirect.File
1181 * [2] = Indirect.Index
1182 * .x = Indirect.SwizzleX
1183 */
1184 if (reg->Register.Indirect) {
1185 union tgsi_exec_channel index2;
1186 union tgsi_exec_channel indir_index;
1187 const uint execmask = mach->ExecMask;
1188 uint i;
1189
1190 /* which address register (always zero now) */
1191 index2.i[0] =
1192 index2.i[1] =
1193 index2.i[2] =
1194 index2.i[3] = reg->Indirect.Index;
1195 /* get current value of address register[swizzle] */
1196 swizzle = reg->Indirect.Swizzle;
1197 fetch_src_file_channel(mach,
1198 chan_index,
1199 reg->Indirect.File,
1200 swizzle,
1201 &index2,
1202 &ZeroVec,
1203 &indir_index);
1204
1205 /* add value of address register to the offset */
1206 index.i[0] += indir_index.i[0];
1207 index.i[1] += indir_index.i[1];
1208 index.i[2] += indir_index.i[2];
1209 index.i[3] += indir_index.i[3];
1210
1211 /* for disabled execution channels, zero-out the index to
1212 * avoid using a potential garbage value.
1213 */
1214 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1215 if ((execmask & (1 << i)) == 0)
1216 index.i[i] = 0;
1217 }
1218 }
1219
1220 /* There is an extra source register that is a second
1221 * subscript to a register file. Effectively it means that
1222 * the register file is actually a 2D array of registers.
1223 *
1224 * file[3][1],
1225 * where:
1226 * [3] = Dimension.Index
1227 */
1228 if (reg->Register.Dimension) {
1229 index2D.i[0] =
1230 index2D.i[1] =
1231 index2D.i[2] =
1232 index2D.i[3] = reg->Dimension.Index;
1233
1234 /* Again, the second subscript index can be addressed indirectly
1235 * identically to the first one.
1236 * Nothing stops us from indirectly addressing the indirect register,
1237 * but there is no need for that, so we won't exercise it.
1238 *
1239 * file[ind[4].y+3][1],
1240 * where:
1241 * ind = DimIndirect.File
1242 * [4] = DimIndirect.Index
1243 * .y = DimIndirect.SwizzleX
1244 */
1245 if (reg->Dimension.Indirect) {
1246 union tgsi_exec_channel index2;
1247 union tgsi_exec_channel indir_index;
1248 const uint execmask = mach->ExecMask;
1249 uint i;
1250
1251 index2.i[0] =
1252 index2.i[1] =
1253 index2.i[2] =
1254 index2.i[3] = reg->DimIndirect.Index;
1255
1256 swizzle = reg->DimIndirect.Swizzle;
1257 fetch_src_file_channel(mach,
1258 chan_index,
1259 reg->DimIndirect.File,
1260 swizzle,
1261 &index2,
1262 &ZeroVec,
1263 &indir_index);
1264
1265 index2D.i[0] += indir_index.i[0];
1266 index2D.i[1] += indir_index.i[1];
1267 index2D.i[2] += indir_index.i[2];
1268 index2D.i[3] += indir_index.i[3];
1269
1270 /* for disabled execution channels, zero-out the index to
1271 * avoid using a potential garbage value.
1272 */
1273 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1274 if ((execmask & (1 << i)) == 0) {
1275 index2D.i[i] = 0;
1276 }
1277 }
1278 }
1279
1280 /* If by any chance there was a need for a 3D array of register
1281 * files, we would have to check whether Dimension is followed
1282 * by a dimension register and continue the saga.
1283 */
1284 } else {
1285 index2D.i[0] =
1286 index2D.i[1] =
1287 index2D.i[2] =
1288 index2D.i[3] = 0;
1289 }
1290
1291 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1292 fetch_src_file_channel(mach,
1293 chan_index,
1294 reg->Register.File,
1295 swizzle,
1296 &index,
1297 &index2D,
1298 chan);
1299
1300 if (reg->Register.Absolute) {
1301 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1302 micro_abs(chan, chan);
1303 } else {
1304 micro_iabs(chan, chan);
1305 }
1306 }
1307
1308 if (reg->Register.Negate) {
1309 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1310 micro_neg(chan, chan);
1311 } else {
1312 micro_ineg(chan, chan);
1313 }
1314 }
1315 }
1316
1317 static void
1318 store_dest(struct tgsi_exec_machine *mach,
1319 const union tgsi_exec_channel *chan,
1320 const struct tgsi_full_dst_register *reg,
1321 const struct tgsi_full_instruction *inst,
1322 uint chan_index,
1323 enum tgsi_exec_datatype dst_datatype)
1324 {
1325 uint i;
1326 union tgsi_exec_channel null;
1327 union tgsi_exec_channel *dst;
1328 union tgsi_exec_channel index2D;
1329 uint execmask = mach->ExecMask;
1330 int offset = 0; /* indirection offset */
1331 int index;
1332
1333 /* for debugging */
1334 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1335 check_inf_or_nan(chan);
1336 }
1337
1338 /* There is an extra source register that indirectly subscripts
1339 * a register file. The direct index now becomes an offset
1340 * that is being added to the indirect register.
1341 *
1342 * file[ind[2].x+1],
1343 * where:
1344 * ind = Indirect.File
1345 * [2] = Indirect.Index
1346 * .x = Indirect.SwizzleX
1347 */
1348 if (reg->Register.Indirect) {
1349 union tgsi_exec_channel index;
1350 union tgsi_exec_channel indir_index;
1351 uint swizzle;
1352
1353 /* which address register (always zero for now) */
1354 index.i[0] =
1355 index.i[1] =
1356 index.i[2] =
1357 index.i[3] = reg->Indirect.Index;
1358
1359 /* get current value of address register[swizzle] */
1360 swizzle = reg->Indirect.Swizzle;
1361
1362 /* fetch values from the address/indirection register */
1363 fetch_src_file_channel(mach,
1364 chan_index,
1365 reg->Indirect.File,
1366 swizzle,
1367 &index,
1368 &ZeroVec,
1369 &indir_index);
1370
1371 /* save indirection offset */
1372 offset = indir_index.i[0];
1373 }
1374
1375 /* There is an extra source register that is a second
1376 * subscript to a register file. Effectively it means that
1377 * the register file is actually a 2D array of registers.
1378 *
1379 * file[3][1],
1380 * where:
1381 * [3] = Dimension.Index
1382 */
1383 if (reg->Register.Dimension) {
1384 index2D.i[0] =
1385 index2D.i[1] =
1386 index2D.i[2] =
1387 index2D.i[3] = reg->Dimension.Index;
1388
1389 /* Again, the second subscript index can be addressed indirectly
1390 * identically to the first one.
1391 * Nothing stops us from indirectly addressing the indirect register,
1392 * but there is no need for that, so we won't exercise it.
1393 *
1394 * file[ind[4].y+3][1],
1395 * where:
1396 * ind = DimIndirect.File
1397 * [4] = DimIndirect.Index
1398 * .y = DimIndirect.SwizzleX
1399 */
1400 if (reg->Dimension.Indirect) {
1401 union tgsi_exec_channel index2;
1402 union tgsi_exec_channel indir_index;
1403 const uint execmask = mach->ExecMask;
1404 unsigned swizzle;
1405 uint i;
1406
1407 index2.i[0] =
1408 index2.i[1] =
1409 index2.i[2] =
1410 index2.i[3] = reg->DimIndirect.Index;
1411
1412 swizzle = reg->DimIndirect.Swizzle;
1413 fetch_src_file_channel(mach,
1414 chan_index,
1415 reg->DimIndirect.File,
1416 swizzle,
1417 &index2,
1418 &ZeroVec,
1419 &indir_index);
1420
1421 index2D.i[0] += indir_index.i[0];
1422 index2D.i[1] += indir_index.i[1];
1423 index2D.i[2] += indir_index.i[2];
1424 index2D.i[3] += indir_index.i[3];
1425
1426 /* for disabled execution channels, zero-out the index to
1427 * avoid using a potential garbage value.
1428 */
1429 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1430 if ((execmask & (1 << i)) == 0) {
1431 index2D.i[i] = 0;
1432 }
1433 }
1434 }
1435
1436 /* If by any chance there was a need for a 3D array of register
1437 * files, we would have to check whether Dimension is followed
1438 * by a dimension register and continue the saga.
1439 */
1440 } else {
1441 index2D.i[0] =
1442 index2D.i[1] =
1443 index2D.i[2] =
1444 index2D.i[3] = 0;
1445 }
1446
1447 switch (reg->Register.File) {
1448 case TGSI_FILE_NULL:
1449 dst = &null;
1450 break;
1451
1452 case TGSI_FILE_OUTPUT:
1453 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1454 + reg->Register.Index;
1455 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1456 #if 0
1457 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1458 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1459 reg->Register.Index);
1460 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1461 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1462 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1463 if (execmask & (1 << i))
1464 debug_printf("%f, ", chan->f[i]);
1465 debug_printf(")\n");
1466 }
1467 #endif
1468 break;
1469
1470 case TGSI_FILE_TEMPORARY:
1471 index = reg->Register.Index;
1472 assert( index < TGSI_EXEC_NUM_TEMPS );
1473 dst = &mach->Temps[offset + index].xyzw[chan_index];
1474 break;
1475
1476 case TGSI_FILE_ADDRESS:
1477 index = reg->Register.Index;
1478 dst = &mach->Addrs[index].xyzw[chan_index];
1479 break;
1480
1481 case TGSI_FILE_PREDICATE:
1482 index = reg->Register.Index;
1483 assert(index < TGSI_EXEC_NUM_PREDS);
1484 dst = &mach->Predicates[index].xyzw[chan_index];
1485 break;
1486
1487 default:
1488 assert( 0 );
1489 return;
1490 }
1491
1492 if (inst->Instruction.Predicate) {
1493 uint swizzle;
1494 union tgsi_exec_channel *pred;
1495
1496 switch (chan_index) {
1497 case TGSI_CHAN_X:
1498 swizzle = inst->Predicate.SwizzleX;
1499 break;
1500 case TGSI_CHAN_Y:
1501 swizzle = inst->Predicate.SwizzleY;
1502 break;
1503 case TGSI_CHAN_Z:
1504 swizzle = inst->Predicate.SwizzleZ;
1505 break;
1506 case TGSI_CHAN_W:
1507 swizzle = inst->Predicate.SwizzleW;
1508 break;
1509 default:
1510 assert(0);
1511 return;
1512 }
1513
1514 assert(inst->Predicate.Index == 0);
1515
1516 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1517
1518 if (inst->Predicate.Negate) {
1519 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1520 if (pred->u[i]) {
1521 execmask &= ~(1 << i);
1522 }
1523 }
1524 } else {
1525 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1526 if (!pred->u[i]) {
1527 execmask &= ~(1 << i);
1528 }
1529 }
1530 }
1531 }
1532
1533 switch (inst->Instruction.Saturate) {
1534 case TGSI_SAT_NONE:
1535 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1536 if (execmask & (1 << i))
1537 dst->i[i] = chan->i[i];
1538 break;
1539
1540 case TGSI_SAT_ZERO_ONE:
1541 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1542 if (execmask & (1 << i)) {
1543 if (chan->f[i] < 0.0f)
1544 dst->f[i] = 0.0f;
1545 else if (chan->f[i] > 1.0f)
1546 dst->f[i] = 1.0f;
1547 else
1548 dst->i[i] = chan->i[i];
1549 }
1550 break;
1551
1552 case TGSI_SAT_MINUS_PLUS_ONE:
1553 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1554 if (execmask & (1 << i)) {
1555 if (chan->f[i] < -1.0f)
1556 dst->f[i] = -1.0f;
1557 else if (chan->f[i] > 1.0f)
1558 dst->f[i] = 1.0f;
1559 else
1560 dst->i[i] = chan->i[i];
1561 }
1562 break;
1563
1564 default:
1565 assert( 0 );
1566 }
1567 }
1568
1569 #define FETCH(VAL,INDEX,CHAN)\
1570 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1571
1572 #define IFETCH(VAL,INDEX,CHAN)\
1573 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1574
1575
1576 /**
1577 * Execute ARB-style KIL which is predicated by a src register.
1578 * Kill fragment if any of the four values is less than zero.
1579 */
1580 static void
1581 exec_kill_if(struct tgsi_exec_machine *mach,
1582 const struct tgsi_full_instruction *inst)
1583 {
1584 uint uniquemask;
1585 uint chan_index;
1586 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1587 union tgsi_exec_channel r[1];
1588
1589 /* This mask stores component bits that were already tested. */
1590 uniquemask = 0;
1591
1592 for (chan_index = 0; chan_index < 4; chan_index++)
1593 {
1594 uint swizzle;
1595 uint i;
1596
1597 /* unswizzle channel */
1598 swizzle = tgsi_util_get_full_src_register_swizzle (
1599 &inst->Src[0],
1600 chan_index);
1601
1602 /* check if the component has not been already tested */
1603 if (uniquemask & (1 << swizzle))
1604 continue;
1605 uniquemask |= 1 << swizzle;
1606
1607 FETCH(&r[0], 0, chan_index);
1608 for (i = 0; i < 4; i++)
1609 if (r[0].f[i] < 0.0f)
1610 kilmask |= 1 << i;
1611 }
1612
1613 /* restrict to fragments currently executing */
1614 kilmask &= mach->ExecMask;
1615
1616 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1617 }
1618
1619 /**
1620 * Unconditional fragment kill/discard.
1621 */
1622 static void
1623 exec_kill(struct tgsi_exec_machine *mach,
1624 const struct tgsi_full_instruction *inst)
1625 {
1626 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1627
1628 /* kill fragment for all fragments currently executing */
1629 kilmask = mach->ExecMask;
1630 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1631 }
1632
1633 static void
1634 emit_vertex(struct tgsi_exec_machine *mach)
1635 {
1636 /* FIXME: check for exec mask correctly
1637 unsigned i;
1638 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1639 if ((mach->ExecMask & (1 << i)))
1640 */
1641 if (mach->ExecMask) {
1642 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1643 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1644 }
1645 }
1646
1647 static void
1648 emit_primitive(struct tgsi_exec_machine *mach)
1649 {
1650 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1651 /* FIXME: check for exec mask correctly
1652 unsigned i;
1653 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1654 if ((mach->ExecMask & (1 << i)))
1655 */
1656 if (mach->ExecMask) {
1657 ++(*prim_count);
1658 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1659 mach->Primitives[*prim_count] = 0;
1660 }
1661 }
1662
1663 static void
1664 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1665 {
1666 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1667 int emitted_verts =
1668 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1669 if (emitted_verts) {
1670 emit_primitive(mach);
1671 }
1672 }
1673 }
1674
1675
1676 /*
1677 * Fetch four texture samples using STR texture coordinates.
1678 */
1679 static void
1680 fetch_texel( struct tgsi_sampler *sampler,
1681 const unsigned sview_idx,
1682 const unsigned sampler_idx,
1683 const union tgsi_exec_channel *s,
1684 const union tgsi_exec_channel *t,
1685 const union tgsi_exec_channel *p,
1686 const union tgsi_exec_channel *c0,
1687 const union tgsi_exec_channel *c1,
1688 float derivs[3][2][TGSI_QUAD_SIZE],
1689 const int8_t offset[3],
1690 enum tgsi_sampler_control control,
1691 union tgsi_exec_channel *r,
1692 union tgsi_exec_channel *g,
1693 union tgsi_exec_channel *b,
1694 union tgsi_exec_channel *a )
1695 {
1696 uint j;
1697 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1698
1699 /* FIXME: handle explicit derivs, offsets */
1700 sampler->get_samples(sampler, sview_idx, sampler_idx,
1701 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1702
1703 for (j = 0; j < 4; j++) {
1704 r->f[j] = rgba[0][j];
1705 g->f[j] = rgba[1][j];
1706 b->f[j] = rgba[2][j];
1707 a->f[j] = rgba[3][j];
1708 }
1709 }
1710
1711
1712 #define TEX_MODIFIER_NONE 0
1713 #define TEX_MODIFIER_PROJECTED 1
1714 #define TEX_MODIFIER_LOD_BIAS 2
1715 #define TEX_MODIFIER_EXPLICIT_LOD 3
1716 #define TEX_MODIFIER_LEVEL_ZERO 4
1717
1718
1719 /*
1720 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1721 */
1722 static void
1723 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1724 const struct tgsi_full_instruction *inst,
1725 int8_t offsets[3])
1726 {
1727 if (inst->Texture.NumOffsets == 1) {
1728 union tgsi_exec_channel index;
1729 union tgsi_exec_channel offset[3];
1730 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1731 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1732 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1733 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1734 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1735 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1736 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1737 offsets[0] = offset[0].i[0];
1738 offsets[1] = offset[1].i[0];
1739 offsets[2] = offset[2].i[0];
1740 } else {
1741 assert(inst->Texture.NumOffsets == 0);
1742 offsets[0] = offsets[1] = offsets[2] = 0;
1743 }
1744 }
1745
1746
1747 /*
1748 * Fetch dx and dy values for one channel (s, t or r).
1749 * Put dx values into one float array, dy values into another.
1750 */
1751 static void
1752 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1753 const struct tgsi_full_instruction *inst,
1754 unsigned regdsrcx,
1755 unsigned chan,
1756 float derivs[2][TGSI_QUAD_SIZE])
1757 {
1758 union tgsi_exec_channel d;
1759 FETCH(&d, regdsrcx, chan);
1760 derivs[0][0] = d.f[0];
1761 derivs[0][1] = d.f[1];
1762 derivs[0][2] = d.f[2];
1763 derivs[0][3] = d.f[3];
1764 FETCH(&d, regdsrcx + 1, chan);
1765 derivs[1][0] = d.f[0];
1766 derivs[1][1] = d.f[1];
1767 derivs[1][2] = d.f[2];
1768 derivs[1][3] = d.f[3];
1769 }
1770
1771
1772 /*
1773 * execute a texture instruction.
1774 *
1775 * modifier is used to control the channel routing for the\
1776 * instruction variants like proj, lod, and texture with lod bias.
1777 * sampler indicates which src register the sampler is contained in.
1778 */
1779 static void
1780 exec_tex(struct tgsi_exec_machine *mach,
1781 const struct tgsi_full_instruction *inst,
1782 uint modifier, uint sampler)
1783 {
1784 const uint unit = inst->Src[sampler].Register.Index;
1785 const union tgsi_exec_channel *args[5], *proj = NULL;
1786 union tgsi_exec_channel r[5];
1787 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
1788 uint chan;
1789 int8_t offsets[3];
1790 int dim, shadow_ref, i;
1791
1792 /* always fetch all 3 offsets, overkill but keeps code simple */
1793 fetch_texel_offsets(mach, inst, offsets);
1794
1795 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
1796 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
1797
1798 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
1799
1800 assert(dim <= 4);
1801 if (shadow_ref >= 0)
1802 assert(shadow_ref >= dim && shadow_ref < Elements(args));
1803
1804 /* fetch modifier to the last argument */
1805 if (modifier != TEX_MODIFIER_NONE) {
1806 const int last = Elements(args) - 1;
1807
1808 /* fetch modifier from src0.w or src1.x */
1809 if (sampler == 1) {
1810 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
1811 FETCH(&r[last], 0, TGSI_CHAN_W);
1812 }
1813 else {
1814 assert(shadow_ref != 4);
1815 FETCH(&r[last], 1, TGSI_CHAN_X);
1816 }
1817
1818 if (modifier != TEX_MODIFIER_PROJECTED) {
1819 args[last] = &r[last];
1820 }
1821 else {
1822 proj = &r[last];
1823 args[last] = &ZeroVec;
1824 }
1825
1826 /* point unused arguments to zero vector */
1827 for (i = dim; i < last; i++)
1828 args[i] = &ZeroVec;
1829
1830 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
1831 control = tgsi_sampler_lod_explicit;
1832 else if (modifier == TEX_MODIFIER_LOD_BIAS)
1833 control = tgsi_sampler_lod_bias;
1834 }
1835 else {
1836 for (i = dim; i < Elements(args); i++)
1837 args[i] = &ZeroVec;
1838 }
1839
1840 /* fetch coordinates */
1841 for (i = 0; i < dim; i++) {
1842 FETCH(&r[i], 0, TGSI_CHAN_X + i);
1843
1844 if (proj)
1845 micro_div(&r[i], &r[i], proj);
1846
1847 args[i] = &r[i];
1848 }
1849
1850 /* fetch reference value */
1851 if (shadow_ref >= 0) {
1852 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
1853
1854 if (proj)
1855 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
1856
1857 args[shadow_ref] = &r[shadow_ref];
1858 }
1859
1860 fetch_texel(mach->Sampler, unit, unit,
1861 args[0], args[1], args[2], args[3], args[4],
1862 NULL, offsets, control,
1863 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1864
1865 #if 0
1866 debug_printf("fetch r: %g %g %g %g\n",
1867 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1868 debug_printf("fetch g: %g %g %g %g\n",
1869 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1870 debug_printf("fetch b: %g %g %g %g\n",
1871 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1872 debug_printf("fetch a: %g %g %g %g\n",
1873 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1874 #endif
1875
1876 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1877 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1878 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1879 }
1880 }
1881 }
1882
1883
1884 static void
1885 exec_txd(struct tgsi_exec_machine *mach,
1886 const struct tgsi_full_instruction *inst)
1887 {
1888 const uint unit = inst->Src[3].Register.Index;
1889 union tgsi_exec_channel r[4];
1890 float derivs[3][2][TGSI_QUAD_SIZE];
1891 uint chan;
1892 int8_t offsets[3];
1893
1894 /* always fetch all 3 offsets, overkill but keeps code simple */
1895 fetch_texel_offsets(mach, inst, offsets);
1896
1897 switch (inst->Texture.Texture) {
1898 case TGSI_TEXTURE_1D:
1899 FETCH(&r[0], 0, TGSI_CHAN_X);
1900
1901 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1902
1903 fetch_texel(mach->Sampler, unit, unit,
1904 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1905 derivs, offsets, tgsi_sampler_derivs_explicit,
1906 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1907 break;
1908
1909 case TGSI_TEXTURE_SHADOW1D:
1910 case TGSI_TEXTURE_1D_ARRAY:
1911 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1912 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
1913 FETCH(&r[0], 0, TGSI_CHAN_X);
1914 FETCH(&r[1], 0, TGSI_CHAN_Y);
1915 FETCH(&r[2], 0, TGSI_CHAN_Z);
1916
1917 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1918
1919 fetch_texel(mach->Sampler, unit, unit,
1920 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1921 derivs, offsets, tgsi_sampler_derivs_explicit,
1922 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1923 break;
1924
1925 case TGSI_TEXTURE_2D:
1926 case TGSI_TEXTURE_RECT:
1927 FETCH(&r[0], 0, TGSI_CHAN_X);
1928 FETCH(&r[1], 0, TGSI_CHAN_Y);
1929
1930 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1931 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1932
1933 fetch_texel(mach->Sampler, unit, unit,
1934 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1935 derivs, offsets, tgsi_sampler_derivs_explicit,
1936 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1937 break;
1938
1939
1940 case TGSI_TEXTURE_SHADOW2D:
1941 case TGSI_TEXTURE_SHADOWRECT:
1942 case TGSI_TEXTURE_2D_ARRAY:
1943 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1944 /* only SHADOW2D_ARRAY actually needs W */
1945 FETCH(&r[0], 0, TGSI_CHAN_X);
1946 FETCH(&r[1], 0, TGSI_CHAN_Y);
1947 FETCH(&r[2], 0, TGSI_CHAN_Z);
1948 FETCH(&r[3], 0, TGSI_CHAN_W);
1949
1950 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1951 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1952
1953 fetch_texel(mach->Sampler, unit, unit,
1954 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1955 derivs, offsets, tgsi_sampler_derivs_explicit,
1956 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1957 break;
1958
1959 case TGSI_TEXTURE_3D:
1960 case TGSI_TEXTURE_CUBE:
1961 case TGSI_TEXTURE_CUBE_ARRAY:
1962 /* only TEXTURE_CUBE_ARRAY actually needs W */
1963 FETCH(&r[0], 0, TGSI_CHAN_X);
1964 FETCH(&r[1], 0, TGSI_CHAN_Y);
1965 FETCH(&r[2], 0, TGSI_CHAN_Z);
1966 FETCH(&r[3], 0, TGSI_CHAN_W);
1967
1968 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1969 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1970 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
1971
1972 fetch_texel(mach->Sampler, unit, unit,
1973 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1974 derivs, offsets, tgsi_sampler_derivs_explicit,
1975 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1976 break;
1977
1978 default:
1979 assert(0);
1980 }
1981
1982 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1983 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1984 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1985 }
1986 }
1987 }
1988
1989
1990 static void
1991 exec_txf(struct tgsi_exec_machine *mach,
1992 const struct tgsi_full_instruction *inst)
1993 {
1994 const uint unit = inst->Src[1].Register.Index;
1995 union tgsi_exec_channel r[4];
1996 uint chan;
1997 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1998 int j;
1999 int8_t offsets[3];
2000 unsigned target;
2001
2002 /* always fetch all 3 offsets, overkill but keeps code simple */
2003 fetch_texel_offsets(mach, inst, offsets);
2004
2005 IFETCH(&r[3], 0, TGSI_CHAN_W);
2006
2007 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2008 target = mach->SamplerViews[unit].Resource;
2009 }
2010 else {
2011 target = inst->Texture.Texture;
2012 }
2013 switch(target) {
2014 case TGSI_TEXTURE_3D:
2015 case TGSI_TEXTURE_2D_ARRAY:
2016 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2017 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2018 /* fallthrough */
2019 case TGSI_TEXTURE_2D:
2020 case TGSI_TEXTURE_RECT:
2021 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2022 case TGSI_TEXTURE_SHADOW2D:
2023 case TGSI_TEXTURE_SHADOWRECT:
2024 case TGSI_TEXTURE_1D_ARRAY:
2025 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2026 /* fallthrough */
2027 case TGSI_TEXTURE_BUFFER:
2028 case TGSI_TEXTURE_1D:
2029 case TGSI_TEXTURE_SHADOW1D:
2030 IFETCH(&r[0], 0, TGSI_CHAN_X);
2031 break;
2032 default:
2033 assert(0);
2034 break;
2035 }
2036
2037 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2038 offsets, rgba);
2039
2040 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2041 r[0].f[j] = rgba[0][j];
2042 r[1].f[j] = rgba[1][j];
2043 r[2].f[j] = rgba[2][j];
2044 r[3].f[j] = rgba[3][j];
2045 }
2046
2047 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2048 unsigned char swizzles[4];
2049 swizzles[0] = inst->Src[1].Register.SwizzleX;
2050 swizzles[1] = inst->Src[1].Register.SwizzleY;
2051 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2052 swizzles[3] = inst->Src[1].Register.SwizzleW;
2053
2054 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2055 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2056 store_dest(mach, &r[swizzles[chan]],
2057 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2058 }
2059 }
2060 }
2061 else {
2062 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2063 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2064 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2065 }
2066 }
2067 }
2068 }
2069
2070 static void
2071 exec_txq(struct tgsi_exec_machine *mach,
2072 const struct tgsi_full_instruction *inst)
2073 {
2074 const uint unit = inst->Src[1].Register.Index;
2075 int result[4];
2076 union tgsi_exec_channel r[4], src;
2077 uint chan;
2078 int i,j;
2079
2080 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2081
2082 /* XXX: This interface can't return per-pixel values */
2083 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2084
2085 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2086 for (j = 0; j < 4; j++) {
2087 r[j].i[i] = result[j];
2088 }
2089 }
2090
2091 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2092 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2093 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2094 TGSI_EXEC_DATA_INT);
2095 }
2096 }
2097 }
2098
2099 static void
2100 exec_sample(struct tgsi_exec_machine *mach,
2101 const struct tgsi_full_instruction *inst,
2102 uint modifier, boolean compare)
2103 {
2104 const uint resource_unit = inst->Src[1].Register.Index;
2105 const uint sampler_unit = inst->Src[2].Register.Index;
2106 union tgsi_exec_channel r[4], c1;
2107 const union tgsi_exec_channel *lod = &ZeroVec;
2108 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2109 uint chan;
2110 unsigned char swizzles[4];
2111 int8_t offsets[3];
2112
2113 /* always fetch all 3 offsets, overkill but keeps code simple */
2114 fetch_texel_offsets(mach, inst, offsets);
2115
2116 assert(modifier != TEX_MODIFIER_PROJECTED);
2117
2118 if (modifier != TEX_MODIFIER_NONE) {
2119 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2120 FETCH(&c1, 3, TGSI_CHAN_X);
2121 lod = &c1;
2122 control = tgsi_sampler_lod_bias;
2123 }
2124 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2125 FETCH(&c1, 3, TGSI_CHAN_X);
2126 lod = &c1;
2127 control = tgsi_sampler_lod_explicit;
2128 }
2129 else {
2130 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2131 control = tgsi_sampler_lod_zero;
2132 }
2133 }
2134
2135 FETCH(&r[0], 0, TGSI_CHAN_X);
2136
2137 switch (mach->SamplerViews[resource_unit].Resource) {
2138 case TGSI_TEXTURE_1D:
2139 if (compare) {
2140 FETCH(&r[2], 3, TGSI_CHAN_X);
2141 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2142 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2143 NULL, offsets, control,
2144 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2145 }
2146 else {
2147 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2148 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2149 NULL, offsets, control,
2150 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2151 }
2152 break;
2153
2154 case TGSI_TEXTURE_1D_ARRAY:
2155 case TGSI_TEXTURE_2D:
2156 case TGSI_TEXTURE_RECT:
2157 FETCH(&r[1], 0, TGSI_CHAN_Y);
2158 if (compare) {
2159 FETCH(&r[2], 3, TGSI_CHAN_X);
2160 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2161 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2162 NULL, offsets, control,
2163 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2164 }
2165 else {
2166 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2167 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2168 NULL, offsets, control,
2169 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2170 }
2171 break;
2172
2173 case TGSI_TEXTURE_2D_ARRAY:
2174 case TGSI_TEXTURE_3D:
2175 case TGSI_TEXTURE_CUBE:
2176 FETCH(&r[1], 0, TGSI_CHAN_Y);
2177 FETCH(&r[2], 0, TGSI_CHAN_Z);
2178 if(compare) {
2179 FETCH(&r[3], 3, TGSI_CHAN_X);
2180 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2181 &r[0], &r[1], &r[2], &r[3], lod,
2182 NULL, offsets, control,
2183 &r[0], &r[1], &r[2], &r[3]);
2184 }
2185 else {
2186 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2187 &r[0], &r[1], &r[2], &ZeroVec, lod,
2188 NULL, offsets, control,
2189 &r[0], &r[1], &r[2], &r[3]);
2190 }
2191 break;
2192
2193 case TGSI_TEXTURE_CUBE_ARRAY:
2194 FETCH(&r[1], 0, TGSI_CHAN_Y);
2195 FETCH(&r[2], 0, TGSI_CHAN_Z);
2196 FETCH(&r[3], 0, TGSI_CHAN_W);
2197 if(compare) {
2198 FETCH(&r[4], 3, TGSI_CHAN_X);
2199 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2200 &r[0], &r[1], &r[2], &r[3], &r[4],
2201 NULL, offsets, control,
2202 &r[0], &r[1], &r[2], &r[3]);
2203 }
2204 else {
2205 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2206 &r[0], &r[1], &r[2], &r[3], lod,
2207 NULL, offsets, control,
2208 &r[0], &r[1], &r[2], &r[3]);
2209 }
2210 break;
2211
2212
2213 default:
2214 assert(0);
2215 }
2216
2217 swizzles[0] = inst->Src[1].Register.SwizzleX;
2218 swizzles[1] = inst->Src[1].Register.SwizzleY;
2219 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2220 swizzles[3] = inst->Src[1].Register.SwizzleW;
2221
2222 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2223 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2224 store_dest(mach, &r[swizzles[chan]],
2225 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2226 }
2227 }
2228 }
2229
2230 static void
2231 exec_sample_d(struct tgsi_exec_machine *mach,
2232 const struct tgsi_full_instruction *inst)
2233 {
2234 const uint resource_unit = inst->Src[1].Register.Index;
2235 const uint sampler_unit = inst->Src[2].Register.Index;
2236 union tgsi_exec_channel r[4];
2237 float derivs[3][2][TGSI_QUAD_SIZE];
2238 uint chan;
2239 unsigned char swizzles[4];
2240 int8_t offsets[3];
2241
2242 /* always fetch all 3 offsets, overkill but keeps code simple */
2243 fetch_texel_offsets(mach, inst, offsets);
2244
2245 FETCH(&r[0], 0, TGSI_CHAN_X);
2246
2247 switch (mach->SamplerViews[resource_unit].Resource) {
2248 case TGSI_TEXTURE_1D:
2249 case TGSI_TEXTURE_1D_ARRAY:
2250 /* only 1D array actually needs Y */
2251 FETCH(&r[1], 0, TGSI_CHAN_Y);
2252
2253 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2254
2255 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2256 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2257 derivs, offsets, tgsi_sampler_derivs_explicit,
2258 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2259 break;
2260
2261 case TGSI_TEXTURE_2D:
2262 case TGSI_TEXTURE_RECT:
2263 case TGSI_TEXTURE_2D_ARRAY:
2264 /* only 2D array actually needs Z */
2265 FETCH(&r[1], 0, TGSI_CHAN_Y);
2266 FETCH(&r[2], 0, TGSI_CHAN_Z);
2267
2268 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2269 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2270
2271 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2272 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2273 derivs, offsets, tgsi_sampler_derivs_explicit,
2274 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2275 break;
2276
2277 case TGSI_TEXTURE_3D:
2278 case TGSI_TEXTURE_CUBE:
2279 case TGSI_TEXTURE_CUBE_ARRAY:
2280 /* only cube array actually needs W */
2281 FETCH(&r[1], 0, TGSI_CHAN_Y);
2282 FETCH(&r[2], 0, TGSI_CHAN_Z);
2283 FETCH(&r[3], 0, TGSI_CHAN_W);
2284
2285 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2286 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2287 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2288
2289 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2290 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2291 derivs, offsets, tgsi_sampler_derivs_explicit,
2292 &r[0], &r[1], &r[2], &r[3]);
2293 break;
2294
2295 default:
2296 assert(0);
2297 }
2298
2299 swizzles[0] = inst->Src[1].Register.SwizzleX;
2300 swizzles[1] = inst->Src[1].Register.SwizzleY;
2301 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2302 swizzles[3] = inst->Src[1].Register.SwizzleW;
2303
2304 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2305 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2306 store_dest(mach, &r[swizzles[chan]],
2307 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2308 }
2309 }
2310 }
2311
2312
2313 /**
2314 * Evaluate a constant-valued coefficient at the position of the
2315 * current quad.
2316 */
2317 static void
2318 eval_constant_coef(
2319 struct tgsi_exec_machine *mach,
2320 unsigned attrib,
2321 unsigned chan )
2322 {
2323 unsigned i;
2324
2325 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2326 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2327 }
2328 }
2329
2330 /**
2331 * Evaluate a linear-valued coefficient at the position of the
2332 * current quad.
2333 */
2334 static void
2335 eval_linear_coef(
2336 struct tgsi_exec_machine *mach,
2337 unsigned attrib,
2338 unsigned chan )
2339 {
2340 const float x = mach->QuadPos.xyzw[0].f[0];
2341 const float y = mach->QuadPos.xyzw[1].f[0];
2342 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2343 const float dady = mach->InterpCoefs[attrib].dady[chan];
2344 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2345 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2346 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2347 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2348 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2349 }
2350
2351 /**
2352 * Evaluate a perspective-valued coefficient at the position of the
2353 * current quad.
2354 */
2355 static void
2356 eval_perspective_coef(
2357 struct tgsi_exec_machine *mach,
2358 unsigned attrib,
2359 unsigned chan )
2360 {
2361 const float x = mach->QuadPos.xyzw[0].f[0];
2362 const float y = mach->QuadPos.xyzw[1].f[0];
2363 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2364 const float dady = mach->InterpCoefs[attrib].dady[chan];
2365 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2366 const float *w = mach->QuadPos.xyzw[3].f;
2367 /* divide by W here */
2368 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2369 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2370 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2371 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2372 }
2373
2374
2375 typedef void (* eval_coef_func)(
2376 struct tgsi_exec_machine *mach,
2377 unsigned attrib,
2378 unsigned chan );
2379
2380 static void
2381 exec_declaration(struct tgsi_exec_machine *mach,
2382 const struct tgsi_full_declaration *decl)
2383 {
2384 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2385 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2386 return;
2387 }
2388
2389 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2390 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2391 uint first, last, mask;
2392
2393 first = decl->Range.First;
2394 last = decl->Range.Last;
2395 mask = decl->Declaration.UsageMask;
2396
2397 /* XXX we could remove this special-case code since
2398 * mach->InterpCoefs[first].a0 should already have the
2399 * front/back-face value. But we should first update the
2400 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2401 * Then, we could remove the tgsi_exec_machine::Face field.
2402 */
2403 /* XXX make FACE a system value */
2404 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2405 uint i;
2406
2407 assert(decl->Semantic.Index == 0);
2408 assert(first == last);
2409
2410 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2411 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2412 }
2413 } else {
2414 eval_coef_func eval;
2415 uint i, j;
2416
2417 switch (decl->Interp.Interpolate) {
2418 case TGSI_INTERPOLATE_CONSTANT:
2419 eval = eval_constant_coef;
2420 break;
2421
2422 case TGSI_INTERPOLATE_LINEAR:
2423 eval = eval_linear_coef;
2424 break;
2425
2426 case TGSI_INTERPOLATE_PERSPECTIVE:
2427 eval = eval_perspective_coef;
2428 break;
2429
2430 case TGSI_INTERPOLATE_COLOR:
2431 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2432 break;
2433
2434 default:
2435 assert(0);
2436 return;
2437 }
2438
2439 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2440 if (mask & (1 << j)) {
2441 for (i = first; i <= last; i++) {
2442 eval(mach, i, j);
2443 }
2444 }
2445 }
2446 }
2447
2448 if (DEBUG_EXECUTION) {
2449 uint i, j;
2450 for (i = first; i <= last; ++i) {
2451 debug_printf("IN[%2u] = ", i);
2452 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2453 if (j > 0) {
2454 debug_printf(" ");
2455 }
2456 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2457 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2458 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2459 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2460 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2461 }
2462 }
2463 }
2464 }
2465 }
2466
2467 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2468 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2469 }
2470 }
2471
2472
2473 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2474
2475 static void
2476 exec_vector(struct tgsi_exec_machine *mach,
2477 const struct tgsi_full_instruction *inst,
2478 micro_op op,
2479 enum tgsi_exec_datatype dst_datatype)
2480 {
2481 unsigned int chan;
2482
2483 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2484 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2485 union tgsi_exec_channel dst;
2486
2487 op(&dst);
2488 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2489 }
2490 }
2491 }
2492
2493 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2494 const union tgsi_exec_channel *src);
2495
2496 static void
2497 exec_scalar_unary(struct tgsi_exec_machine *mach,
2498 const struct tgsi_full_instruction *inst,
2499 micro_unary_op op,
2500 enum tgsi_exec_datatype dst_datatype,
2501 enum tgsi_exec_datatype src_datatype)
2502 {
2503 unsigned int chan;
2504 union tgsi_exec_channel src;
2505 union tgsi_exec_channel dst;
2506
2507 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2508 op(&dst, &src);
2509 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2510 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2511 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2512 }
2513 }
2514 }
2515
2516 static void
2517 exec_vector_unary(struct tgsi_exec_machine *mach,
2518 const struct tgsi_full_instruction *inst,
2519 micro_unary_op op,
2520 enum tgsi_exec_datatype dst_datatype,
2521 enum tgsi_exec_datatype src_datatype)
2522 {
2523 unsigned int chan;
2524 struct tgsi_exec_vector dst;
2525
2526 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2527 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2528 union tgsi_exec_channel src;
2529
2530 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2531 op(&dst.xyzw[chan], &src);
2532 }
2533 }
2534 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2535 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2536 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2537 }
2538 }
2539 }
2540
2541 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2542 const union tgsi_exec_channel *src0,
2543 const union tgsi_exec_channel *src1);
2544
2545 static void
2546 exec_scalar_binary(struct tgsi_exec_machine *mach,
2547 const struct tgsi_full_instruction *inst,
2548 micro_binary_op op,
2549 enum tgsi_exec_datatype dst_datatype,
2550 enum tgsi_exec_datatype src_datatype)
2551 {
2552 unsigned int chan;
2553 union tgsi_exec_channel src[2];
2554 union tgsi_exec_channel dst;
2555
2556 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2557 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2558 op(&dst, &src[0], &src[1]);
2559 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2560 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2561 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2562 }
2563 }
2564 }
2565
2566 static void
2567 exec_vector_binary(struct tgsi_exec_machine *mach,
2568 const struct tgsi_full_instruction *inst,
2569 micro_binary_op op,
2570 enum tgsi_exec_datatype dst_datatype,
2571 enum tgsi_exec_datatype src_datatype)
2572 {
2573 unsigned int chan;
2574 struct tgsi_exec_vector dst;
2575
2576 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2577 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2578 union tgsi_exec_channel src[2];
2579
2580 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2581 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2582 op(&dst.xyzw[chan], &src[0], &src[1]);
2583 }
2584 }
2585 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2586 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2587 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2588 }
2589 }
2590 }
2591
2592 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2593 const union tgsi_exec_channel *src0,
2594 const union tgsi_exec_channel *src1,
2595 const union tgsi_exec_channel *src2);
2596
2597 static void
2598 exec_vector_trinary(struct tgsi_exec_machine *mach,
2599 const struct tgsi_full_instruction *inst,
2600 micro_trinary_op op,
2601 enum tgsi_exec_datatype dst_datatype,
2602 enum tgsi_exec_datatype src_datatype)
2603 {
2604 unsigned int chan;
2605 struct tgsi_exec_vector dst;
2606
2607 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2608 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2609 union tgsi_exec_channel src[3];
2610
2611 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2612 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2613 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2614 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2615 }
2616 }
2617 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2618 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2619 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2620 }
2621 }
2622 }
2623
2624 static void
2625 exec_dp3(struct tgsi_exec_machine *mach,
2626 const struct tgsi_full_instruction *inst)
2627 {
2628 unsigned int chan;
2629 union tgsi_exec_channel arg[3];
2630
2631 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2632 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2633 micro_mul(&arg[2], &arg[0], &arg[1]);
2634
2635 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2636 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2637 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2638 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2639 }
2640
2641 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2642 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2643 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2644 }
2645 }
2646 }
2647
2648 static void
2649 exec_dp4(struct tgsi_exec_machine *mach,
2650 const struct tgsi_full_instruction *inst)
2651 {
2652 unsigned int chan;
2653 union tgsi_exec_channel arg[3];
2654
2655 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2656 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2657 micro_mul(&arg[2], &arg[0], &arg[1]);
2658
2659 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2660 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2661 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2662 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2663 }
2664
2665 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2666 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2667 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2668 }
2669 }
2670 }
2671
2672 static void
2673 exec_dp2a(struct tgsi_exec_machine *mach,
2674 const struct tgsi_full_instruction *inst)
2675 {
2676 unsigned int chan;
2677 union tgsi_exec_channel arg[3];
2678
2679 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2680 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2681 micro_mul(&arg[2], &arg[0], &arg[1]);
2682
2683 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2684 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2685 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2686
2687 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2688 micro_add(&arg[0], &arg[0], &arg[1]);
2689
2690 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2691 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2692 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2693 }
2694 }
2695 }
2696
2697 static void
2698 exec_dph(struct tgsi_exec_machine *mach,
2699 const struct tgsi_full_instruction *inst)
2700 {
2701 unsigned int chan;
2702 union tgsi_exec_channel arg[3];
2703
2704 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2705 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2706 micro_mul(&arg[2], &arg[0], &arg[1]);
2707
2708 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2709 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2710 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2711
2712 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2713 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2714 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2715
2716 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2717 micro_add(&arg[0], &arg[0], &arg[1]);
2718
2719 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2720 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2721 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2722 }
2723 }
2724 }
2725
2726 static void
2727 exec_dp2(struct tgsi_exec_machine *mach,
2728 const struct tgsi_full_instruction *inst)
2729 {
2730 unsigned int chan;
2731 union tgsi_exec_channel arg[3];
2732
2733 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2734 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2735 micro_mul(&arg[2], &arg[0], &arg[1]);
2736
2737 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2738 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2739 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2740
2741 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2742 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2743 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2744 }
2745 }
2746 }
2747
2748 static void
2749 exec_nrm4(struct tgsi_exec_machine *mach,
2750 const struct tgsi_full_instruction *inst)
2751 {
2752 unsigned int chan;
2753 union tgsi_exec_channel arg[4];
2754 union tgsi_exec_channel scale;
2755
2756 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2757 micro_mul(&scale, &arg[0], &arg[0]);
2758
2759 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2760 union tgsi_exec_channel product;
2761
2762 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2763 micro_mul(&product, &arg[chan], &arg[chan]);
2764 micro_add(&scale, &scale, &product);
2765 }
2766
2767 micro_rsq(&scale, &scale);
2768
2769 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_W; chan++) {
2770 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2771 micro_mul(&arg[chan], &arg[chan], &scale);
2772 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2773 }
2774 }
2775 }
2776
2777 static void
2778 exec_nrm3(struct tgsi_exec_machine *mach,
2779 const struct tgsi_full_instruction *inst)
2780 {
2781 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2782 unsigned int chan;
2783 union tgsi_exec_channel arg[3];
2784 union tgsi_exec_channel scale;
2785
2786 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2787 micro_mul(&scale, &arg[0], &arg[0]);
2788
2789 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2790 union tgsi_exec_channel product;
2791
2792 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2793 micro_mul(&product, &arg[chan], &arg[chan]);
2794 micro_add(&scale, &scale, &product);
2795 }
2796
2797 micro_rsq(&scale, &scale);
2798
2799 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_Z; chan++) {
2800 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2801 micro_mul(&arg[chan], &arg[chan], &scale);
2802 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2803 }
2804 }
2805 }
2806
2807 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2808 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2809 }
2810 }
2811
2812 static void
2813 exec_scs(struct tgsi_exec_machine *mach,
2814 const struct tgsi_full_instruction *inst)
2815 {
2816 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2817 union tgsi_exec_channel arg;
2818 union tgsi_exec_channel result;
2819
2820 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2821
2822 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2823 micro_cos(&result, &arg);
2824 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2825 }
2826 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2827 micro_sin(&result, &arg);
2828 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2829 }
2830 }
2831 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2832 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2833 }
2834 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2835 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2836 }
2837 }
2838
2839 static void
2840 exec_x2d(struct tgsi_exec_machine *mach,
2841 const struct tgsi_full_instruction *inst)
2842 {
2843 union tgsi_exec_channel r[4];
2844 union tgsi_exec_channel d[2];
2845
2846 fetch_source(mach, &r[0], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2847 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2848 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2849 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2850 micro_mul(&r[2], &r[2], &r[0]);
2851 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2852 micro_mul(&r[3], &r[3], &r[1]);
2853 micro_add(&r[2], &r[2], &r[3]);
2854 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2855 micro_add(&d[0], &r[2], &r[3]);
2856 }
2857 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2858 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2859 micro_mul(&r[2], &r[2], &r[0]);
2860 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2861 micro_mul(&r[3], &r[3], &r[1]);
2862 micro_add(&r[2], &r[2], &r[3]);
2863 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2864 micro_add(&d[1], &r[2], &r[3]);
2865 }
2866 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2867 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2868 }
2869 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2870 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2871 }
2872 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2873 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2874 }
2875 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2876 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2877 }
2878 }
2879
2880 static void
2881 exec_rfl(struct tgsi_exec_machine *mach,
2882 const struct tgsi_full_instruction *inst)
2883 {
2884 union tgsi_exec_channel r[9];
2885
2886 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2887 /* r0 = dp3(src0, src0) */
2888 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2889 micro_mul(&r[0], &r[2], &r[2]);
2890 fetch_source(mach, &r[4], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2891 micro_mul(&r[8], &r[4], &r[4]);
2892 micro_add(&r[0], &r[0], &r[8]);
2893 fetch_source(mach, &r[6], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2894 micro_mul(&r[8], &r[6], &r[6]);
2895 micro_add(&r[0], &r[0], &r[8]);
2896
2897 /* r1 = dp3(src0, src1) */
2898 fetch_source(mach, &r[3], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2899 micro_mul(&r[1], &r[2], &r[3]);
2900 fetch_source(mach, &r[5], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2901 micro_mul(&r[8], &r[4], &r[5]);
2902 micro_add(&r[1], &r[1], &r[8]);
2903 fetch_source(mach, &r[7], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2904 micro_mul(&r[8], &r[6], &r[7]);
2905 micro_add(&r[1], &r[1], &r[8]);
2906
2907 /* r1 = 2 * r1 / r0 */
2908 micro_add(&r[1], &r[1], &r[1]);
2909 micro_div(&r[1], &r[1], &r[0]);
2910
2911 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2912 micro_mul(&r[2], &r[2], &r[1]);
2913 micro_sub(&r[2], &r[2], &r[3]);
2914 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2915 }
2916 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2917 micro_mul(&r[4], &r[4], &r[1]);
2918 micro_sub(&r[4], &r[4], &r[5]);
2919 store_dest(mach, &r[4], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2920 }
2921 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2922 micro_mul(&r[6], &r[6], &r[1]);
2923 micro_sub(&r[6], &r[6], &r[7]);
2924 store_dest(mach, &r[6], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2925 }
2926 }
2927 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2928 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2929 }
2930 }
2931
2932 static void
2933 exec_xpd(struct tgsi_exec_machine *mach,
2934 const struct tgsi_full_instruction *inst)
2935 {
2936 union tgsi_exec_channel r[6];
2937 union tgsi_exec_channel d[3];
2938
2939 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2940 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2941
2942 micro_mul(&r[2], &r[0], &r[1]);
2943
2944 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2945 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2946
2947 micro_mul(&r[5], &r[3], &r[4] );
2948 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
2949
2950 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2951
2952 micro_mul(&r[3], &r[3], &r[2]);
2953
2954 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2955
2956 micro_mul(&r[1], &r[1], &r[5]);
2957 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
2958
2959 micro_mul(&r[5], &r[5], &r[4]);
2960 micro_mul(&r[0], &r[0], &r[2]);
2961 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
2962
2963 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2964 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2965 }
2966 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2967 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2968 }
2969 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2970 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2971 }
2972 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2973 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2974 }
2975 }
2976
2977 static void
2978 exec_dst(struct tgsi_exec_machine *mach,
2979 const struct tgsi_full_instruction *inst)
2980 {
2981 union tgsi_exec_channel r[2];
2982 union tgsi_exec_channel d[4];
2983
2984 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2985 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2986 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2987 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
2988 }
2989 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2990 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2991 }
2992 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2993 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2994 }
2995
2996 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2997 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2998 }
2999 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3000 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3001 }
3002 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3003 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3004 }
3005 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3006 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3007 }
3008 }
3009
3010 static void
3011 exec_log(struct tgsi_exec_machine *mach,
3012 const struct tgsi_full_instruction *inst)
3013 {
3014 union tgsi_exec_channel r[3];
3015
3016 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3017 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3018 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3019 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3020 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3021 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3022 }
3023 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3024 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3025 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3026 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3027 }
3028 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3029 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3030 }
3031 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3032 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3033 }
3034 }
3035
3036 static void
3037 exec_exp(struct tgsi_exec_machine *mach,
3038 const struct tgsi_full_instruction *inst)
3039 {
3040 union tgsi_exec_channel r[3];
3041
3042 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3043 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3044 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3045 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3046 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3047 }
3048 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3049 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3050 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3051 }
3052 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3053 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3054 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3055 }
3056 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3057 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3058 }
3059 }
3060
3061 static void
3062 exec_lit(struct tgsi_exec_machine *mach,
3063 const struct tgsi_full_instruction *inst)
3064 {
3065 union tgsi_exec_channel r[3];
3066 union tgsi_exec_channel d[3];
3067
3068 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3069 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3070 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3071 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3072 micro_max(&r[1], &r[1], &ZeroVec);
3073
3074 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3075 micro_min(&r[2], &r[2], &P128Vec);
3076 micro_max(&r[2], &r[2], &M128Vec);
3077 micro_pow(&r[1], &r[1], &r[2]);
3078 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3079 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3080 }
3081 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3082 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3083 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3084 }
3085 }
3086 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3087 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3088 }
3089
3090 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3091 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3092 }
3093 }
3094
3095 static void
3096 exec_break(struct tgsi_exec_machine *mach)
3097 {
3098 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3099 /* turn off loop channels for each enabled exec channel */
3100 mach->LoopMask &= ~mach->ExecMask;
3101 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3102 UPDATE_EXEC_MASK(mach);
3103 } else {
3104 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3105
3106 mach->Switch.mask = 0x0;
3107
3108 UPDATE_EXEC_MASK(mach);
3109 }
3110 }
3111
3112 static void
3113 exec_switch(struct tgsi_exec_machine *mach,
3114 const struct tgsi_full_instruction *inst)
3115 {
3116 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3117 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3118
3119 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3120 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3121 mach->Switch.mask = 0x0;
3122 mach->Switch.defaultMask = 0x0;
3123
3124 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3125 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3126
3127 UPDATE_EXEC_MASK(mach);
3128 }
3129
3130 static void
3131 exec_case(struct tgsi_exec_machine *mach,
3132 const struct tgsi_full_instruction *inst)
3133 {
3134 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3135 union tgsi_exec_channel src;
3136 uint mask = 0;
3137
3138 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3139
3140 if (mach->Switch.selector.u[0] == src.u[0]) {
3141 mask |= 0x1;
3142 }
3143 if (mach->Switch.selector.u[1] == src.u[1]) {
3144 mask |= 0x2;
3145 }
3146 if (mach->Switch.selector.u[2] == src.u[2]) {
3147 mask |= 0x4;
3148 }
3149 if (mach->Switch.selector.u[3] == src.u[3]) {
3150 mask |= 0x8;
3151 }
3152
3153 mach->Switch.defaultMask |= mask;
3154
3155 mach->Switch.mask |= mask & prevMask;
3156
3157 UPDATE_EXEC_MASK(mach);
3158 }
3159
3160 /* FIXME: this will only work if default is last */
3161 static void
3162 exec_default(struct tgsi_exec_machine *mach)
3163 {
3164 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3165
3166 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3167
3168 UPDATE_EXEC_MASK(mach);
3169 }
3170
3171 static void
3172 exec_endswitch(struct tgsi_exec_machine *mach)
3173 {
3174 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3175 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3176
3177 UPDATE_EXEC_MASK(mach);
3178 }
3179
3180 static void
3181 micro_i2f(union tgsi_exec_channel *dst,
3182 const union tgsi_exec_channel *src)
3183 {
3184 dst->f[0] = (float)src->i[0];
3185 dst->f[1] = (float)src->i[1];
3186 dst->f[2] = (float)src->i[2];
3187 dst->f[3] = (float)src->i[3];
3188 }
3189
3190 static void
3191 micro_not(union tgsi_exec_channel *dst,
3192 const union tgsi_exec_channel *src)
3193 {
3194 dst->u[0] = ~src->u[0];
3195 dst->u[1] = ~src->u[1];
3196 dst->u[2] = ~src->u[2];
3197 dst->u[3] = ~src->u[3];
3198 }
3199
3200 static void
3201 micro_shl(union tgsi_exec_channel *dst,
3202 const union tgsi_exec_channel *src0,
3203 const union tgsi_exec_channel *src1)
3204 {
3205 unsigned masked_count;
3206 masked_count = src1->u[0] & 0x1f;
3207 dst->u[0] = src0->u[0] << masked_count;
3208 masked_count = src1->u[1] & 0x1f;
3209 dst->u[1] = src0->u[1] << masked_count;
3210 masked_count = src1->u[2] & 0x1f;
3211 dst->u[2] = src0->u[2] << masked_count;
3212 masked_count = src1->u[3] & 0x1f;
3213 dst->u[3] = src0->u[3] << masked_count;
3214 }
3215
3216 static void
3217 micro_and(union tgsi_exec_channel *dst,
3218 const union tgsi_exec_channel *src0,
3219 const union tgsi_exec_channel *src1)
3220 {
3221 dst->u[0] = src0->u[0] & src1->u[0];
3222 dst->u[1] = src0->u[1] & src1->u[1];
3223 dst->u[2] = src0->u[2] & src1->u[2];
3224 dst->u[3] = src0->u[3] & src1->u[3];
3225 }
3226
3227 static void
3228 micro_or(union tgsi_exec_channel *dst,
3229 const union tgsi_exec_channel *src0,
3230 const union tgsi_exec_channel *src1)
3231 {
3232 dst->u[0] = src0->u[0] | src1->u[0];
3233 dst->u[1] = src0->u[1] | src1->u[1];
3234 dst->u[2] = src0->u[2] | src1->u[2];
3235 dst->u[3] = src0->u[3] | src1->u[3];
3236 }
3237
3238 static void
3239 micro_xor(union tgsi_exec_channel *dst,
3240 const union tgsi_exec_channel *src0,
3241 const union tgsi_exec_channel *src1)
3242 {
3243 dst->u[0] = src0->u[0] ^ src1->u[0];
3244 dst->u[1] = src0->u[1] ^ src1->u[1];
3245 dst->u[2] = src0->u[2] ^ src1->u[2];
3246 dst->u[3] = src0->u[3] ^ src1->u[3];
3247 }
3248
3249 static void
3250 micro_mod(union tgsi_exec_channel *dst,
3251 const union tgsi_exec_channel *src0,
3252 const union tgsi_exec_channel *src1)
3253 {
3254 dst->i[0] = src0->i[0] % src1->i[0];
3255 dst->i[1] = src0->i[1] % src1->i[1];
3256 dst->i[2] = src0->i[2] % src1->i[2];
3257 dst->i[3] = src0->i[3] % src1->i[3];
3258 }
3259
3260 static void
3261 micro_f2i(union tgsi_exec_channel *dst,
3262 const union tgsi_exec_channel *src)
3263 {
3264 dst->i[0] = (int)src->f[0];
3265 dst->i[1] = (int)src->f[1];
3266 dst->i[2] = (int)src->f[2];
3267 dst->i[3] = (int)src->f[3];
3268 }
3269
3270 static void
3271 micro_fseq(union tgsi_exec_channel *dst,
3272 const union tgsi_exec_channel *src0,
3273 const union tgsi_exec_channel *src1)
3274 {
3275 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
3276 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
3277 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
3278 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
3279 }
3280
3281 static void
3282 micro_fsge(union tgsi_exec_channel *dst,
3283 const union tgsi_exec_channel *src0,
3284 const union tgsi_exec_channel *src1)
3285 {
3286 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
3287 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
3288 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
3289 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
3290 }
3291
3292 static void
3293 micro_fslt(union tgsi_exec_channel *dst,
3294 const union tgsi_exec_channel *src0,
3295 const union tgsi_exec_channel *src1)
3296 {
3297 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
3298 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
3299 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
3300 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
3301 }
3302
3303 static void
3304 micro_fsne(union tgsi_exec_channel *dst,
3305 const union tgsi_exec_channel *src0,
3306 const union tgsi_exec_channel *src1)
3307 {
3308 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
3309 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
3310 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
3311 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
3312 }
3313
3314 static void
3315 micro_idiv(union tgsi_exec_channel *dst,
3316 const union tgsi_exec_channel *src0,
3317 const union tgsi_exec_channel *src1)
3318 {
3319 dst->i[0] = src0->i[0] / src1->i[0];
3320 dst->i[1] = src0->i[1] / src1->i[1];
3321 dst->i[2] = src0->i[2] / src1->i[2];
3322 dst->i[3] = src0->i[3] / src1->i[3];
3323 }
3324
3325 static void
3326 micro_imax(union tgsi_exec_channel *dst,
3327 const union tgsi_exec_channel *src0,
3328 const union tgsi_exec_channel *src1)
3329 {
3330 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3331 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3332 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3333 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3334 }
3335
3336 static void
3337 micro_imin(union tgsi_exec_channel *dst,
3338 const union tgsi_exec_channel *src0,
3339 const union tgsi_exec_channel *src1)
3340 {
3341 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3342 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3343 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3344 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3345 }
3346
3347 static void
3348 micro_isge(union tgsi_exec_channel *dst,
3349 const union tgsi_exec_channel *src0,
3350 const union tgsi_exec_channel *src1)
3351 {
3352 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3353 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3354 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3355 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3356 }
3357
3358 static void
3359 micro_ishr(union tgsi_exec_channel *dst,
3360 const union tgsi_exec_channel *src0,
3361 const union tgsi_exec_channel *src1)
3362 {
3363 unsigned masked_count;
3364 masked_count = src1->i[0] & 0x1f;
3365 dst->i[0] = src0->i[0] >> masked_count;
3366 masked_count = src1->i[1] & 0x1f;
3367 dst->i[1] = src0->i[1] >> masked_count;
3368 masked_count = src1->i[2] & 0x1f;
3369 dst->i[2] = src0->i[2] >> masked_count;
3370 masked_count = src1->i[3] & 0x1f;
3371 dst->i[3] = src0->i[3] >> masked_count;
3372 }
3373
3374 static void
3375 micro_islt(union tgsi_exec_channel *dst,
3376 const union tgsi_exec_channel *src0,
3377 const union tgsi_exec_channel *src1)
3378 {
3379 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3380 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3381 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3382 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3383 }
3384
3385 static void
3386 micro_f2u(union tgsi_exec_channel *dst,
3387 const union tgsi_exec_channel *src)
3388 {
3389 dst->u[0] = (uint)src->f[0];
3390 dst->u[1] = (uint)src->f[1];
3391 dst->u[2] = (uint)src->f[2];
3392 dst->u[3] = (uint)src->f[3];
3393 }
3394
3395 static void
3396 micro_u2f(union tgsi_exec_channel *dst,
3397 const union tgsi_exec_channel *src)
3398 {
3399 dst->f[0] = (float)src->u[0];
3400 dst->f[1] = (float)src->u[1];
3401 dst->f[2] = (float)src->u[2];
3402 dst->f[3] = (float)src->u[3];
3403 }
3404
3405 static void
3406 micro_uadd(union tgsi_exec_channel *dst,
3407 const union tgsi_exec_channel *src0,
3408 const union tgsi_exec_channel *src1)
3409 {
3410 dst->u[0] = src0->u[0] + src1->u[0];
3411 dst->u[1] = src0->u[1] + src1->u[1];
3412 dst->u[2] = src0->u[2] + src1->u[2];
3413 dst->u[3] = src0->u[3] + src1->u[3];
3414 }
3415
3416 static void
3417 micro_udiv(union tgsi_exec_channel *dst,
3418 const union tgsi_exec_channel *src0,
3419 const union tgsi_exec_channel *src1)
3420 {
3421 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
3422 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
3423 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
3424 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
3425 }
3426
3427 static void
3428 micro_umad(union tgsi_exec_channel *dst,
3429 const union tgsi_exec_channel *src0,
3430 const union tgsi_exec_channel *src1,
3431 const union tgsi_exec_channel *src2)
3432 {
3433 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3434 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3435 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3436 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3437 }
3438
3439 static void
3440 micro_umax(union tgsi_exec_channel *dst,
3441 const union tgsi_exec_channel *src0,
3442 const union tgsi_exec_channel *src1)
3443 {
3444 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3445 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3446 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3447 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3448 }
3449
3450 static void
3451 micro_umin(union tgsi_exec_channel *dst,
3452 const union tgsi_exec_channel *src0,
3453 const union tgsi_exec_channel *src1)
3454 {
3455 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3456 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3457 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3458 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3459 }
3460
3461 static void
3462 micro_umod(union tgsi_exec_channel *dst,
3463 const union tgsi_exec_channel *src0,
3464 const union tgsi_exec_channel *src1)
3465 {
3466 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
3467 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
3468 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
3469 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
3470 }
3471
3472 static void
3473 micro_umul(union tgsi_exec_channel *dst,
3474 const union tgsi_exec_channel *src0,
3475 const union tgsi_exec_channel *src1)
3476 {
3477 dst->u[0] = src0->u[0] * src1->u[0];
3478 dst->u[1] = src0->u[1] * src1->u[1];
3479 dst->u[2] = src0->u[2] * src1->u[2];
3480 dst->u[3] = src0->u[3] * src1->u[3];
3481 }
3482
3483 static void
3484 micro_imul_hi(union tgsi_exec_channel *dst,
3485 const union tgsi_exec_channel *src0,
3486 const union tgsi_exec_channel *src1)
3487 {
3488 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3489 dst->i[0] = I64M(src0->i[0], src1->i[0]);
3490 dst->i[1] = I64M(src0->i[1], src1->i[1]);
3491 dst->i[2] = I64M(src0->i[2], src1->i[2]);
3492 dst->i[3] = I64M(src0->i[3], src1->i[3]);
3493 #undef I64M
3494 }
3495
3496 static void
3497 micro_umul_hi(union tgsi_exec_channel *dst,
3498 const union tgsi_exec_channel *src0,
3499 const union tgsi_exec_channel *src1)
3500 {
3501 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3502 dst->u[0] = U64M(src0->u[0], src1->u[0]);
3503 dst->u[1] = U64M(src0->u[1], src1->u[1]);
3504 dst->u[2] = U64M(src0->u[2], src1->u[2]);
3505 dst->u[3] = U64M(src0->u[3], src1->u[3]);
3506 #undef U64M
3507 }
3508
3509 static void
3510 micro_useq(union tgsi_exec_channel *dst,
3511 const union tgsi_exec_channel *src0,
3512 const union tgsi_exec_channel *src1)
3513 {
3514 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3515 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3516 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3517 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3518 }
3519
3520 static void
3521 micro_usge(union tgsi_exec_channel *dst,
3522 const union tgsi_exec_channel *src0,
3523 const union tgsi_exec_channel *src1)
3524 {
3525 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3526 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3527 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3528 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3529 }
3530
3531 static void
3532 micro_ushr(union tgsi_exec_channel *dst,
3533 const union tgsi_exec_channel *src0,
3534 const union tgsi_exec_channel *src1)
3535 {
3536 unsigned masked_count;
3537 masked_count = src1->u[0] & 0x1f;
3538 dst->u[0] = src0->u[0] >> masked_count;
3539 masked_count = src1->u[1] & 0x1f;
3540 dst->u[1] = src0->u[1] >> masked_count;
3541 masked_count = src1->u[2] & 0x1f;
3542 dst->u[2] = src0->u[2] >> masked_count;
3543 masked_count = src1->u[3] & 0x1f;
3544 dst->u[3] = src0->u[3] >> masked_count;
3545 }
3546
3547 static void
3548 micro_uslt(union tgsi_exec_channel *dst,
3549 const union tgsi_exec_channel *src0,
3550 const union tgsi_exec_channel *src1)
3551 {
3552 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3553 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3554 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3555 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3556 }
3557
3558 static void
3559 micro_usne(union tgsi_exec_channel *dst,
3560 const union tgsi_exec_channel *src0,
3561 const union tgsi_exec_channel *src1)
3562 {
3563 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3564 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3565 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3566 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3567 }
3568
3569 static void
3570 micro_uarl(union tgsi_exec_channel *dst,
3571 const union tgsi_exec_channel *src)
3572 {
3573 dst->i[0] = src->u[0];
3574 dst->i[1] = src->u[1];
3575 dst->i[2] = src->u[2];
3576 dst->i[3] = src->u[3];
3577 }
3578
3579 static void
3580 micro_ucmp(union tgsi_exec_channel *dst,
3581 const union tgsi_exec_channel *src0,
3582 const union tgsi_exec_channel *src1,
3583 const union tgsi_exec_channel *src2)
3584 {
3585 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3586 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3587 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3588 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3589 }
3590
3591 static void
3592 exec_instruction(
3593 struct tgsi_exec_machine *mach,
3594 const struct tgsi_full_instruction *inst,
3595 int *pc )
3596 {
3597 union tgsi_exec_channel r[10];
3598
3599 (*pc)++;
3600
3601 switch (inst->Instruction.Opcode) {
3602 case TGSI_OPCODE_ARL:
3603 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3604 break;
3605
3606 case TGSI_OPCODE_MOV:
3607 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3608 break;
3609
3610 case TGSI_OPCODE_LIT:
3611 exec_lit(mach, inst);
3612 break;
3613
3614 case TGSI_OPCODE_RCP:
3615 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3616 break;
3617
3618 case TGSI_OPCODE_RSQ:
3619 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3620 break;
3621
3622 case TGSI_OPCODE_EXP:
3623 exec_exp(mach, inst);
3624 break;
3625
3626 case TGSI_OPCODE_LOG:
3627 exec_log(mach, inst);
3628 break;
3629
3630 case TGSI_OPCODE_MUL:
3631 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3632 break;
3633
3634 case TGSI_OPCODE_ADD:
3635 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3636 break;
3637
3638 case TGSI_OPCODE_DP3:
3639 exec_dp3(mach, inst);
3640 break;
3641
3642 case TGSI_OPCODE_DP4:
3643 exec_dp4(mach, inst);
3644 break;
3645
3646 case TGSI_OPCODE_DST:
3647 exec_dst(mach, inst);
3648 break;
3649
3650 case TGSI_OPCODE_MIN:
3651 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3652 break;
3653
3654 case TGSI_OPCODE_MAX:
3655 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3656 break;
3657
3658 case TGSI_OPCODE_SLT:
3659 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3660 break;
3661
3662 case TGSI_OPCODE_SGE:
3663 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3664 break;
3665
3666 case TGSI_OPCODE_MAD:
3667 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3668 break;
3669
3670 case TGSI_OPCODE_SUB:
3671 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3672 break;
3673
3674 case TGSI_OPCODE_LRP:
3675 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3676 break;
3677
3678 case TGSI_OPCODE_CND:
3679 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3680 break;
3681
3682 case TGSI_OPCODE_SQRT:
3683 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3684 break;
3685
3686 case TGSI_OPCODE_DP2A:
3687 exec_dp2a(mach, inst);
3688 break;
3689
3690 case TGSI_OPCODE_FRC:
3691 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3692 break;
3693
3694 case TGSI_OPCODE_CLAMP:
3695 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3696 break;
3697
3698 case TGSI_OPCODE_FLR:
3699 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3700 break;
3701
3702 case TGSI_OPCODE_ROUND:
3703 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3704 break;
3705
3706 case TGSI_OPCODE_EX2:
3707 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3708 break;
3709
3710 case TGSI_OPCODE_LG2:
3711 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3712 break;
3713
3714 case TGSI_OPCODE_POW:
3715 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3716 break;
3717
3718 case TGSI_OPCODE_XPD:
3719 exec_xpd(mach, inst);
3720 break;
3721
3722 case TGSI_OPCODE_ABS:
3723 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3724 break;
3725
3726 case TGSI_OPCODE_RCC:
3727 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3728 break;
3729
3730 case TGSI_OPCODE_DPH:
3731 exec_dph(mach, inst);
3732 break;
3733
3734 case TGSI_OPCODE_COS:
3735 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3736 break;
3737
3738 case TGSI_OPCODE_DDX:
3739 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3740 break;
3741
3742 case TGSI_OPCODE_DDY:
3743 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3744 break;
3745
3746 case TGSI_OPCODE_KILL:
3747 exec_kill (mach, inst);
3748 break;
3749
3750 case TGSI_OPCODE_KILL_IF:
3751 exec_kill_if (mach, inst);
3752 break;
3753
3754 case TGSI_OPCODE_PK2H:
3755 assert (0);
3756 break;
3757
3758 case TGSI_OPCODE_PK2US:
3759 assert (0);
3760 break;
3761
3762 case TGSI_OPCODE_PK4B:
3763 assert (0);
3764 break;
3765
3766 case TGSI_OPCODE_PK4UB:
3767 assert (0);
3768 break;
3769
3770 case TGSI_OPCODE_RFL:
3771 exec_rfl(mach, inst);
3772 break;
3773
3774 case TGSI_OPCODE_SEQ:
3775 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3776 break;
3777
3778 case TGSI_OPCODE_SFL:
3779 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3780 break;
3781
3782 case TGSI_OPCODE_SGT:
3783 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3784 break;
3785
3786 case TGSI_OPCODE_SIN:
3787 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3788 break;
3789
3790 case TGSI_OPCODE_SLE:
3791 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3792 break;
3793
3794 case TGSI_OPCODE_SNE:
3795 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3796 break;
3797
3798 case TGSI_OPCODE_STR:
3799 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3800 break;
3801
3802 case TGSI_OPCODE_TEX:
3803 /* simple texture lookup */
3804 /* src[0] = texcoord */
3805 /* src[1] = sampler unit */
3806 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
3807 break;
3808
3809 case TGSI_OPCODE_TXB:
3810 /* Texture lookup with lod bias */
3811 /* src[0] = texcoord (src[0].w = LOD bias) */
3812 /* src[1] = sampler unit */
3813 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
3814 break;
3815
3816 case TGSI_OPCODE_TXD:
3817 /* Texture lookup with explict partial derivatives */
3818 /* src[0] = texcoord */
3819 /* src[1] = d[strq]/dx */
3820 /* src[2] = d[strq]/dy */
3821 /* src[3] = sampler unit */
3822 exec_txd(mach, inst);
3823 break;
3824
3825 case TGSI_OPCODE_TXL:
3826 /* Texture lookup with explit LOD */
3827 /* src[0] = texcoord (src[0].w = LOD) */
3828 /* src[1] = sampler unit */
3829 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
3830 break;
3831
3832 case TGSI_OPCODE_TXP:
3833 /* Texture lookup with projection */
3834 /* src[0] = texcoord (src[0].w = projection) */
3835 /* src[1] = sampler unit */
3836 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
3837 break;
3838
3839 case TGSI_OPCODE_UP2H:
3840 assert (0);
3841 break;
3842
3843 case TGSI_OPCODE_UP2US:
3844 assert (0);
3845 break;
3846
3847 case TGSI_OPCODE_UP4B:
3848 assert (0);
3849 break;
3850
3851 case TGSI_OPCODE_UP4UB:
3852 assert (0);
3853 break;
3854
3855 case TGSI_OPCODE_X2D:
3856 exec_x2d(mach, inst);
3857 break;
3858
3859 case TGSI_OPCODE_ARA:
3860 assert (0);
3861 break;
3862
3863 case TGSI_OPCODE_ARR:
3864 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3865 break;
3866
3867 case TGSI_OPCODE_BRA:
3868 assert (0);
3869 break;
3870
3871 case TGSI_OPCODE_CAL:
3872 /* skip the call if no execution channels are enabled */
3873 if (mach->ExecMask) {
3874 /* do the call */
3875
3876 /* First, record the depths of the execution stacks.
3877 * This is important for deeply nested/looped return statements.
3878 * We have to unwind the stacks by the correct amount. For a
3879 * real code generator, we could determine the number of entries
3880 * to pop off each stack with simple static analysis and avoid
3881 * implementing this data structure at run time.
3882 */
3883 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3884 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3885 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3886 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3887 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3888 /* note that PC was already incremented above */
3889 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3890
3891 mach->CallStackTop++;
3892
3893 /* Second, push the Cond, Loop, Cont, Func stacks */
3894 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3895 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3896 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3897 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3898 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3899 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3900
3901 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3902 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3903 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3904 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3905 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3906 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3907
3908 /* Finally, jump to the subroutine */
3909 *pc = inst->Label.Label;
3910 }
3911 break;
3912
3913 case TGSI_OPCODE_RET:
3914 mach->FuncMask &= ~mach->ExecMask;
3915 UPDATE_EXEC_MASK(mach);
3916
3917 if (mach->FuncMask == 0x0) {
3918 /* really return now (otherwise, keep executing */
3919
3920 if (mach->CallStackTop == 0) {
3921 /* returning from main() */
3922 mach->CondStackTop = 0;
3923 mach->LoopStackTop = 0;
3924 *pc = -1;
3925 return;
3926 }
3927
3928 assert(mach->CallStackTop > 0);
3929 mach->CallStackTop--;
3930
3931 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3932 mach->CondMask = mach->CondStack[mach->CondStackTop];
3933
3934 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3935 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3936
3937 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3938 mach->ContMask = mach->ContStack[mach->ContStackTop];
3939
3940 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3941 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3942
3943 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3944 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3945
3946 assert(mach->FuncStackTop > 0);
3947 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3948
3949 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3950
3951 UPDATE_EXEC_MASK(mach);
3952 }
3953 break;
3954
3955 case TGSI_OPCODE_SSG:
3956 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3957 break;
3958
3959 case TGSI_OPCODE_CMP:
3960 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3961 break;
3962
3963 case TGSI_OPCODE_SCS:
3964 exec_scs(mach, inst);
3965 break;
3966
3967 case TGSI_OPCODE_NRM:
3968 exec_nrm3(mach, inst);
3969 break;
3970
3971 case TGSI_OPCODE_NRM4:
3972 exec_nrm4(mach, inst);
3973 break;
3974
3975 case TGSI_OPCODE_DIV:
3976 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3977 break;
3978
3979 case TGSI_OPCODE_DP2:
3980 exec_dp2(mach, inst);
3981 break;
3982
3983 case TGSI_OPCODE_IF:
3984 /* push CondMask */
3985 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3986 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3987 FETCH( &r[0], 0, TGSI_CHAN_X );
3988 /* update CondMask */
3989 if( ! r[0].f[0] ) {
3990 mach->CondMask &= ~0x1;
3991 }
3992 if( ! r[0].f[1] ) {
3993 mach->CondMask &= ~0x2;
3994 }
3995 if( ! r[0].f[2] ) {
3996 mach->CondMask &= ~0x4;
3997 }
3998 if( ! r[0].f[3] ) {
3999 mach->CondMask &= ~0x8;
4000 }
4001 UPDATE_EXEC_MASK(mach);
4002 /* Todo: If CondMask==0, jump to ELSE */
4003 break;
4004
4005 case TGSI_OPCODE_UIF:
4006 /* push CondMask */
4007 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4008 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4009 IFETCH( &r[0], 0, TGSI_CHAN_X );
4010 /* update CondMask */
4011 if( ! r[0].u[0] ) {
4012 mach->CondMask &= ~0x1;
4013 }
4014 if( ! r[0].u[1] ) {
4015 mach->CondMask &= ~0x2;
4016 }
4017 if( ! r[0].u[2] ) {
4018 mach->CondMask &= ~0x4;
4019 }
4020 if( ! r[0].u[3] ) {
4021 mach->CondMask &= ~0x8;
4022 }
4023 UPDATE_EXEC_MASK(mach);
4024 /* Todo: If CondMask==0, jump to ELSE */
4025 break;
4026
4027 case TGSI_OPCODE_ELSE:
4028 /* invert CondMask wrt previous mask */
4029 {
4030 uint prevMask;
4031 assert(mach->CondStackTop > 0);
4032 prevMask = mach->CondStack[mach->CondStackTop - 1];
4033 mach->CondMask = ~mach->CondMask & prevMask;
4034 UPDATE_EXEC_MASK(mach);
4035 /* Todo: If CondMask==0, jump to ENDIF */
4036 }
4037 break;
4038
4039 case TGSI_OPCODE_ENDIF:
4040 /* pop CondMask */
4041 assert(mach->CondStackTop > 0);
4042 mach->CondMask = mach->CondStack[--mach->CondStackTop];
4043 UPDATE_EXEC_MASK(mach);
4044 break;
4045
4046 case TGSI_OPCODE_END:
4047 /* make sure we end primitives which haven't
4048 * been explicitly emitted */
4049 conditional_emit_primitive(mach);
4050 /* halt execution */
4051 *pc = -1;
4052 break;
4053
4054 case TGSI_OPCODE_PUSHA:
4055 assert (0);
4056 break;
4057
4058 case TGSI_OPCODE_POPA:
4059 assert (0);
4060 break;
4061
4062 case TGSI_OPCODE_CEIL:
4063 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4064 break;
4065
4066 case TGSI_OPCODE_I2F:
4067 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
4068 break;
4069
4070 case TGSI_OPCODE_NOT:
4071 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4072 break;
4073
4074 case TGSI_OPCODE_TRUNC:
4075 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4076 break;
4077
4078 case TGSI_OPCODE_SHL:
4079 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4080 break;
4081
4082 case TGSI_OPCODE_AND:
4083 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4084 break;
4085
4086 case TGSI_OPCODE_OR:
4087 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4088 break;
4089
4090 case TGSI_OPCODE_MOD:
4091 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4092 break;
4093
4094 case TGSI_OPCODE_XOR:
4095 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4096 break;
4097
4098 case TGSI_OPCODE_SAD:
4099 assert (0);
4100 break;
4101
4102 case TGSI_OPCODE_TXF:
4103 exec_txf(mach, inst);
4104 break;
4105
4106 case TGSI_OPCODE_TXQ:
4107 exec_txq(mach, inst);
4108 break;
4109
4110 case TGSI_OPCODE_EMIT:
4111 emit_vertex(mach);
4112 break;
4113
4114 case TGSI_OPCODE_ENDPRIM:
4115 emit_primitive(mach);
4116 break;
4117
4118 case TGSI_OPCODE_BGNLOOP:
4119 /* push LoopMask and ContMasks */
4120 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4121 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4122 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4123 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4124
4125 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4126 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4127 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4128 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4129 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4130 break;
4131
4132 case TGSI_OPCODE_ENDLOOP:
4133 /* Restore ContMask, but don't pop */
4134 assert(mach->ContStackTop > 0);
4135 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4136 UPDATE_EXEC_MASK(mach);
4137 if (mach->ExecMask) {
4138 /* repeat loop: jump to instruction just past BGNLOOP */
4139 assert(mach->LoopLabelStackTop > 0);
4140 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4141 }
4142 else {
4143 /* exit loop: pop LoopMask */
4144 assert(mach->LoopStackTop > 0);
4145 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4146 /* pop ContMask */
4147 assert(mach->ContStackTop > 0);
4148 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4149 assert(mach->LoopLabelStackTop > 0);
4150 --mach->LoopLabelStackTop;
4151
4152 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4153 }
4154 UPDATE_EXEC_MASK(mach);
4155 break;
4156
4157 case TGSI_OPCODE_BRK:
4158 exec_break(mach);
4159 break;
4160
4161 case TGSI_OPCODE_CONT:
4162 /* turn off cont channels for each enabled exec channel */
4163 mach->ContMask &= ~mach->ExecMask;
4164 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4165 UPDATE_EXEC_MASK(mach);
4166 break;
4167
4168 case TGSI_OPCODE_BGNSUB:
4169 /* no-op */
4170 break;
4171
4172 case TGSI_OPCODE_ENDSUB:
4173 /*
4174 * XXX: This really should be a no-op. We should never reach this opcode.
4175 */
4176
4177 assert(mach->CallStackTop > 0);
4178 mach->CallStackTop--;
4179
4180 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4181 mach->CondMask = mach->CondStack[mach->CondStackTop];
4182
4183 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4184 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4185
4186 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4187 mach->ContMask = mach->ContStack[mach->ContStackTop];
4188
4189 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4190 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4191
4192 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4193 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4194
4195 assert(mach->FuncStackTop > 0);
4196 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4197
4198 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4199
4200 UPDATE_EXEC_MASK(mach);
4201 break;
4202
4203 case TGSI_OPCODE_NOP:
4204 break;
4205
4206 case TGSI_OPCODE_BREAKC:
4207 IFETCH(&r[0], 0, TGSI_CHAN_X);
4208 /* update CondMask */
4209 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4210 mach->LoopMask &= ~0x1;
4211 }
4212 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4213 mach->LoopMask &= ~0x2;
4214 }
4215 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4216 mach->LoopMask &= ~0x4;
4217 }
4218 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4219 mach->LoopMask &= ~0x8;
4220 }
4221 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4222 UPDATE_EXEC_MASK(mach);
4223 break;
4224
4225 case TGSI_OPCODE_F2I:
4226 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4227 break;
4228
4229 case TGSI_OPCODE_FSEQ:
4230 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4231 break;
4232
4233 case TGSI_OPCODE_FSGE:
4234 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4235 break;
4236
4237 case TGSI_OPCODE_FSLT:
4238 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4239 break;
4240
4241 case TGSI_OPCODE_FSNE:
4242 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4243 break;
4244
4245 case TGSI_OPCODE_IDIV:
4246 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4247 break;
4248
4249 case TGSI_OPCODE_IMAX:
4250 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4251 break;
4252
4253 case TGSI_OPCODE_IMIN:
4254 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4255 break;
4256
4257 case TGSI_OPCODE_INEG:
4258 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4259 break;
4260
4261 case TGSI_OPCODE_ISGE:
4262 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4263 break;
4264
4265 case TGSI_OPCODE_ISHR:
4266 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4267 break;
4268
4269 case TGSI_OPCODE_ISLT:
4270 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4271 break;
4272
4273 case TGSI_OPCODE_F2U:
4274 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4275 break;
4276
4277 case TGSI_OPCODE_U2F:
4278 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4279 break;
4280
4281 case TGSI_OPCODE_UADD:
4282 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4283 break;
4284
4285 case TGSI_OPCODE_UDIV:
4286 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4287 break;
4288
4289 case TGSI_OPCODE_UMAD:
4290 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4291 break;
4292
4293 case TGSI_OPCODE_UMAX:
4294 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4295 break;
4296
4297 case TGSI_OPCODE_UMIN:
4298 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4299 break;
4300
4301 case TGSI_OPCODE_UMOD:
4302 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4303 break;
4304
4305 case TGSI_OPCODE_UMUL:
4306 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4307 break;
4308
4309 case TGSI_OPCODE_IMUL_HI:
4310 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4311 break;
4312
4313 case TGSI_OPCODE_UMUL_HI:
4314 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4315 break;
4316
4317 case TGSI_OPCODE_USEQ:
4318 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4319 break;
4320
4321 case TGSI_OPCODE_USGE:
4322 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4323 break;
4324
4325 case TGSI_OPCODE_USHR:
4326 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4327 break;
4328
4329 case TGSI_OPCODE_USLT:
4330 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4331 break;
4332
4333 case TGSI_OPCODE_USNE:
4334 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4335 break;
4336
4337 case TGSI_OPCODE_SWITCH:
4338 exec_switch(mach, inst);
4339 break;
4340
4341 case TGSI_OPCODE_CASE:
4342 exec_case(mach, inst);
4343 break;
4344
4345 case TGSI_OPCODE_DEFAULT:
4346 exec_default(mach);
4347 break;
4348
4349 case TGSI_OPCODE_ENDSWITCH:
4350 exec_endswitch(mach);
4351 break;
4352
4353 case TGSI_OPCODE_SAMPLE_I:
4354 exec_txf(mach, inst);
4355 break;
4356
4357 case TGSI_OPCODE_SAMPLE_I_MS:
4358 assert(0);
4359 break;
4360
4361 case TGSI_OPCODE_SAMPLE:
4362 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4363 break;
4364
4365 case TGSI_OPCODE_SAMPLE_B:
4366 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4367 break;
4368
4369 case TGSI_OPCODE_SAMPLE_C:
4370 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4371 break;
4372
4373 case TGSI_OPCODE_SAMPLE_C_LZ:
4374 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4375 break;
4376
4377 case TGSI_OPCODE_SAMPLE_D:
4378 exec_sample_d(mach, inst);
4379 break;
4380
4381 case TGSI_OPCODE_SAMPLE_L:
4382 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4383 break;
4384
4385 case TGSI_OPCODE_GATHER4:
4386 assert(0);
4387 break;
4388
4389 case TGSI_OPCODE_SVIEWINFO:
4390 exec_txq(mach, inst);
4391 break;
4392
4393 case TGSI_OPCODE_SAMPLE_POS:
4394 assert(0);
4395 break;
4396
4397 case TGSI_OPCODE_SAMPLE_INFO:
4398 assert(0);
4399 break;
4400
4401 case TGSI_OPCODE_UARL:
4402 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4403 break;
4404
4405 case TGSI_OPCODE_UCMP:
4406 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4407 break;
4408
4409 case TGSI_OPCODE_IABS:
4410 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4411 break;
4412
4413 case TGSI_OPCODE_ISSG:
4414 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4415 break;
4416
4417 case TGSI_OPCODE_TEX2:
4418 /* simple texture lookup */
4419 /* src[0] = texcoord */
4420 /* src[1] = compare */
4421 /* src[2] = sampler unit */
4422 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4423 break;
4424 case TGSI_OPCODE_TXB2:
4425 /* simple texture lookup */
4426 /* src[0] = texcoord */
4427 /* src[1] = bias */
4428 /* src[2] = sampler unit */
4429 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4430 break;
4431 case TGSI_OPCODE_TXL2:
4432 /* simple texture lookup */
4433 /* src[0] = texcoord */
4434 /* src[1] = lod */
4435 /* src[2] = sampler unit */
4436 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4437 break;
4438 default:
4439 assert( 0 );
4440 }
4441 }
4442
4443
4444 /**
4445 * Run TGSI interpreter.
4446 * \return bitmask of "alive" quad components
4447 */
4448 uint
4449 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4450 {
4451 uint i;
4452 int pc = 0;
4453 uint default_mask = 0xf;
4454
4455 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4456 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4457
4458 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4459 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4460 mach->Primitives[0] = 0;
4461 /* GS runs on a single primitive for now */
4462 default_mask = 0x1;
4463 }
4464
4465 mach->CondMask = default_mask;
4466 mach->LoopMask = default_mask;
4467 mach->ContMask = default_mask;
4468 mach->FuncMask = default_mask;
4469 mach->ExecMask = default_mask;
4470
4471 mach->Switch.mask = default_mask;
4472
4473 assert(mach->CondStackTop == 0);
4474 assert(mach->LoopStackTop == 0);
4475 assert(mach->ContStackTop == 0);
4476 assert(mach->SwitchStackTop == 0);
4477 assert(mach->BreakStackTop == 0);
4478 assert(mach->CallStackTop == 0);
4479
4480
4481 /* execute declarations (interpolants) */
4482 for (i = 0; i < mach->NumDeclarations; i++) {
4483 exec_declaration( mach, mach->Declarations+i );
4484 }
4485
4486 {
4487 #if DEBUG_EXECUTION
4488 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4489 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4490 uint inst = 1;
4491
4492 memset(mach->Temps, 0, sizeof(temps));
4493 memset(mach->Outputs, 0, sizeof(outputs));
4494 memset(temps, 0, sizeof(temps));
4495 memset(outputs, 0, sizeof(outputs));
4496 #endif
4497
4498 /* execute instructions, until pc is set to -1 */
4499 while (pc != -1) {
4500
4501 #if DEBUG_EXECUTION
4502 uint i;
4503
4504 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4505 #endif
4506
4507 assert(pc < (int) mach->NumInstructions);
4508 exec_instruction(mach, mach->Instructions + pc, &pc);
4509
4510 #if DEBUG_EXECUTION
4511 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4512 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4513 uint j;
4514
4515 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4516 debug_printf("TEMP[%2u] = ", i);
4517 for (j = 0; j < 4; j++) {
4518 if (j > 0) {
4519 debug_printf(" ");
4520 }
4521 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4522 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4523 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4524 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4525 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4526 }
4527 }
4528 }
4529 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4530 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4531 uint j;
4532
4533 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4534 debug_printf("OUT[%2u] = ", i);
4535 for (j = 0; j < 4; j++) {
4536 if (j > 0) {
4537 debug_printf(" ");
4538 }
4539 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4540 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4541 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4542 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4543 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4544 }
4545 }
4546 }
4547 #endif
4548 }
4549 }
4550
4551 #if 0
4552 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4553 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4554 /*
4555 * Scale back depth component.
4556 */
4557 for (i = 0; i < 4; i++)
4558 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4559 }
4560 #endif
4561
4562 /* Strictly speaking, these assertions aren't really needed but they
4563 * can potentially catch some bugs in the control flow code.
4564 */
4565 assert(mach->CondStackTop == 0);
4566 assert(mach->LoopStackTop == 0);
4567 assert(mach->ContStackTop == 0);
4568 assert(mach->SwitchStackTop == 0);
4569 assert(mach->BreakStackTop == 0);
4570 assert(mach->CallStackTop == 0);
4571
4572 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4573 }