1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
67 #define DEBUG_EXECUTION 0
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
77 union tgsi_double_channel
{
78 double d
[TGSI_QUAD_SIZE
];
79 unsigned u
[TGSI_QUAD_SIZE
][2];
80 uint64_t u64
[TGSI_QUAD_SIZE
];
81 int64_t i64
[TGSI_QUAD_SIZE
];
84 struct tgsi_double_vector
{
85 union tgsi_double_channel xy
;
86 union tgsi_double_channel zw
;
90 micro_abs(union tgsi_exec_channel
*dst
,
91 const union tgsi_exec_channel
*src
)
93 dst
->f
[0] = fabsf(src
->f
[0]);
94 dst
->f
[1] = fabsf(src
->f
[1]);
95 dst
->f
[2] = fabsf(src
->f
[2]);
96 dst
->f
[3] = fabsf(src
->f
[3]);
100 micro_arl(union tgsi_exec_channel
*dst
,
101 const union tgsi_exec_channel
*src
)
103 dst
->i
[0] = (int)floorf(src
->f
[0]);
104 dst
->i
[1] = (int)floorf(src
->f
[1]);
105 dst
->i
[2] = (int)floorf(src
->f
[2]);
106 dst
->i
[3] = (int)floorf(src
->f
[3]);
110 micro_arr(union tgsi_exec_channel
*dst
,
111 const union tgsi_exec_channel
*src
)
113 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
114 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
115 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
116 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
120 micro_ceil(union tgsi_exec_channel
*dst
,
121 const union tgsi_exec_channel
*src
)
123 dst
->f
[0] = ceilf(src
->f
[0]);
124 dst
->f
[1] = ceilf(src
->f
[1]);
125 dst
->f
[2] = ceilf(src
->f
[2]);
126 dst
->f
[3] = ceilf(src
->f
[3]);
130 micro_cmp(union tgsi_exec_channel
*dst
,
131 const union tgsi_exec_channel
*src0
,
132 const union tgsi_exec_channel
*src1
,
133 const union tgsi_exec_channel
*src2
)
135 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
136 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
137 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
138 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
142 micro_cos(union tgsi_exec_channel
*dst
,
143 const union tgsi_exec_channel
*src
)
145 dst
->f
[0] = cosf(src
->f
[0]);
146 dst
->f
[1] = cosf(src
->f
[1]);
147 dst
->f
[2] = cosf(src
->f
[2]);
148 dst
->f
[3] = cosf(src
->f
[3]);
152 micro_d2f(union tgsi_exec_channel
*dst
,
153 const union tgsi_double_channel
*src
)
155 dst
->f
[0] = (float)src
->d
[0];
156 dst
->f
[1] = (float)src
->d
[1];
157 dst
->f
[2] = (float)src
->d
[2];
158 dst
->f
[3] = (float)src
->d
[3];
162 micro_d2i(union tgsi_exec_channel
*dst
,
163 const union tgsi_double_channel
*src
)
165 dst
->i
[0] = (int)src
->d
[0];
166 dst
->i
[1] = (int)src
->d
[1];
167 dst
->i
[2] = (int)src
->d
[2];
168 dst
->i
[3] = (int)src
->d
[3];
172 micro_d2u(union tgsi_exec_channel
*dst
,
173 const union tgsi_double_channel
*src
)
175 dst
->u
[0] = (unsigned)src
->d
[0];
176 dst
->u
[1] = (unsigned)src
->d
[1];
177 dst
->u
[2] = (unsigned)src
->d
[2];
178 dst
->u
[3] = (unsigned)src
->d
[3];
181 micro_dabs(union tgsi_double_channel
*dst
,
182 const union tgsi_double_channel
*src
)
184 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
185 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
186 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
187 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
191 micro_dadd(union tgsi_double_channel
*dst
,
192 const union tgsi_double_channel
*src
)
194 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
195 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
196 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
197 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
201 micro_ddiv(union tgsi_double_channel
*dst
,
202 const union tgsi_double_channel
*src
)
204 dst
->d
[0] = src
[0].d
[0] / src
[1].d
[0];
205 dst
->d
[1] = src
[0].d
[1] / src
[1].d
[1];
206 dst
->d
[2] = src
[0].d
[2] / src
[1].d
[2];
207 dst
->d
[3] = src
[0].d
[3] / src
[1].d
[3];
211 micro_ddx(union tgsi_exec_channel
*dst
,
212 const union tgsi_exec_channel
*src
)
217 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
221 micro_ddy(union tgsi_exec_channel
*dst
,
222 const union tgsi_exec_channel
*src
)
227 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
231 micro_dmul(union tgsi_double_channel
*dst
,
232 const union tgsi_double_channel
*src
)
234 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
235 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
236 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
237 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
241 micro_dmax(union tgsi_double_channel
*dst
,
242 const union tgsi_double_channel
*src
)
244 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
245 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
246 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
247 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
251 micro_dmin(union tgsi_double_channel
*dst
,
252 const union tgsi_double_channel
*src
)
254 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
255 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
256 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
257 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
261 micro_dneg(union tgsi_double_channel
*dst
,
262 const union tgsi_double_channel
*src
)
264 dst
->d
[0] = -src
->d
[0];
265 dst
->d
[1] = -src
->d
[1];
266 dst
->d
[2] = -src
->d
[2];
267 dst
->d
[3] = -src
->d
[3];
271 micro_dslt(union tgsi_double_channel
*dst
,
272 const union tgsi_double_channel
*src
)
274 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
275 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
276 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
277 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
281 micro_dsne(union tgsi_double_channel
*dst
,
282 const union tgsi_double_channel
*src
)
284 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
285 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
286 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
287 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
291 micro_dsge(union tgsi_double_channel
*dst
,
292 const union tgsi_double_channel
*src
)
294 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
295 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
296 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
297 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
301 micro_dseq(union tgsi_double_channel
*dst
,
302 const union tgsi_double_channel
*src
)
304 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
305 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
306 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
307 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
311 micro_drcp(union tgsi_double_channel
*dst
,
312 const union tgsi_double_channel
*src
)
314 dst
->d
[0] = 1.0 / src
->d
[0];
315 dst
->d
[1] = 1.0 / src
->d
[1];
316 dst
->d
[2] = 1.0 / src
->d
[2];
317 dst
->d
[3] = 1.0 / src
->d
[3];
321 micro_dsqrt(union tgsi_double_channel
*dst
,
322 const union tgsi_double_channel
*src
)
324 dst
->d
[0] = sqrt(src
->d
[0]);
325 dst
->d
[1] = sqrt(src
->d
[1]);
326 dst
->d
[2] = sqrt(src
->d
[2]);
327 dst
->d
[3] = sqrt(src
->d
[3]);
331 micro_drsq(union tgsi_double_channel
*dst
,
332 const union tgsi_double_channel
*src
)
334 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
335 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
336 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
337 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
341 micro_dmad(union tgsi_double_channel
*dst
,
342 const union tgsi_double_channel
*src
)
344 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
345 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
346 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
347 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
351 micro_dfrac(union tgsi_double_channel
*dst
,
352 const union tgsi_double_channel
*src
)
354 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
355 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
356 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
357 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
361 micro_dldexp(union tgsi_double_channel
*dst
,
362 const union tgsi_double_channel
*src0
,
363 union tgsi_exec_channel
*src1
)
365 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
366 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
367 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
368 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
372 micro_dfracexp(union tgsi_double_channel
*dst
,
373 union tgsi_exec_channel
*dst_exp
,
374 const union tgsi_double_channel
*src
)
376 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
377 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
378 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
379 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
383 micro_exp2(union tgsi_exec_channel
*dst
,
384 const union tgsi_exec_channel
*src
)
387 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
388 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
389 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
390 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
393 /* Inf is okay for this instruction, so clamp it to silence assertions. */
395 union tgsi_exec_channel clamped
;
397 for (i
= 0; i
< 4; i
++) {
398 if (src
->f
[i
] > 127.99999f
) {
399 clamped
.f
[i
] = 127.99999f
;
400 } else if (src
->f
[i
] < -126.99999f
) {
401 clamped
.f
[i
] = -126.99999f
;
403 clamped
.f
[i
] = src
->f
[i
];
409 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
410 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
411 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
412 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
413 #endif /* FAST_MATH */
417 micro_f2d(union tgsi_double_channel
*dst
,
418 const union tgsi_exec_channel
*src
)
420 dst
->d
[0] = (double)src
->f
[0];
421 dst
->d
[1] = (double)src
->f
[1];
422 dst
->d
[2] = (double)src
->f
[2];
423 dst
->d
[3] = (double)src
->f
[3];
427 micro_flr(union tgsi_exec_channel
*dst
,
428 const union tgsi_exec_channel
*src
)
430 dst
->f
[0] = floorf(src
->f
[0]);
431 dst
->f
[1] = floorf(src
->f
[1]);
432 dst
->f
[2] = floorf(src
->f
[2]);
433 dst
->f
[3] = floorf(src
->f
[3]);
437 micro_frc(union tgsi_exec_channel
*dst
,
438 const union tgsi_exec_channel
*src
)
440 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
441 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
442 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
443 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
447 micro_i2d(union tgsi_double_channel
*dst
,
448 const union tgsi_exec_channel
*src
)
450 dst
->d
[0] = (double)src
->i
[0];
451 dst
->d
[1] = (double)src
->i
[1];
452 dst
->d
[2] = (double)src
->i
[2];
453 dst
->d
[3] = (double)src
->i
[3];
457 micro_iabs(union tgsi_exec_channel
*dst
,
458 const union tgsi_exec_channel
*src
)
460 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
461 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
462 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
463 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
467 micro_ineg(union tgsi_exec_channel
*dst
,
468 const union tgsi_exec_channel
*src
)
470 dst
->i
[0] = -src
->i
[0];
471 dst
->i
[1] = -src
->i
[1];
472 dst
->i
[2] = -src
->i
[2];
473 dst
->i
[3] = -src
->i
[3];
477 micro_lg2(union tgsi_exec_channel
*dst
,
478 const union tgsi_exec_channel
*src
)
481 dst
->f
[0] = util_fast_log2(src
->f
[0]);
482 dst
->f
[1] = util_fast_log2(src
->f
[1]);
483 dst
->f
[2] = util_fast_log2(src
->f
[2]);
484 dst
->f
[3] = util_fast_log2(src
->f
[3]);
486 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
487 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
488 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
489 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
494 micro_lrp(union tgsi_exec_channel
*dst
,
495 const union tgsi_exec_channel
*src0
,
496 const union tgsi_exec_channel
*src1
,
497 const union tgsi_exec_channel
*src2
)
499 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
500 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
501 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
502 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
506 micro_mad(union tgsi_exec_channel
*dst
,
507 const union tgsi_exec_channel
*src0
,
508 const union tgsi_exec_channel
*src1
,
509 const union tgsi_exec_channel
*src2
)
511 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
512 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
513 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
514 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
518 micro_mov(union tgsi_exec_channel
*dst
,
519 const union tgsi_exec_channel
*src
)
521 dst
->u
[0] = src
->u
[0];
522 dst
->u
[1] = src
->u
[1];
523 dst
->u
[2] = src
->u
[2];
524 dst
->u
[3] = src
->u
[3];
528 micro_rcp(union tgsi_exec_channel
*dst
,
529 const union tgsi_exec_channel
*src
)
531 #if 0 /* for debugging */
532 assert(src
->f
[0] != 0.0f
);
533 assert(src
->f
[1] != 0.0f
);
534 assert(src
->f
[2] != 0.0f
);
535 assert(src
->f
[3] != 0.0f
);
537 dst
->f
[0] = 1.0f
/ src
->f
[0];
538 dst
->f
[1] = 1.0f
/ src
->f
[1];
539 dst
->f
[2] = 1.0f
/ src
->f
[2];
540 dst
->f
[3] = 1.0f
/ src
->f
[3];
544 micro_rnd(union tgsi_exec_channel
*dst
,
545 const union tgsi_exec_channel
*src
)
547 dst
->f
[0] = _mesa_roundevenf(src
->f
[0]);
548 dst
->f
[1] = _mesa_roundevenf(src
->f
[1]);
549 dst
->f
[2] = _mesa_roundevenf(src
->f
[2]);
550 dst
->f
[3] = _mesa_roundevenf(src
->f
[3]);
554 micro_rsq(union tgsi_exec_channel
*dst
,
555 const union tgsi_exec_channel
*src
)
557 #if 0 /* for debugging */
558 assert(src
->f
[0] != 0.0f
);
559 assert(src
->f
[1] != 0.0f
);
560 assert(src
->f
[2] != 0.0f
);
561 assert(src
->f
[3] != 0.0f
);
563 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
564 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
565 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
566 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
570 micro_sqrt(union tgsi_exec_channel
*dst
,
571 const union tgsi_exec_channel
*src
)
573 dst
->f
[0] = sqrtf(src
->f
[0]);
574 dst
->f
[1] = sqrtf(src
->f
[1]);
575 dst
->f
[2] = sqrtf(src
->f
[2]);
576 dst
->f
[3] = sqrtf(src
->f
[3]);
580 micro_seq(union tgsi_exec_channel
*dst
,
581 const union tgsi_exec_channel
*src0
,
582 const union tgsi_exec_channel
*src1
)
584 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
585 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
586 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
587 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
591 micro_sge(union tgsi_exec_channel
*dst
,
592 const union tgsi_exec_channel
*src0
,
593 const union tgsi_exec_channel
*src1
)
595 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
596 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
597 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
598 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
602 micro_sgn(union tgsi_exec_channel
*dst
,
603 const union tgsi_exec_channel
*src
)
605 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
606 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
607 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
608 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
612 micro_isgn(union tgsi_exec_channel
*dst
,
613 const union tgsi_exec_channel
*src
)
615 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
616 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
617 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
618 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
622 micro_sgt(union tgsi_exec_channel
*dst
,
623 const union tgsi_exec_channel
*src0
,
624 const union tgsi_exec_channel
*src1
)
626 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
627 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
628 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
629 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
633 micro_sin(union tgsi_exec_channel
*dst
,
634 const union tgsi_exec_channel
*src
)
636 dst
->f
[0] = sinf(src
->f
[0]);
637 dst
->f
[1] = sinf(src
->f
[1]);
638 dst
->f
[2] = sinf(src
->f
[2]);
639 dst
->f
[3] = sinf(src
->f
[3]);
643 micro_sle(union tgsi_exec_channel
*dst
,
644 const union tgsi_exec_channel
*src0
,
645 const union tgsi_exec_channel
*src1
)
647 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
648 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
649 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
650 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
654 micro_slt(union tgsi_exec_channel
*dst
,
655 const union tgsi_exec_channel
*src0
,
656 const union tgsi_exec_channel
*src1
)
658 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
659 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
660 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
661 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
665 micro_sne(union tgsi_exec_channel
*dst
,
666 const union tgsi_exec_channel
*src0
,
667 const union tgsi_exec_channel
*src1
)
669 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
670 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
671 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
672 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
676 micro_trunc(union tgsi_exec_channel
*dst
,
677 const union tgsi_exec_channel
*src
)
679 dst
->f
[0] = truncf(src
->f
[0]);
680 dst
->f
[1] = truncf(src
->f
[1]);
681 dst
->f
[2] = truncf(src
->f
[2]);
682 dst
->f
[3] = truncf(src
->f
[3]);
686 micro_u2d(union tgsi_double_channel
*dst
,
687 const union tgsi_exec_channel
*src
)
689 dst
->d
[0] = (double)src
->u
[0];
690 dst
->d
[1] = (double)src
->u
[1];
691 dst
->d
[2] = (double)src
->u
[2];
692 dst
->d
[3] = (double)src
->u
[3];
696 micro_i64abs(union tgsi_double_channel
*dst
,
697 const union tgsi_double_channel
*src
)
699 dst
->i64
[0] = src
->i64
[0] >= 0.0 ? src
->i64
[0] : -src
->i64
[0];
700 dst
->i64
[1] = src
->i64
[1] >= 0.0 ? src
->i64
[1] : -src
->i64
[1];
701 dst
->i64
[2] = src
->i64
[2] >= 0.0 ? src
->i64
[2] : -src
->i64
[2];
702 dst
->i64
[3] = src
->i64
[3] >= 0.0 ? src
->i64
[3] : -src
->i64
[3];
706 micro_i64sgn(union tgsi_double_channel
*dst
,
707 const union tgsi_double_channel
*src
)
709 dst
->i64
[0] = src
->i64
[0] < 0 ? -1 : src
->i64
[0] > 0 ? 1 : 0;
710 dst
->i64
[1] = src
->i64
[1] < 0 ? -1 : src
->i64
[1] > 0 ? 1 : 0;
711 dst
->i64
[2] = src
->i64
[2] < 0 ? -1 : src
->i64
[2] > 0 ? 1 : 0;
712 dst
->i64
[3] = src
->i64
[3] < 0 ? -1 : src
->i64
[3] > 0 ? 1 : 0;
716 micro_i64neg(union tgsi_double_channel
*dst
,
717 const union tgsi_double_channel
*src
)
719 dst
->i64
[0] = -src
->i64
[0];
720 dst
->i64
[1] = -src
->i64
[1];
721 dst
->i64
[2] = -src
->i64
[2];
722 dst
->i64
[3] = -src
->i64
[3];
726 micro_u64seq(union tgsi_double_channel
*dst
,
727 const union tgsi_double_channel
*src
)
729 dst
->u
[0][0] = src
[0].u64
[0] == src
[1].u64
[0] ? ~0U : 0U;
730 dst
->u
[1][0] = src
[0].u64
[1] == src
[1].u64
[1] ? ~0U : 0U;
731 dst
->u
[2][0] = src
[0].u64
[2] == src
[1].u64
[2] ? ~0U : 0U;
732 dst
->u
[3][0] = src
[0].u64
[3] == src
[1].u64
[3] ? ~0U : 0U;
736 micro_u64sne(union tgsi_double_channel
*dst
,
737 const union tgsi_double_channel
*src
)
739 dst
->u
[0][0] = src
[0].u64
[0] != src
[1].u64
[0] ? ~0U : 0U;
740 dst
->u
[1][0] = src
[0].u64
[1] != src
[1].u64
[1] ? ~0U : 0U;
741 dst
->u
[2][0] = src
[0].u64
[2] != src
[1].u64
[2] ? ~0U : 0U;
742 dst
->u
[3][0] = src
[0].u64
[3] != src
[1].u64
[3] ? ~0U : 0U;
746 micro_i64slt(union tgsi_double_channel
*dst
,
747 const union tgsi_double_channel
*src
)
749 dst
->u
[0][0] = src
[0].i64
[0] < src
[1].i64
[0] ? ~0U : 0U;
750 dst
->u
[1][0] = src
[0].i64
[1] < src
[1].i64
[1] ? ~0U : 0U;
751 dst
->u
[2][0] = src
[0].i64
[2] < src
[1].i64
[2] ? ~0U : 0U;
752 dst
->u
[3][0] = src
[0].i64
[3] < src
[1].i64
[3] ? ~0U : 0U;
756 micro_u64slt(union tgsi_double_channel
*dst
,
757 const union tgsi_double_channel
*src
)
759 dst
->u
[0][0] = src
[0].u64
[0] < src
[1].u64
[0] ? ~0U : 0U;
760 dst
->u
[1][0] = src
[0].u64
[1] < src
[1].u64
[1] ? ~0U : 0U;
761 dst
->u
[2][0] = src
[0].u64
[2] < src
[1].u64
[2] ? ~0U : 0U;
762 dst
->u
[3][0] = src
[0].u64
[3] < src
[1].u64
[3] ? ~0U : 0U;
766 micro_i64sge(union tgsi_double_channel
*dst
,
767 const union tgsi_double_channel
*src
)
769 dst
->u
[0][0] = src
[0].i64
[0] >= src
[1].i64
[0] ? ~0U : 0U;
770 dst
->u
[1][0] = src
[0].i64
[1] >= src
[1].i64
[1] ? ~0U : 0U;
771 dst
->u
[2][0] = src
[0].i64
[2] >= src
[1].i64
[2] ? ~0U : 0U;
772 dst
->u
[3][0] = src
[0].i64
[3] >= src
[1].i64
[3] ? ~0U : 0U;
776 micro_u64sge(union tgsi_double_channel
*dst
,
777 const union tgsi_double_channel
*src
)
779 dst
->u
[0][0] = src
[0].u64
[0] >= src
[1].u64
[0] ? ~0U : 0U;
780 dst
->u
[1][0] = src
[0].u64
[1] >= src
[1].u64
[1] ? ~0U : 0U;
781 dst
->u
[2][0] = src
[0].u64
[2] >= src
[1].u64
[2] ? ~0U : 0U;
782 dst
->u
[3][0] = src
[0].u64
[3] >= src
[1].u64
[3] ? ~0U : 0U;
786 micro_u64max(union tgsi_double_channel
*dst
,
787 const union tgsi_double_channel
*src
)
789 dst
->u64
[0] = src
[0].u64
[0] > src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
790 dst
->u64
[1] = src
[0].u64
[1] > src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
791 dst
->u64
[2] = src
[0].u64
[2] > src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
792 dst
->u64
[3] = src
[0].u64
[3] > src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
796 micro_i64max(union tgsi_double_channel
*dst
,
797 const union tgsi_double_channel
*src
)
799 dst
->i64
[0] = src
[0].i64
[0] > src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
800 dst
->i64
[1] = src
[0].i64
[1] > src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
801 dst
->i64
[2] = src
[0].i64
[2] > src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
802 dst
->i64
[3] = src
[0].i64
[3] > src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
806 micro_u64min(union tgsi_double_channel
*dst
,
807 const union tgsi_double_channel
*src
)
809 dst
->u64
[0] = src
[0].u64
[0] < src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
810 dst
->u64
[1] = src
[0].u64
[1] < src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
811 dst
->u64
[2] = src
[0].u64
[2] < src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
812 dst
->u64
[3] = src
[0].u64
[3] < src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
816 micro_i64min(union tgsi_double_channel
*dst
,
817 const union tgsi_double_channel
*src
)
819 dst
->i64
[0] = src
[0].i64
[0] < src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
820 dst
->i64
[1] = src
[0].i64
[1] < src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
821 dst
->i64
[2] = src
[0].i64
[2] < src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
822 dst
->i64
[3] = src
[0].i64
[3] < src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
826 micro_u64add(union tgsi_double_channel
*dst
,
827 const union tgsi_double_channel
*src
)
829 dst
->u64
[0] = src
[0].u64
[0] + src
[1].u64
[0];
830 dst
->u64
[1] = src
[0].u64
[1] + src
[1].u64
[1];
831 dst
->u64
[2] = src
[0].u64
[2] + src
[1].u64
[2];
832 dst
->u64
[3] = src
[0].u64
[3] + src
[1].u64
[3];
836 micro_u64mul(union tgsi_double_channel
*dst
,
837 const union tgsi_double_channel
*src
)
839 dst
->u64
[0] = src
[0].u64
[0] * src
[1].u64
[0];
840 dst
->u64
[1] = src
[0].u64
[1] * src
[1].u64
[1];
841 dst
->u64
[2] = src
[0].u64
[2] * src
[1].u64
[2];
842 dst
->u64
[3] = src
[0].u64
[3] * src
[1].u64
[3];
846 micro_u64div(union tgsi_double_channel
*dst
,
847 const union tgsi_double_channel
*src
)
849 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] / src
[1].u64
[0] : ~0ull;
850 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] / src
[1].u64
[1] : ~0ull;
851 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] / src
[1].u64
[2] : ~0ull;
852 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] / src
[1].u64
[3] : ~0ull;
856 micro_i64div(union tgsi_double_channel
*dst
,
857 const union tgsi_double_channel
*src
)
859 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] / src
[1].i64
[0] : 0;
860 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] / src
[1].i64
[1] : 0;
861 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] / src
[1].i64
[2] : 0;
862 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] / src
[1].i64
[3] : 0;
866 micro_u64mod(union tgsi_double_channel
*dst
,
867 const union tgsi_double_channel
*src
)
869 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] % src
[1].u64
[0] : ~0ull;
870 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] % src
[1].u64
[1] : ~0ull;
871 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] % src
[1].u64
[2] : ~0ull;
872 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] % src
[1].u64
[3] : ~0ull;
876 micro_i64mod(union tgsi_double_channel
*dst
,
877 const union tgsi_double_channel
*src
)
879 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] % src
[1].i64
[0] : ~0ll;
880 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] % src
[1].i64
[1] : ~0ll;
881 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] % src
[1].i64
[2] : ~0ll;
882 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] % src
[1].i64
[3] : ~0ll;
886 micro_u64shl(union tgsi_double_channel
*dst
,
887 const union tgsi_double_channel
*src0
,
888 union tgsi_exec_channel
*src1
)
890 unsigned masked_count
;
891 masked_count
= src1
->u
[0] & 0x3f;
892 dst
->u64
[0] = src0
->u64
[0] << masked_count
;
893 masked_count
= src1
->u
[1] & 0x3f;
894 dst
->u64
[1] = src0
->u64
[1] << masked_count
;
895 masked_count
= src1
->u
[2] & 0x3f;
896 dst
->u64
[2] = src0
->u64
[2] << masked_count
;
897 masked_count
= src1
->u
[3] & 0x3f;
898 dst
->u64
[3] = src0
->u64
[3] << masked_count
;
902 micro_i64shr(union tgsi_double_channel
*dst
,
903 const union tgsi_double_channel
*src0
,
904 union tgsi_exec_channel
*src1
)
906 unsigned masked_count
;
907 masked_count
= src1
->u
[0] & 0x3f;
908 dst
->i64
[0] = src0
->i64
[0] >> masked_count
;
909 masked_count
= src1
->u
[1] & 0x3f;
910 dst
->i64
[1] = src0
->i64
[1] >> masked_count
;
911 masked_count
= src1
->u
[2] & 0x3f;
912 dst
->i64
[2] = src0
->i64
[2] >> masked_count
;
913 masked_count
= src1
->u
[3] & 0x3f;
914 dst
->i64
[3] = src0
->i64
[3] >> masked_count
;
918 micro_u64shr(union tgsi_double_channel
*dst
,
919 const union tgsi_double_channel
*src0
,
920 union tgsi_exec_channel
*src1
)
922 unsigned masked_count
;
923 masked_count
= src1
->u
[0] & 0x3f;
924 dst
->u64
[0] = src0
->u64
[0] >> masked_count
;
925 masked_count
= src1
->u
[1] & 0x3f;
926 dst
->u64
[1] = src0
->u64
[1] >> masked_count
;
927 masked_count
= src1
->u
[2] & 0x3f;
928 dst
->u64
[2] = src0
->u64
[2] >> masked_count
;
929 masked_count
= src1
->u
[3] & 0x3f;
930 dst
->u64
[3] = src0
->u64
[3] >> masked_count
;
933 enum tgsi_exec_datatype
{
934 TGSI_EXEC_DATA_FLOAT
,
937 TGSI_EXEC_DATA_DOUBLE
,
938 TGSI_EXEC_DATA_INT64
,
939 TGSI_EXEC_DATA_UINT64
,
943 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
945 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
946 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
947 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
948 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
949 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
950 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
953 /** The execution mask depends on the conditional mask and the loop mask */
954 #define UPDATE_EXEC_MASK(MACH) \
955 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
958 static const union tgsi_exec_channel ZeroVec
=
959 { { 0.0, 0.0, 0.0, 0.0 } };
961 static const union tgsi_exec_channel OneVec
= {
962 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
965 static const union tgsi_exec_channel P128Vec
= {
966 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
969 static const union tgsi_exec_channel M128Vec
= {
970 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
975 * Assert that none of the float values in 'chan' are infinite or NaN.
976 * NaN and Inf may occur normally during program execution and should
977 * not lead to crashes, etc. But when debugging, it's helpful to catch
981 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
983 assert(!util_is_inf_or_nan((chan
)->f
[0]));
984 assert(!util_is_inf_or_nan((chan
)->f
[1]));
985 assert(!util_is_inf_or_nan((chan
)->f
[2]));
986 assert(!util_is_inf_or_nan((chan
)->f
[3]));
992 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
994 debug_printf("%s = {%f, %f, %f, %f}\n",
995 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
1002 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
1004 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
1006 debug_printf("Temp[%u] =\n", index
);
1007 for (i
= 0; i
< 4; i
++) {
1008 debug_printf(" %c: { %f, %f, %f, %f }\n",
1020 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
1023 const unsigned *buf_sizes
)
1027 for (i
= 0; i
< num_bufs
; i
++) {
1028 mach
->Consts
[i
] = bufs
[i
];
1029 mach
->ConstsSize
[i
] = buf_sizes
[i
];
1035 * Check if there's a potential src/dst register data dependency when
1036 * using SOA execution.
1039 * This would expand into:
1044 * The second instruction will have the wrong value for t0 if executed as-is.
1047 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
1051 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
1052 if (writemask
== TGSI_WRITEMASK_X
||
1053 writemask
== TGSI_WRITEMASK_Y
||
1054 writemask
== TGSI_WRITEMASK_Z
||
1055 writemask
== TGSI_WRITEMASK_W
||
1056 writemask
== TGSI_WRITEMASK_NONE
) {
1057 /* no chance of data dependency */
1061 /* loop over src regs */
1062 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1063 if ((inst
->Src
[i
].Register
.File
==
1064 inst
->Dst
[0].Register
.File
) &&
1065 ((inst
->Src
[i
].Register
.Index
==
1066 inst
->Dst
[0].Register
.Index
) ||
1067 inst
->Src
[i
].Register
.Indirect
||
1068 inst
->Dst
[0].Register
.Indirect
)) {
1069 /* loop over dest channels */
1070 uint channelsWritten
= 0x0;
1071 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1072 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1073 /* check if we're reading a channel that's been written */
1074 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
1075 if (channelsWritten
& (1 << swizzle
)) {
1079 channelsWritten
|= (1 << chan
);
1089 * Initialize machine state by expanding tokens to full instructions,
1090 * allocating temporary storage, setting up constants, etc.
1091 * After this, we can call tgsi_exec_machine_run() many times.
1094 tgsi_exec_machine_bind_shader(
1095 struct tgsi_exec_machine
*mach
,
1096 const struct tgsi_token
*tokens
,
1097 struct tgsi_sampler
*sampler
,
1098 struct tgsi_image
*image
,
1099 struct tgsi_buffer
*buffer
)
1102 struct tgsi_parse_context parse
;
1103 struct tgsi_full_instruction
*instructions
;
1104 struct tgsi_full_declaration
*declarations
;
1105 uint maxInstructions
= 10, numInstructions
= 0;
1106 uint maxDeclarations
= 10, numDeclarations
= 0;
1109 tgsi_dump(tokens
, 0);
1115 mach
->Tokens
= tokens
;
1116 mach
->Sampler
= sampler
;
1117 mach
->Image
= image
;
1118 mach
->Buffer
= buffer
;
1121 /* unbind and free all */
1122 FREE(mach
->Declarations
);
1123 mach
->Declarations
= NULL
;
1124 mach
->NumDeclarations
= 0;
1126 FREE(mach
->Instructions
);
1127 mach
->Instructions
= NULL
;
1128 mach
->NumInstructions
= 0;
1133 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
1134 if (k
!= TGSI_PARSE_OK
) {
1135 debug_printf( "Problem parsing!\n" );
1140 mach
->NumOutputs
= 0;
1142 for (k
= 0; k
< TGSI_SEMANTIC_COUNT
; k
++)
1143 mach
->SysSemanticToIndex
[k
] = -1;
1145 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
&&
1146 !mach
->UsedGeometryShader
) {
1147 struct tgsi_exec_vector
*inputs
;
1148 struct tgsi_exec_vector
*outputs
;
1150 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1151 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
1157 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1158 TGSI_MAX_TOTAL_VERTICES
, 16);
1165 align_free(mach
->Inputs
);
1166 align_free(mach
->Outputs
);
1168 mach
->Inputs
= inputs
;
1169 mach
->Outputs
= outputs
;
1170 mach
->UsedGeometryShader
= TRUE
;
1173 declarations
= (struct tgsi_full_declaration
*)
1174 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
1176 if (!declarations
) {
1180 instructions
= (struct tgsi_full_instruction
*)
1181 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
1183 if (!instructions
) {
1184 FREE( declarations
);
1188 while( !tgsi_parse_end_of_tokens( &parse
) ) {
1191 tgsi_parse_token( &parse
);
1192 switch( parse
.FullToken
.Token
.Type
) {
1193 case TGSI_TOKEN_TYPE_DECLARATION
:
1194 /* save expanded declaration */
1195 if (numDeclarations
== maxDeclarations
) {
1196 declarations
= REALLOC(declarations
,
1198 * sizeof(struct tgsi_full_declaration
),
1199 (maxDeclarations
+ 10)
1200 * sizeof(struct tgsi_full_declaration
));
1201 maxDeclarations
+= 10;
1203 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
1205 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
1206 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
1211 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1212 const struct tgsi_full_declaration
*decl
= &parse
.FullToken
.FullDeclaration
;
1213 mach
->SysSemanticToIndex
[decl
->Semantic
.Name
] = decl
->Range
.First
;
1216 memcpy(declarations
+ numDeclarations
,
1217 &parse
.FullToken
.FullDeclaration
,
1218 sizeof(declarations
[0]));
1222 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1224 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
1225 assert( size
<= 4 );
1226 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
1228 for( i
= 0; i
< size
; i
++ ) {
1229 mach
->Imms
[mach
->ImmLimit
][i
] =
1230 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
1232 mach
->ImmLimit
+= 1;
1236 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1238 /* save expanded instruction */
1239 if (numInstructions
== maxInstructions
) {
1240 instructions
= REALLOC(instructions
,
1242 * sizeof(struct tgsi_full_instruction
),
1243 (maxInstructions
+ 10)
1244 * sizeof(struct tgsi_full_instruction
));
1245 maxInstructions
+= 10;
1248 memcpy(instructions
+ numInstructions
,
1249 &parse
.FullToken
.FullInstruction
,
1250 sizeof(instructions
[0]));
1255 case TGSI_TOKEN_TYPE_PROPERTY
:
1256 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
1257 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1258 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1267 tgsi_parse_free (&parse
);
1269 FREE(mach
->Declarations
);
1270 mach
->Declarations
= declarations
;
1271 mach
->NumDeclarations
= numDeclarations
;
1273 FREE(mach
->Instructions
);
1274 mach
->Instructions
= instructions
;
1275 mach
->NumInstructions
= numInstructions
;
1279 struct tgsi_exec_machine
*
1280 tgsi_exec_machine_create(enum pipe_shader_type shader_type
)
1282 struct tgsi_exec_machine
*mach
;
1285 mach
= align_malloc( sizeof *mach
, 16 );
1289 memset(mach
, 0, sizeof(*mach
));
1291 mach
->ShaderType
= shader_type
;
1292 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1293 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1295 if (shader_type
!= PIPE_SHADER_COMPUTE
) {
1296 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1297 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1298 if (!mach
->Inputs
|| !mach
->Outputs
)
1302 /* Setup constants needed by the SSE2 executor. */
1303 for( i
= 0; i
< 4; i
++ ) {
1304 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
1305 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
1306 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
1307 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
1308 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
1309 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
1310 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
1311 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
1312 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
1313 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
1317 /* silence warnings */
1326 align_free(mach
->Inputs
);
1327 align_free(mach
->Outputs
);
1335 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1338 FREE(mach
->Instructions
);
1339 FREE(mach
->Declarations
);
1341 align_free(mach
->Inputs
);
1342 align_free(mach
->Outputs
);
1349 micro_add(union tgsi_exec_channel
*dst
,
1350 const union tgsi_exec_channel
*src0
,
1351 const union tgsi_exec_channel
*src1
)
1353 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1354 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1355 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1356 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1361 union tgsi_exec_channel
*dst
,
1362 const union tgsi_exec_channel
*src0
,
1363 const union tgsi_exec_channel
*src1
)
1365 if (src1
->f
[0] != 0) {
1366 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1368 if (src1
->f
[1] != 0) {
1369 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1371 if (src1
->f
[2] != 0) {
1372 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1374 if (src1
->f
[3] != 0) {
1375 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1381 union tgsi_exec_channel
*dst
,
1382 const union tgsi_exec_channel
*src0
,
1383 const union tgsi_exec_channel
*src1
,
1384 const union tgsi_exec_channel
*src2
,
1385 const union tgsi_exec_channel
*src3
)
1387 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1388 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1389 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1390 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1394 micro_max(union tgsi_exec_channel
*dst
,
1395 const union tgsi_exec_channel
*src0
,
1396 const union tgsi_exec_channel
*src1
)
1398 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1399 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1400 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1401 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1405 micro_min(union tgsi_exec_channel
*dst
,
1406 const union tgsi_exec_channel
*src0
,
1407 const union tgsi_exec_channel
*src1
)
1409 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1410 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1411 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1412 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1416 micro_mul(union tgsi_exec_channel
*dst
,
1417 const union tgsi_exec_channel
*src0
,
1418 const union tgsi_exec_channel
*src1
)
1420 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1421 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1422 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1423 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1428 union tgsi_exec_channel
*dst
,
1429 const union tgsi_exec_channel
*src
)
1431 dst
->f
[0] = -src
->f
[0];
1432 dst
->f
[1] = -src
->f
[1];
1433 dst
->f
[2] = -src
->f
[2];
1434 dst
->f
[3] = -src
->f
[3];
1439 union tgsi_exec_channel
*dst
,
1440 const union tgsi_exec_channel
*src0
,
1441 const union tgsi_exec_channel
*src1
)
1444 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1445 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1446 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1447 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1449 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1450 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1451 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1452 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1457 micro_sub(union tgsi_exec_channel
*dst
,
1458 const union tgsi_exec_channel
*src0
,
1459 const union tgsi_exec_channel
*src1
)
1461 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1462 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1463 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1464 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1468 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1469 const uint chan_index
,
1472 const union tgsi_exec_channel
*index
,
1473 const union tgsi_exec_channel
*index2D
,
1474 union tgsi_exec_channel
*chan
)
1478 assert(swizzle
< 4);
1481 case TGSI_FILE_CONSTANT
:
1482 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1483 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1484 assert(mach
->Consts
[index2D
->i
[i
]]);
1486 if (index
->i
[i
] < 0) {
1489 /* NOTE: copying the const value as a uint instead of float */
1490 const uint constbuf
= index2D
->i
[i
];
1491 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1492 const int pos
= index
->i
[i
] * 4 + swizzle
;
1493 /* const buffer bounds check */
1494 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1496 /* Debug: print warning */
1497 static int count
= 0;
1499 debug_printf("TGSI Exec: const buffer index %d"
1500 " out of bounds\n", pos
);
1505 chan
->u
[i
] = buf
[pos
];
1510 case TGSI_FILE_INPUT
:
1511 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1513 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1514 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1515 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1516 index2D->i[i], index->i[i]);
1518 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1520 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1521 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1525 case TGSI_FILE_SYSTEM_VALUE
:
1526 /* XXX no swizzling at this point. Will be needed if we put
1527 * gl_FragCoord, for example, in a sys value register.
1529 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1530 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1534 case TGSI_FILE_TEMPORARY
:
1535 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1536 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1537 assert(index2D
->i
[i
] == 0);
1539 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1543 case TGSI_FILE_IMMEDIATE
:
1544 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1545 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1546 assert(index2D
->i
[i
] == 0);
1548 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1552 case TGSI_FILE_ADDRESS
:
1553 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1554 assert(index
->i
[i
] >= 0);
1555 assert(index2D
->i
[i
] == 0);
1557 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1561 case TGSI_FILE_OUTPUT
:
1562 /* vertex/fragment output vars can be read too */
1563 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1564 assert(index
->i
[i
] >= 0);
1565 assert(index2D
->i
[i
] == 0);
1567 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1573 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1580 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1581 union tgsi_exec_channel
*chan
,
1582 const struct tgsi_full_src_register
*reg
,
1583 const uint chan_index
,
1584 enum tgsi_exec_datatype src_datatype
)
1586 union tgsi_exec_channel index
;
1587 union tgsi_exec_channel index2D
;
1590 /* We start with a direct index into a register file.
1594 * file = Register.File
1595 * [1] = Register.Index
1600 index
.i
[3] = reg
->Register
.Index
;
1602 /* There is an extra source register that indirectly subscripts
1603 * a register file. The direct index now becomes an offset
1604 * that is being added to the indirect register.
1608 * ind = Indirect.File
1609 * [2] = Indirect.Index
1610 * .x = Indirect.SwizzleX
1612 if (reg
->Register
.Indirect
) {
1613 union tgsi_exec_channel index2
;
1614 union tgsi_exec_channel indir_index
;
1615 const uint execmask
= mach
->ExecMask
;
1618 /* which address register (always zero now) */
1622 index2
.i
[3] = reg
->Indirect
.Index
;
1623 /* get current value of address register[swizzle] */
1624 swizzle
= reg
->Indirect
.Swizzle
;
1625 fetch_src_file_channel(mach
,
1633 /* add value of address register to the offset */
1634 index
.i
[0] += indir_index
.i
[0];
1635 index
.i
[1] += indir_index
.i
[1];
1636 index
.i
[2] += indir_index
.i
[2];
1637 index
.i
[3] += indir_index
.i
[3];
1639 /* for disabled execution channels, zero-out the index to
1640 * avoid using a potential garbage value.
1642 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1643 if ((execmask
& (1 << i
)) == 0)
1648 /* There is an extra source register that is a second
1649 * subscript to a register file. Effectively it means that
1650 * the register file is actually a 2D array of registers.
1654 * [3] = Dimension.Index
1656 if (reg
->Register
.Dimension
) {
1660 index2D
.i
[3] = reg
->Dimension
.Index
;
1662 /* Again, the second subscript index can be addressed indirectly
1663 * identically to the first one.
1664 * Nothing stops us from indirectly addressing the indirect register,
1665 * but there is no need for that, so we won't exercise it.
1667 * file[ind[4].y+3][1],
1669 * ind = DimIndirect.File
1670 * [4] = DimIndirect.Index
1671 * .y = DimIndirect.SwizzleX
1673 if (reg
->Dimension
.Indirect
) {
1674 union tgsi_exec_channel index2
;
1675 union tgsi_exec_channel indir_index
;
1676 const uint execmask
= mach
->ExecMask
;
1682 index2
.i
[3] = reg
->DimIndirect
.Index
;
1684 swizzle
= reg
->DimIndirect
.Swizzle
;
1685 fetch_src_file_channel(mach
,
1687 reg
->DimIndirect
.File
,
1693 index2D
.i
[0] += indir_index
.i
[0];
1694 index2D
.i
[1] += indir_index
.i
[1];
1695 index2D
.i
[2] += indir_index
.i
[2];
1696 index2D
.i
[3] += indir_index
.i
[3];
1698 /* for disabled execution channels, zero-out the index to
1699 * avoid using a potential garbage value.
1701 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1702 if ((execmask
& (1 << i
)) == 0) {
1708 /* If by any chance there was a need for a 3D array of register
1709 * files, we would have to check whether Dimension is followed
1710 * by a dimension register and continue the saga.
1719 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1720 fetch_src_file_channel(mach
,
1730 fetch_source(const struct tgsi_exec_machine
*mach
,
1731 union tgsi_exec_channel
*chan
,
1732 const struct tgsi_full_src_register
*reg
,
1733 const uint chan_index
,
1734 enum tgsi_exec_datatype src_datatype
)
1736 fetch_source_d(mach
, chan
, reg
, chan_index
, src_datatype
);
1738 if (reg
->Register
.Absolute
) {
1739 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1740 micro_abs(chan
, chan
);
1742 micro_iabs(chan
, chan
);
1746 if (reg
->Register
.Negate
) {
1747 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1748 micro_neg(chan
, chan
);
1750 micro_ineg(chan
, chan
);
1755 static union tgsi_exec_channel
*
1756 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1757 const union tgsi_exec_channel
*chan
,
1758 const struct tgsi_full_dst_register
*reg
,
1759 const struct tgsi_full_instruction
*inst
,
1761 enum tgsi_exec_datatype dst_datatype
)
1763 static union tgsi_exec_channel null
;
1764 union tgsi_exec_channel
*dst
;
1765 union tgsi_exec_channel index2D
;
1766 int offset
= 0; /* indirection offset */
1770 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1771 check_inf_or_nan(chan
);
1774 /* There is an extra source register that indirectly subscripts
1775 * a register file. The direct index now becomes an offset
1776 * that is being added to the indirect register.
1780 * ind = Indirect.File
1781 * [2] = Indirect.Index
1782 * .x = Indirect.SwizzleX
1784 if (reg
->Register
.Indirect
) {
1785 union tgsi_exec_channel index
;
1786 union tgsi_exec_channel indir_index
;
1789 /* which address register (always zero for now) */
1793 index
.i
[3] = reg
->Indirect
.Index
;
1795 /* get current value of address register[swizzle] */
1796 swizzle
= reg
->Indirect
.Swizzle
;
1798 /* fetch values from the address/indirection register */
1799 fetch_src_file_channel(mach
,
1807 /* save indirection offset */
1808 offset
= indir_index
.i
[0];
1811 /* There is an extra source register that is a second
1812 * subscript to a register file. Effectively it means that
1813 * the register file is actually a 2D array of registers.
1817 * [3] = Dimension.Index
1819 if (reg
->Register
.Dimension
) {
1823 index2D
.i
[3] = reg
->Dimension
.Index
;
1825 /* Again, the second subscript index can be addressed indirectly
1826 * identically to the first one.
1827 * Nothing stops us from indirectly addressing the indirect register,
1828 * but there is no need for that, so we won't exercise it.
1830 * file[ind[4].y+3][1],
1832 * ind = DimIndirect.File
1833 * [4] = DimIndirect.Index
1834 * .y = DimIndirect.SwizzleX
1836 if (reg
->Dimension
.Indirect
) {
1837 union tgsi_exec_channel index2
;
1838 union tgsi_exec_channel indir_index
;
1839 const uint execmask
= mach
->ExecMask
;
1846 index2
.i
[3] = reg
->DimIndirect
.Index
;
1848 swizzle
= reg
->DimIndirect
.Swizzle
;
1849 fetch_src_file_channel(mach
,
1851 reg
->DimIndirect
.File
,
1857 index2D
.i
[0] += indir_index
.i
[0];
1858 index2D
.i
[1] += indir_index
.i
[1];
1859 index2D
.i
[2] += indir_index
.i
[2];
1860 index2D
.i
[3] += indir_index
.i
[3];
1862 /* for disabled execution channels, zero-out the index to
1863 * avoid using a potential garbage value.
1865 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1866 if ((execmask
& (1 << i
)) == 0) {
1872 /* If by any chance there was a need for a 3D array of register
1873 * files, we would have to check whether Dimension is followed
1874 * by a dimension register and continue the saga.
1883 switch (reg
->Register
.File
) {
1884 case TGSI_FILE_NULL
:
1888 case TGSI_FILE_OUTPUT
:
1889 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1890 + reg
->Register
.Index
;
1891 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1893 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1894 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1895 reg
->Register
.Index
);
1896 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1897 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1898 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1899 if (execmask
& (1 << i
))
1900 debug_printf("%f, ", chan
->f
[i
]);
1901 debug_printf(")\n");
1906 case TGSI_FILE_TEMPORARY
:
1907 index
= reg
->Register
.Index
;
1908 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1909 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1912 case TGSI_FILE_ADDRESS
:
1913 index
= reg
->Register
.Index
;
1914 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1926 store_dest_double(struct tgsi_exec_machine
*mach
,
1927 const union tgsi_exec_channel
*chan
,
1928 const struct tgsi_full_dst_register
*reg
,
1929 const struct tgsi_full_instruction
*inst
,
1931 enum tgsi_exec_datatype dst_datatype
)
1933 union tgsi_exec_channel
*dst
;
1934 const uint execmask
= mach
->ExecMask
;
1937 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
1943 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1944 if (execmask
& (1 << i
))
1945 dst
->i
[i
] = chan
->i
[i
];
1949 store_dest(struct tgsi_exec_machine
*mach
,
1950 const union tgsi_exec_channel
*chan
,
1951 const struct tgsi_full_dst_register
*reg
,
1952 const struct tgsi_full_instruction
*inst
,
1954 enum tgsi_exec_datatype dst_datatype
)
1956 union tgsi_exec_channel
*dst
;
1957 const uint execmask
= mach
->ExecMask
;
1960 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
1965 if (!inst
->Instruction
.Saturate
) {
1966 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1967 if (execmask
& (1 << i
))
1968 dst
->i
[i
] = chan
->i
[i
];
1971 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1972 if (execmask
& (1 << i
)) {
1973 if (chan
->f
[i
] < 0.0f
)
1975 else if (chan
->f
[i
] > 1.0f
)
1978 dst
->i
[i
] = chan
->i
[i
];
1983 #define FETCH(VAL,INDEX,CHAN)\
1984 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1986 #define IFETCH(VAL,INDEX,CHAN)\
1987 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1991 * Execute ARB-style KIL which is predicated by a src register.
1992 * Kill fragment if any of the four values is less than zero.
1995 exec_kill_if(struct tgsi_exec_machine
*mach
,
1996 const struct tgsi_full_instruction
*inst
)
2000 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2001 union tgsi_exec_channel r
[1];
2003 /* This mask stores component bits that were already tested. */
2006 for (chan_index
= 0; chan_index
< 4; chan_index
++)
2011 /* unswizzle channel */
2012 swizzle
= tgsi_util_get_full_src_register_swizzle (
2016 /* check if the component has not been already tested */
2017 if (uniquemask
& (1 << swizzle
))
2019 uniquemask
|= 1 << swizzle
;
2021 FETCH(&r
[0], 0, chan_index
);
2022 for (i
= 0; i
< 4; i
++)
2023 if (r
[0].f
[i
] < 0.0f
)
2027 /* restrict to fragments currently executing */
2028 kilmask
&= mach
->ExecMask
;
2030 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2034 * Unconditional fragment kill/discard.
2037 exec_kill(struct tgsi_exec_machine
*mach
,
2038 const struct tgsi_full_instruction
*inst
)
2040 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2042 /* kill fragment for all fragments currently executing */
2043 kilmask
= mach
->ExecMask
;
2044 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2048 emit_vertex(struct tgsi_exec_machine
*mach
)
2050 /* FIXME: check for exec mask correctly
2052 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2053 if ((mach->ExecMask & (1 << i)))
2055 if (mach
->ExecMask
) {
2056 if (mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]] >= mach
->MaxOutputVertices
)
2059 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
2060 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
2065 emit_primitive(struct tgsi_exec_machine
*mach
)
2067 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
2068 /* FIXME: check for exec mask correctly
2070 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2071 if ((mach->ExecMask & (1 << i)))
2073 if (mach
->ExecMask
) {
2075 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
2076 mach
->Primitives
[*prim_count
] = 0;
2081 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
2083 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
2085 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
2086 if (emitted_verts
) {
2087 emit_primitive(mach
);
2094 * Fetch four texture samples using STR texture coordinates.
2097 fetch_texel( struct tgsi_sampler
*sampler
,
2098 const unsigned sview_idx
,
2099 const unsigned sampler_idx
,
2100 const union tgsi_exec_channel
*s
,
2101 const union tgsi_exec_channel
*t
,
2102 const union tgsi_exec_channel
*p
,
2103 const union tgsi_exec_channel
*c0
,
2104 const union tgsi_exec_channel
*c1
,
2105 float derivs
[3][2][TGSI_QUAD_SIZE
],
2106 const int8_t offset
[3],
2107 enum tgsi_sampler_control control
,
2108 union tgsi_exec_channel
*r
,
2109 union tgsi_exec_channel
*g
,
2110 union tgsi_exec_channel
*b
,
2111 union tgsi_exec_channel
*a
)
2114 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2116 /* FIXME: handle explicit derivs, offsets */
2117 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
2118 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
2120 for (j
= 0; j
< 4; j
++) {
2121 r
->f
[j
] = rgba
[0][j
];
2122 g
->f
[j
] = rgba
[1][j
];
2123 b
->f
[j
] = rgba
[2][j
];
2124 a
->f
[j
] = rgba
[3][j
];
2129 #define TEX_MODIFIER_NONE 0
2130 #define TEX_MODIFIER_PROJECTED 1
2131 #define TEX_MODIFIER_LOD_BIAS 2
2132 #define TEX_MODIFIER_EXPLICIT_LOD 3
2133 #define TEX_MODIFIER_LEVEL_ZERO 4
2134 #define TEX_MODIFIER_GATHER 5
2137 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
2140 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
2141 const struct tgsi_full_instruction
*inst
,
2144 if (inst
->Texture
.NumOffsets
== 1) {
2145 union tgsi_exec_channel index
;
2146 union tgsi_exec_channel offset
[3];
2147 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
2148 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
2149 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
2150 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
2151 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
2152 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
2153 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
2154 offsets
[0] = offset
[0].i
[0];
2155 offsets
[1] = offset
[1].i
[0];
2156 offsets
[2] = offset
[2].i
[0];
2158 assert(inst
->Texture
.NumOffsets
== 0);
2159 offsets
[0] = offsets
[1] = offsets
[2] = 0;
2165 * Fetch dx and dy values for one channel (s, t or r).
2166 * Put dx values into one float array, dy values into another.
2169 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
2170 const struct tgsi_full_instruction
*inst
,
2173 float derivs
[2][TGSI_QUAD_SIZE
])
2175 union tgsi_exec_channel d
;
2176 FETCH(&d
, regdsrcx
, chan
);
2177 derivs
[0][0] = d
.f
[0];
2178 derivs
[0][1] = d
.f
[1];
2179 derivs
[0][2] = d
.f
[2];
2180 derivs
[0][3] = d
.f
[3];
2181 FETCH(&d
, regdsrcx
+ 1, chan
);
2182 derivs
[1][0] = d
.f
[0];
2183 derivs
[1][1] = d
.f
[1];
2184 derivs
[1][2] = d
.f
[2];
2185 derivs
[1][3] = d
.f
[3];
2189 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
2190 const struct tgsi_full_instruction
*inst
,
2195 if (inst
->Src
[sampler
].Register
.Indirect
) {
2196 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2197 union tgsi_exec_channel indir_index
, index2
;
2198 const uint execmask
= mach
->ExecMask
;
2202 index2
.i
[3] = reg
->Indirect
.Index
;
2204 fetch_src_file_channel(mach
,
2207 reg
->Indirect
.Swizzle
,
2211 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2212 if (execmask
& (1 << i
)) {
2213 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[i
];
2219 unit
= inst
->Src
[sampler
].Register
.Index
;
2225 * execute a texture instruction.
2227 * modifier is used to control the channel routing for the
2228 * instruction variants like proj, lod, and texture with lod bias.
2229 * sampler indicates which src register the sampler is contained in.
2232 exec_tex(struct tgsi_exec_machine
*mach
,
2233 const struct tgsi_full_instruction
*inst
,
2234 uint modifier
, uint sampler
)
2236 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2237 union tgsi_exec_channel r
[5];
2238 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2242 int dim
, shadow_ref
, i
;
2244 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2245 /* always fetch all 3 offsets, overkill but keeps code simple */
2246 fetch_texel_offsets(mach
, inst
, offsets
);
2248 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2249 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2251 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2252 shadow_ref
= tgsi_util_get_shadow_ref_src_index(inst
->Texture
.Texture
);
2255 if (shadow_ref
>= 0)
2256 assert(shadow_ref
>= dim
&& shadow_ref
< ARRAY_SIZE(args
));
2258 /* fetch modifier to the last argument */
2259 if (modifier
!= TEX_MODIFIER_NONE
) {
2260 const int last
= ARRAY_SIZE(args
) - 1;
2262 /* fetch modifier from src0.w or src1.x */
2264 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2265 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2268 assert(shadow_ref
!= 4);
2269 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2272 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2273 args
[last
] = &r
[last
];
2277 args
[last
] = &ZeroVec
;
2280 /* point unused arguments to zero vector */
2281 for (i
= dim
; i
< last
; i
++)
2284 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2285 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2286 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2287 control
= TGSI_SAMPLER_LOD_BIAS
;
2288 else if (modifier
== TEX_MODIFIER_GATHER
)
2289 control
= TGSI_SAMPLER_GATHER
;
2292 for (i
= dim
; i
< ARRAY_SIZE(args
); i
++)
2296 /* fetch coordinates */
2297 for (i
= 0; i
< dim
; i
++) {
2298 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2301 micro_div(&r
[i
], &r
[i
], proj
);
2306 /* fetch reference value */
2307 if (shadow_ref
>= 0) {
2308 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2311 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2313 args
[shadow_ref
] = &r
[shadow_ref
];
2316 fetch_texel(mach
->Sampler
, unit
, unit
,
2317 args
[0], args
[1], args
[2], args
[3], args
[4],
2318 NULL
, offsets
, control
,
2319 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2322 debug_printf("fetch r: %g %g %g %g\n",
2323 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2324 debug_printf("fetch g: %g %g %g %g\n",
2325 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2326 debug_printf("fetch b: %g %g %g %g\n",
2327 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2328 debug_printf("fetch a: %g %g %g %g\n",
2329 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2332 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2333 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2334 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2340 exec_lodq(struct tgsi_exec_machine
*mach
,
2341 const struct tgsi_full_instruction
*inst
)
2346 union tgsi_exec_channel coords
[4];
2347 const union tgsi_exec_channel
*args
[ARRAY_SIZE(coords
)];
2348 union tgsi_exec_channel r
[2];
2350 unit
= fetch_sampler_unit(mach
, inst
, 1);
2351 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2352 assert(dim
<= ARRAY_SIZE(coords
));
2353 /* fetch coordinates */
2354 for (i
= 0; i
< dim
; i
++) {
2355 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2356 args
[i
] = &coords
[i
];
2358 for (i
= dim
; i
< ARRAY_SIZE(coords
); i
++) {
2361 mach
->Sampler
->query_lod(mach
->Sampler
, unit
, unit
,
2366 TGSI_SAMPLER_LOD_NONE
,
2370 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2371 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2372 TGSI_EXEC_DATA_FLOAT
);
2374 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2375 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2376 TGSI_EXEC_DATA_FLOAT
);
2381 exec_txd(struct tgsi_exec_machine
*mach
,
2382 const struct tgsi_full_instruction
*inst
)
2384 union tgsi_exec_channel r
[4];
2385 float derivs
[3][2][TGSI_QUAD_SIZE
];
2390 unit
= fetch_sampler_unit(mach
, inst
, 3);
2391 /* always fetch all 3 offsets, overkill but keeps code simple */
2392 fetch_texel_offsets(mach
, inst
, offsets
);
2394 switch (inst
->Texture
.Texture
) {
2395 case TGSI_TEXTURE_1D
:
2396 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2398 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2400 fetch_texel(mach
->Sampler
, unit
, unit
,
2401 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2402 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2403 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2406 case TGSI_TEXTURE_SHADOW1D
:
2407 case TGSI_TEXTURE_1D_ARRAY
:
2408 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2409 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2410 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2411 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2412 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2414 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2416 fetch_texel(mach
->Sampler
, unit
, unit
,
2417 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2418 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2419 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2422 case TGSI_TEXTURE_2D
:
2423 case TGSI_TEXTURE_RECT
:
2424 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2425 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2427 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2428 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2430 fetch_texel(mach
->Sampler
, unit
, unit
,
2431 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2432 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2433 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2437 case TGSI_TEXTURE_SHADOW2D
:
2438 case TGSI_TEXTURE_SHADOWRECT
:
2439 case TGSI_TEXTURE_2D_ARRAY
:
2440 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2441 /* only SHADOW2D_ARRAY actually needs W */
2442 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2443 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2444 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2445 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2447 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2448 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2450 fetch_texel(mach
->Sampler
, unit
, unit
,
2451 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2452 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2453 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2456 case TGSI_TEXTURE_3D
:
2457 case TGSI_TEXTURE_CUBE
:
2458 case TGSI_TEXTURE_CUBE_ARRAY
:
2459 case TGSI_TEXTURE_SHADOWCUBE
:
2460 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2461 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2462 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2463 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2464 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2466 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2467 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2468 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2470 fetch_texel(mach
->Sampler
, unit
, unit
,
2471 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2472 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2473 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2480 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2481 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2482 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2489 exec_txf(struct tgsi_exec_machine
*mach
,
2490 const struct tgsi_full_instruction
*inst
)
2492 union tgsi_exec_channel r
[4];
2495 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2500 unit
= fetch_sampler_unit(mach
, inst
, 1);
2501 /* always fetch all 3 offsets, overkill but keeps code simple */
2502 fetch_texel_offsets(mach
, inst
, offsets
);
2504 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2506 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2507 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2508 target
= mach
->SamplerViews
[unit
].Resource
;
2511 target
= inst
->Texture
.Texture
;
2514 case TGSI_TEXTURE_3D
:
2515 case TGSI_TEXTURE_2D_ARRAY
:
2516 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2517 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2518 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2520 case TGSI_TEXTURE_2D
:
2521 case TGSI_TEXTURE_RECT
:
2522 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2523 case TGSI_TEXTURE_SHADOW2D
:
2524 case TGSI_TEXTURE_SHADOWRECT
:
2525 case TGSI_TEXTURE_1D_ARRAY
:
2526 case TGSI_TEXTURE_2D_MSAA
:
2527 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2529 case TGSI_TEXTURE_BUFFER
:
2530 case TGSI_TEXTURE_1D
:
2531 case TGSI_TEXTURE_SHADOW1D
:
2532 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2539 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2542 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2543 r
[0].f
[j
] = rgba
[0][j
];
2544 r
[1].f
[j
] = rgba
[1][j
];
2545 r
[2].f
[j
] = rgba
[2][j
];
2546 r
[3].f
[j
] = rgba
[3][j
];
2549 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2550 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2551 unsigned char swizzles
[4];
2552 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2553 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2554 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2555 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2557 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2558 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2559 store_dest(mach
, &r
[swizzles
[chan
]],
2560 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2565 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2566 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2567 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2574 exec_txq(struct tgsi_exec_machine
*mach
,
2575 const struct tgsi_full_instruction
*inst
)
2578 union tgsi_exec_channel r
[4], src
;
2583 unit
= fetch_sampler_unit(mach
, inst
, 1);
2585 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2587 /* XXX: This interface can't return per-pixel values */
2588 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2590 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2591 for (j
= 0; j
< 4; j
++) {
2592 r
[j
].i
[i
] = result
[j
];
2596 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2597 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2598 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2599 TGSI_EXEC_DATA_INT
);
2605 exec_sample(struct tgsi_exec_machine
*mach
,
2606 const struct tgsi_full_instruction
*inst
,
2607 uint modifier
, boolean compare
)
2609 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2610 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2611 union tgsi_exec_channel r
[5], c1
;
2612 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2613 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2615 unsigned char swizzles
[4];
2618 /* always fetch all 3 offsets, overkill but keeps code simple */
2619 fetch_texel_offsets(mach
, inst
, offsets
);
2621 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2623 if (modifier
!= TEX_MODIFIER_NONE
) {
2624 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2625 FETCH(&c1
, 3, TGSI_CHAN_X
);
2627 control
= TGSI_SAMPLER_LOD_BIAS
;
2629 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2630 FETCH(&c1
, 3, TGSI_CHAN_X
);
2632 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2635 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2636 control
= TGSI_SAMPLER_LOD_ZERO
;
2640 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2642 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2643 case TGSI_TEXTURE_1D
:
2645 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2646 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2647 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2648 NULL
, offsets
, control
,
2649 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2652 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2653 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2654 NULL
, offsets
, control
,
2655 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2659 case TGSI_TEXTURE_1D_ARRAY
:
2660 case TGSI_TEXTURE_2D
:
2661 case TGSI_TEXTURE_RECT
:
2662 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2664 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2665 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2666 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2667 NULL
, offsets
, control
,
2668 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2671 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2672 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2673 NULL
, offsets
, control
,
2674 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2678 case TGSI_TEXTURE_2D_ARRAY
:
2679 case TGSI_TEXTURE_3D
:
2680 case TGSI_TEXTURE_CUBE
:
2681 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2682 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2684 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2685 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2686 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2687 NULL
, offsets
, control
,
2688 &r
[0], &r
[1], &r
[2], &r
[3]);
2691 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2692 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2693 NULL
, offsets
, control
,
2694 &r
[0], &r
[1], &r
[2], &r
[3]);
2698 case TGSI_TEXTURE_CUBE_ARRAY
:
2699 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2700 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2701 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2703 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2704 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2705 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2706 NULL
, offsets
, control
,
2707 &r
[0], &r
[1], &r
[2], &r
[3]);
2710 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2711 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2712 NULL
, offsets
, control
,
2713 &r
[0], &r
[1], &r
[2], &r
[3]);
2722 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2723 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2724 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2725 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2727 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2728 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2729 store_dest(mach
, &r
[swizzles
[chan
]],
2730 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2736 exec_sample_d(struct tgsi_exec_machine
*mach
,
2737 const struct tgsi_full_instruction
*inst
)
2739 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2740 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2741 union tgsi_exec_channel r
[4];
2742 float derivs
[3][2][TGSI_QUAD_SIZE
];
2744 unsigned char swizzles
[4];
2747 /* always fetch all 3 offsets, overkill but keeps code simple */
2748 fetch_texel_offsets(mach
, inst
, offsets
);
2750 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2752 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2753 case TGSI_TEXTURE_1D
:
2754 case TGSI_TEXTURE_1D_ARRAY
:
2755 /* only 1D array actually needs Y */
2756 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2758 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2760 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2761 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2762 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2763 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2766 case TGSI_TEXTURE_2D
:
2767 case TGSI_TEXTURE_RECT
:
2768 case TGSI_TEXTURE_2D_ARRAY
:
2769 /* only 2D array actually needs Z */
2770 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2771 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2773 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2774 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2776 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2777 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2778 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2779 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2782 case TGSI_TEXTURE_3D
:
2783 case TGSI_TEXTURE_CUBE
:
2784 case TGSI_TEXTURE_CUBE_ARRAY
:
2785 /* only cube array actually needs W */
2786 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2787 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2788 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2790 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2791 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2792 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2794 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2795 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2796 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2797 &r
[0], &r
[1], &r
[2], &r
[3]);
2804 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2805 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2806 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2807 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2809 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2810 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2811 store_dest(mach
, &r
[swizzles
[chan
]],
2812 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2819 * Evaluate a constant-valued coefficient at the position of the
2824 struct tgsi_exec_machine
*mach
,
2830 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2831 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2836 * Evaluate a linear-valued coefficient at the position of the
2841 struct tgsi_exec_machine
*mach
,
2845 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2846 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2847 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2848 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2849 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2850 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2851 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2852 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2853 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2857 * Evaluate a perspective-valued coefficient at the position of the
2861 eval_perspective_coef(
2862 struct tgsi_exec_machine
*mach
,
2866 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2867 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2868 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2869 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2870 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2871 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2872 /* divide by W here */
2873 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2874 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2875 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2876 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2880 typedef void (* eval_coef_func
)(
2881 struct tgsi_exec_machine
*mach
,
2886 exec_declaration(struct tgsi_exec_machine
*mach
,
2887 const struct tgsi_full_declaration
*decl
)
2889 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2890 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2894 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
2895 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2896 uint first
, last
, mask
;
2898 first
= decl
->Range
.First
;
2899 last
= decl
->Range
.Last
;
2900 mask
= decl
->Declaration
.UsageMask
;
2902 /* XXX we could remove this special-case code since
2903 * mach->InterpCoefs[first].a0 should already have the
2904 * front/back-face value. But we should first update the
2905 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2906 * Then, we could remove the tgsi_exec_machine::Face field.
2908 /* XXX make FACE a system value */
2909 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2912 assert(decl
->Semantic
.Index
== 0);
2913 assert(first
== last
);
2915 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2916 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2919 eval_coef_func eval
;
2922 switch (decl
->Interp
.Interpolate
) {
2923 case TGSI_INTERPOLATE_CONSTANT
:
2924 eval
= eval_constant_coef
;
2927 case TGSI_INTERPOLATE_LINEAR
:
2928 eval
= eval_linear_coef
;
2931 case TGSI_INTERPOLATE_PERSPECTIVE
:
2932 eval
= eval_perspective_coef
;
2935 case TGSI_INTERPOLATE_COLOR
:
2936 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
2944 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2945 if (mask
& (1 << j
)) {
2946 for (i
= first
; i
<= last
; i
++) {
2953 if (DEBUG_EXECUTION
) {
2955 for (i
= first
; i
<= last
; ++i
) {
2956 debug_printf("IN[%2u] = ", i
);
2957 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2961 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2962 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
2963 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
2964 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
2965 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
2974 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
2975 const union tgsi_exec_channel
*src
);
2978 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
2979 const struct tgsi_full_instruction
*inst
,
2981 enum tgsi_exec_datatype dst_datatype
,
2982 enum tgsi_exec_datatype src_datatype
)
2985 union tgsi_exec_channel src
;
2986 union tgsi_exec_channel dst
;
2988 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2990 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2991 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2992 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2998 exec_vector_unary(struct tgsi_exec_machine
*mach
,
2999 const struct tgsi_full_instruction
*inst
,
3001 enum tgsi_exec_datatype dst_datatype
,
3002 enum tgsi_exec_datatype src_datatype
)
3005 struct tgsi_exec_vector dst
;
3007 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3008 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3009 union tgsi_exec_channel src
;
3011 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
3012 op(&dst
.xyzw
[chan
], &src
);
3015 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3016 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3017 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3022 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
3023 const union tgsi_exec_channel
*src0
,
3024 const union tgsi_exec_channel
*src1
);
3027 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
3028 const struct tgsi_full_instruction
*inst
,
3030 enum tgsi_exec_datatype dst_datatype
,
3031 enum tgsi_exec_datatype src_datatype
)
3034 union tgsi_exec_channel src
[2];
3035 union tgsi_exec_channel dst
;
3037 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3038 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
3039 op(&dst
, &src
[0], &src
[1]);
3040 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3041 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3042 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3048 exec_vector_binary(struct tgsi_exec_machine
*mach
,
3049 const struct tgsi_full_instruction
*inst
,
3051 enum tgsi_exec_datatype dst_datatype
,
3052 enum tgsi_exec_datatype src_datatype
)
3055 struct tgsi_exec_vector dst
;
3057 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3058 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3059 union tgsi_exec_channel src
[2];
3061 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3062 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3063 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
3066 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3067 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3068 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3073 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
3074 const union tgsi_exec_channel
*src0
,
3075 const union tgsi_exec_channel
*src1
,
3076 const union tgsi_exec_channel
*src2
);
3079 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
3080 const struct tgsi_full_instruction
*inst
,
3081 micro_trinary_op op
,
3082 enum tgsi_exec_datatype dst_datatype
,
3083 enum tgsi_exec_datatype src_datatype
)
3086 struct tgsi_exec_vector dst
;
3088 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3089 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3090 union tgsi_exec_channel src
[3];
3092 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3093 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3094 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3095 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3098 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3099 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3100 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3105 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
3106 const union tgsi_exec_channel
*src0
,
3107 const union tgsi_exec_channel
*src1
,
3108 const union tgsi_exec_channel
*src2
,
3109 const union tgsi_exec_channel
*src3
);
3112 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
3113 const struct tgsi_full_instruction
*inst
,
3114 micro_quaternary_op op
,
3115 enum tgsi_exec_datatype dst_datatype
,
3116 enum tgsi_exec_datatype src_datatype
)
3119 struct tgsi_exec_vector dst
;
3121 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3122 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3123 union tgsi_exec_channel src
[4];
3125 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3126 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3127 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3128 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
3129 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
3132 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3133 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3134 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3140 exec_dp3(struct tgsi_exec_machine
*mach
,
3141 const struct tgsi_full_instruction
*inst
)
3144 union tgsi_exec_channel arg
[3];
3146 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3147 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3148 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3150 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
3151 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3152 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3153 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3156 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3157 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3158 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3164 exec_dp4(struct tgsi_exec_machine
*mach
,
3165 const struct tgsi_full_instruction
*inst
)
3168 union tgsi_exec_channel arg
[3];
3170 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3171 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3172 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3174 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
3175 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3176 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3177 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3180 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3181 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3182 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3188 exec_dp2(struct tgsi_exec_machine
*mach
,
3189 const struct tgsi_full_instruction
*inst
)
3192 union tgsi_exec_channel arg
[3];
3194 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3195 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3196 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3198 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3199 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3200 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3202 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3203 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3204 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3210 exec_pk2h(struct tgsi_exec_machine
*mach
,
3211 const struct tgsi_full_instruction
*inst
)
3214 union tgsi_exec_channel arg
[2], dst
;
3216 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3217 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3218 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3219 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3220 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3222 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3223 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3224 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3230 exec_up2h(struct tgsi_exec_machine
*mach
,
3231 const struct tgsi_full_instruction
*inst
)
3234 union tgsi_exec_channel arg
, dst
[2];
3236 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3237 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3238 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3239 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3241 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3242 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3243 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3249 micro_ucmp(union tgsi_exec_channel
*dst
,
3250 const union tgsi_exec_channel
*src0
,
3251 const union tgsi_exec_channel
*src1
,
3252 const union tgsi_exec_channel
*src2
)
3254 dst
->f
[0] = src0
->u
[0] ? src1
->f
[0] : src2
->f
[0];
3255 dst
->f
[1] = src0
->u
[1] ? src1
->f
[1] : src2
->f
[1];
3256 dst
->f
[2] = src0
->u
[2] ? src1
->f
[2] : src2
->f
[2];
3257 dst
->f
[3] = src0
->u
[3] ? src1
->f
[3] : src2
->f
[3];
3261 exec_ucmp(struct tgsi_exec_machine
*mach
,
3262 const struct tgsi_full_instruction
*inst
)
3265 struct tgsi_exec_vector dst
;
3267 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3268 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3269 union tgsi_exec_channel src
[3];
3271 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
,
3272 TGSI_EXEC_DATA_UINT
);
3273 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
,
3274 TGSI_EXEC_DATA_FLOAT
);
3275 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
,
3276 TGSI_EXEC_DATA_FLOAT
);
3277 micro_ucmp(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3280 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3281 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3282 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
,
3283 TGSI_EXEC_DATA_FLOAT
);
3289 exec_scs(struct tgsi_exec_machine
*mach
,
3290 const struct tgsi_full_instruction
*inst
)
3292 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
3293 union tgsi_exec_channel arg
;
3294 union tgsi_exec_channel result
;
3296 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3298 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3299 micro_cos(&result
, &arg
);
3300 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3302 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3303 micro_sin(&result
, &arg
);
3304 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3307 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3308 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3310 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3311 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3316 exec_xpd(struct tgsi_exec_machine
*mach
,
3317 const struct tgsi_full_instruction
*inst
)
3319 union tgsi_exec_channel r
[6];
3320 union tgsi_exec_channel d
[3];
3322 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3323 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3325 micro_mul(&r
[2], &r
[0], &r
[1]);
3327 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3328 fetch_source(mach
, &r
[4], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3330 micro_mul(&r
[5], &r
[3], &r
[4] );
3331 micro_sub(&d
[TGSI_CHAN_X
], &r
[2], &r
[5]);
3333 fetch_source(mach
, &r
[2], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3335 micro_mul(&r
[3], &r
[3], &r
[2]);
3337 fetch_source(mach
, &r
[5], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3339 micro_mul(&r
[1], &r
[1], &r
[5]);
3340 micro_sub(&d
[TGSI_CHAN_Y
], &r
[3], &r
[1]);
3342 micro_mul(&r
[5], &r
[5], &r
[4]);
3343 micro_mul(&r
[0], &r
[0], &r
[2]);
3344 micro_sub(&d
[TGSI_CHAN_Z
], &r
[5], &r
[0]);
3346 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3347 store_dest(mach
, &d
[TGSI_CHAN_X
], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3349 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3350 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3352 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3353 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3355 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3356 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3361 exec_dst(struct tgsi_exec_machine
*mach
,
3362 const struct tgsi_full_instruction
*inst
)
3364 union tgsi_exec_channel r
[2];
3365 union tgsi_exec_channel d
[4];
3367 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3368 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3369 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3370 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3372 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3373 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3375 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3376 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3379 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3380 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3382 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3383 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3385 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3386 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3388 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3389 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3394 exec_log(struct tgsi_exec_machine
*mach
,
3395 const struct tgsi_full_instruction
*inst
)
3397 union tgsi_exec_channel r
[3];
3399 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3400 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3401 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3402 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3403 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3404 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3406 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3407 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3408 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3409 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3411 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3412 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3414 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3415 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3420 exec_exp(struct tgsi_exec_machine
*mach
,
3421 const struct tgsi_full_instruction
*inst
)
3423 union tgsi_exec_channel r
[3];
3425 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3426 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3427 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3428 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3429 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3431 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3432 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3433 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3435 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3436 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3437 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3439 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3440 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3445 exec_lit(struct tgsi_exec_machine
*mach
,
3446 const struct tgsi_full_instruction
*inst
)
3448 union tgsi_exec_channel r
[3];
3449 union tgsi_exec_channel d
[3];
3451 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3452 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3453 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3454 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3455 micro_max(&r
[1], &r
[1], &ZeroVec
);
3457 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3458 micro_min(&r
[2], &r
[2], &P128Vec
);
3459 micro_max(&r
[2], &r
[2], &M128Vec
);
3460 micro_pow(&r
[1], &r
[1], &r
[2]);
3461 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3462 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3464 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3465 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3466 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3469 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3470 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3473 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3474 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3479 exec_break(struct tgsi_exec_machine
*mach
)
3481 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3482 /* turn off loop channels for each enabled exec channel */
3483 mach
->LoopMask
&= ~mach
->ExecMask
;
3484 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3485 UPDATE_EXEC_MASK(mach
);
3487 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3489 mach
->Switch
.mask
= 0x0;
3491 UPDATE_EXEC_MASK(mach
);
3496 exec_switch(struct tgsi_exec_machine
*mach
,
3497 const struct tgsi_full_instruction
*inst
)
3499 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3500 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3502 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3503 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3504 mach
->Switch
.mask
= 0x0;
3505 mach
->Switch
.defaultMask
= 0x0;
3507 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3508 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3510 UPDATE_EXEC_MASK(mach
);
3514 exec_case(struct tgsi_exec_machine
*mach
,
3515 const struct tgsi_full_instruction
*inst
)
3517 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3518 union tgsi_exec_channel src
;
3521 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3523 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3526 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3529 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3532 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3536 mach
->Switch
.defaultMask
|= mask
;
3538 mach
->Switch
.mask
|= mask
& prevMask
;
3540 UPDATE_EXEC_MASK(mach
);
3543 /* FIXME: this will only work if default is last */
3545 exec_default(struct tgsi_exec_machine
*mach
)
3547 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3549 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3551 UPDATE_EXEC_MASK(mach
);
3555 exec_endswitch(struct tgsi_exec_machine
*mach
)
3557 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3558 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3560 UPDATE_EXEC_MASK(mach
);
3563 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3564 const union tgsi_double_channel
*src
);
3566 typedef void (* micro_dop_sop
)(union tgsi_double_channel
*dst
,
3567 const union tgsi_double_channel
*src0
,
3568 union tgsi_exec_channel
*src1
);
3570 typedef void (* micro_dop_s
)(union tgsi_double_channel
*dst
,
3571 const union tgsi_exec_channel
*src
);
3573 typedef void (* micro_sop_d
)(union tgsi_exec_channel
*dst
,
3574 const union tgsi_double_channel
*src
);
3577 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3578 union tgsi_double_channel
*chan
,
3579 const struct tgsi_full_src_register
*reg
,
3583 union tgsi_exec_channel src
[2];
3586 fetch_source_d(mach
, &src
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3587 fetch_source_d(mach
, &src
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3589 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3590 chan
->u
[i
][0] = src
[0].u
[i
];
3591 chan
->u
[i
][1] = src
[1].u
[i
];
3593 if (reg
->Register
.Absolute
) {
3594 micro_dabs(chan
, chan
);
3596 if (reg
->Register
.Negate
) {
3597 micro_dneg(chan
, chan
);
3602 store_double_channel(struct tgsi_exec_machine
*mach
,
3603 const union tgsi_double_channel
*chan
,
3604 const struct tgsi_full_dst_register
*reg
,
3605 const struct tgsi_full_instruction
*inst
,
3609 union tgsi_exec_channel dst
[2];
3611 union tgsi_double_channel temp
;
3612 const uint execmask
= mach
->ExecMask
;
3614 if (!inst
->Instruction
.Saturate
) {
3615 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3616 if (execmask
& (1 << i
)) {
3617 dst
[0].u
[i
] = chan
->u
[i
][0];
3618 dst
[1].u
[i
] = chan
->u
[i
][1];
3622 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3623 if (execmask
& (1 << i
)) {
3624 if (chan
->d
[i
] < 0.0)
3626 else if (chan
->d
[i
] > 1.0)
3629 temp
.d
[i
] = chan
->d
[i
];
3631 dst
[0].u
[i
] = temp
.u
[i
][0];
3632 dst
[1].u
[i
] = temp
.u
[i
][1];
3636 store_dest_double(mach
, &dst
[0], reg
, inst
, chan_0
, TGSI_EXEC_DATA_UINT
);
3638 store_dest_double(mach
, &dst
[1], reg
, inst
, chan_1
, TGSI_EXEC_DATA_UINT
);
3642 exec_double_unary(struct tgsi_exec_machine
*mach
,
3643 const struct tgsi_full_instruction
*inst
,
3646 union tgsi_double_channel src
;
3647 union tgsi_double_channel dst
;
3649 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3650 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3652 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3654 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3655 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3657 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3662 exec_double_binary(struct tgsi_exec_machine
*mach
,
3663 const struct tgsi_full_instruction
*inst
,
3665 enum tgsi_exec_datatype dst_datatype
)
3667 union tgsi_double_channel src
[2];
3668 union tgsi_double_channel dst
;
3669 int first_dest_chan
, second_dest_chan
;
3672 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3673 /* these are & because of the way DSLT etc store their destinations */
3674 if (wmask
& TGSI_WRITEMASK_XY
) {
3675 first_dest_chan
= TGSI_CHAN_X
;
3676 second_dest_chan
= TGSI_CHAN_Y
;
3677 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3678 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3679 second_dest_chan
= -1;
3682 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3683 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3685 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3688 if (wmask
& TGSI_WRITEMASK_ZW
) {
3689 first_dest_chan
= TGSI_CHAN_Z
;
3690 second_dest_chan
= TGSI_CHAN_W
;
3691 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3692 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3693 second_dest_chan
= -1;
3696 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3697 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3699 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3704 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3705 const struct tgsi_full_instruction
*inst
,
3708 union tgsi_double_channel src
[3];
3709 union tgsi_double_channel dst
;
3711 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3712 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3713 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3714 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3716 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3718 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3719 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3720 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3721 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3723 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3728 exec_dldexp(struct tgsi_exec_machine
*mach
,
3729 const struct tgsi_full_instruction
*inst
)
3731 union tgsi_double_channel src0
;
3732 union tgsi_exec_channel src1
;
3733 union tgsi_double_channel dst
;
3736 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3737 if (wmask
& TGSI_WRITEMASK_XY
) {
3738 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3739 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3740 micro_dldexp(&dst
, &src0
, &src1
);
3741 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3744 if (wmask
& TGSI_WRITEMASK_ZW
) {
3745 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3746 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3747 micro_dldexp(&dst
, &src0
, &src1
);
3748 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3753 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3754 const struct tgsi_full_instruction
*inst
)
3756 union tgsi_double_channel src
;
3757 union tgsi_double_channel dst
;
3758 union tgsi_exec_channel dst_exp
;
3760 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)) {
3761 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3762 micro_dfracexp(&dst
, &dst_exp
, &src
);
3763 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3764 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3766 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)) {
3767 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3768 micro_dfracexp(&dst
, &dst_exp
, &src
);
3769 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3770 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3775 exec_arg0_64_arg1_32(struct tgsi_exec_machine
*mach
,
3776 const struct tgsi_full_instruction
*inst
,
3779 union tgsi_double_channel src0
;
3780 union tgsi_exec_channel src1
;
3781 union tgsi_double_channel dst
;
3784 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3785 if (wmask
& TGSI_WRITEMASK_XY
) {
3786 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3787 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3788 op(&dst
, &src0
, &src1
);
3789 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3792 if (wmask
& TGSI_WRITEMASK_ZW
) {
3793 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3794 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3795 op(&dst
, &src0
, &src1
);
3796 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3801 get_image_coord_dim(unsigned tgsi_tex
)
3805 case TGSI_TEXTURE_BUFFER
:
3806 case TGSI_TEXTURE_1D
:
3809 case TGSI_TEXTURE_2D
:
3810 case TGSI_TEXTURE_RECT
:
3811 case TGSI_TEXTURE_1D_ARRAY
:
3812 case TGSI_TEXTURE_2D_MSAA
:
3815 case TGSI_TEXTURE_3D
:
3816 case TGSI_TEXTURE_CUBE
:
3817 case TGSI_TEXTURE_2D_ARRAY
:
3818 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3819 case TGSI_TEXTURE_CUBE_ARRAY
:
3823 assert(!"unknown texture target");
3832 get_image_coord_sample(unsigned tgsi_tex
)
3836 case TGSI_TEXTURE_2D_MSAA
:
3839 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3849 exec_load_img(struct tgsi_exec_machine
*mach
,
3850 const struct tgsi_full_instruction
*inst
)
3852 union tgsi_exec_channel r
[4], sample_r
;
3858 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3859 struct tgsi_image_params params
;
3860 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3862 unit
= fetch_sampler_unit(mach
, inst
, 0);
3863 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3864 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3867 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3869 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3870 params
.format
= inst
->Memory
.Format
;
3872 for (i
= 0; i
< dim
; i
++) {
3873 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3877 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3879 mach
->Image
->load(mach
->Image
, ¶ms
,
3880 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3882 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3883 r
[0].f
[j
] = rgba
[0][j
];
3884 r
[1].f
[j
] = rgba
[1][j
];
3885 r
[2].f
[j
] = rgba
[2][j
];
3886 r
[3].f
[j
] = rgba
[3][j
];
3888 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3889 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3890 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3896 exec_load_buf(struct tgsi_exec_machine
*mach
,
3897 const struct tgsi_full_instruction
*inst
)
3899 union tgsi_exec_channel r
[4];
3903 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3904 struct tgsi_buffer_params params
;
3905 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3907 unit
= fetch_sampler_unit(mach
, inst
, 0);
3909 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3911 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3913 mach
->Buffer
->load(mach
->Buffer
, ¶ms
,
3915 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3916 r
[0].f
[j
] = rgba
[0][j
];
3917 r
[1].f
[j
] = rgba
[1][j
];
3918 r
[2].f
[j
] = rgba
[2][j
];
3919 r
[3].f
[j
] = rgba
[3][j
];
3921 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3922 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3923 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3929 exec_load_mem(struct tgsi_exec_machine
*mach
,
3930 const struct tgsi_full_instruction
*inst
)
3932 union tgsi_exec_channel r
[4];
3934 char *ptr
= mach
->LocalMem
;
3938 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3939 if (r
[0].u
[0] >= mach
->LocalMemSize
)
3945 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3946 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3947 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3948 memcpy(&r
[chan
].u
[j
], ptr
+ (4 * chan
), 4);
3953 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3954 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3955 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3961 exec_load(struct tgsi_exec_machine
*mach
,
3962 const struct tgsi_full_instruction
*inst
)
3964 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
3965 exec_load_img(mach
, inst
);
3966 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
3967 exec_load_buf(mach
, inst
);
3968 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
3969 exec_load_mem(mach
, inst
);
3973 exec_store_img(struct tgsi_exec_machine
*mach
,
3974 const struct tgsi_full_instruction
*inst
)
3976 union tgsi_exec_channel r
[3], sample_r
;
3977 union tgsi_exec_channel value
[4];
3978 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3979 struct tgsi_image_params params
;
3984 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3985 unit
= inst
->Dst
[0].Register
.Index
;
3986 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3987 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3990 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3992 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3993 params
.format
= inst
->Memory
.Format
;
3995 for (i
= 0; i
< dim
; i
++) {
3996 IFETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
3999 for (i
= 0; i
< 4; i
++) {
4000 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4003 IFETCH(&sample_r
, 0, TGSI_CHAN_X
+ sample
);
4005 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4006 rgba
[0][j
] = value
[0].f
[j
];
4007 rgba
[1][j
] = value
[1].f
[j
];
4008 rgba
[2][j
] = value
[2].f
[j
];
4009 rgba
[3][j
] = value
[3].f
[j
];
4012 mach
->Image
->store(mach
->Image
, ¶ms
,
4013 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4018 exec_store_buf(struct tgsi_exec_machine
*mach
,
4019 const struct tgsi_full_instruction
*inst
)
4021 union tgsi_exec_channel r
[3];
4022 union tgsi_exec_channel value
[4];
4023 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4024 struct tgsi_buffer_params params
;
4027 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4029 unit
= inst
->Dst
[0].Register
.Index
;
4031 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4033 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4035 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4036 for (i
= 0; i
< 4; i
++) {
4037 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4040 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4041 rgba
[0][j
] = value
[0].f
[j
];
4042 rgba
[1][j
] = value
[1].f
[j
];
4043 rgba
[2][j
] = value
[2].f
[j
];
4044 rgba
[3][j
] = value
[3].f
[j
];
4047 mach
->Buffer
->store(mach
->Buffer
, ¶ms
,
4053 exec_store_mem(struct tgsi_exec_machine
*mach
,
4054 const struct tgsi_full_instruction
*inst
)
4056 union tgsi_exec_channel r
[3];
4057 union tgsi_exec_channel value
[4];
4059 char *ptr
= mach
->LocalMem
;
4060 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4061 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4063 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4065 for (i
= 0; i
< 4; i
++) {
4066 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4069 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4073 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4074 if (execmask
& (1 << i
)) {
4075 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4076 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4077 memcpy(ptr
+ (chan
* 4), &value
[chan
].u
[0], 4);
4085 exec_store(struct tgsi_exec_machine
*mach
,
4086 const struct tgsi_full_instruction
*inst
)
4088 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
)
4089 exec_store_img(mach
, inst
);
4090 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
)
4091 exec_store_buf(mach
, inst
);
4092 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
)
4093 exec_store_mem(mach
, inst
);
4097 exec_atomop_img(struct tgsi_exec_machine
*mach
,
4098 const struct tgsi_full_instruction
*inst
)
4100 union tgsi_exec_channel r
[4], sample_r
;
4101 union tgsi_exec_channel value
[4], value2
[4];
4102 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4103 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4104 struct tgsi_image_params params
;
4109 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4110 unit
= fetch_sampler_unit(mach
, inst
, 0);
4111 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4112 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4115 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4117 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4118 params
.format
= inst
->Memory
.Format
;
4120 for (i
= 0; i
< dim
; i
++) {
4121 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
4124 for (i
= 0; i
< 4; i
++) {
4125 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4126 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4127 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4130 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
4132 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4133 rgba
[0][j
] = value
[0].f
[j
];
4134 rgba
[1][j
] = value
[1].f
[j
];
4135 rgba
[2][j
] = value
[2].f
[j
];
4136 rgba
[3][j
] = value
[3].f
[j
];
4138 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4139 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4140 rgba2
[0][j
] = value2
[0].f
[j
];
4141 rgba2
[1][j
] = value2
[1].f
[j
];
4142 rgba2
[2][j
] = value2
[2].f
[j
];
4143 rgba2
[3][j
] = value2
[3].f
[j
];
4147 mach
->Image
->op(mach
->Image
, ¶ms
, inst
->Instruction
.Opcode
,
4148 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4151 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4152 r
[0].f
[j
] = rgba
[0][j
];
4153 r
[1].f
[j
] = rgba
[1][j
];
4154 r
[2].f
[j
] = rgba
[2][j
];
4155 r
[3].f
[j
] = rgba
[3][j
];
4157 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4158 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4159 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4165 exec_atomop_buf(struct tgsi_exec_machine
*mach
,
4166 const struct tgsi_full_instruction
*inst
)
4168 union tgsi_exec_channel r
[4];
4169 union tgsi_exec_channel value
[4], value2
[4];
4170 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4171 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4172 struct tgsi_buffer_params params
;
4175 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4177 unit
= fetch_sampler_unit(mach
, inst
, 0);
4179 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4181 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4183 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4185 for (i
= 0; i
< 4; i
++) {
4186 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4187 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4188 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4191 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4192 rgba
[0][j
] = value
[0].f
[j
];
4193 rgba
[1][j
] = value
[1].f
[j
];
4194 rgba
[2][j
] = value
[2].f
[j
];
4195 rgba
[3][j
] = value
[3].f
[j
];
4197 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4198 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4199 rgba2
[0][j
] = value2
[0].f
[j
];
4200 rgba2
[1][j
] = value2
[1].f
[j
];
4201 rgba2
[2][j
] = value2
[2].f
[j
];
4202 rgba2
[3][j
] = value2
[3].f
[j
];
4206 mach
->Buffer
->op(mach
->Buffer
, ¶ms
, inst
->Instruction
.Opcode
,
4210 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4211 r
[0].f
[j
] = rgba
[0][j
];
4212 r
[1].f
[j
] = rgba
[1][j
];
4213 r
[2].f
[j
] = rgba
[2][j
];
4214 r
[3].f
[j
] = rgba
[3][j
];
4216 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4217 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4218 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4224 exec_atomop_mem(struct tgsi_exec_machine
*mach
,
4225 const struct tgsi_full_instruction
*inst
)
4227 union tgsi_exec_channel r
[4];
4228 union tgsi_exec_channel value
[4], value2
[4];
4229 char *ptr
= mach
->LocalMem
;
4233 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4234 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4235 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4237 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4242 for (i
= 0; i
< 4; i
++) {
4243 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4244 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4245 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4248 memcpy(&r
[0].u
[0], ptr
, 4);
4250 switch (inst
->Instruction
.Opcode
) {
4251 case TGSI_OPCODE_ATOMUADD
:
4252 val
+= value
[0].u
[0];
4254 case TGSI_OPCODE_ATOMXOR
:
4255 val
^= value
[0].u
[0];
4257 case TGSI_OPCODE_ATOMOR
:
4258 val
|= value
[0].u
[0];
4260 case TGSI_OPCODE_ATOMAND
:
4261 val
&= value
[0].u
[0];
4263 case TGSI_OPCODE_ATOMUMIN
:
4264 val
= MIN2(val
, value
[0].u
[0]);
4266 case TGSI_OPCODE_ATOMUMAX
:
4267 val
= MAX2(val
, value
[0].u
[0]);
4269 case TGSI_OPCODE_ATOMIMIN
:
4270 val
= MIN2(r
[0].i
[0], value
[0].i
[0]);
4272 case TGSI_OPCODE_ATOMIMAX
:
4273 val
= MAX2(r
[0].i
[0], value
[0].i
[0]);
4275 case TGSI_OPCODE_ATOMXCHG
:
4276 val
= value
[0].i
[0];
4278 case TGSI_OPCODE_ATOMCAS
:
4279 if (val
== value
[0].u
[0])
4280 val
= value2
[0].u
[0];
4285 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
4286 if (execmask
& (1 << i
))
4287 memcpy(ptr
, &val
, 4);
4289 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4290 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4291 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4297 exec_atomop(struct tgsi_exec_machine
*mach
,
4298 const struct tgsi_full_instruction
*inst
)
4300 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4301 exec_atomop_img(mach
, inst
);
4302 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4303 exec_atomop_buf(mach
, inst
);
4304 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4305 exec_atomop_mem(mach
, inst
);
4309 exec_resq_img(struct tgsi_exec_machine
*mach
,
4310 const struct tgsi_full_instruction
*inst
)
4313 union tgsi_exec_channel r
[4];
4316 struct tgsi_image_params params
;
4317 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4319 unit
= fetch_sampler_unit(mach
, inst
, 0);
4321 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4323 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4324 params
.format
= inst
->Memory
.Format
;
4326 mach
->Image
->get_dims(mach
->Image
, ¶ms
, result
);
4328 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4329 for (j
= 0; j
< 4; j
++) {
4330 r
[j
].i
[i
] = result
[j
];
4334 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4335 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4336 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4337 TGSI_EXEC_DATA_INT
);
4343 exec_resq_buf(struct tgsi_exec_machine
*mach
,
4344 const struct tgsi_full_instruction
*inst
)
4347 union tgsi_exec_channel r
[4];
4350 struct tgsi_buffer_params params
;
4351 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4353 unit
= fetch_sampler_unit(mach
, inst
, 0);
4355 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4358 mach
->Buffer
->get_dims(mach
->Buffer
, ¶ms
, &result
);
4360 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4364 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4365 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4366 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4367 TGSI_EXEC_DATA_INT
);
4373 exec_resq(struct tgsi_exec_machine
*mach
,
4374 const struct tgsi_full_instruction
*inst
)
4376 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4377 exec_resq_img(mach
, inst
);
4379 exec_resq_buf(mach
, inst
);
4383 micro_f2u64(union tgsi_double_channel
*dst
,
4384 const union tgsi_exec_channel
*src
)
4386 dst
->u64
[0] = (uint64_t)src
->f
[0];
4387 dst
->u64
[1] = (uint64_t)src
->f
[1];
4388 dst
->u64
[2] = (uint64_t)src
->f
[2];
4389 dst
->u64
[3] = (uint64_t)src
->f
[3];
4393 micro_f2i64(union tgsi_double_channel
*dst
,
4394 const union tgsi_exec_channel
*src
)
4396 dst
->i64
[0] = (int64_t)src
->f
[0];
4397 dst
->i64
[1] = (int64_t)src
->f
[1];
4398 dst
->i64
[2] = (int64_t)src
->f
[2];
4399 dst
->i64
[3] = (int64_t)src
->f
[3];
4403 micro_u2i64(union tgsi_double_channel
*dst
,
4404 const union tgsi_exec_channel
*src
)
4406 dst
->u64
[0] = (uint64_t)src
->u
[0];
4407 dst
->u64
[1] = (uint64_t)src
->u
[1];
4408 dst
->u64
[2] = (uint64_t)src
->u
[2];
4409 dst
->u64
[3] = (uint64_t)src
->u
[3];
4413 micro_i2i64(union tgsi_double_channel
*dst
,
4414 const union tgsi_exec_channel
*src
)
4416 dst
->i64
[0] = (int64_t)src
->i
[0];
4417 dst
->i64
[1] = (int64_t)src
->i
[1];
4418 dst
->i64
[2] = (int64_t)src
->i
[2];
4419 dst
->i64
[3] = (int64_t)src
->i
[3];
4423 micro_d2u64(union tgsi_double_channel
*dst
,
4424 const union tgsi_double_channel
*src
)
4426 dst
->u64
[0] = (uint64_t)src
->d
[0];
4427 dst
->u64
[1] = (uint64_t)src
->d
[1];
4428 dst
->u64
[2] = (uint64_t)src
->d
[2];
4429 dst
->u64
[3] = (uint64_t)src
->d
[3];
4433 micro_d2i64(union tgsi_double_channel
*dst
,
4434 const union tgsi_double_channel
*src
)
4436 dst
->i64
[0] = (int64_t)src
->d
[0];
4437 dst
->i64
[1] = (int64_t)src
->d
[1];
4438 dst
->i64
[2] = (int64_t)src
->d
[2];
4439 dst
->i64
[3] = (int64_t)src
->d
[3];
4443 micro_u642d(union tgsi_double_channel
*dst
,
4444 const union tgsi_double_channel
*src
)
4446 dst
->d
[0] = (double)src
->u64
[0];
4447 dst
->d
[1] = (double)src
->u64
[1];
4448 dst
->d
[2] = (double)src
->u64
[2];
4449 dst
->d
[3] = (double)src
->u64
[3];
4453 micro_i642d(union tgsi_double_channel
*dst
,
4454 const union tgsi_double_channel
*src
)
4456 dst
->d
[0] = (double)src
->i64
[0];
4457 dst
->d
[1] = (double)src
->i64
[1];
4458 dst
->d
[2] = (double)src
->i64
[2];
4459 dst
->d
[3] = (double)src
->i64
[3];
4463 micro_u642f(union tgsi_exec_channel
*dst
,
4464 const union tgsi_double_channel
*src
)
4466 dst
->f
[0] = (float)src
->u64
[0];
4467 dst
->f
[1] = (float)src
->u64
[1];
4468 dst
->f
[2] = (float)src
->u64
[2];
4469 dst
->f
[3] = (float)src
->u64
[3];
4473 micro_i642f(union tgsi_exec_channel
*dst
,
4474 const union tgsi_double_channel
*src
)
4476 dst
->f
[0] = (float)src
->i64
[0];
4477 dst
->f
[1] = (float)src
->i64
[1];
4478 dst
->f
[2] = (float)src
->i64
[2];
4479 dst
->f
[3] = (float)src
->i64
[3];
4483 exec_t_2_64(struct tgsi_exec_machine
*mach
,
4484 const struct tgsi_full_instruction
*inst
,
4486 enum tgsi_exec_datatype src_datatype
)
4488 union tgsi_exec_channel src
;
4489 union tgsi_double_channel dst
;
4491 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
4492 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
4494 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
4496 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
4497 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, src_datatype
);
4499 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
4504 exec_64_2_t(struct tgsi_exec_machine
*mach
,
4505 const struct tgsi_full_instruction
*inst
,
4507 enum tgsi_exec_datatype dst_datatype
)
4509 union tgsi_double_channel src
;
4510 union tgsi_exec_channel dst
;
4511 int wm
= inst
->Dst
[0].Register
.WriteMask
;
4514 for (i
= 0; i
< 2; i
++) {
4517 wm
&= ~(1 << (bit
- 1));
4519 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
4521 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
4523 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, dst_datatype
);
4529 micro_i2f(union tgsi_exec_channel
*dst
,
4530 const union tgsi_exec_channel
*src
)
4532 dst
->f
[0] = (float)src
->i
[0];
4533 dst
->f
[1] = (float)src
->i
[1];
4534 dst
->f
[2] = (float)src
->i
[2];
4535 dst
->f
[3] = (float)src
->i
[3];
4539 micro_not(union tgsi_exec_channel
*dst
,
4540 const union tgsi_exec_channel
*src
)
4542 dst
->u
[0] = ~src
->u
[0];
4543 dst
->u
[1] = ~src
->u
[1];
4544 dst
->u
[2] = ~src
->u
[2];
4545 dst
->u
[3] = ~src
->u
[3];
4549 micro_shl(union tgsi_exec_channel
*dst
,
4550 const union tgsi_exec_channel
*src0
,
4551 const union tgsi_exec_channel
*src1
)
4553 unsigned masked_count
;
4554 masked_count
= src1
->u
[0] & 0x1f;
4555 dst
->u
[0] = src0
->u
[0] << masked_count
;
4556 masked_count
= src1
->u
[1] & 0x1f;
4557 dst
->u
[1] = src0
->u
[1] << masked_count
;
4558 masked_count
= src1
->u
[2] & 0x1f;
4559 dst
->u
[2] = src0
->u
[2] << masked_count
;
4560 masked_count
= src1
->u
[3] & 0x1f;
4561 dst
->u
[3] = src0
->u
[3] << masked_count
;
4565 micro_and(union tgsi_exec_channel
*dst
,
4566 const union tgsi_exec_channel
*src0
,
4567 const union tgsi_exec_channel
*src1
)
4569 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
4570 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
4571 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
4572 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
4576 micro_or(union tgsi_exec_channel
*dst
,
4577 const union tgsi_exec_channel
*src0
,
4578 const union tgsi_exec_channel
*src1
)
4580 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
4581 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
4582 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
4583 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
4587 micro_xor(union tgsi_exec_channel
*dst
,
4588 const union tgsi_exec_channel
*src0
,
4589 const union tgsi_exec_channel
*src1
)
4591 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
4592 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
4593 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
4594 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
4598 micro_mod(union tgsi_exec_channel
*dst
,
4599 const union tgsi_exec_channel
*src0
,
4600 const union tgsi_exec_channel
*src1
)
4602 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] % src1
->i
[0] : ~0;
4603 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] % src1
->i
[1] : ~0;
4604 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] % src1
->i
[2] : ~0;
4605 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] % src1
->i
[3] : ~0;
4609 micro_f2i(union tgsi_exec_channel
*dst
,
4610 const union tgsi_exec_channel
*src
)
4612 dst
->i
[0] = (int)src
->f
[0];
4613 dst
->i
[1] = (int)src
->f
[1];
4614 dst
->i
[2] = (int)src
->f
[2];
4615 dst
->i
[3] = (int)src
->f
[3];
4619 micro_fseq(union tgsi_exec_channel
*dst
,
4620 const union tgsi_exec_channel
*src0
,
4621 const union tgsi_exec_channel
*src1
)
4623 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
4624 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
4625 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
4626 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
4630 micro_fsge(union tgsi_exec_channel
*dst
,
4631 const union tgsi_exec_channel
*src0
,
4632 const union tgsi_exec_channel
*src1
)
4634 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
4635 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
4636 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
4637 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
4641 micro_fslt(union tgsi_exec_channel
*dst
,
4642 const union tgsi_exec_channel
*src0
,
4643 const union tgsi_exec_channel
*src1
)
4645 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
4646 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
4647 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
4648 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
4652 micro_fsne(union tgsi_exec_channel
*dst
,
4653 const union tgsi_exec_channel
*src0
,
4654 const union tgsi_exec_channel
*src1
)
4656 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
4657 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
4658 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
4659 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
4663 micro_idiv(union tgsi_exec_channel
*dst
,
4664 const union tgsi_exec_channel
*src0
,
4665 const union tgsi_exec_channel
*src1
)
4667 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
4668 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
4669 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
4670 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
4674 micro_imax(union tgsi_exec_channel
*dst
,
4675 const union tgsi_exec_channel
*src0
,
4676 const union tgsi_exec_channel
*src1
)
4678 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4679 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4680 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4681 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4685 micro_imin(union tgsi_exec_channel
*dst
,
4686 const union tgsi_exec_channel
*src0
,
4687 const union tgsi_exec_channel
*src1
)
4689 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4690 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4691 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4692 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4696 micro_isge(union tgsi_exec_channel
*dst
,
4697 const union tgsi_exec_channel
*src0
,
4698 const union tgsi_exec_channel
*src1
)
4700 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
4701 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
4702 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
4703 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
4707 micro_ishr(union tgsi_exec_channel
*dst
,
4708 const union tgsi_exec_channel
*src0
,
4709 const union tgsi_exec_channel
*src1
)
4711 unsigned masked_count
;
4712 masked_count
= src1
->i
[0] & 0x1f;
4713 dst
->i
[0] = src0
->i
[0] >> masked_count
;
4714 masked_count
= src1
->i
[1] & 0x1f;
4715 dst
->i
[1] = src0
->i
[1] >> masked_count
;
4716 masked_count
= src1
->i
[2] & 0x1f;
4717 dst
->i
[2] = src0
->i
[2] >> masked_count
;
4718 masked_count
= src1
->i
[3] & 0x1f;
4719 dst
->i
[3] = src0
->i
[3] >> masked_count
;
4723 micro_islt(union tgsi_exec_channel
*dst
,
4724 const union tgsi_exec_channel
*src0
,
4725 const union tgsi_exec_channel
*src1
)
4727 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
4728 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
4729 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
4730 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
4734 micro_f2u(union tgsi_exec_channel
*dst
,
4735 const union tgsi_exec_channel
*src
)
4737 dst
->u
[0] = (uint
)src
->f
[0];
4738 dst
->u
[1] = (uint
)src
->f
[1];
4739 dst
->u
[2] = (uint
)src
->f
[2];
4740 dst
->u
[3] = (uint
)src
->f
[3];
4744 micro_u2f(union tgsi_exec_channel
*dst
,
4745 const union tgsi_exec_channel
*src
)
4747 dst
->f
[0] = (float)src
->u
[0];
4748 dst
->f
[1] = (float)src
->u
[1];
4749 dst
->f
[2] = (float)src
->u
[2];
4750 dst
->f
[3] = (float)src
->u
[3];
4754 micro_uadd(union tgsi_exec_channel
*dst
,
4755 const union tgsi_exec_channel
*src0
,
4756 const union tgsi_exec_channel
*src1
)
4758 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
4759 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
4760 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
4761 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
4765 micro_udiv(union tgsi_exec_channel
*dst
,
4766 const union tgsi_exec_channel
*src0
,
4767 const union tgsi_exec_channel
*src1
)
4769 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
4770 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
4771 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
4772 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
4776 micro_umad(union tgsi_exec_channel
*dst
,
4777 const union tgsi_exec_channel
*src0
,
4778 const union tgsi_exec_channel
*src1
,
4779 const union tgsi_exec_channel
*src2
)
4781 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
4782 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
4783 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
4784 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
4788 micro_umax(union tgsi_exec_channel
*dst
,
4789 const union tgsi_exec_channel
*src0
,
4790 const union tgsi_exec_channel
*src1
)
4792 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4793 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4794 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4795 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4799 micro_umin(union tgsi_exec_channel
*dst
,
4800 const union tgsi_exec_channel
*src0
,
4801 const union tgsi_exec_channel
*src1
)
4803 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4804 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4805 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4806 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4810 micro_umod(union tgsi_exec_channel
*dst
,
4811 const union tgsi_exec_channel
*src0
,
4812 const union tgsi_exec_channel
*src1
)
4814 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
4815 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
4816 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
4817 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
4821 micro_umul(union tgsi_exec_channel
*dst
,
4822 const union tgsi_exec_channel
*src0
,
4823 const union tgsi_exec_channel
*src1
)
4825 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4826 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4827 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4828 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4832 micro_imul_hi(union tgsi_exec_channel
*dst
,
4833 const union tgsi_exec_channel
*src0
,
4834 const union tgsi_exec_channel
*src1
)
4836 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4837 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4838 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4839 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4840 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4845 micro_umul_hi(union tgsi_exec_channel
*dst
,
4846 const union tgsi_exec_channel
*src0
,
4847 const union tgsi_exec_channel
*src1
)
4849 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4850 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4851 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4852 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4853 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4858 micro_useq(union tgsi_exec_channel
*dst
,
4859 const union tgsi_exec_channel
*src0
,
4860 const union tgsi_exec_channel
*src1
)
4862 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4863 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4864 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4865 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4869 micro_usge(union tgsi_exec_channel
*dst
,
4870 const union tgsi_exec_channel
*src0
,
4871 const union tgsi_exec_channel
*src1
)
4873 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4874 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4875 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4876 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4880 micro_ushr(union tgsi_exec_channel
*dst
,
4881 const union tgsi_exec_channel
*src0
,
4882 const union tgsi_exec_channel
*src1
)
4884 unsigned masked_count
;
4885 masked_count
= src1
->u
[0] & 0x1f;
4886 dst
->u
[0] = src0
->u
[0] >> masked_count
;
4887 masked_count
= src1
->u
[1] & 0x1f;
4888 dst
->u
[1] = src0
->u
[1] >> masked_count
;
4889 masked_count
= src1
->u
[2] & 0x1f;
4890 dst
->u
[2] = src0
->u
[2] >> masked_count
;
4891 masked_count
= src1
->u
[3] & 0x1f;
4892 dst
->u
[3] = src0
->u
[3] >> masked_count
;
4896 micro_uslt(union tgsi_exec_channel
*dst
,
4897 const union tgsi_exec_channel
*src0
,
4898 const union tgsi_exec_channel
*src1
)
4900 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
4901 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
4902 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
4903 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
4907 micro_usne(union tgsi_exec_channel
*dst
,
4908 const union tgsi_exec_channel
*src0
,
4909 const union tgsi_exec_channel
*src1
)
4911 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
4912 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
4913 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
4914 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
4918 micro_uarl(union tgsi_exec_channel
*dst
,
4919 const union tgsi_exec_channel
*src
)
4921 dst
->i
[0] = src
->u
[0];
4922 dst
->i
[1] = src
->u
[1];
4923 dst
->i
[2] = src
->u
[2];
4924 dst
->i
[3] = src
->u
[3];
4928 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4931 micro_ibfe(union tgsi_exec_channel
*dst
,
4932 const union tgsi_exec_channel
*src0
,
4933 const union tgsi_exec_channel
*src1
,
4934 const union tgsi_exec_channel
*src2
)
4937 for (i
= 0; i
< 4; i
++) {
4938 int width
= src2
->i
[i
] & 0x1f;
4939 int offset
= src1
->i
[i
] & 0x1f;
4942 else if (width
+ offset
< 32)
4943 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
4945 dst
->i
[i
] = src0
->i
[i
] >> offset
;
4950 * Unsigned bitfield extract
4953 micro_ubfe(union tgsi_exec_channel
*dst
,
4954 const union tgsi_exec_channel
*src0
,
4955 const union tgsi_exec_channel
*src1
,
4956 const union tgsi_exec_channel
*src2
)
4959 for (i
= 0; i
< 4; i
++) {
4960 int width
= src2
->u
[i
] & 0x1f;
4961 int offset
= src1
->u
[i
] & 0x1f;
4964 else if (width
+ offset
< 32)
4965 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
4967 dst
->u
[i
] = src0
->u
[i
] >> offset
;
4972 * Bitfield insert: copy low bits from src1 into a region of src0.
4975 micro_bfi(union tgsi_exec_channel
*dst
,
4976 const union tgsi_exec_channel
*src0
,
4977 const union tgsi_exec_channel
*src1
,
4978 const union tgsi_exec_channel
*src2
,
4979 const union tgsi_exec_channel
*src3
)
4982 for (i
= 0; i
< 4; i
++) {
4983 int width
= src3
->u
[i
] & 0x1f;
4984 int offset
= src2
->u
[i
] & 0x1f;
4985 int bitmask
= ((1 << width
) - 1) << offset
;
4986 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
4991 micro_brev(union tgsi_exec_channel
*dst
,
4992 const union tgsi_exec_channel
*src
)
4994 dst
->u
[0] = util_bitreverse(src
->u
[0]);
4995 dst
->u
[1] = util_bitreverse(src
->u
[1]);
4996 dst
->u
[2] = util_bitreverse(src
->u
[2]);
4997 dst
->u
[3] = util_bitreverse(src
->u
[3]);
5001 micro_popc(union tgsi_exec_channel
*dst
,
5002 const union tgsi_exec_channel
*src
)
5004 dst
->u
[0] = util_bitcount(src
->u
[0]);
5005 dst
->u
[1] = util_bitcount(src
->u
[1]);
5006 dst
->u
[2] = util_bitcount(src
->u
[2]);
5007 dst
->u
[3] = util_bitcount(src
->u
[3]);
5011 micro_lsb(union tgsi_exec_channel
*dst
,
5012 const union tgsi_exec_channel
*src
)
5014 dst
->i
[0] = ffs(src
->u
[0]) - 1;
5015 dst
->i
[1] = ffs(src
->u
[1]) - 1;
5016 dst
->i
[2] = ffs(src
->u
[2]) - 1;
5017 dst
->i
[3] = ffs(src
->u
[3]) - 1;
5021 micro_imsb(union tgsi_exec_channel
*dst
,
5022 const union tgsi_exec_channel
*src
)
5024 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
5025 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
5026 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
5027 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
5031 micro_umsb(union tgsi_exec_channel
*dst
,
5032 const union tgsi_exec_channel
*src
)
5034 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
5035 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
5036 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
5037 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
5041 * Execute a TGSI instruction.
5042 * Returns TRUE if a barrier instruction is hit,
5047 struct tgsi_exec_machine
*mach
,
5048 const struct tgsi_full_instruction
*inst
,
5051 union tgsi_exec_channel r
[10];
5055 switch (inst
->Instruction
.Opcode
) {
5056 case TGSI_OPCODE_ARL
:
5057 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5060 case TGSI_OPCODE_MOV
:
5061 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5064 case TGSI_OPCODE_LIT
:
5065 exec_lit(mach
, inst
);
5068 case TGSI_OPCODE_RCP
:
5069 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5072 case TGSI_OPCODE_RSQ
:
5073 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5076 case TGSI_OPCODE_EXP
:
5077 exec_exp(mach
, inst
);
5080 case TGSI_OPCODE_LOG
:
5081 exec_log(mach
, inst
);
5084 case TGSI_OPCODE_MUL
:
5085 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5088 case TGSI_OPCODE_ADD
:
5089 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5092 case TGSI_OPCODE_DP3
:
5093 exec_dp3(mach
, inst
);
5096 case TGSI_OPCODE_DP4
:
5097 exec_dp4(mach
, inst
);
5100 case TGSI_OPCODE_DST
:
5101 exec_dst(mach
, inst
);
5104 case TGSI_OPCODE_MIN
:
5105 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5108 case TGSI_OPCODE_MAX
:
5109 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5112 case TGSI_OPCODE_SLT
:
5113 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5116 case TGSI_OPCODE_SGE
:
5117 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5120 case TGSI_OPCODE_MAD
:
5121 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5124 case TGSI_OPCODE_LRP
:
5125 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5128 case TGSI_OPCODE_SQRT
:
5129 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5132 case TGSI_OPCODE_FRC
:
5133 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5136 case TGSI_OPCODE_FLR
:
5137 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5140 case TGSI_OPCODE_ROUND
:
5141 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5144 case TGSI_OPCODE_EX2
:
5145 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5148 case TGSI_OPCODE_LG2
:
5149 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5152 case TGSI_OPCODE_POW
:
5153 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5156 case TGSI_OPCODE_XPD
:
5157 exec_xpd(mach
, inst
);
5160 case TGSI_OPCODE_COS
:
5161 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5164 case TGSI_OPCODE_DDX
:
5165 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5168 case TGSI_OPCODE_DDY
:
5169 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5172 case TGSI_OPCODE_KILL
:
5173 exec_kill (mach
, inst
);
5176 case TGSI_OPCODE_KILL_IF
:
5177 exec_kill_if (mach
, inst
);
5180 case TGSI_OPCODE_PK2H
:
5181 exec_pk2h(mach
, inst
);
5184 case TGSI_OPCODE_PK2US
:
5188 case TGSI_OPCODE_PK4B
:
5192 case TGSI_OPCODE_PK4UB
:
5196 case TGSI_OPCODE_SEQ
:
5197 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5200 case TGSI_OPCODE_SGT
:
5201 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5204 case TGSI_OPCODE_SIN
:
5205 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5208 case TGSI_OPCODE_SLE
:
5209 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5212 case TGSI_OPCODE_SNE
:
5213 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5216 case TGSI_OPCODE_TEX
:
5217 /* simple texture lookup */
5218 /* src[0] = texcoord */
5219 /* src[1] = sampler unit */
5220 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
5223 case TGSI_OPCODE_TXB
:
5224 /* Texture lookup with lod bias */
5225 /* src[0] = texcoord (src[0].w = LOD bias) */
5226 /* src[1] = sampler unit */
5227 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
5230 case TGSI_OPCODE_TXD
:
5231 /* Texture lookup with explict partial derivatives */
5232 /* src[0] = texcoord */
5233 /* src[1] = d[strq]/dx */
5234 /* src[2] = d[strq]/dy */
5235 /* src[3] = sampler unit */
5236 exec_txd(mach
, inst
);
5239 case TGSI_OPCODE_TXL
:
5240 /* Texture lookup with explit LOD */
5241 /* src[0] = texcoord (src[0].w = LOD) */
5242 /* src[1] = sampler unit */
5243 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
5246 case TGSI_OPCODE_TXP
:
5247 /* Texture lookup with projection */
5248 /* src[0] = texcoord (src[0].w = projection) */
5249 /* src[1] = sampler unit */
5250 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
5253 case TGSI_OPCODE_TG4
:
5254 /* src[0] = texcoord */
5255 /* src[1] = component */
5256 /* src[2] = sampler unit */
5257 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
5260 case TGSI_OPCODE_LODQ
:
5261 /* src[0] = texcoord */
5262 /* src[1] = sampler unit */
5263 exec_lodq(mach
, inst
);
5266 case TGSI_OPCODE_UP2H
:
5267 exec_up2h(mach
, inst
);
5270 case TGSI_OPCODE_UP2US
:
5274 case TGSI_OPCODE_UP4B
:
5278 case TGSI_OPCODE_UP4UB
:
5282 case TGSI_OPCODE_ARR
:
5283 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5286 case TGSI_OPCODE_CAL
:
5287 /* skip the call if no execution channels are enabled */
5288 if (mach
->ExecMask
) {
5291 /* First, record the depths of the execution stacks.
5292 * This is important for deeply nested/looped return statements.
5293 * We have to unwind the stacks by the correct amount. For a
5294 * real code generator, we could determine the number of entries
5295 * to pop off each stack with simple static analysis and avoid
5296 * implementing this data structure at run time.
5298 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
5299 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
5300 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
5301 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
5302 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
5303 /* note that PC was already incremented above */
5304 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
5306 mach
->CallStackTop
++;
5308 /* Second, push the Cond, Loop, Cont, Func stacks */
5309 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5310 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5311 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5312 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
5313 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5314 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
5316 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5317 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5318 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5319 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
5320 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5321 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
5323 /* Finally, jump to the subroutine. The label is a pointer
5324 * (an instruction number) to the BGNSUB instruction.
5326 *pc
= inst
->Label
.Label
;
5327 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
5328 == TGSI_OPCODE_BGNSUB
);
5332 case TGSI_OPCODE_RET
:
5333 mach
->FuncMask
&= ~mach
->ExecMask
;
5334 UPDATE_EXEC_MASK(mach
);
5336 if (mach
->FuncMask
== 0x0) {
5337 /* really return now (otherwise, keep executing */
5339 if (mach
->CallStackTop
== 0) {
5340 /* returning from main() */
5341 mach
->CondStackTop
= 0;
5342 mach
->LoopStackTop
= 0;
5343 mach
->ContStackTop
= 0;
5344 mach
->LoopLabelStackTop
= 0;
5345 mach
->SwitchStackTop
= 0;
5346 mach
->BreakStackTop
= 0;
5351 assert(mach
->CallStackTop
> 0);
5352 mach
->CallStackTop
--;
5354 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5355 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5357 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5358 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5360 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5361 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5363 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5364 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5366 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5367 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5369 assert(mach
->FuncStackTop
> 0);
5370 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5372 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5374 UPDATE_EXEC_MASK(mach
);
5378 case TGSI_OPCODE_SSG
:
5379 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5382 case TGSI_OPCODE_CMP
:
5383 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5386 case TGSI_OPCODE_SCS
:
5387 exec_scs(mach
, inst
);
5390 case TGSI_OPCODE_DIV
:
5391 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5394 case TGSI_OPCODE_DP2
:
5395 exec_dp2(mach
, inst
);
5398 case TGSI_OPCODE_IF
:
5400 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5401 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5402 FETCH( &r
[0], 0, TGSI_CHAN_X
);
5403 /* update CondMask */
5405 mach
->CondMask
&= ~0x1;
5408 mach
->CondMask
&= ~0x2;
5411 mach
->CondMask
&= ~0x4;
5414 mach
->CondMask
&= ~0x8;
5416 UPDATE_EXEC_MASK(mach
);
5417 /* Todo: If CondMask==0, jump to ELSE */
5420 case TGSI_OPCODE_UIF
:
5422 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5423 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5424 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
5425 /* update CondMask */
5427 mach
->CondMask
&= ~0x1;
5430 mach
->CondMask
&= ~0x2;
5433 mach
->CondMask
&= ~0x4;
5436 mach
->CondMask
&= ~0x8;
5438 UPDATE_EXEC_MASK(mach
);
5439 /* Todo: If CondMask==0, jump to ELSE */
5442 case TGSI_OPCODE_ELSE
:
5443 /* invert CondMask wrt previous mask */
5446 assert(mach
->CondStackTop
> 0);
5447 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
5448 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
5449 UPDATE_EXEC_MASK(mach
);
5450 /* Todo: If CondMask==0, jump to ENDIF */
5454 case TGSI_OPCODE_ENDIF
:
5456 assert(mach
->CondStackTop
> 0);
5457 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
5458 UPDATE_EXEC_MASK(mach
);
5461 case TGSI_OPCODE_END
:
5462 /* make sure we end primitives which haven't
5463 * been explicitly emitted */
5464 conditional_emit_primitive(mach
);
5465 /* halt execution */
5469 case TGSI_OPCODE_CEIL
:
5470 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5473 case TGSI_OPCODE_I2F
:
5474 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
5477 case TGSI_OPCODE_NOT
:
5478 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5481 case TGSI_OPCODE_TRUNC
:
5482 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5485 case TGSI_OPCODE_SHL
:
5486 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5489 case TGSI_OPCODE_AND
:
5490 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5493 case TGSI_OPCODE_OR
:
5494 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5497 case TGSI_OPCODE_MOD
:
5498 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5501 case TGSI_OPCODE_XOR
:
5502 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5505 case TGSI_OPCODE_TXF
:
5506 exec_txf(mach
, inst
);
5509 case TGSI_OPCODE_TXQ
:
5510 exec_txq(mach
, inst
);
5513 case TGSI_OPCODE_EMIT
:
5517 case TGSI_OPCODE_ENDPRIM
:
5518 emit_primitive(mach
);
5521 case TGSI_OPCODE_BGNLOOP
:
5522 /* push LoopMask and ContMasks */
5523 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5524 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5525 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5526 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5528 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5529 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5530 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
5531 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5532 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
5535 case TGSI_OPCODE_ENDLOOP
:
5536 /* Restore ContMask, but don't pop */
5537 assert(mach
->ContStackTop
> 0);
5538 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
5539 UPDATE_EXEC_MASK(mach
);
5540 if (mach
->ExecMask
) {
5541 /* repeat loop: jump to instruction just past BGNLOOP */
5542 assert(mach
->LoopLabelStackTop
> 0);
5543 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
5546 /* exit loop: pop LoopMask */
5547 assert(mach
->LoopStackTop
> 0);
5548 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
5550 assert(mach
->ContStackTop
> 0);
5551 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
5552 assert(mach
->LoopLabelStackTop
> 0);
5553 --mach
->LoopLabelStackTop
;
5555 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
5557 UPDATE_EXEC_MASK(mach
);
5560 case TGSI_OPCODE_BRK
:
5564 case TGSI_OPCODE_CONT
:
5565 /* turn off cont channels for each enabled exec channel */
5566 mach
->ContMask
&= ~mach
->ExecMask
;
5567 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5568 UPDATE_EXEC_MASK(mach
);
5571 case TGSI_OPCODE_BGNSUB
:
5575 case TGSI_OPCODE_ENDSUB
:
5577 * XXX: This really should be a no-op. We should never reach this opcode.
5580 assert(mach
->CallStackTop
> 0);
5581 mach
->CallStackTop
--;
5583 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5584 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5586 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5587 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5589 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5590 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5592 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5593 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5595 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5596 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5598 assert(mach
->FuncStackTop
> 0);
5599 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5601 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5603 UPDATE_EXEC_MASK(mach
);
5606 case TGSI_OPCODE_NOP
:
5609 case TGSI_OPCODE_BREAKC
:
5610 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
5611 /* update CondMask */
5612 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
5613 mach
->LoopMask
&= ~0x1;
5615 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
5616 mach
->LoopMask
&= ~0x2;
5618 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
5619 mach
->LoopMask
&= ~0x4;
5621 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
5622 mach
->LoopMask
&= ~0x8;
5624 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5625 UPDATE_EXEC_MASK(mach
);
5628 case TGSI_OPCODE_F2I
:
5629 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5632 case TGSI_OPCODE_FSEQ
:
5633 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5636 case TGSI_OPCODE_FSGE
:
5637 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5640 case TGSI_OPCODE_FSLT
:
5641 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5644 case TGSI_OPCODE_FSNE
:
5645 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5648 case TGSI_OPCODE_IDIV
:
5649 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5652 case TGSI_OPCODE_IMAX
:
5653 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5656 case TGSI_OPCODE_IMIN
:
5657 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5660 case TGSI_OPCODE_INEG
:
5661 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5664 case TGSI_OPCODE_ISGE
:
5665 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5668 case TGSI_OPCODE_ISHR
:
5669 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5672 case TGSI_OPCODE_ISLT
:
5673 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5676 case TGSI_OPCODE_F2U
:
5677 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5680 case TGSI_OPCODE_U2F
:
5681 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
5684 case TGSI_OPCODE_UADD
:
5685 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5688 case TGSI_OPCODE_UDIV
:
5689 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5692 case TGSI_OPCODE_UMAD
:
5693 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5696 case TGSI_OPCODE_UMAX
:
5697 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5700 case TGSI_OPCODE_UMIN
:
5701 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5704 case TGSI_OPCODE_UMOD
:
5705 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5708 case TGSI_OPCODE_UMUL
:
5709 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5712 case TGSI_OPCODE_IMUL_HI
:
5713 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5716 case TGSI_OPCODE_UMUL_HI
:
5717 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5720 case TGSI_OPCODE_USEQ
:
5721 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5724 case TGSI_OPCODE_USGE
:
5725 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5728 case TGSI_OPCODE_USHR
:
5729 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5732 case TGSI_OPCODE_USLT
:
5733 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5736 case TGSI_OPCODE_USNE
:
5737 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5740 case TGSI_OPCODE_SWITCH
:
5741 exec_switch(mach
, inst
);
5744 case TGSI_OPCODE_CASE
:
5745 exec_case(mach
, inst
);
5748 case TGSI_OPCODE_DEFAULT
:
5752 case TGSI_OPCODE_ENDSWITCH
:
5753 exec_endswitch(mach
);
5756 case TGSI_OPCODE_SAMPLE_I
:
5757 exec_txf(mach
, inst
);
5760 case TGSI_OPCODE_SAMPLE_I_MS
:
5761 exec_txf(mach
, inst
);
5764 case TGSI_OPCODE_SAMPLE
:
5765 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
5768 case TGSI_OPCODE_SAMPLE_B
:
5769 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
5772 case TGSI_OPCODE_SAMPLE_C
:
5773 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
5776 case TGSI_OPCODE_SAMPLE_C_LZ
:
5777 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
5780 case TGSI_OPCODE_SAMPLE_D
:
5781 exec_sample_d(mach
, inst
);
5784 case TGSI_OPCODE_SAMPLE_L
:
5785 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
5788 case TGSI_OPCODE_GATHER4
:
5792 case TGSI_OPCODE_SVIEWINFO
:
5793 exec_txq(mach
, inst
);
5796 case TGSI_OPCODE_SAMPLE_POS
:
5800 case TGSI_OPCODE_SAMPLE_INFO
:
5804 case TGSI_OPCODE_UARL
:
5805 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5808 case TGSI_OPCODE_UCMP
:
5809 exec_ucmp(mach
, inst
);
5812 case TGSI_OPCODE_IABS
:
5813 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5816 case TGSI_OPCODE_ISSG
:
5817 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5820 case TGSI_OPCODE_TEX2
:
5821 /* simple texture lookup */
5822 /* src[0] = texcoord */
5823 /* src[1] = compare */
5824 /* src[2] = sampler unit */
5825 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
5827 case TGSI_OPCODE_TXB2
:
5828 /* simple texture lookup */
5829 /* src[0] = texcoord */
5831 /* src[2] = sampler unit */
5832 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
5834 case TGSI_OPCODE_TXL2
:
5835 /* simple texture lookup */
5836 /* src[0] = texcoord */
5838 /* src[2] = sampler unit */
5839 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
5842 case TGSI_OPCODE_IBFE
:
5843 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5845 case TGSI_OPCODE_UBFE
:
5846 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5848 case TGSI_OPCODE_BFI
:
5849 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5851 case TGSI_OPCODE_BREV
:
5852 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5854 case TGSI_OPCODE_POPC
:
5855 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5857 case TGSI_OPCODE_LSB
:
5858 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5860 case TGSI_OPCODE_IMSB
:
5861 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5863 case TGSI_OPCODE_UMSB
:
5864 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5867 case TGSI_OPCODE_F2D
:
5868 exec_t_2_64(mach
, inst
, micro_f2d
, TGSI_EXEC_DATA_FLOAT
);
5871 case TGSI_OPCODE_D2F
:
5872 exec_64_2_t(mach
, inst
, micro_d2f
, TGSI_EXEC_DATA_FLOAT
);
5875 case TGSI_OPCODE_DABS
:
5876 exec_double_unary(mach
, inst
, micro_dabs
);
5879 case TGSI_OPCODE_DNEG
:
5880 exec_double_unary(mach
, inst
, micro_dneg
);
5883 case TGSI_OPCODE_DADD
:
5884 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
5887 case TGSI_OPCODE_DDIV
:
5888 exec_double_binary(mach
, inst
, micro_ddiv
, TGSI_EXEC_DATA_DOUBLE
);
5891 case TGSI_OPCODE_DMUL
:
5892 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
5895 case TGSI_OPCODE_DMAX
:
5896 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
5899 case TGSI_OPCODE_DMIN
:
5900 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
5903 case TGSI_OPCODE_DSLT
:
5904 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
5907 case TGSI_OPCODE_DSGE
:
5908 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
5911 case TGSI_OPCODE_DSEQ
:
5912 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
5915 case TGSI_OPCODE_DSNE
:
5916 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
5919 case TGSI_OPCODE_DRCP
:
5920 exec_double_unary(mach
, inst
, micro_drcp
);
5923 case TGSI_OPCODE_DSQRT
:
5924 exec_double_unary(mach
, inst
, micro_dsqrt
);
5927 case TGSI_OPCODE_DRSQ
:
5928 exec_double_unary(mach
, inst
, micro_drsq
);
5931 case TGSI_OPCODE_DMAD
:
5932 exec_double_trinary(mach
, inst
, micro_dmad
);
5935 case TGSI_OPCODE_DFRAC
:
5936 exec_double_unary(mach
, inst
, micro_dfrac
);
5939 case TGSI_OPCODE_DLDEXP
:
5940 exec_dldexp(mach
, inst
);
5943 case TGSI_OPCODE_DFRACEXP
:
5944 exec_dfracexp(mach
, inst
);
5947 case TGSI_OPCODE_I2D
:
5948 exec_t_2_64(mach
, inst
, micro_i2d
, TGSI_EXEC_DATA_INT
);
5951 case TGSI_OPCODE_D2I
:
5952 exec_64_2_t(mach
, inst
, micro_d2i
, TGSI_EXEC_DATA_INT
);
5955 case TGSI_OPCODE_U2D
:
5956 exec_t_2_64(mach
, inst
, micro_u2d
, TGSI_EXEC_DATA_UINT
);
5959 case TGSI_OPCODE_D2U
:
5960 exec_64_2_t(mach
, inst
, micro_d2u
, TGSI_EXEC_DATA_INT
);
5963 case TGSI_OPCODE_LOAD
:
5964 exec_load(mach
, inst
);
5967 case TGSI_OPCODE_STORE
:
5968 exec_store(mach
, inst
);
5971 case TGSI_OPCODE_ATOMUADD
:
5972 case TGSI_OPCODE_ATOMXCHG
:
5973 case TGSI_OPCODE_ATOMCAS
:
5974 case TGSI_OPCODE_ATOMAND
:
5975 case TGSI_OPCODE_ATOMOR
:
5976 case TGSI_OPCODE_ATOMXOR
:
5977 case TGSI_OPCODE_ATOMUMIN
:
5978 case TGSI_OPCODE_ATOMUMAX
:
5979 case TGSI_OPCODE_ATOMIMIN
:
5980 case TGSI_OPCODE_ATOMIMAX
:
5981 exec_atomop(mach
, inst
);
5984 case TGSI_OPCODE_RESQ
:
5985 exec_resq(mach
, inst
);
5987 case TGSI_OPCODE_BARRIER
:
5988 case TGSI_OPCODE_MEMBAR
:
5992 case TGSI_OPCODE_I64ABS
:
5993 exec_double_unary(mach
, inst
, micro_i64abs
);
5996 case TGSI_OPCODE_I64SSG
:
5997 exec_double_unary(mach
, inst
, micro_i64sgn
);
6000 case TGSI_OPCODE_I64NEG
:
6001 exec_double_unary(mach
, inst
, micro_i64neg
);
6004 case TGSI_OPCODE_U64SEQ
:
6005 exec_double_binary(mach
, inst
, micro_u64seq
, TGSI_EXEC_DATA_UINT
);
6008 case TGSI_OPCODE_U64SNE
:
6009 exec_double_binary(mach
, inst
, micro_u64sne
, TGSI_EXEC_DATA_UINT
);
6012 case TGSI_OPCODE_I64SLT
:
6013 exec_double_binary(mach
, inst
, micro_i64slt
, TGSI_EXEC_DATA_UINT
);
6015 case TGSI_OPCODE_U64SLT
:
6016 exec_double_binary(mach
, inst
, micro_u64slt
, TGSI_EXEC_DATA_UINT
);
6019 case TGSI_OPCODE_I64SGE
:
6020 exec_double_binary(mach
, inst
, micro_i64sge
, TGSI_EXEC_DATA_UINT
);
6022 case TGSI_OPCODE_U64SGE
:
6023 exec_double_binary(mach
, inst
, micro_u64sge
, TGSI_EXEC_DATA_UINT
);
6026 case TGSI_OPCODE_I64MIN
:
6027 exec_double_binary(mach
, inst
, micro_i64min
, TGSI_EXEC_DATA_INT64
);
6029 case TGSI_OPCODE_U64MIN
:
6030 exec_double_binary(mach
, inst
, micro_u64min
, TGSI_EXEC_DATA_UINT64
);
6032 case TGSI_OPCODE_I64MAX
:
6033 exec_double_binary(mach
, inst
, micro_i64max
, TGSI_EXEC_DATA_INT64
);
6035 case TGSI_OPCODE_U64MAX
:
6036 exec_double_binary(mach
, inst
, micro_u64max
, TGSI_EXEC_DATA_UINT64
);
6038 case TGSI_OPCODE_U64ADD
:
6039 exec_double_binary(mach
, inst
, micro_u64add
, TGSI_EXEC_DATA_UINT64
);
6041 case TGSI_OPCODE_U64MUL
:
6042 exec_double_binary(mach
, inst
, micro_u64mul
, TGSI_EXEC_DATA_UINT64
);
6044 case TGSI_OPCODE_U64SHL
:
6045 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shl
);
6047 case TGSI_OPCODE_I64SHR
:
6048 exec_arg0_64_arg1_32(mach
, inst
, micro_i64shr
);
6050 case TGSI_OPCODE_U64SHR
:
6051 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shr
);
6053 case TGSI_OPCODE_U64DIV
:
6054 exec_double_binary(mach
, inst
, micro_u64div
, TGSI_EXEC_DATA_UINT64
);
6056 case TGSI_OPCODE_I64DIV
:
6057 exec_double_binary(mach
, inst
, micro_i64div
, TGSI_EXEC_DATA_INT64
);
6059 case TGSI_OPCODE_U64MOD
:
6060 exec_double_binary(mach
, inst
, micro_u64mod
, TGSI_EXEC_DATA_UINT64
);
6062 case TGSI_OPCODE_I64MOD
:
6063 exec_double_binary(mach
, inst
, micro_i64mod
, TGSI_EXEC_DATA_INT64
);
6066 case TGSI_OPCODE_F2U64
:
6067 exec_t_2_64(mach
, inst
, micro_f2u64
, TGSI_EXEC_DATA_FLOAT
);
6070 case TGSI_OPCODE_F2I64
:
6071 exec_t_2_64(mach
, inst
, micro_f2i64
, TGSI_EXEC_DATA_FLOAT
);
6074 case TGSI_OPCODE_U2I64
:
6075 exec_t_2_64(mach
, inst
, micro_u2i64
, TGSI_EXEC_DATA_INT
);
6077 case TGSI_OPCODE_I2I64
:
6078 exec_t_2_64(mach
, inst
, micro_i2i64
, TGSI_EXEC_DATA_INT
);
6081 case TGSI_OPCODE_D2U64
:
6082 exec_double_unary(mach
, inst
, micro_d2u64
);
6085 case TGSI_OPCODE_D2I64
:
6086 exec_double_unary(mach
, inst
, micro_d2i64
);
6089 case TGSI_OPCODE_U642F
:
6090 exec_64_2_t(mach
, inst
, micro_u642f
, TGSI_EXEC_DATA_FLOAT
);
6092 case TGSI_OPCODE_I642F
:
6093 exec_64_2_t(mach
, inst
, micro_i642f
, TGSI_EXEC_DATA_FLOAT
);
6096 case TGSI_OPCODE_U642D
:
6097 exec_double_unary(mach
, inst
, micro_u642d
);
6099 case TGSI_OPCODE_I642D
:
6100 exec_double_unary(mach
, inst
, micro_i642d
);
6110 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine
*mach
)
6112 uint default_mask
= 0xf;
6114 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
6115 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
6117 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
6118 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
6119 mach
->Primitives
[0] = 0;
6120 /* GS runs on a single primitive for now */
6124 if (mach
->NonHelperMask
== 0)
6125 mach
->NonHelperMask
= default_mask
;
6126 mach
->CondMask
= default_mask
;
6127 mach
->LoopMask
= default_mask
;
6128 mach
->ContMask
= default_mask
;
6129 mach
->FuncMask
= default_mask
;
6130 mach
->ExecMask
= default_mask
;
6132 mach
->Switch
.mask
= default_mask
;
6134 assert(mach
->CondStackTop
== 0);
6135 assert(mach
->LoopStackTop
== 0);
6136 assert(mach
->ContStackTop
== 0);
6137 assert(mach
->SwitchStackTop
== 0);
6138 assert(mach
->BreakStackTop
== 0);
6139 assert(mach
->CallStackTop
== 0);
6143 * Run TGSI interpreter.
6144 * \return bitmask of "alive" quad components
6147 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
, int start_pc
)
6151 mach
->pc
= start_pc
;
6154 tgsi_exec_machine_setup_masks(mach
);
6156 /* execute declarations (interpolants) */
6157 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
6158 exec_declaration( mach
, mach
->Declarations
+i
);
6164 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
6165 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
6169 memset(mach
->Temps
, 0, sizeof(temps
));
6171 memset(mach
->Outputs
, 0, sizeof(outputs
));
6172 memset(temps
, 0, sizeof(temps
));
6173 memset(outputs
, 0, sizeof(outputs
));
6177 /* execute instructions, until pc is set to -1 */
6178 while (mach
->pc
!= -1) {
6179 boolean barrier_hit
;
6183 tgsi_dump_instruction(&mach
->Instructions
[mach
->pc
], inst
++);
6186 assert(mach
->pc
< (int) mach
->NumInstructions
);
6187 barrier_hit
= exec_instruction(mach
, mach
->Instructions
+ mach
->pc
, &mach
->pc
);
6189 /* for compute shaders if we hit a barrier return now for later rescheduling */
6190 if (barrier_hit
&& mach
->ShaderType
== PIPE_SHADER_COMPUTE
)
6194 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
6195 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
6198 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
6199 debug_printf("TEMP[%2u] = ", i
);
6200 for (j
= 0; j
< 4; j
++) {
6204 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6205 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
6206 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
6207 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
6208 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
6212 if (mach
->Outputs
) {
6213 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
6214 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
6217 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
6218 debug_printf("OUT[%2u] = ", i
);
6219 for (j
= 0; j
< 4; j
++) {
6223 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6224 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
6225 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
6226 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
6227 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
6237 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
6238 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
6240 * Scale back depth component.
6242 for (i
= 0; i
< 4; i
++)
6243 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
6247 /* Strictly speaking, these assertions aren't really needed but they
6248 * can potentially catch some bugs in the control flow code.
6250 assert(mach
->CondStackTop
== 0);
6251 assert(mach
->LoopStackTop
== 0);
6252 assert(mach
->ContStackTop
== 0);
6253 assert(mach
->SwitchStackTop
== 0);
6254 assert(mach
->BreakStackTop
== 0);
6255 assert(mach
->CallStackTop
== 0);
6257 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];