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softpipe: fix texture sampling from 1D texture array
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 1
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_clamp(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src0,
115 const union tgsi_exec_channel *src1,
116 const union tgsi_exec_channel *src2)
117 {
118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
122 }
123
124 static void
125 micro_cmp(union tgsi_exec_channel *dst,
126 const union tgsi_exec_channel *src0,
127 const union tgsi_exec_channel *src1,
128 const union tgsi_exec_channel *src2)
129 {
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
134 }
135
136 static void
137 micro_cnd(union tgsi_exec_channel *dst,
138 const union tgsi_exec_channel *src0,
139 const union tgsi_exec_channel *src1,
140 const union tgsi_exec_channel *src2)
141 {
142 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
143 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
144 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
145 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
146 }
147
148 static void
149 micro_cos(union tgsi_exec_channel *dst,
150 const union tgsi_exec_channel *src)
151 {
152 dst->f[0] = cosf(src->f[0]);
153 dst->f[1] = cosf(src->f[1]);
154 dst->f[2] = cosf(src->f[2]);
155 dst->f[3] = cosf(src->f[3]);
156 }
157
158 static void
159 micro_ddx(union tgsi_exec_channel *dst,
160 const union tgsi_exec_channel *src)
161 {
162 dst->f[0] =
163 dst->f[1] =
164 dst->f[2] =
165 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
166 }
167
168 static void
169 micro_ddy(union tgsi_exec_channel *dst,
170 const union tgsi_exec_channel *src)
171 {
172 dst->f[0] =
173 dst->f[1] =
174 dst->f[2] =
175 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
176 }
177
178 static void
179 micro_exp2(union tgsi_exec_channel *dst,
180 const union tgsi_exec_channel *src)
181 {
182 #if FAST_MATH
183 dst->f[0] = util_fast_exp2(src->f[0]);
184 dst->f[1] = util_fast_exp2(src->f[1]);
185 dst->f[2] = util_fast_exp2(src->f[2]);
186 dst->f[3] = util_fast_exp2(src->f[3]);
187 #else
188 #if DEBUG
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
190 uint i;
191 union tgsi_exec_channel clamped;
192
193 for (i = 0; i < 4; i++) {
194 if (src->f[i] > 127.99999f) {
195 clamped.f[i] = 127.99999f;
196 } else if (src->f[i] < -126.99999f) {
197 clamped.f[i] = -126.99999f;
198 } else {
199 clamped.f[i] = src->f[i];
200 }
201 }
202 src = &clamped;
203 #endif /* DEBUG */
204
205 dst->f[0] = powf(2.0f, src->f[0]);
206 dst->f[1] = powf(2.0f, src->f[1]);
207 dst->f[2] = powf(2.0f, src->f[2]);
208 dst->f[3] = powf(2.0f, src->f[3]);
209 #endif /* FAST_MATH */
210 }
211
212 static void
213 micro_flr(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
215 {
216 dst->f[0] = floorf(src->f[0]);
217 dst->f[1] = floorf(src->f[1]);
218 dst->f[2] = floorf(src->f[2]);
219 dst->f[3] = floorf(src->f[3]);
220 }
221
222 static void
223 micro_frc(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
225 {
226 dst->f[0] = src->f[0] - floorf(src->f[0]);
227 dst->f[1] = src->f[1] - floorf(src->f[1]);
228 dst->f[2] = src->f[2] - floorf(src->f[2]);
229 dst->f[3] = src->f[3] - floorf(src->f[3]);
230 }
231
232 static void
233 micro_iabs(union tgsi_exec_channel *dst,
234 const union tgsi_exec_channel *src)
235 {
236 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
237 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
238 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
239 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
240 }
241
242 static void
243 micro_ineg(union tgsi_exec_channel *dst,
244 const union tgsi_exec_channel *src)
245 {
246 dst->i[0] = -src->i[0];
247 dst->i[1] = -src->i[1];
248 dst->i[2] = -src->i[2];
249 dst->i[3] = -src->i[3];
250 }
251
252 static void
253 micro_lg2(union tgsi_exec_channel *dst,
254 const union tgsi_exec_channel *src)
255 {
256 #if FAST_MATH
257 dst->f[0] = util_fast_log2(src->f[0]);
258 dst->f[1] = util_fast_log2(src->f[1]);
259 dst->f[2] = util_fast_log2(src->f[2]);
260 dst->f[3] = util_fast_log2(src->f[3]);
261 #else
262 dst->f[0] = logf(src->f[0]) * 1.442695f;
263 dst->f[1] = logf(src->f[1]) * 1.442695f;
264 dst->f[2] = logf(src->f[2]) * 1.442695f;
265 dst->f[3] = logf(src->f[3]) * 1.442695f;
266 #endif
267 }
268
269 static void
270 micro_lrp(union tgsi_exec_channel *dst,
271 const union tgsi_exec_channel *src0,
272 const union tgsi_exec_channel *src1,
273 const union tgsi_exec_channel *src2)
274 {
275 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
276 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
277 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
278 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
279 }
280
281 static void
282 micro_mad(union tgsi_exec_channel *dst,
283 const union tgsi_exec_channel *src0,
284 const union tgsi_exec_channel *src1,
285 const union tgsi_exec_channel *src2)
286 {
287 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
288 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
289 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
290 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
291 }
292
293 static void
294 micro_mov(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 dst->u[0] = src->u[0];
298 dst->u[1] = src->u[1];
299 dst->u[2] = src->u[2];
300 dst->u[3] = src->u[3];
301 }
302
303 static void
304 micro_rcp(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
306 {
307 #if 0 /* for debugging */
308 assert(src->f[0] != 0.0f);
309 assert(src->f[1] != 0.0f);
310 assert(src->f[2] != 0.0f);
311 assert(src->f[3] != 0.0f);
312 #endif
313 dst->f[0] = 1.0f / src->f[0];
314 dst->f[1] = 1.0f / src->f[1];
315 dst->f[2] = 1.0f / src->f[2];
316 dst->f[3] = 1.0f / src->f[3];
317 }
318
319 static void
320 micro_rnd(union tgsi_exec_channel *dst,
321 const union tgsi_exec_channel *src)
322 {
323 dst->f[0] = floorf(src->f[0] + 0.5f);
324 dst->f[1] = floorf(src->f[1] + 0.5f);
325 dst->f[2] = floorf(src->f[2] + 0.5f);
326 dst->f[3] = floorf(src->f[3] + 0.5f);
327 }
328
329 static void
330 micro_rsq(union tgsi_exec_channel *dst,
331 const union tgsi_exec_channel *src)
332 {
333 #if 0 /* for debugging */
334 assert(src->f[0] != 0.0f);
335 assert(src->f[1] != 0.0f);
336 assert(src->f[2] != 0.0f);
337 assert(src->f[3] != 0.0f);
338 #endif
339 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
340 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
341 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
342 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
343 }
344
345 static void
346 micro_seq(union tgsi_exec_channel *dst,
347 const union tgsi_exec_channel *src0,
348 const union tgsi_exec_channel *src1)
349 {
350 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
351 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
352 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
353 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
354 }
355
356 static void
357 micro_sge(union tgsi_exec_channel *dst,
358 const union tgsi_exec_channel *src0,
359 const union tgsi_exec_channel *src1)
360 {
361 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
362 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
363 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
364 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
365 }
366
367 static void
368 micro_sgn(union tgsi_exec_channel *dst,
369 const union tgsi_exec_channel *src)
370 {
371 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
372 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
373 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
374 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
375 }
376
377 static void
378 micro_sgt(union tgsi_exec_channel *dst,
379 const union tgsi_exec_channel *src0,
380 const union tgsi_exec_channel *src1)
381 {
382 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
383 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
384 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
385 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
386 }
387
388 static void
389 micro_sin(union tgsi_exec_channel *dst,
390 const union tgsi_exec_channel *src)
391 {
392 dst->f[0] = sinf(src->f[0]);
393 dst->f[1] = sinf(src->f[1]);
394 dst->f[2] = sinf(src->f[2]);
395 dst->f[3] = sinf(src->f[3]);
396 }
397
398 static void
399 micro_sle(union tgsi_exec_channel *dst,
400 const union tgsi_exec_channel *src0,
401 const union tgsi_exec_channel *src1)
402 {
403 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
404 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
405 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
406 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
407 }
408
409 static void
410 micro_slt(union tgsi_exec_channel *dst,
411 const union tgsi_exec_channel *src0,
412 const union tgsi_exec_channel *src1)
413 {
414 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
415 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
416 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
417 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
418 }
419
420 static void
421 micro_sne(union tgsi_exec_channel *dst,
422 const union tgsi_exec_channel *src0,
423 const union tgsi_exec_channel *src1)
424 {
425 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
426 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
427 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
428 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
429 }
430
431 static void
432 micro_sfl(union tgsi_exec_channel *dst)
433 {
434 dst->f[0] = 0.0f;
435 dst->f[1] = 0.0f;
436 dst->f[2] = 0.0f;
437 dst->f[3] = 0.0f;
438 }
439
440 static void
441 micro_str(union tgsi_exec_channel *dst)
442 {
443 dst->f[0] = 1.0f;
444 dst->f[1] = 1.0f;
445 dst->f[2] = 1.0f;
446 dst->f[3] = 1.0f;
447 }
448
449 static void
450 micro_trunc(union tgsi_exec_channel *dst,
451 const union tgsi_exec_channel *src)
452 {
453 dst->f[0] = (float)(int)src->f[0];
454 dst->f[1] = (float)(int)src->f[1];
455 dst->f[2] = (float)(int)src->f[2];
456 dst->f[3] = (float)(int)src->f[3];
457 }
458
459
460 #define CHAN_X 0
461 #define CHAN_Y 1
462 #define CHAN_Z 2
463 #define CHAN_W 3
464
465 enum tgsi_exec_datatype {
466 TGSI_EXEC_DATA_FLOAT,
467 TGSI_EXEC_DATA_INT,
468 TGSI_EXEC_DATA_UINT
469 };
470
471 /*
472 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
473 */
474 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
475 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
476 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
477 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
478 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
479 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
480
481
482 /** The execution mask depends on the conditional mask and the loop mask */
483 #define UPDATE_EXEC_MASK(MACH) \
484 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
485
486
487 static const union tgsi_exec_channel ZeroVec =
488 { { 0.0, 0.0, 0.0, 0.0 } };
489
490 static const union tgsi_exec_channel OneVec = {
491 {1.0f, 1.0f, 1.0f, 1.0f}
492 };
493
494 static const union tgsi_exec_channel P128Vec = {
495 {128.0f, 128.0f, 128.0f, 128.0f}
496 };
497
498 static const union tgsi_exec_channel M128Vec = {
499 {-128.0f, -128.0f, -128.0f, -128.0f}
500 };
501
502
503 /**
504 * Assert that none of the float values in 'chan' are infinite or NaN.
505 * NaN and Inf may occur normally during program execution and should
506 * not lead to crashes, etc. But when debugging, it's helpful to catch
507 * them.
508 */
509 static INLINE void
510 check_inf_or_nan(const union tgsi_exec_channel *chan)
511 {
512 assert(!util_is_inf_or_nan((chan)->f[0]));
513 assert(!util_is_inf_or_nan((chan)->f[1]));
514 assert(!util_is_inf_or_nan((chan)->f[2]));
515 assert(!util_is_inf_or_nan((chan)->f[3]));
516 }
517
518
519 #ifdef DEBUG
520 static void
521 print_chan(const char *msg, const union tgsi_exec_channel *chan)
522 {
523 debug_printf("%s = {%f, %f, %f, %f}\n",
524 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
525 }
526 #endif
527
528
529 #ifdef DEBUG
530 static void
531 print_temp(const struct tgsi_exec_machine *mach, uint index)
532 {
533 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
534 int i;
535 debug_printf("Temp[%u] =\n", index);
536 for (i = 0; i < 4; i++) {
537 debug_printf(" %c: { %f, %f, %f, %f }\n",
538 "XYZW"[i],
539 tmp->xyzw[i].f[0],
540 tmp->xyzw[i].f[1],
541 tmp->xyzw[i].f[2],
542 tmp->xyzw[i].f[3]);
543 }
544 }
545 #endif
546
547
548 void
549 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
550 unsigned num_bufs,
551 const void **bufs,
552 const unsigned *buf_sizes)
553 {
554 unsigned i;
555
556 for (i = 0; i < num_bufs; i++) {
557 mach->Consts[i] = bufs[i];
558 mach->ConstsSize[i] = buf_sizes[i];
559 }
560 }
561
562
563 /**
564 * Check if there's a potential src/dst register data dependency when
565 * using SOA execution.
566 * Example:
567 * MOV T, T.yxwz;
568 * This would expand into:
569 * MOV t0, t1;
570 * MOV t1, t0;
571 * MOV t2, t3;
572 * MOV t3, t2;
573 * The second instruction will have the wrong value for t0 if executed as-is.
574 */
575 boolean
576 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
577 {
578 uint i, chan;
579
580 uint writemask = inst->Dst[0].Register.WriteMask;
581 if (writemask == TGSI_WRITEMASK_X ||
582 writemask == TGSI_WRITEMASK_Y ||
583 writemask == TGSI_WRITEMASK_Z ||
584 writemask == TGSI_WRITEMASK_W ||
585 writemask == TGSI_WRITEMASK_NONE) {
586 /* no chance of data dependency */
587 return FALSE;
588 }
589
590 /* loop over src regs */
591 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
592 if ((inst->Src[i].Register.File ==
593 inst->Dst[0].Register.File) &&
594 ((inst->Src[i].Register.Index ==
595 inst->Dst[0].Register.Index) ||
596 inst->Src[i].Register.Indirect ||
597 inst->Dst[0].Register.Indirect)) {
598 /* loop over dest channels */
599 uint channelsWritten = 0x0;
600 for (chan = 0; chan < NUM_CHANNELS; chan++) {
601 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
602 /* check if we're reading a channel that's been written */
603 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
604 if (channelsWritten & (1 << swizzle)) {
605 return TRUE;
606 }
607
608 channelsWritten |= (1 << chan);
609 }
610 }
611 }
612 }
613 return FALSE;
614 }
615
616
617 /**
618 * Initialize machine state by expanding tokens to full instructions,
619 * allocating temporary storage, setting up constants, etc.
620 * After this, we can call tgsi_exec_machine_run() many times.
621 */
622 void
623 tgsi_exec_machine_bind_shader(
624 struct tgsi_exec_machine *mach,
625 const struct tgsi_token *tokens,
626 uint numSamplers,
627 struct tgsi_sampler **samplers)
628 {
629 uint k;
630 struct tgsi_parse_context parse;
631 struct tgsi_full_instruction *instructions;
632 struct tgsi_full_declaration *declarations;
633 uint maxInstructions = 10, numInstructions = 0;
634 uint maxDeclarations = 10, numDeclarations = 0;
635
636 #if 0
637 tgsi_dump(tokens, 0);
638 #endif
639
640 util_init_math();
641
642 if (numSamplers) {
643 assert(samplers);
644 }
645
646 mach->Tokens = tokens;
647 mach->Samplers = samplers;
648
649 if (!tokens) {
650 /* unbind and free all */
651 if (mach->Declarations) {
652 FREE( mach->Declarations );
653 }
654 mach->Declarations = NULL;
655 mach->NumDeclarations = 0;
656
657 if (mach->Instructions) {
658 FREE( mach->Instructions );
659 }
660 mach->Instructions = NULL;
661 mach->NumInstructions = 0;
662
663 return;
664 }
665
666 k = tgsi_parse_init (&parse, mach->Tokens);
667 if (k != TGSI_PARSE_OK) {
668 debug_printf( "Problem parsing!\n" );
669 return;
670 }
671
672 mach->Processor = parse.FullHeader.Processor.Processor;
673 mach->ImmLimit = 0;
674
675 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
676 !mach->UsedGeometryShader) {
677 struct tgsi_exec_vector *inputs;
678 struct tgsi_exec_vector *outputs;
679
680 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
681 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS,
682 16);
683
684 if (!inputs)
685 return;
686
687 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
688 TGSI_MAX_TOTAL_VERTICES, 16);
689
690 if (!outputs) {
691 align_free(inputs);
692 return;
693 }
694
695 align_free(mach->Inputs);
696 align_free(mach->Outputs);
697
698 mach->Inputs = inputs;
699 mach->Outputs = outputs;
700 mach->UsedGeometryShader = TRUE;
701 }
702
703 declarations = (struct tgsi_full_declaration *)
704 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
705
706 if (!declarations) {
707 return;
708 }
709
710 instructions = (struct tgsi_full_instruction *)
711 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
712
713 if (!instructions) {
714 FREE( declarations );
715 return;
716 }
717
718 while( !tgsi_parse_end_of_tokens( &parse ) ) {
719 uint i;
720
721 tgsi_parse_token( &parse );
722 switch( parse.FullToken.Token.Type ) {
723 case TGSI_TOKEN_TYPE_DECLARATION:
724 /* save expanded declaration */
725 if (numDeclarations == maxDeclarations) {
726 declarations = REALLOC(declarations,
727 maxDeclarations
728 * sizeof(struct tgsi_full_declaration),
729 (maxDeclarations + 10)
730 * sizeof(struct tgsi_full_declaration));
731 maxDeclarations += 10;
732 }
733 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
734 unsigned reg;
735 for (reg = parse.FullToken.FullDeclaration.Range.First;
736 reg <= parse.FullToken.FullDeclaration.Range.Last;
737 ++reg) {
738 ++mach->NumOutputs;
739 }
740 }
741 if (parse.FullToken.FullDeclaration.Declaration.File ==
742 TGSI_FILE_IMMEDIATE_ARRAY) {
743 unsigned reg;
744 struct tgsi_full_declaration *decl =
745 &parse.FullToken.FullDeclaration;
746 debug_assert(decl->Range.Last < TGSI_EXEC_NUM_IMMEDIATES);
747 for (reg = decl->Range.First; reg <= decl->Range.Last; ++reg) {
748 for( i = 0; i < 4; i++ ) {
749 int idx = reg * 4 + i;
750 mach->ImmArray[reg][i] = decl->ImmediateData.u[idx].Float;
751 }
752 }
753 }
754 memcpy(declarations + numDeclarations,
755 &parse.FullToken.FullDeclaration,
756 sizeof(declarations[0]));
757 numDeclarations++;
758 break;
759
760 case TGSI_TOKEN_TYPE_IMMEDIATE:
761 {
762 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
763 assert( size <= 4 );
764 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
765
766 for( i = 0; i < size; i++ ) {
767 mach->Imms[mach->ImmLimit][i] =
768 parse.FullToken.FullImmediate.u[i].Float;
769 }
770 mach->ImmLimit += 1;
771 }
772 break;
773
774 case TGSI_TOKEN_TYPE_INSTRUCTION:
775
776 /* save expanded instruction */
777 if (numInstructions == maxInstructions) {
778 instructions = REALLOC(instructions,
779 maxInstructions
780 * sizeof(struct tgsi_full_instruction),
781 (maxInstructions + 10)
782 * sizeof(struct tgsi_full_instruction));
783 maxInstructions += 10;
784 }
785
786 memcpy(instructions + numInstructions,
787 &parse.FullToken.FullInstruction,
788 sizeof(instructions[0]));
789
790 numInstructions++;
791 break;
792
793 case TGSI_TOKEN_TYPE_PROPERTY:
794 break;
795
796 default:
797 assert( 0 );
798 }
799 }
800 tgsi_parse_free (&parse);
801
802 if (mach->Declarations) {
803 FREE( mach->Declarations );
804 }
805 mach->Declarations = declarations;
806 mach->NumDeclarations = numDeclarations;
807
808 if (mach->Instructions) {
809 FREE( mach->Instructions );
810 }
811 mach->Instructions = instructions;
812 mach->NumInstructions = numInstructions;
813 }
814
815
816 struct tgsi_exec_machine *
817 tgsi_exec_machine_create( void )
818 {
819 struct tgsi_exec_machine *mach;
820 uint i;
821
822 mach = align_malloc( sizeof *mach, 16 );
823 if (!mach)
824 goto fail;
825
826 memset(mach, 0, sizeof(*mach));
827
828 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
829 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
830 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
831
832 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
833 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
834 if (!mach->Inputs || !mach->Outputs)
835 goto fail;
836
837 /* Setup constants needed by the SSE2 executor. */
838 for( i = 0; i < 4; i++ ) {
839 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
840 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
841 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
842 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
843 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
844 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
845 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
846 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
847 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
848 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
849 }
850
851 #ifdef DEBUG
852 /* silence warnings */
853 (void) print_chan;
854 (void) print_temp;
855 #endif
856
857 return mach;
858
859 fail:
860 if (mach) {
861 align_free(mach->Inputs);
862 align_free(mach->Outputs);
863 align_free(mach);
864 }
865 return NULL;
866 }
867
868
869 void
870 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
871 {
872 if (mach) {
873 if (mach->Instructions)
874 FREE(mach->Instructions);
875 if (mach->Declarations)
876 FREE(mach->Declarations);
877
878 align_free(mach->Inputs);
879 align_free(mach->Outputs);
880
881 align_free(mach);
882 }
883 }
884
885 static void
886 micro_add(union tgsi_exec_channel *dst,
887 const union tgsi_exec_channel *src0,
888 const union tgsi_exec_channel *src1)
889 {
890 dst->f[0] = src0->f[0] + src1->f[0];
891 dst->f[1] = src0->f[1] + src1->f[1];
892 dst->f[2] = src0->f[2] + src1->f[2];
893 dst->f[3] = src0->f[3] + src1->f[3];
894 }
895
896 static void
897 micro_div(
898 union tgsi_exec_channel *dst,
899 const union tgsi_exec_channel *src0,
900 const union tgsi_exec_channel *src1 )
901 {
902 if (src1->f[0] != 0) {
903 dst->f[0] = src0->f[0] / src1->f[0];
904 }
905 if (src1->f[1] != 0) {
906 dst->f[1] = src0->f[1] / src1->f[1];
907 }
908 if (src1->f[2] != 0) {
909 dst->f[2] = src0->f[2] / src1->f[2];
910 }
911 if (src1->f[3] != 0) {
912 dst->f[3] = src0->f[3] / src1->f[3];
913 }
914 }
915
916 static void
917 micro_rcc(union tgsi_exec_channel *dst,
918 const union tgsi_exec_channel *src)
919 {
920 uint i;
921
922 for (i = 0; i < 4; i++) {
923 float recip = 1.0f / src->f[i];
924
925 if (recip > 0.0f) {
926 if (recip > 1.884467e+019f) {
927 dst->f[i] = 1.884467e+019f;
928 }
929 else if (recip < 5.42101e-020f) {
930 dst->f[i] = 5.42101e-020f;
931 }
932 else {
933 dst->f[i] = recip;
934 }
935 }
936 else {
937 if (recip < -1.884467e+019f) {
938 dst->f[i] = -1.884467e+019f;
939 }
940 else if (recip > -5.42101e-020f) {
941 dst->f[i] = -5.42101e-020f;
942 }
943 else {
944 dst->f[i] = recip;
945 }
946 }
947 }
948 }
949
950 static void
951 micro_lt(
952 union tgsi_exec_channel *dst,
953 const union tgsi_exec_channel *src0,
954 const union tgsi_exec_channel *src1,
955 const union tgsi_exec_channel *src2,
956 const union tgsi_exec_channel *src3 )
957 {
958 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
959 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
960 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
961 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
962 }
963
964 static void
965 micro_max(union tgsi_exec_channel *dst,
966 const union tgsi_exec_channel *src0,
967 const union tgsi_exec_channel *src1)
968 {
969 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
970 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
971 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
972 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
973 }
974
975 static void
976 micro_min(union tgsi_exec_channel *dst,
977 const union tgsi_exec_channel *src0,
978 const union tgsi_exec_channel *src1)
979 {
980 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
981 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
982 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
983 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
984 }
985
986 static void
987 micro_mul(union tgsi_exec_channel *dst,
988 const union tgsi_exec_channel *src0,
989 const union tgsi_exec_channel *src1)
990 {
991 dst->f[0] = src0->f[0] * src1->f[0];
992 dst->f[1] = src0->f[1] * src1->f[1];
993 dst->f[2] = src0->f[2] * src1->f[2];
994 dst->f[3] = src0->f[3] * src1->f[3];
995 }
996
997 static void
998 micro_neg(
999 union tgsi_exec_channel *dst,
1000 const union tgsi_exec_channel *src )
1001 {
1002 dst->f[0] = -src->f[0];
1003 dst->f[1] = -src->f[1];
1004 dst->f[2] = -src->f[2];
1005 dst->f[3] = -src->f[3];
1006 }
1007
1008 static void
1009 micro_pow(
1010 union tgsi_exec_channel *dst,
1011 const union tgsi_exec_channel *src0,
1012 const union tgsi_exec_channel *src1 )
1013 {
1014 #if FAST_MATH
1015 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1016 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1017 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1018 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1019 #else
1020 dst->f[0] = powf( src0->f[0], src1->f[0] );
1021 dst->f[1] = powf( src0->f[1], src1->f[1] );
1022 dst->f[2] = powf( src0->f[2], src1->f[2] );
1023 dst->f[3] = powf( src0->f[3], src1->f[3] );
1024 #endif
1025 }
1026
1027 static void
1028 micro_sub(union tgsi_exec_channel *dst,
1029 const union tgsi_exec_channel *src0,
1030 const union tgsi_exec_channel *src1)
1031 {
1032 dst->f[0] = src0->f[0] - src1->f[0];
1033 dst->f[1] = src0->f[1] - src1->f[1];
1034 dst->f[2] = src0->f[2] - src1->f[2];
1035 dst->f[3] = src0->f[3] - src1->f[3];
1036 }
1037
1038 static void
1039 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1040 const uint file,
1041 const uint swizzle,
1042 const union tgsi_exec_channel *index,
1043 const union tgsi_exec_channel *index2D,
1044 union tgsi_exec_channel *chan)
1045 {
1046 uint i;
1047
1048 assert(swizzle < 4);
1049
1050 switch (file) {
1051 case TGSI_FILE_CONSTANT:
1052 for (i = 0; i < QUAD_SIZE; i++) {
1053 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1054 assert(mach->Consts[index2D->i[i]]);
1055
1056 if (index->i[i] < 0) {
1057 chan->u[i] = 0;
1058 } else {
1059 /* NOTE: copying the const value as a uint instead of float */
1060 const uint constbuf = index2D->i[i];
1061 const uint *buf = (const uint *)mach->Consts[constbuf];
1062 const int pos = index->i[i] * 4 + swizzle;
1063 /* const buffer bounds check */
1064 if (pos < 0 || pos >= mach->ConstsSize[constbuf]) {
1065 if (0) {
1066 /* Debug: print warning */
1067 static int count = 0;
1068 if (count++ < 100)
1069 debug_printf("TGSI Exec: const buffer index %d"
1070 " out of bounds\n", pos);
1071 }
1072 chan->u[i] = 0;
1073 }
1074 else
1075 chan->u[i] = buf[pos];
1076 }
1077 }
1078 break;
1079
1080 case TGSI_FILE_INPUT:
1081 for (i = 0; i < QUAD_SIZE; i++) {
1082 /*
1083 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1084 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1085 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1086 index2D->i[i], index->i[i]);
1087 }*/
1088 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1089 assert(pos >= 0);
1090 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1091 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1092 }
1093 break;
1094
1095 case TGSI_FILE_SYSTEM_VALUE:
1096 /* XXX no swizzling at this point. Will be needed if we put
1097 * gl_FragCoord, for example, in a sys value register.
1098 */
1099 for (i = 0; i < QUAD_SIZE; i++) {
1100 chan->f[i] = mach->SystemValue[index->i[i]][0];
1101 }
1102 break;
1103
1104 case TGSI_FILE_TEMPORARY:
1105 for (i = 0; i < QUAD_SIZE; i++) {
1106 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1107 assert(index2D->i[i] == 0);
1108
1109 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1110 }
1111 break;
1112
1113 case TGSI_FILE_TEMPORARY_ARRAY:
1114 for (i = 0; i < QUAD_SIZE; i++) {
1115 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1116 assert(index2D->i[i] < TGSI_EXEC_NUM_TEMP_ARRAYS);
1117
1118 chan->u[i] =
1119 mach->TempArray[index2D->i[i]][index->i[i]].xyzw[swizzle].u[i];
1120 }
1121 break;
1122
1123 case TGSI_FILE_IMMEDIATE:
1124 for (i = 0; i < QUAD_SIZE; i++) {
1125 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1126 assert(index2D->i[i] == 0);
1127
1128 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1129 }
1130 break;
1131
1132 case TGSI_FILE_IMMEDIATE_ARRAY:
1133 for (i = 0; i < QUAD_SIZE; i++) {
1134 assert(index2D->i[i] == 0);
1135
1136 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1137 }
1138 break;
1139
1140 case TGSI_FILE_ADDRESS:
1141 for (i = 0; i < QUAD_SIZE; i++) {
1142 assert(index->i[i] >= 0);
1143 assert(index2D->i[i] == 0);
1144
1145 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1146 }
1147 break;
1148
1149 case TGSI_FILE_PREDICATE:
1150 for (i = 0; i < QUAD_SIZE; i++) {
1151 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1152 assert(index2D->i[i] == 0);
1153
1154 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1155 }
1156 break;
1157
1158 case TGSI_FILE_OUTPUT:
1159 /* vertex/fragment output vars can be read too */
1160 for (i = 0; i < QUAD_SIZE; i++) {
1161 assert(index->i[i] >= 0);
1162 assert(index2D->i[i] == 0);
1163
1164 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1165 }
1166 break;
1167
1168 default:
1169 assert(0);
1170 for (i = 0; i < QUAD_SIZE; i++) {
1171 chan->u[i] = 0;
1172 }
1173 }
1174 }
1175
1176 static void
1177 fetch_source(const struct tgsi_exec_machine *mach,
1178 union tgsi_exec_channel *chan,
1179 const struct tgsi_full_src_register *reg,
1180 const uint chan_index,
1181 enum tgsi_exec_datatype src_datatype)
1182 {
1183 union tgsi_exec_channel index;
1184 union tgsi_exec_channel index2D;
1185 uint swizzle;
1186
1187 /* We start with a direct index into a register file.
1188 *
1189 * file[1],
1190 * where:
1191 * file = Register.File
1192 * [1] = Register.Index
1193 */
1194 index.i[0] =
1195 index.i[1] =
1196 index.i[2] =
1197 index.i[3] = reg->Register.Index;
1198
1199 /* There is an extra source register that indirectly subscripts
1200 * a register file. The direct index now becomes an offset
1201 * that is being added to the indirect register.
1202 *
1203 * file[ind[2].x+1],
1204 * where:
1205 * ind = Indirect.File
1206 * [2] = Indirect.Index
1207 * .x = Indirect.SwizzleX
1208 */
1209 if (reg->Register.Indirect) {
1210 union tgsi_exec_channel index2;
1211 union tgsi_exec_channel indir_index;
1212 const uint execmask = mach->ExecMask;
1213 uint i;
1214
1215 /* which address register (always zero now) */
1216 index2.i[0] =
1217 index2.i[1] =
1218 index2.i[2] =
1219 index2.i[3] = reg->Indirect.Index;
1220 assert(reg->Indirect.File == TGSI_FILE_ADDRESS);
1221 /* get current value of address register[swizzle] */
1222 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1223 fetch_src_file_channel(mach,
1224 reg->Indirect.File,
1225 swizzle,
1226 &index2,
1227 &ZeroVec,
1228 &indir_index);
1229
1230 /* add value of address register to the offset */
1231 index.i[0] += indir_index.i[0];
1232 index.i[1] += indir_index.i[1];
1233 index.i[2] += indir_index.i[2];
1234 index.i[3] += indir_index.i[3];
1235
1236 /* for disabled execution channels, zero-out the index to
1237 * avoid using a potential garbage value.
1238 */
1239 for (i = 0; i < QUAD_SIZE; i++) {
1240 if ((execmask & (1 << i)) == 0)
1241 index.i[i] = 0;
1242 }
1243 }
1244
1245 /* There is an extra source register that is a second
1246 * subscript to a register file. Effectively it means that
1247 * the register file is actually a 2D array of registers.
1248 *
1249 * file[3][1],
1250 * where:
1251 * [3] = Dimension.Index
1252 */
1253 if (reg->Register.Dimension) {
1254 index2D.i[0] =
1255 index2D.i[1] =
1256 index2D.i[2] =
1257 index2D.i[3] = reg->Dimension.Index;
1258
1259 /* Again, the second subscript index can be addressed indirectly
1260 * identically to the first one.
1261 * Nothing stops us from indirectly addressing the indirect register,
1262 * but there is no need for that, so we won't exercise it.
1263 *
1264 * file[ind[4].y+3][1],
1265 * where:
1266 * ind = DimIndirect.File
1267 * [4] = DimIndirect.Index
1268 * .y = DimIndirect.SwizzleX
1269 */
1270 if (reg->Dimension.Indirect) {
1271 union tgsi_exec_channel index2;
1272 union tgsi_exec_channel indir_index;
1273 const uint execmask = mach->ExecMask;
1274 uint i;
1275
1276 index2.i[0] =
1277 index2.i[1] =
1278 index2.i[2] =
1279 index2.i[3] = reg->DimIndirect.Index;
1280
1281 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1282 fetch_src_file_channel(mach,
1283 reg->DimIndirect.File,
1284 swizzle,
1285 &index2,
1286 &ZeroVec,
1287 &indir_index);
1288
1289 index2D.i[0] += indir_index.i[0];
1290 index2D.i[1] += indir_index.i[1];
1291 index2D.i[2] += indir_index.i[2];
1292 index2D.i[3] += indir_index.i[3];
1293
1294 /* for disabled execution channels, zero-out the index to
1295 * avoid using a potential garbage value.
1296 */
1297 for (i = 0; i < QUAD_SIZE; i++) {
1298 if ((execmask & (1 << i)) == 0) {
1299 index2D.i[i] = 0;
1300 }
1301 }
1302 }
1303
1304 /* If by any chance there was a need for a 3D array of register
1305 * files, we would have to check whether Dimension is followed
1306 * by a dimension register and continue the saga.
1307 */
1308 } else {
1309 index2D.i[0] =
1310 index2D.i[1] =
1311 index2D.i[2] =
1312 index2D.i[3] = 0;
1313 }
1314
1315 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1316 fetch_src_file_channel(mach,
1317 reg->Register.File,
1318 swizzle,
1319 &index,
1320 &index2D,
1321 chan);
1322
1323 if (reg->Register.Absolute) {
1324 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1325 micro_abs(chan, chan);
1326 } else {
1327 micro_iabs(chan, chan);
1328 }
1329 }
1330
1331 if (reg->Register.Negate) {
1332 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1333 micro_neg(chan, chan);
1334 } else {
1335 micro_ineg(chan, chan);
1336 }
1337 }
1338 }
1339
1340 static void
1341 store_dest(struct tgsi_exec_machine *mach,
1342 const union tgsi_exec_channel *chan,
1343 const struct tgsi_full_dst_register *reg,
1344 const struct tgsi_full_instruction *inst,
1345 uint chan_index,
1346 enum tgsi_exec_datatype dst_datatype)
1347 {
1348 uint i;
1349 union tgsi_exec_channel null;
1350 union tgsi_exec_channel *dst;
1351 union tgsi_exec_channel index2D;
1352 uint execmask = mach->ExecMask;
1353 int offset = 0; /* indirection offset */
1354 int index;
1355
1356 /* for debugging */
1357 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1358 check_inf_or_nan(chan);
1359 }
1360
1361 /* There is an extra source register that indirectly subscripts
1362 * a register file. The direct index now becomes an offset
1363 * that is being added to the indirect register.
1364 *
1365 * file[ind[2].x+1],
1366 * where:
1367 * ind = Indirect.File
1368 * [2] = Indirect.Index
1369 * .x = Indirect.SwizzleX
1370 */
1371 if (reg->Register.Indirect) {
1372 union tgsi_exec_channel index;
1373 union tgsi_exec_channel indir_index;
1374 uint swizzle;
1375
1376 /* which address register (always zero for now) */
1377 index.i[0] =
1378 index.i[1] =
1379 index.i[2] =
1380 index.i[3] = reg->Indirect.Index;
1381
1382 /* get current value of address register[swizzle] */
1383 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1384
1385 /* fetch values from the address/indirection register */
1386 fetch_src_file_channel(mach,
1387 reg->Indirect.File,
1388 swizzle,
1389 &index,
1390 &ZeroVec,
1391 &indir_index);
1392
1393 /* save indirection offset */
1394 offset = indir_index.i[0];
1395 }
1396
1397 /* There is an extra source register that is a second
1398 * subscript to a register file. Effectively it means that
1399 * the register file is actually a 2D array of registers.
1400 *
1401 * file[3][1],
1402 * where:
1403 * [3] = Dimension.Index
1404 */
1405 if (reg->Register.Dimension) {
1406 index2D.i[0] =
1407 index2D.i[1] =
1408 index2D.i[2] =
1409 index2D.i[3] = reg->Dimension.Index;
1410
1411 /* Again, the second subscript index can be addressed indirectly
1412 * identically to the first one.
1413 * Nothing stops us from indirectly addressing the indirect register,
1414 * but there is no need for that, so we won't exercise it.
1415 *
1416 * file[ind[4].y+3][1],
1417 * where:
1418 * ind = DimIndirect.File
1419 * [4] = DimIndirect.Index
1420 * .y = DimIndirect.SwizzleX
1421 */
1422 if (reg->Dimension.Indirect) {
1423 union tgsi_exec_channel index2;
1424 union tgsi_exec_channel indir_index;
1425 const uint execmask = mach->ExecMask;
1426 unsigned swizzle;
1427 uint i;
1428
1429 index2.i[0] =
1430 index2.i[1] =
1431 index2.i[2] =
1432 index2.i[3] = reg->DimIndirect.Index;
1433
1434 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1435 fetch_src_file_channel(mach,
1436 reg->DimIndirect.File,
1437 swizzle,
1438 &index2,
1439 &ZeroVec,
1440 &indir_index);
1441
1442 index2D.i[0] += indir_index.i[0];
1443 index2D.i[1] += indir_index.i[1];
1444 index2D.i[2] += indir_index.i[2];
1445 index2D.i[3] += indir_index.i[3];
1446
1447 /* for disabled execution channels, zero-out the index to
1448 * avoid using a potential garbage value.
1449 */
1450 for (i = 0; i < QUAD_SIZE; i++) {
1451 if ((execmask & (1 << i)) == 0) {
1452 index2D.i[i] = 0;
1453 }
1454 }
1455 }
1456
1457 /* If by any chance there was a need for a 3D array of register
1458 * files, we would have to check whether Dimension is followed
1459 * by a dimension register and continue the saga.
1460 */
1461 } else {
1462 index2D.i[0] =
1463 index2D.i[1] =
1464 index2D.i[2] =
1465 index2D.i[3] = 0;
1466 }
1467
1468 switch (reg->Register.File) {
1469 case TGSI_FILE_NULL:
1470 dst = &null;
1471 break;
1472
1473 case TGSI_FILE_OUTPUT:
1474 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1475 + reg->Register.Index;
1476 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1477 #if 0
1478 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1479 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1480 for (i = 0; i < QUAD_SIZE; i++)
1481 if (execmask & (1 << i))
1482 fprintf(stderr, "%f, ", chan->f[i]);
1483 fprintf(stderr, ")\n");
1484 }
1485 #endif
1486 break;
1487
1488 case TGSI_FILE_TEMPORARY:
1489 index = reg->Register.Index;
1490 assert( index < TGSI_EXEC_NUM_TEMPS );
1491 dst = &mach->Temps[offset + index].xyzw[chan_index];
1492 break;
1493
1494 case TGSI_FILE_TEMPORARY_ARRAY:
1495 index = reg->Register.Index;
1496 assert( index < TGSI_EXEC_NUM_TEMPS );
1497 assert( index2D.i[0] < TGSI_EXEC_NUM_TEMP_ARRAYS );
1498 /* XXX we use index2D.i[0] here but somehow we might
1499 * end up with someone trying to store indirectly in
1500 * different buffers */
1501 dst = &mach->TempArray[index2D.i[0]][offset + index].xyzw[chan_index];
1502 break;
1503
1504 case TGSI_FILE_ADDRESS:
1505 index = reg->Register.Index;
1506 dst = &mach->Addrs[index].xyzw[chan_index];
1507 break;
1508
1509 case TGSI_FILE_PREDICATE:
1510 index = reg->Register.Index;
1511 assert(index < TGSI_EXEC_NUM_PREDS);
1512 dst = &mach->Predicates[index].xyzw[chan_index];
1513 break;
1514
1515 default:
1516 assert( 0 );
1517 return;
1518 }
1519
1520 if (inst->Instruction.Predicate) {
1521 uint swizzle;
1522 union tgsi_exec_channel *pred;
1523
1524 switch (chan_index) {
1525 case CHAN_X:
1526 swizzle = inst->Predicate.SwizzleX;
1527 break;
1528 case CHAN_Y:
1529 swizzle = inst->Predicate.SwizzleY;
1530 break;
1531 case CHAN_Z:
1532 swizzle = inst->Predicate.SwizzleZ;
1533 break;
1534 case CHAN_W:
1535 swizzle = inst->Predicate.SwizzleW;
1536 break;
1537 default:
1538 assert(0);
1539 return;
1540 }
1541
1542 assert(inst->Predicate.Index == 0);
1543
1544 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1545
1546 if (inst->Predicate.Negate) {
1547 for (i = 0; i < QUAD_SIZE; i++) {
1548 if (pred->u[i]) {
1549 execmask &= ~(1 << i);
1550 }
1551 }
1552 } else {
1553 for (i = 0; i < QUAD_SIZE; i++) {
1554 if (!pred->u[i]) {
1555 execmask &= ~(1 << i);
1556 }
1557 }
1558 }
1559 }
1560
1561 switch (inst->Instruction.Saturate) {
1562 case TGSI_SAT_NONE:
1563 for (i = 0; i < QUAD_SIZE; i++)
1564 if (execmask & (1 << i))
1565 dst->i[i] = chan->i[i];
1566 break;
1567
1568 case TGSI_SAT_ZERO_ONE:
1569 for (i = 0; i < QUAD_SIZE; i++)
1570 if (execmask & (1 << i)) {
1571 if (chan->f[i] < 0.0f)
1572 dst->f[i] = 0.0f;
1573 else if (chan->f[i] > 1.0f)
1574 dst->f[i] = 1.0f;
1575 else
1576 dst->i[i] = chan->i[i];
1577 }
1578 break;
1579
1580 case TGSI_SAT_MINUS_PLUS_ONE:
1581 for (i = 0; i < QUAD_SIZE; i++)
1582 if (execmask & (1 << i)) {
1583 if (chan->f[i] < -1.0f)
1584 dst->f[i] = -1.0f;
1585 else if (chan->f[i] > 1.0f)
1586 dst->f[i] = 1.0f;
1587 else
1588 dst->i[i] = chan->i[i];
1589 }
1590 break;
1591
1592 default:
1593 assert( 0 );
1594 }
1595 }
1596
1597 #define FETCH(VAL,INDEX,CHAN)\
1598 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1599
1600 #define IFETCH(VAL,INDEX,CHAN)\
1601 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1602
1603
1604 /**
1605 * Execute ARB-style KIL which is predicated by a src register.
1606 * Kill fragment if any of the four values is less than zero.
1607 */
1608 static void
1609 exec_kil(struct tgsi_exec_machine *mach,
1610 const struct tgsi_full_instruction *inst)
1611 {
1612 uint uniquemask;
1613 uint chan_index;
1614 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1615 union tgsi_exec_channel r[1];
1616
1617 /* This mask stores component bits that were already tested. */
1618 uniquemask = 0;
1619
1620 for (chan_index = 0; chan_index < 4; chan_index++)
1621 {
1622 uint swizzle;
1623 uint i;
1624
1625 /* unswizzle channel */
1626 swizzle = tgsi_util_get_full_src_register_swizzle (
1627 &inst->Src[0],
1628 chan_index);
1629
1630 /* check if the component has not been already tested */
1631 if (uniquemask & (1 << swizzle))
1632 continue;
1633 uniquemask |= 1 << swizzle;
1634
1635 FETCH(&r[0], 0, chan_index);
1636 for (i = 0; i < 4; i++)
1637 if (r[0].f[i] < 0.0f)
1638 kilmask |= 1 << i;
1639 }
1640
1641 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1642 }
1643
1644 /**
1645 * Execute NVIDIA-style KIL which is predicated by a condition code.
1646 * Kill fragment if the condition code is TRUE.
1647 */
1648 static void
1649 exec_kilp(struct tgsi_exec_machine *mach,
1650 const struct tgsi_full_instruction *inst)
1651 {
1652 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1653
1654 /* "unconditional" kil */
1655 kilmask = mach->ExecMask;
1656 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1657 }
1658
1659 static void
1660 emit_vertex(struct tgsi_exec_machine *mach)
1661 {
1662 /* FIXME: check for exec mask correctly
1663 unsigned i;
1664 for (i = 0; i < QUAD_SIZE; ++i) {
1665 if ((mach->ExecMask & (1 << i)))
1666 */
1667 if (mach->ExecMask) {
1668 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1669 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1670 }
1671 }
1672
1673 static void
1674 emit_primitive(struct tgsi_exec_machine *mach)
1675 {
1676 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1677 /* FIXME: check for exec mask correctly
1678 unsigned i;
1679 for (i = 0; i < QUAD_SIZE; ++i) {
1680 if ((mach->ExecMask & (1 << i)))
1681 */
1682 if (mach->ExecMask) {
1683 ++(*prim_count);
1684 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1685 mach->Primitives[*prim_count] = 0;
1686 }
1687 }
1688
1689 static void
1690 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1691 {
1692 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1693 int emitted_verts =
1694 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1695 if (emitted_verts) {
1696 emit_primitive(mach);
1697 }
1698 }
1699 }
1700
1701
1702 /*
1703 * Fetch four texture samples using STR texture coordinates.
1704 */
1705 static void
1706 fetch_texel( struct tgsi_sampler *sampler,
1707 const union tgsi_exec_channel *s,
1708 const union tgsi_exec_channel *t,
1709 const union tgsi_exec_channel *p,
1710 const union tgsi_exec_channel *c0,
1711 enum tgsi_sampler_control control,
1712 union tgsi_exec_channel *r,
1713 union tgsi_exec_channel *g,
1714 union tgsi_exec_channel *b,
1715 union tgsi_exec_channel *a )
1716 {
1717 uint j;
1718 float rgba[NUM_CHANNELS][QUAD_SIZE];
1719
1720 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, control, rgba);
1721
1722 for (j = 0; j < 4; j++) {
1723 r->f[j] = rgba[0][j];
1724 g->f[j] = rgba[1][j];
1725 b->f[j] = rgba[2][j];
1726 a->f[j] = rgba[3][j];
1727 }
1728 }
1729
1730
1731 #define TEX_MODIFIER_NONE 0
1732 #define TEX_MODIFIER_PROJECTED 1
1733 #define TEX_MODIFIER_LOD_BIAS 2
1734 #define TEX_MODIFIER_EXPLICIT_LOD 3
1735
1736
1737 static void
1738 exec_tex(struct tgsi_exec_machine *mach,
1739 const struct tgsi_full_instruction *inst,
1740 uint modifier)
1741 {
1742 const uint unit = inst->Src[1].Register.Index;
1743 union tgsi_exec_channel r[4];
1744 const union tgsi_exec_channel *lod = &ZeroVec;
1745 enum tgsi_sampler_control control;
1746 uint chan;
1747
1748 if (modifier != TEX_MODIFIER_NONE) {
1749 FETCH(&r[3], 0, CHAN_W);
1750 if (modifier != TEX_MODIFIER_PROJECTED) {
1751 lod = &r[3];
1752 }
1753 }
1754
1755 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1756 control = tgsi_sampler_lod_explicit;
1757 } else {
1758 control = tgsi_sampler_lod_bias;
1759 }
1760
1761 switch (inst->Texture.Texture) {
1762 case TGSI_TEXTURE_1D:
1763 case TGSI_TEXTURE_SHADOW1D:
1764 FETCH(&r[0], 0, CHAN_X);
1765
1766 if (modifier == TEX_MODIFIER_PROJECTED) {
1767 micro_div(&r[0], &r[0], &r[3]);
1768 }
1769
1770 fetch_texel(mach->Samplers[unit],
1771 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1772 control,
1773 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1774 break;
1775
1776 case TGSI_TEXTURE_2D:
1777 case TGSI_TEXTURE_RECT:
1778 case TGSI_TEXTURE_SHADOW2D:
1779 case TGSI_TEXTURE_SHADOWRECT:
1780 FETCH(&r[0], 0, CHAN_X);
1781 FETCH(&r[1], 0, CHAN_Y);
1782 FETCH(&r[2], 0, CHAN_Z);
1783
1784 if (modifier == TEX_MODIFIER_PROJECTED) {
1785 micro_div(&r[0], &r[0], &r[3]);
1786 micro_div(&r[1], &r[1], &r[3]);
1787 micro_div(&r[2], &r[2], &r[3]);
1788 }
1789
1790 fetch_texel(mach->Samplers[unit],
1791 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1792 control,
1793 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1794 break;
1795
1796 case TGSI_TEXTURE_1D_ARRAY:
1797 FETCH(&r[0], 0, CHAN_X);
1798 FETCH(&r[1], 0, CHAN_Y);
1799
1800 if (modifier == TEX_MODIFIER_PROJECTED) {
1801 micro_div(&r[0], &r[0], &r[3]);
1802 }
1803
1804 fetch_texel(mach->Samplers[unit],
1805 &r[0], &r[1], &ZeroVec, lod, /* S, T, P, LOD */
1806 control,
1807 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1808 break;
1809 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1810 FETCH(&r[0], 0, CHAN_X);
1811 FETCH(&r[1], 0, CHAN_Y);
1812 FETCH(&r[2], 0, CHAN_Z);
1813
1814 if (modifier == TEX_MODIFIER_PROJECTED) {
1815 micro_div(&r[0], &r[0], &r[3]);
1816 }
1817
1818 fetch_texel(mach->Samplers[unit],
1819 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1820 control,
1821 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1822 break;
1823
1824 case TGSI_TEXTURE_2D_ARRAY:
1825 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1826 FETCH(&r[0], 0, CHAN_X);
1827 FETCH(&r[1], 0, CHAN_Y);
1828 FETCH(&r[2], 0, CHAN_Z);
1829
1830 if (modifier == TEX_MODIFIER_PROJECTED) {
1831 micro_div(&r[0], &r[0], &r[3]);
1832 micro_div(&r[1], &r[1], &r[3]);
1833 }
1834
1835 fetch_texel(mach->Samplers[unit],
1836 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1837 control,
1838 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1839 break;
1840
1841 case TGSI_TEXTURE_3D:
1842 case TGSI_TEXTURE_CUBE:
1843 FETCH(&r[0], 0, CHAN_X);
1844 FETCH(&r[1], 0, CHAN_Y);
1845 FETCH(&r[2], 0, CHAN_Z);
1846
1847 if (modifier == TEX_MODIFIER_PROJECTED) {
1848 micro_div(&r[0], &r[0], &r[3]);
1849 micro_div(&r[1], &r[1], &r[3]);
1850 micro_div(&r[2], &r[2], &r[3]);
1851 }
1852
1853 fetch_texel(mach->Samplers[unit],
1854 &r[0], &r[1], &r[2], lod,
1855 control,
1856 &r[0], &r[1], &r[2], &r[3]);
1857 break;
1858
1859 default:
1860 assert(0);
1861 }
1862
1863 #if 0
1864 debug_printf("fetch r: %g %g %g %g\n",
1865 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1866 debug_printf("fetch g: %g %g %g %g\n",
1867 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1868 debug_printf("fetch b: %g %g %g %g\n",
1869 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1870 debug_printf("fetch a: %g %g %g %g\n",
1871 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1872 #endif
1873
1874 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1875 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1876 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1877 }
1878 }
1879 }
1880
1881 static void
1882 exec_txd(struct tgsi_exec_machine *mach,
1883 const struct tgsi_full_instruction *inst)
1884 {
1885 const uint unit = inst->Src[3].Register.Index;
1886 union tgsi_exec_channel r[4];
1887 uint chan;
1888
1889 /*
1890 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1891 */
1892
1893 switch (inst->Texture.Texture) {
1894 case TGSI_TEXTURE_1D:
1895 case TGSI_TEXTURE_SHADOW1D:
1896
1897 FETCH(&r[0], 0, CHAN_X);
1898
1899 fetch_texel(mach->Samplers[unit],
1900 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1901 tgsi_sampler_lod_bias,
1902 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1903 break;
1904
1905 case TGSI_TEXTURE_1D_ARRAY:
1906 case TGSI_TEXTURE_2D:
1907 case TGSI_TEXTURE_RECT:
1908 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1909 case TGSI_TEXTURE_SHADOW2D:
1910 case TGSI_TEXTURE_SHADOWRECT:
1911
1912 FETCH(&r[0], 0, CHAN_X);
1913 FETCH(&r[1], 0, CHAN_Y);
1914 FETCH(&r[2], 0, CHAN_Z);
1915
1916 fetch_texel(mach->Samplers[unit],
1917 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
1918 tgsi_sampler_lod_bias,
1919 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1920 break;
1921
1922 case TGSI_TEXTURE_2D_ARRAY:
1923 case TGSI_TEXTURE_3D:
1924 case TGSI_TEXTURE_CUBE:
1925
1926 FETCH(&r[0], 0, CHAN_X);
1927 FETCH(&r[1], 0, CHAN_Y);
1928 FETCH(&r[2], 0, CHAN_Z);
1929
1930 fetch_texel(mach->Samplers[unit],
1931 &r[0], &r[1], &r[2], &ZeroVec,
1932 tgsi_sampler_lod_bias,
1933 &r[0], &r[1], &r[2], &r[3]);
1934 break;
1935
1936 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1937
1938 FETCH(&r[0], 0, CHAN_X);
1939 FETCH(&r[1], 0, CHAN_Y);
1940 FETCH(&r[2], 0, CHAN_Z);
1941 FETCH(&r[3], 0, CHAN_W);
1942
1943 fetch_texel(mach->Samplers[unit],
1944 &r[0], &r[1], &r[2], &r[3],
1945 tgsi_sampler_lod_bias,
1946 &r[0], &r[1], &r[2], &r[3]);
1947 break;
1948
1949 default:
1950 assert(0);
1951 }
1952
1953 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1954 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1955 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1956 }
1957 }
1958 }
1959
1960
1961 static void
1962 exec_txf(struct tgsi_exec_machine *mach,
1963 const struct tgsi_full_instruction *inst)
1964 {
1965 struct tgsi_sampler *sampler;
1966 const uint unit = inst->Src[2].Register.Index;
1967 union tgsi_exec_channel r[4];
1968 union tgsi_exec_channel offset[3];
1969 uint chan;
1970 float rgba[NUM_CHANNELS][QUAD_SIZE];
1971 int j;
1972 int8_t offsets[3];
1973
1974 if (inst->Texture.NumOffsets == 1) {
1975 union tgsi_exec_channel index;
1976 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1977 fetch_src_file_channel(mach, inst->TexOffsets[0].File,
1978 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1979 fetch_src_file_channel(mach, inst->TexOffsets[0].File,
1980 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1981 fetch_src_file_channel(mach, inst->TexOffsets[0].File,
1982 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1983 offsets[0] = offset[0].i[0];
1984 offsets[1] = offset[1].i[0];
1985 offsets[2] = offset[2].i[0];
1986 } else
1987 offsets[0] = offsets[1] = offsets[2] = 0;
1988
1989 IFETCH(&r[3], 0, CHAN_W);
1990
1991 switch(inst->Texture.Texture) {
1992 case TGSI_TEXTURE_3D:
1993 case TGSI_TEXTURE_2D_ARRAY:
1994 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1995 IFETCH(&r[2], 0, CHAN_Z);
1996 /* fallthrough */
1997 case TGSI_TEXTURE_2D:
1998 case TGSI_TEXTURE_RECT:
1999 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2000 case TGSI_TEXTURE_SHADOW2D:
2001 case TGSI_TEXTURE_SHADOWRECT:
2002 case TGSI_TEXTURE_1D_ARRAY:
2003 IFETCH(&r[1], 0, CHAN_Y);
2004 /* fallthrough */
2005 case TGSI_TEXTURE_1D:
2006 case TGSI_TEXTURE_SHADOW1D:
2007 IFETCH(&r[0], 0, CHAN_X);
2008 break;
2009 default:
2010 assert(0);
2011 break;
2012 }
2013
2014 sampler = mach->Samplers[unit];
2015 sampler->get_texel(sampler, r[0].i, r[1].i, r[2].i, r[3].i,
2016 offsets, rgba);
2017
2018 for (j = 0; j < QUAD_SIZE; j++) {
2019 r[0].f[j] = rgba[0][j];
2020 r[1].f[j] = rgba[1][j];
2021 r[2].f[j] = rgba[2][j];
2022 r[3].f[j] = rgba[3][j];
2023 }
2024
2025 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2026 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2027 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2028 }
2029 }
2030 }
2031
2032 static void
2033 exec_txq(struct tgsi_exec_machine *mach,
2034 const struct tgsi_full_instruction *inst)
2035 {
2036 struct tgsi_sampler *sampler;
2037 const uint unit = inst->Src[1].Register.Index;
2038 int result[4];
2039 union tgsi_exec_channel r[4], src;
2040 uint chan;
2041 int i,j;
2042
2043 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_INT);
2044 sampler = mach->Samplers[unit];
2045
2046 sampler->get_dims(sampler, src.i[0], result);
2047
2048 for (i = 0; i < QUAD_SIZE; i++) {
2049 for (j = 0; j < 4; j++) {
2050 r[j].i[i] = result[j];
2051 }
2052 }
2053
2054 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2055 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2056 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2057 TGSI_EXEC_DATA_INT);
2058 }
2059 }
2060 }
2061
2062 static void
2063 exec_sample(struct tgsi_exec_machine *mach,
2064 const struct tgsi_full_instruction *inst,
2065 uint modifier)
2066 {
2067 const uint resource_unit = inst->Src[1].Register.Index;
2068 const uint sampler_unit = inst->Src[2].Register.Index;
2069 union tgsi_exec_channel r[4];
2070 const union tgsi_exec_channel *lod = &ZeroVec;
2071 enum tgsi_sampler_control control;
2072 uint chan;
2073
2074 if (modifier != TEX_MODIFIER_NONE) {
2075 if (modifier == TEX_MODIFIER_LOD_BIAS)
2076 FETCH(&r[3], 3, CHAN_X);
2077 else /*TEX_MODIFIER_LOD*/
2078 FETCH(&r[3], 0, CHAN_W);
2079
2080 if (modifier != TEX_MODIFIER_PROJECTED) {
2081 lod = &r[3];
2082 }
2083 }
2084
2085 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2086 control = tgsi_sampler_lod_explicit;
2087 } else {
2088 control = tgsi_sampler_lod_bias;
2089 }
2090
2091 switch (mach->Resources[resource_unit].Resource) {
2092 case TGSI_TEXTURE_1D:
2093 case TGSI_TEXTURE_SHADOW1D:
2094 FETCH(&r[0], 0, CHAN_X);
2095
2096 if (modifier == TEX_MODIFIER_PROJECTED) {
2097 micro_div(&r[0], &r[0], &r[3]);
2098 }
2099
2100 fetch_texel(mach->Samplers[sampler_unit],
2101 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
2102 control,
2103 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2104 break;
2105
2106 case TGSI_TEXTURE_1D_ARRAY:
2107 case TGSI_TEXTURE_2D:
2108 case TGSI_TEXTURE_RECT:
2109 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2110 case TGSI_TEXTURE_SHADOW2D:
2111 case TGSI_TEXTURE_SHADOWRECT:
2112 FETCH(&r[0], 0, CHAN_X);
2113 FETCH(&r[1], 0, CHAN_Y);
2114 FETCH(&r[2], 0, CHAN_Z);
2115
2116 if (modifier == TEX_MODIFIER_PROJECTED) {
2117 micro_div(&r[0], &r[0], &r[3]);
2118 micro_div(&r[1], &r[1], &r[3]);
2119 micro_div(&r[2], &r[2], &r[3]);
2120 }
2121
2122 fetch_texel(mach->Samplers[sampler_unit],
2123 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
2124 control,
2125 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2126 break;
2127
2128 case TGSI_TEXTURE_2D_ARRAY:
2129 case TGSI_TEXTURE_3D:
2130 case TGSI_TEXTURE_CUBE:
2131 FETCH(&r[0], 0, CHAN_X);
2132 FETCH(&r[1], 0, CHAN_Y);
2133 FETCH(&r[2], 0, CHAN_Z);
2134
2135 if (modifier == TEX_MODIFIER_PROJECTED) {
2136 micro_div(&r[0], &r[0], &r[3]);
2137 micro_div(&r[1], &r[1], &r[3]);
2138 micro_div(&r[2], &r[2], &r[3]);
2139 }
2140
2141 fetch_texel(mach->Samplers[sampler_unit],
2142 &r[0], &r[1], &r[2], lod,
2143 control,
2144 &r[0], &r[1], &r[2], &r[3]);
2145 break;
2146
2147 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2148 FETCH(&r[0], 0, CHAN_X);
2149 FETCH(&r[1], 0, CHAN_Y);
2150 FETCH(&r[2], 0, CHAN_Z);
2151 FETCH(&r[3], 0, CHAN_W);
2152
2153 assert(modifier != TEX_MODIFIER_PROJECTED);
2154
2155 fetch_texel(mach->Samplers[sampler_unit],
2156 &r[0], &r[1], &r[2], &r[3],
2157 control,
2158 &r[0], &r[1], &r[2], &r[3]);
2159 break;
2160
2161 default:
2162 assert(0);
2163 }
2164
2165 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2166 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2167 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2168 }
2169 }
2170 }
2171
2172 static void
2173 exec_sample_d(struct tgsi_exec_machine *mach,
2174 const struct tgsi_full_instruction *inst)
2175 {
2176 const uint resource_unit = inst->Src[1].Register.Index;
2177 const uint sampler_unit = inst->Src[2].Register.Index;
2178 union tgsi_exec_channel r[4];
2179 uint chan;
2180 /*
2181 * XXX: This is fake SAMPLE_D -- the derivatives are not taken into account, yet.
2182 */
2183
2184 switch (mach->Resources[resource_unit].Resource) {
2185 case TGSI_TEXTURE_1D:
2186 case TGSI_TEXTURE_SHADOW1D:
2187
2188 FETCH(&r[0], 0, CHAN_X);
2189
2190 fetch_texel(mach->Samplers[sampler_unit],
2191 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
2192 tgsi_sampler_lod_bias,
2193 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2194 break;
2195
2196 case TGSI_TEXTURE_2D:
2197 case TGSI_TEXTURE_RECT:
2198 case TGSI_TEXTURE_SHADOW2D:
2199 case TGSI_TEXTURE_SHADOWRECT:
2200
2201 FETCH(&r[0], 0, CHAN_X);
2202 FETCH(&r[1], 0, CHAN_Y);
2203 FETCH(&r[2], 0, CHAN_Z);
2204
2205 fetch_texel(mach->Samplers[sampler_unit],
2206 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
2207 tgsi_sampler_lod_bias,
2208 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2209 break;
2210
2211 case TGSI_TEXTURE_3D:
2212 case TGSI_TEXTURE_CUBE:
2213
2214 FETCH(&r[0], 0, CHAN_X);
2215 FETCH(&r[1], 0, CHAN_Y);
2216 FETCH(&r[2], 0, CHAN_Z);
2217
2218 fetch_texel(mach->Samplers[sampler_unit],
2219 &r[0], &r[1], &r[2], &ZeroVec,
2220 tgsi_sampler_lod_bias,
2221 &r[0], &r[1], &r[2], &r[3]);
2222 break;
2223
2224 default:
2225 assert(0);
2226 }
2227
2228 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2229 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2230 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2231 }
2232 }
2233 }
2234
2235
2236 /**
2237 * Evaluate a constant-valued coefficient at the position of the
2238 * current quad.
2239 */
2240 static void
2241 eval_constant_coef(
2242 struct tgsi_exec_machine *mach,
2243 unsigned attrib,
2244 unsigned chan )
2245 {
2246 unsigned i;
2247
2248 for( i = 0; i < QUAD_SIZE; i++ ) {
2249 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2250 }
2251 }
2252
2253 /**
2254 * Evaluate a linear-valued coefficient at the position of the
2255 * current quad.
2256 */
2257 static void
2258 eval_linear_coef(
2259 struct tgsi_exec_machine *mach,
2260 unsigned attrib,
2261 unsigned chan )
2262 {
2263 const float x = mach->QuadPos.xyzw[0].f[0];
2264 const float y = mach->QuadPos.xyzw[1].f[0];
2265 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2266 const float dady = mach->InterpCoefs[attrib].dady[chan];
2267 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2268 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2269 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2270 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2271 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2272 }
2273
2274 /**
2275 * Evaluate a perspective-valued coefficient at the position of the
2276 * current quad.
2277 */
2278 static void
2279 eval_perspective_coef(
2280 struct tgsi_exec_machine *mach,
2281 unsigned attrib,
2282 unsigned chan )
2283 {
2284 const float x = mach->QuadPos.xyzw[0].f[0];
2285 const float y = mach->QuadPos.xyzw[1].f[0];
2286 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2287 const float dady = mach->InterpCoefs[attrib].dady[chan];
2288 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2289 const float *w = mach->QuadPos.xyzw[3].f;
2290 /* divide by W here */
2291 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2292 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2293 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2294 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2295 }
2296
2297
2298 typedef void (* eval_coef_func)(
2299 struct tgsi_exec_machine *mach,
2300 unsigned attrib,
2301 unsigned chan );
2302
2303 static void
2304 exec_declaration(struct tgsi_exec_machine *mach,
2305 const struct tgsi_full_declaration *decl)
2306 {
2307 if (decl->Declaration.File == TGSI_FILE_RESOURCE) {
2308 mach->Resources[decl->Range.First] = decl->Resource;
2309 return;
2310 }
2311
2312 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2313 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2314 uint first, last, mask;
2315
2316 first = decl->Range.First;
2317 last = decl->Range.Last;
2318 mask = decl->Declaration.UsageMask;
2319
2320 /* XXX we could remove this special-case code since
2321 * mach->InterpCoefs[first].a0 should already have the
2322 * front/back-face value. But we should first update the
2323 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2324 * Then, we could remove the tgsi_exec_machine::Face field.
2325 */
2326 /* XXX make FACE a system value */
2327 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2328 uint i;
2329
2330 assert(decl->Semantic.Index == 0);
2331 assert(first == last);
2332
2333 for (i = 0; i < QUAD_SIZE; i++) {
2334 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2335 }
2336 } else {
2337 eval_coef_func eval;
2338 uint i, j;
2339
2340 switch (decl->Declaration.Interpolate) {
2341 case TGSI_INTERPOLATE_CONSTANT:
2342 eval = eval_constant_coef;
2343 break;
2344
2345 case TGSI_INTERPOLATE_LINEAR:
2346 eval = eval_linear_coef;
2347 break;
2348
2349 case TGSI_INTERPOLATE_PERSPECTIVE:
2350 eval = eval_perspective_coef;
2351 break;
2352
2353 default:
2354 assert(0);
2355 return;
2356 }
2357
2358 for (j = 0; j < NUM_CHANNELS; j++) {
2359 if (mask & (1 << j)) {
2360 for (i = first; i <= last; i++) {
2361 eval(mach, i, j);
2362 }
2363 }
2364 }
2365 }
2366 }
2367 }
2368
2369 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2370 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2371 }
2372 }
2373
2374
2375 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2376
2377 static void
2378 exec_vector(struct tgsi_exec_machine *mach,
2379 const struct tgsi_full_instruction *inst,
2380 micro_op op,
2381 enum tgsi_exec_datatype dst_datatype)
2382 {
2383 unsigned int chan;
2384
2385 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2386 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2387 union tgsi_exec_channel dst;
2388
2389 op(&dst);
2390 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2391 }
2392 }
2393 }
2394
2395 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2396 const union tgsi_exec_channel *src);
2397
2398 static void
2399 exec_scalar_unary(struct tgsi_exec_machine *mach,
2400 const struct tgsi_full_instruction *inst,
2401 micro_unary_op op,
2402 enum tgsi_exec_datatype dst_datatype,
2403 enum tgsi_exec_datatype src_datatype)
2404 {
2405 unsigned int chan;
2406 union tgsi_exec_channel src;
2407 union tgsi_exec_channel dst;
2408
2409 fetch_source(mach, &src, &inst->Src[0], CHAN_X, src_datatype);
2410 op(&dst, &src);
2411 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2412 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2413 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2414 }
2415 }
2416 }
2417
2418 static void
2419 exec_vector_unary(struct tgsi_exec_machine *mach,
2420 const struct tgsi_full_instruction *inst,
2421 micro_unary_op op,
2422 enum tgsi_exec_datatype dst_datatype,
2423 enum tgsi_exec_datatype src_datatype)
2424 {
2425 unsigned int chan;
2426 struct tgsi_exec_vector dst;
2427
2428 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2429 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2430 union tgsi_exec_channel src;
2431
2432 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2433 op(&dst.xyzw[chan], &src);
2434 }
2435 }
2436 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2437 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2438 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2439 }
2440 }
2441 }
2442
2443 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2444 const union tgsi_exec_channel *src0,
2445 const union tgsi_exec_channel *src1);
2446
2447 static void
2448 exec_scalar_binary(struct tgsi_exec_machine *mach,
2449 const struct tgsi_full_instruction *inst,
2450 micro_binary_op op,
2451 enum tgsi_exec_datatype dst_datatype,
2452 enum tgsi_exec_datatype src_datatype)
2453 {
2454 unsigned int chan;
2455 union tgsi_exec_channel src[2];
2456 union tgsi_exec_channel dst;
2457
2458 fetch_source(mach, &src[0], &inst->Src[0], CHAN_X, src_datatype);
2459 fetch_source(mach, &src[1], &inst->Src[1], CHAN_Y, src_datatype);
2460 op(&dst, &src[0], &src[1]);
2461 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2462 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2463 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2464 }
2465 }
2466 }
2467
2468 static void
2469 exec_vector_binary(struct tgsi_exec_machine *mach,
2470 const struct tgsi_full_instruction *inst,
2471 micro_binary_op op,
2472 enum tgsi_exec_datatype dst_datatype,
2473 enum tgsi_exec_datatype src_datatype)
2474 {
2475 unsigned int chan;
2476 struct tgsi_exec_vector dst;
2477
2478 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2479 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2480 union tgsi_exec_channel src[2];
2481
2482 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2483 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2484 op(&dst.xyzw[chan], &src[0], &src[1]);
2485 }
2486 }
2487 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2488 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2489 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2490 }
2491 }
2492 }
2493
2494 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2495 const union tgsi_exec_channel *src0,
2496 const union tgsi_exec_channel *src1,
2497 const union tgsi_exec_channel *src2);
2498
2499 static void
2500 exec_vector_trinary(struct tgsi_exec_machine *mach,
2501 const struct tgsi_full_instruction *inst,
2502 micro_trinary_op op,
2503 enum tgsi_exec_datatype dst_datatype,
2504 enum tgsi_exec_datatype src_datatype)
2505 {
2506 unsigned int chan;
2507 struct tgsi_exec_vector dst;
2508
2509 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2510 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2511 union tgsi_exec_channel src[3];
2512
2513 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2514 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2515 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2516 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2517 }
2518 }
2519 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2520 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2521 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2522 }
2523 }
2524 }
2525
2526 static void
2527 exec_dp3(struct tgsi_exec_machine *mach,
2528 const struct tgsi_full_instruction *inst)
2529 {
2530 unsigned int chan;
2531 union tgsi_exec_channel arg[3];
2532
2533 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2534 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2535 micro_mul(&arg[2], &arg[0], &arg[1]);
2536
2537 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2538 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2539 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2540 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2541 }
2542
2543 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2544 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2545 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2546 }
2547 }
2548 }
2549
2550 static void
2551 exec_dp4(struct tgsi_exec_machine *mach,
2552 const struct tgsi_full_instruction *inst)
2553 {
2554 unsigned int chan;
2555 union tgsi_exec_channel arg[3];
2556
2557 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2558 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2559 micro_mul(&arg[2], &arg[0], &arg[1]);
2560
2561 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2562 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2563 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2564 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2565 }
2566
2567 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2568 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2569 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2570 }
2571 }
2572 }
2573
2574 static void
2575 exec_dp2a(struct tgsi_exec_machine *mach,
2576 const struct tgsi_full_instruction *inst)
2577 {
2578 unsigned int chan;
2579 union tgsi_exec_channel arg[3];
2580
2581 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2582 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2583 micro_mul(&arg[2], &arg[0], &arg[1]);
2584
2585 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2586 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2587 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2588
2589 fetch_source(mach, &arg[1], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2590 micro_add(&arg[0], &arg[0], &arg[1]);
2591
2592 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2593 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2594 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2595 }
2596 }
2597 }
2598
2599 static void
2600 exec_dph(struct tgsi_exec_machine *mach,
2601 const struct tgsi_full_instruction *inst)
2602 {
2603 unsigned int chan;
2604 union tgsi_exec_channel arg[3];
2605
2606 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2607 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2608 micro_mul(&arg[2], &arg[0], &arg[1]);
2609
2610 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2611 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2612 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2613
2614 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2615 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2616 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2617
2618 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2619 micro_add(&arg[0], &arg[0], &arg[1]);
2620
2621 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2622 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2623 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2624 }
2625 }
2626 }
2627
2628 static void
2629 exec_dp2(struct tgsi_exec_machine *mach,
2630 const struct tgsi_full_instruction *inst)
2631 {
2632 unsigned int chan;
2633 union tgsi_exec_channel arg[3];
2634
2635 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2636 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2637 micro_mul(&arg[2], &arg[0], &arg[1]);
2638
2639 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2640 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2641 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2642
2643 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2644 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2645 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2646 }
2647 }
2648 }
2649
2650 static void
2651 exec_nrm4(struct tgsi_exec_machine *mach,
2652 const struct tgsi_full_instruction *inst)
2653 {
2654 unsigned int chan;
2655 union tgsi_exec_channel arg[4];
2656 union tgsi_exec_channel scale;
2657
2658 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2659 micro_mul(&scale, &arg[0], &arg[0]);
2660
2661 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2662 union tgsi_exec_channel product;
2663
2664 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2665 micro_mul(&product, &arg[chan], &arg[chan]);
2666 micro_add(&scale, &scale, &product);
2667 }
2668
2669 micro_rsq(&scale, &scale);
2670
2671 for (chan = CHAN_X; chan <= CHAN_W; chan++) {
2672 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2673 micro_mul(&arg[chan], &arg[chan], &scale);
2674 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2675 }
2676 }
2677 }
2678
2679 static void
2680 exec_nrm3(struct tgsi_exec_machine *mach,
2681 const struct tgsi_full_instruction *inst)
2682 {
2683 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2684 unsigned int chan;
2685 union tgsi_exec_channel arg[3];
2686 union tgsi_exec_channel scale;
2687
2688 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2689 micro_mul(&scale, &arg[0], &arg[0]);
2690
2691 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2692 union tgsi_exec_channel product;
2693
2694 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2695 micro_mul(&product, &arg[chan], &arg[chan]);
2696 micro_add(&scale, &scale, &product);
2697 }
2698
2699 micro_rsq(&scale, &scale);
2700
2701 for (chan = CHAN_X; chan <= CHAN_Z; chan++) {
2702 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2703 micro_mul(&arg[chan], &arg[chan], &scale);
2704 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2705 }
2706 }
2707 }
2708
2709 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2710 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2711 }
2712 }
2713
2714 static void
2715 exec_scs(struct tgsi_exec_machine *mach,
2716 const struct tgsi_full_instruction *inst)
2717 {
2718 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2719 union tgsi_exec_channel arg;
2720 union tgsi_exec_channel result;
2721
2722 fetch_source(mach, &arg, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2723
2724 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2725 micro_cos(&result, &arg);
2726 store_dest(mach, &result, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2727 }
2728 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2729 micro_sin(&result, &arg);
2730 store_dest(mach, &result, &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2731 }
2732 }
2733 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2734 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2735 }
2736 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2737 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2738 }
2739 }
2740
2741 static void
2742 exec_x2d(struct tgsi_exec_machine *mach,
2743 const struct tgsi_full_instruction *inst)
2744 {
2745 union tgsi_exec_channel r[4];
2746 union tgsi_exec_channel d[2];
2747
2748 fetch_source(mach, &r[0], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2749 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2750 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2751 fetch_source(mach, &r[2], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2752 micro_mul(&r[2], &r[2], &r[0]);
2753 fetch_source(mach, &r[3], &inst->Src[2], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2754 micro_mul(&r[3], &r[3], &r[1]);
2755 micro_add(&r[2], &r[2], &r[3]);
2756 fetch_source(mach, &r[3], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2757 micro_add(&d[0], &r[2], &r[3]);
2758 }
2759 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2760 fetch_source(mach, &r[2], &inst->Src[2], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2761 micro_mul(&r[2], &r[2], &r[0]);
2762 fetch_source(mach, &r[3], &inst->Src[2], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2763 micro_mul(&r[3], &r[3], &r[1]);
2764 micro_add(&r[2], &r[2], &r[3]);
2765 fetch_source(mach, &r[3], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2766 micro_add(&d[1], &r[2], &r[3]);
2767 }
2768 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2769 store_dest(mach, &d[0], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2770 }
2771 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2772 store_dest(mach, &d[1], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2773 }
2774 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2775 store_dest(mach, &d[0], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2776 }
2777 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2778 store_dest(mach, &d[1], &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2779 }
2780 }
2781
2782 static void
2783 exec_rfl(struct tgsi_exec_machine *mach,
2784 const struct tgsi_full_instruction *inst)
2785 {
2786 union tgsi_exec_channel r[9];
2787
2788 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2789 /* r0 = dp3(src0, src0) */
2790 fetch_source(mach, &r[2], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2791 micro_mul(&r[0], &r[2], &r[2]);
2792 fetch_source(mach, &r[4], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2793 micro_mul(&r[8], &r[4], &r[4]);
2794 micro_add(&r[0], &r[0], &r[8]);
2795 fetch_source(mach, &r[6], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2796 micro_mul(&r[8], &r[6], &r[6]);
2797 micro_add(&r[0], &r[0], &r[8]);
2798
2799 /* r1 = dp3(src0, src1) */
2800 fetch_source(mach, &r[3], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2801 micro_mul(&r[1], &r[2], &r[3]);
2802 fetch_source(mach, &r[5], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2803 micro_mul(&r[8], &r[4], &r[5]);
2804 micro_add(&r[1], &r[1], &r[8]);
2805 fetch_source(mach, &r[7], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2806 micro_mul(&r[8], &r[6], &r[7]);
2807 micro_add(&r[1], &r[1], &r[8]);
2808
2809 /* r1 = 2 * r1 / r0 */
2810 micro_add(&r[1], &r[1], &r[1]);
2811 micro_div(&r[1], &r[1], &r[0]);
2812
2813 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2814 micro_mul(&r[2], &r[2], &r[1]);
2815 micro_sub(&r[2], &r[2], &r[3]);
2816 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2817 }
2818 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2819 micro_mul(&r[4], &r[4], &r[1]);
2820 micro_sub(&r[4], &r[4], &r[5]);
2821 store_dest(mach, &r[4], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2822 }
2823 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2824 micro_mul(&r[6], &r[6], &r[1]);
2825 micro_sub(&r[6], &r[6], &r[7]);
2826 store_dest(mach, &r[6], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2827 }
2828 }
2829 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2830 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2831 }
2832 }
2833
2834 static void
2835 exec_xpd(struct tgsi_exec_machine *mach,
2836 const struct tgsi_full_instruction *inst)
2837 {
2838 union tgsi_exec_channel r[6];
2839 union tgsi_exec_channel d[3];
2840
2841 fetch_source(mach, &r[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2842 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2843
2844 micro_mul(&r[2], &r[0], &r[1]);
2845
2846 fetch_source(mach, &r[3], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2847 fetch_source(mach, &r[4], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2848
2849 micro_mul(&r[5], &r[3], &r[4] );
2850 micro_sub(&d[CHAN_X], &r[2], &r[5]);
2851
2852 fetch_source(mach, &r[2], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2853
2854 micro_mul(&r[3], &r[3], &r[2]);
2855
2856 fetch_source(mach, &r[5], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2857
2858 micro_mul(&r[1], &r[1], &r[5]);
2859 micro_sub(&d[CHAN_Y], &r[3], &r[1]);
2860
2861 micro_mul(&r[5], &r[5], &r[4]);
2862 micro_mul(&r[0], &r[0], &r[2]);
2863 micro_sub(&d[CHAN_Z], &r[5], &r[0]);
2864
2865 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2866 store_dest(mach, &d[CHAN_X], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2867 }
2868 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2869 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2870 }
2871 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2872 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2873 }
2874 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2875 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2876 }
2877 }
2878
2879 static void
2880 exec_dst(struct tgsi_exec_machine *mach,
2881 const struct tgsi_full_instruction *inst)
2882 {
2883 union tgsi_exec_channel r[2];
2884 union tgsi_exec_channel d[4];
2885
2886 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2887 fetch_source(mach, &r[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2888 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2889 micro_mul(&d[CHAN_Y], &r[0], &r[1]);
2890 }
2891 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2892 fetch_source(mach, &d[CHAN_Z], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2893 }
2894 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2895 fetch_source(mach, &d[CHAN_W], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2896 }
2897
2898 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2899 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2900 }
2901 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2902 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2903 }
2904 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2905 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2906 }
2907 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2908 store_dest(mach, &d[CHAN_W], &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2909 }
2910 }
2911
2912 static void
2913 exec_log(struct tgsi_exec_machine *mach,
2914 const struct tgsi_full_instruction *inst)
2915 {
2916 union tgsi_exec_channel r[3];
2917
2918 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2919 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
2920 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
2921 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
2922 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2923 store_dest(mach, &r[0], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2924 }
2925 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2926 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
2927 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
2928 store_dest(mach, &r[0], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2929 }
2930 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2931 store_dest(mach, &r[1], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2932 }
2933 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2934 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2935 }
2936 }
2937
2938 static void
2939 exec_exp(struct tgsi_exec_machine *mach,
2940 const struct tgsi_full_instruction *inst)
2941 {
2942 union tgsi_exec_channel r[3];
2943
2944 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2945 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
2946 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2947 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
2948 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2949 }
2950 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2951 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
2952 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2953 }
2954 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2955 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
2956 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2957 }
2958 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2959 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2960 }
2961 }
2962
2963 static void
2964 exec_lit(struct tgsi_exec_machine *mach,
2965 const struct tgsi_full_instruction *inst)
2966 {
2967 union tgsi_exec_channel r[3];
2968 union tgsi_exec_channel d[3];
2969
2970 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2971 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2972 }
2973 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
2974 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2975 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2976 micro_max(&d[CHAN_Y], &r[0], &ZeroVec);
2977 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2978 }
2979
2980 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2981 fetch_source(mach, &r[1], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2982 micro_max(&r[1], &r[1], &ZeroVec);
2983
2984 fetch_source(mach, &r[2], &inst->Src[0], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2985 micro_min(&r[2], &r[2], &P128Vec);
2986 micro_max(&r[2], &r[2], &M128Vec);
2987 micro_pow(&r[1], &r[1], &r[2]);
2988 micro_lt(&d[CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
2989 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2990 }
2991 }
2992 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2993 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2994 }
2995 }
2996
2997 static void
2998 exec_break(struct tgsi_exec_machine *mach)
2999 {
3000 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3001 /* turn off loop channels for each enabled exec channel */
3002 mach->LoopMask &= ~mach->ExecMask;
3003 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3004 UPDATE_EXEC_MASK(mach);
3005 } else {
3006 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3007
3008 mach->Switch.mask = 0x0;
3009
3010 UPDATE_EXEC_MASK(mach);
3011 }
3012 }
3013
3014 static void
3015 exec_switch(struct tgsi_exec_machine *mach,
3016 const struct tgsi_full_instruction *inst)
3017 {
3018 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3019 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3020
3021 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3022 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
3023 mach->Switch.mask = 0x0;
3024 mach->Switch.defaultMask = 0x0;
3025
3026 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3027 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3028
3029 UPDATE_EXEC_MASK(mach);
3030 }
3031
3032 static void
3033 exec_case(struct tgsi_exec_machine *mach,
3034 const struct tgsi_full_instruction *inst)
3035 {
3036 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3037 union tgsi_exec_channel src;
3038 uint mask = 0;
3039
3040 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
3041
3042 if (mach->Switch.selector.u[0] == src.u[0]) {
3043 mask |= 0x1;
3044 }
3045 if (mach->Switch.selector.u[1] == src.u[1]) {
3046 mask |= 0x2;
3047 }
3048 if (mach->Switch.selector.u[2] == src.u[2]) {
3049 mask |= 0x4;
3050 }
3051 if (mach->Switch.selector.u[3] == src.u[3]) {
3052 mask |= 0x8;
3053 }
3054
3055 mach->Switch.defaultMask |= mask;
3056
3057 mach->Switch.mask |= mask & prevMask;
3058
3059 UPDATE_EXEC_MASK(mach);
3060 }
3061
3062 static void
3063 exec_default(struct tgsi_exec_machine *mach)
3064 {
3065 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3066
3067 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3068
3069 UPDATE_EXEC_MASK(mach);
3070 }
3071
3072 static void
3073 exec_endswitch(struct tgsi_exec_machine *mach)
3074 {
3075 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3076 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3077
3078 UPDATE_EXEC_MASK(mach);
3079 }
3080
3081 static void
3082 micro_i2f(union tgsi_exec_channel *dst,
3083 const union tgsi_exec_channel *src)
3084 {
3085 dst->f[0] = (float)src->i[0];
3086 dst->f[1] = (float)src->i[1];
3087 dst->f[2] = (float)src->i[2];
3088 dst->f[3] = (float)src->i[3];
3089 }
3090
3091 static void
3092 micro_not(union tgsi_exec_channel *dst,
3093 const union tgsi_exec_channel *src)
3094 {
3095 dst->u[0] = ~src->u[0];
3096 dst->u[1] = ~src->u[1];
3097 dst->u[2] = ~src->u[2];
3098 dst->u[3] = ~src->u[3];
3099 }
3100
3101 static void
3102 micro_shl(union tgsi_exec_channel *dst,
3103 const union tgsi_exec_channel *src0,
3104 const union tgsi_exec_channel *src1)
3105 {
3106 dst->u[0] = src0->u[0] << src1->u[0];
3107 dst->u[1] = src0->u[1] << src1->u[1];
3108 dst->u[2] = src0->u[2] << src1->u[2];
3109 dst->u[3] = src0->u[3] << src1->u[3];
3110 }
3111
3112 static void
3113 micro_and(union tgsi_exec_channel *dst,
3114 const union tgsi_exec_channel *src0,
3115 const union tgsi_exec_channel *src1)
3116 {
3117 dst->u[0] = src0->u[0] & src1->u[0];
3118 dst->u[1] = src0->u[1] & src1->u[1];
3119 dst->u[2] = src0->u[2] & src1->u[2];
3120 dst->u[3] = src0->u[3] & src1->u[3];
3121 }
3122
3123 static void
3124 micro_or(union tgsi_exec_channel *dst,
3125 const union tgsi_exec_channel *src0,
3126 const union tgsi_exec_channel *src1)
3127 {
3128 dst->u[0] = src0->u[0] | src1->u[0];
3129 dst->u[1] = src0->u[1] | src1->u[1];
3130 dst->u[2] = src0->u[2] | src1->u[2];
3131 dst->u[3] = src0->u[3] | src1->u[3];
3132 }
3133
3134 static void
3135 micro_xor(union tgsi_exec_channel *dst,
3136 const union tgsi_exec_channel *src0,
3137 const union tgsi_exec_channel *src1)
3138 {
3139 dst->u[0] = src0->u[0] ^ src1->u[0];
3140 dst->u[1] = src0->u[1] ^ src1->u[1];
3141 dst->u[2] = src0->u[2] ^ src1->u[2];
3142 dst->u[3] = src0->u[3] ^ src1->u[3];
3143 }
3144
3145 static void
3146 micro_mod(union tgsi_exec_channel *dst,
3147 const union tgsi_exec_channel *src0,
3148 const union tgsi_exec_channel *src1)
3149 {
3150 dst->i[0] = src0->i[0] % src1->i[0];
3151 dst->i[1] = src0->i[1] % src1->i[1];
3152 dst->i[2] = src0->i[2] % src1->i[2];
3153 dst->i[3] = src0->i[3] % src1->i[3];
3154 }
3155
3156 static void
3157 micro_f2i(union tgsi_exec_channel *dst,
3158 const union tgsi_exec_channel *src)
3159 {
3160 dst->i[0] = (int)src->f[0];
3161 dst->i[1] = (int)src->f[1];
3162 dst->i[2] = (int)src->f[2];
3163 dst->i[3] = (int)src->f[3];
3164 }
3165
3166 static void
3167 micro_idiv(union tgsi_exec_channel *dst,
3168 const union tgsi_exec_channel *src0,
3169 const union tgsi_exec_channel *src1)
3170 {
3171 dst->i[0] = src0->i[0] / src1->i[0];
3172 dst->i[1] = src0->i[1] / src1->i[1];
3173 dst->i[2] = src0->i[2] / src1->i[2];
3174 dst->i[3] = src0->i[3] / src1->i[3];
3175 }
3176
3177 static void
3178 micro_imax(union tgsi_exec_channel *dst,
3179 const union tgsi_exec_channel *src0,
3180 const union tgsi_exec_channel *src1)
3181 {
3182 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3183 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3184 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3185 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3186 }
3187
3188 static void
3189 micro_imin(union tgsi_exec_channel *dst,
3190 const union tgsi_exec_channel *src0,
3191 const union tgsi_exec_channel *src1)
3192 {
3193 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3194 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3195 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3196 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3197 }
3198
3199 static void
3200 micro_isge(union tgsi_exec_channel *dst,
3201 const union tgsi_exec_channel *src0,
3202 const union tgsi_exec_channel *src1)
3203 {
3204 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3205 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3206 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3207 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3208 }
3209
3210 static void
3211 micro_ishr(union tgsi_exec_channel *dst,
3212 const union tgsi_exec_channel *src0,
3213 const union tgsi_exec_channel *src1)
3214 {
3215 dst->i[0] = src0->i[0] >> src1->i[0];
3216 dst->i[1] = src0->i[1] >> src1->i[1];
3217 dst->i[2] = src0->i[2] >> src1->i[2];
3218 dst->i[3] = src0->i[3] >> src1->i[3];
3219 }
3220
3221 static void
3222 micro_islt(union tgsi_exec_channel *dst,
3223 const union tgsi_exec_channel *src0,
3224 const union tgsi_exec_channel *src1)
3225 {
3226 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3227 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3228 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3229 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3230 }
3231
3232 static void
3233 micro_f2u(union tgsi_exec_channel *dst,
3234 const union tgsi_exec_channel *src)
3235 {
3236 dst->u[0] = (uint)src->f[0];
3237 dst->u[1] = (uint)src->f[1];
3238 dst->u[2] = (uint)src->f[2];
3239 dst->u[3] = (uint)src->f[3];
3240 }
3241
3242 static void
3243 micro_u2f(union tgsi_exec_channel *dst,
3244 const union tgsi_exec_channel *src)
3245 {
3246 dst->f[0] = (float)src->u[0];
3247 dst->f[1] = (float)src->u[1];
3248 dst->f[2] = (float)src->u[2];
3249 dst->f[3] = (float)src->u[3];
3250 }
3251
3252 static void
3253 micro_uadd(union tgsi_exec_channel *dst,
3254 const union tgsi_exec_channel *src0,
3255 const union tgsi_exec_channel *src1)
3256 {
3257 dst->u[0] = src0->u[0] + src1->u[0];
3258 dst->u[1] = src0->u[1] + src1->u[1];
3259 dst->u[2] = src0->u[2] + src1->u[2];
3260 dst->u[3] = src0->u[3] + src1->u[3];
3261 }
3262
3263 static void
3264 micro_udiv(union tgsi_exec_channel *dst,
3265 const union tgsi_exec_channel *src0,
3266 const union tgsi_exec_channel *src1)
3267 {
3268 dst->u[0] = src0->u[0] / src1->u[0];
3269 dst->u[1] = src0->u[1] / src1->u[1];
3270 dst->u[2] = src0->u[2] / src1->u[2];
3271 dst->u[3] = src0->u[3] / src1->u[3];
3272 }
3273
3274 static void
3275 micro_umad(union tgsi_exec_channel *dst,
3276 const union tgsi_exec_channel *src0,
3277 const union tgsi_exec_channel *src1,
3278 const union tgsi_exec_channel *src2)
3279 {
3280 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3281 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3282 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3283 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3284 }
3285
3286 static void
3287 micro_umax(union tgsi_exec_channel *dst,
3288 const union tgsi_exec_channel *src0,
3289 const union tgsi_exec_channel *src1)
3290 {
3291 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3292 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3293 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3294 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3295 }
3296
3297 static void
3298 micro_umin(union tgsi_exec_channel *dst,
3299 const union tgsi_exec_channel *src0,
3300 const union tgsi_exec_channel *src1)
3301 {
3302 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3303 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3304 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3305 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3306 }
3307
3308 static void
3309 micro_umod(union tgsi_exec_channel *dst,
3310 const union tgsi_exec_channel *src0,
3311 const union tgsi_exec_channel *src1)
3312 {
3313 dst->u[0] = src0->u[0] % src1->u[0];
3314 dst->u[1] = src0->u[1] % src1->u[1];
3315 dst->u[2] = src0->u[2] % src1->u[2];
3316 dst->u[3] = src0->u[3] % src1->u[3];
3317 }
3318
3319 static void
3320 micro_umul(union tgsi_exec_channel *dst,
3321 const union tgsi_exec_channel *src0,
3322 const union tgsi_exec_channel *src1)
3323 {
3324 dst->u[0] = src0->u[0] * src1->u[0];
3325 dst->u[1] = src0->u[1] * src1->u[1];
3326 dst->u[2] = src0->u[2] * src1->u[2];
3327 dst->u[3] = src0->u[3] * src1->u[3];
3328 }
3329
3330 static void
3331 micro_useq(union tgsi_exec_channel *dst,
3332 const union tgsi_exec_channel *src0,
3333 const union tgsi_exec_channel *src1)
3334 {
3335 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3336 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3337 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3338 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3339 }
3340
3341 static void
3342 micro_usge(union tgsi_exec_channel *dst,
3343 const union tgsi_exec_channel *src0,
3344 const union tgsi_exec_channel *src1)
3345 {
3346 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3347 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3348 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3349 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3350 }
3351
3352 static void
3353 micro_ushr(union tgsi_exec_channel *dst,
3354 const union tgsi_exec_channel *src0,
3355 const union tgsi_exec_channel *src1)
3356 {
3357 dst->u[0] = src0->u[0] >> src1->u[0];
3358 dst->u[1] = src0->u[1] >> src1->u[1];
3359 dst->u[2] = src0->u[2] >> src1->u[2];
3360 dst->u[3] = src0->u[3] >> src1->u[3];
3361 }
3362
3363 static void
3364 micro_uslt(union tgsi_exec_channel *dst,
3365 const union tgsi_exec_channel *src0,
3366 const union tgsi_exec_channel *src1)
3367 {
3368 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3369 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3370 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3371 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3372 }
3373
3374 static void
3375 micro_usne(union tgsi_exec_channel *dst,
3376 const union tgsi_exec_channel *src0,
3377 const union tgsi_exec_channel *src1)
3378 {
3379 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3380 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3381 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3382 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3383 }
3384
3385 static void
3386 micro_uarl(union tgsi_exec_channel *dst,
3387 const union tgsi_exec_channel *src)
3388 {
3389 dst->i[0] = src->u[0];
3390 dst->i[1] = src->u[1];
3391 dst->i[2] = src->u[2];
3392 dst->i[3] = src->u[3];
3393 }
3394
3395 static void
3396 micro_ucmp(union tgsi_exec_channel *dst,
3397 const union tgsi_exec_channel *src0,
3398 const union tgsi_exec_channel *src1,
3399 const union tgsi_exec_channel *src2)
3400 {
3401 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3402 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3403 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3404 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3405 }
3406
3407 static void
3408 exec_instruction(
3409 struct tgsi_exec_machine *mach,
3410 const struct tgsi_full_instruction *inst,
3411 int *pc )
3412 {
3413 union tgsi_exec_channel r[10];
3414
3415 (*pc)++;
3416
3417 switch (inst->Instruction.Opcode) {
3418 case TGSI_OPCODE_ARL:
3419 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3420 break;
3421
3422 case TGSI_OPCODE_MOV:
3423 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3424 break;
3425
3426 case TGSI_OPCODE_LIT:
3427 exec_lit(mach, inst);
3428 break;
3429
3430 case TGSI_OPCODE_RCP:
3431 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3432 break;
3433
3434 case TGSI_OPCODE_RSQ:
3435 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3436 break;
3437
3438 case TGSI_OPCODE_EXP:
3439 exec_exp(mach, inst);
3440 break;
3441
3442 case TGSI_OPCODE_LOG:
3443 exec_log(mach, inst);
3444 break;
3445
3446 case TGSI_OPCODE_MUL:
3447 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3448 break;
3449
3450 case TGSI_OPCODE_ADD:
3451 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3452 break;
3453
3454 case TGSI_OPCODE_DP3:
3455 exec_dp3(mach, inst);
3456 break;
3457
3458 case TGSI_OPCODE_DP4:
3459 exec_dp4(mach, inst);
3460 break;
3461
3462 case TGSI_OPCODE_DST:
3463 exec_dst(mach, inst);
3464 break;
3465
3466 case TGSI_OPCODE_MIN:
3467 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3468 break;
3469
3470 case TGSI_OPCODE_MAX:
3471 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3472 break;
3473
3474 case TGSI_OPCODE_SLT:
3475 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3476 break;
3477
3478 case TGSI_OPCODE_SGE:
3479 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3480 break;
3481
3482 case TGSI_OPCODE_MAD:
3483 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3484 break;
3485
3486 case TGSI_OPCODE_SUB:
3487 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3488 break;
3489
3490 case TGSI_OPCODE_LRP:
3491 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3492 break;
3493
3494 case TGSI_OPCODE_CND:
3495 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3496 break;
3497
3498 case TGSI_OPCODE_DP2A:
3499 exec_dp2a(mach, inst);
3500 break;
3501
3502 case TGSI_OPCODE_FRC:
3503 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3504 break;
3505
3506 case TGSI_OPCODE_CLAMP:
3507 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3508 break;
3509
3510 case TGSI_OPCODE_FLR:
3511 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3512 break;
3513
3514 case TGSI_OPCODE_ROUND:
3515 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3516 break;
3517
3518 case TGSI_OPCODE_EX2:
3519 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3520 break;
3521
3522 case TGSI_OPCODE_LG2:
3523 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3524 break;
3525
3526 case TGSI_OPCODE_POW:
3527 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3528 break;
3529
3530 case TGSI_OPCODE_XPD:
3531 exec_xpd(mach, inst);
3532 break;
3533
3534 case TGSI_OPCODE_ABS:
3535 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3536 break;
3537
3538 case TGSI_OPCODE_RCC:
3539 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3540 break;
3541
3542 case TGSI_OPCODE_DPH:
3543 exec_dph(mach, inst);
3544 break;
3545
3546 case TGSI_OPCODE_COS:
3547 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3548 break;
3549
3550 case TGSI_OPCODE_DDX:
3551 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3552 break;
3553
3554 case TGSI_OPCODE_DDY:
3555 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3556 break;
3557
3558 case TGSI_OPCODE_KILP:
3559 exec_kilp (mach, inst);
3560 break;
3561
3562 case TGSI_OPCODE_KIL:
3563 exec_kil (mach, inst);
3564 break;
3565
3566 case TGSI_OPCODE_PK2H:
3567 assert (0);
3568 break;
3569
3570 case TGSI_OPCODE_PK2US:
3571 assert (0);
3572 break;
3573
3574 case TGSI_OPCODE_PK4B:
3575 assert (0);
3576 break;
3577
3578 case TGSI_OPCODE_PK4UB:
3579 assert (0);
3580 break;
3581
3582 case TGSI_OPCODE_RFL:
3583 exec_rfl(mach, inst);
3584 break;
3585
3586 case TGSI_OPCODE_SEQ:
3587 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3588 break;
3589
3590 case TGSI_OPCODE_SFL:
3591 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3592 break;
3593
3594 case TGSI_OPCODE_SGT:
3595 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3596 break;
3597
3598 case TGSI_OPCODE_SIN:
3599 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3600 break;
3601
3602 case TGSI_OPCODE_SLE:
3603 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3604 break;
3605
3606 case TGSI_OPCODE_SNE:
3607 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3608 break;
3609
3610 case TGSI_OPCODE_STR:
3611 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3612 break;
3613
3614 case TGSI_OPCODE_TEX:
3615 /* simple texture lookup */
3616 /* src[0] = texcoord */
3617 /* src[1] = sampler unit */
3618 exec_tex(mach, inst, TEX_MODIFIER_NONE);
3619 break;
3620
3621 case TGSI_OPCODE_TXB:
3622 /* Texture lookup with lod bias */
3623 /* src[0] = texcoord (src[0].w = LOD bias) */
3624 /* src[1] = sampler unit */
3625 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS);
3626 break;
3627
3628 case TGSI_OPCODE_TXD:
3629 /* Texture lookup with explict partial derivatives */
3630 /* src[0] = texcoord */
3631 /* src[1] = d[strq]/dx */
3632 /* src[2] = d[strq]/dy */
3633 /* src[3] = sampler unit */
3634 exec_txd(mach, inst);
3635 break;
3636
3637 case TGSI_OPCODE_TXL:
3638 /* Texture lookup with explit LOD */
3639 /* src[0] = texcoord (src[0].w = LOD) */
3640 /* src[1] = sampler unit */
3641 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
3642 break;
3643
3644 case TGSI_OPCODE_TXP:
3645 /* Texture lookup with projection */
3646 /* src[0] = texcoord (src[0].w = projection) */
3647 /* src[1] = sampler unit */
3648 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED);
3649 break;
3650
3651 case TGSI_OPCODE_UP2H:
3652 assert (0);
3653 break;
3654
3655 case TGSI_OPCODE_UP2US:
3656 assert (0);
3657 break;
3658
3659 case TGSI_OPCODE_UP4B:
3660 assert (0);
3661 break;
3662
3663 case TGSI_OPCODE_UP4UB:
3664 assert (0);
3665 break;
3666
3667 case TGSI_OPCODE_X2D:
3668 exec_x2d(mach, inst);
3669 break;
3670
3671 case TGSI_OPCODE_ARA:
3672 assert (0);
3673 break;
3674
3675 case TGSI_OPCODE_ARR:
3676 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3677 break;
3678
3679 case TGSI_OPCODE_BRA:
3680 assert (0);
3681 break;
3682
3683 case TGSI_OPCODE_CAL:
3684 /* skip the call if no execution channels are enabled */
3685 if (mach->ExecMask) {
3686 /* do the call */
3687
3688 /* First, record the depths of the execution stacks.
3689 * This is important for deeply nested/looped return statements.
3690 * We have to unwind the stacks by the correct amount. For a
3691 * real code generator, we could determine the number of entries
3692 * to pop off each stack with simple static analysis and avoid
3693 * implementing this data structure at run time.
3694 */
3695 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3696 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3697 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3698 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3699 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3700 /* note that PC was already incremented above */
3701 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3702
3703 mach->CallStackTop++;
3704
3705 /* Second, push the Cond, Loop, Cont, Func stacks */
3706 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3707 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3708 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3709 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3710 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3711 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3712
3713 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3714 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3715 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3716 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3717 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3718 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3719
3720 /* Finally, jump to the subroutine */
3721 *pc = inst->Label.Label;
3722 }
3723 break;
3724
3725 case TGSI_OPCODE_RET:
3726 mach->FuncMask &= ~mach->ExecMask;
3727 UPDATE_EXEC_MASK(mach);
3728
3729 if (mach->FuncMask == 0x0) {
3730 /* really return now (otherwise, keep executing */
3731
3732 if (mach->CallStackTop == 0) {
3733 /* returning from main() */
3734 mach->CondStackTop = 0;
3735 mach->LoopStackTop = 0;
3736 *pc = -1;
3737 return;
3738 }
3739
3740 assert(mach->CallStackTop > 0);
3741 mach->CallStackTop--;
3742
3743 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3744 mach->CondMask = mach->CondStack[mach->CondStackTop];
3745
3746 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3747 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3748
3749 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3750 mach->ContMask = mach->ContStack[mach->ContStackTop];
3751
3752 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3753 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3754
3755 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3756 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3757
3758 assert(mach->FuncStackTop > 0);
3759 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3760
3761 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3762
3763 UPDATE_EXEC_MASK(mach);
3764 }
3765 break;
3766
3767 case TGSI_OPCODE_SSG:
3768 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3769 break;
3770
3771 case TGSI_OPCODE_CMP:
3772 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3773 break;
3774
3775 case TGSI_OPCODE_SCS:
3776 exec_scs(mach, inst);
3777 break;
3778
3779 case TGSI_OPCODE_NRM:
3780 exec_nrm3(mach, inst);
3781 break;
3782
3783 case TGSI_OPCODE_NRM4:
3784 exec_nrm4(mach, inst);
3785 break;
3786
3787 case TGSI_OPCODE_DIV:
3788 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3789 break;
3790
3791 case TGSI_OPCODE_DP2:
3792 exec_dp2(mach, inst);
3793 break;
3794
3795 case TGSI_OPCODE_IF:
3796 /* push CondMask */
3797 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3798 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3799 FETCH( &r[0], 0, CHAN_X );
3800 /* update CondMask */
3801 if( ! r[0].u[0] ) {
3802 mach->CondMask &= ~0x1;
3803 }
3804 if( ! r[0].u[1] ) {
3805 mach->CondMask &= ~0x2;
3806 }
3807 if( ! r[0].u[2] ) {
3808 mach->CondMask &= ~0x4;
3809 }
3810 if( ! r[0].u[3] ) {
3811 mach->CondMask &= ~0x8;
3812 }
3813 UPDATE_EXEC_MASK(mach);
3814 /* Todo: If CondMask==0, jump to ELSE */
3815 break;
3816
3817 case TGSI_OPCODE_ELSE:
3818 /* invert CondMask wrt previous mask */
3819 {
3820 uint prevMask;
3821 assert(mach->CondStackTop > 0);
3822 prevMask = mach->CondStack[mach->CondStackTop - 1];
3823 mach->CondMask = ~mach->CondMask & prevMask;
3824 UPDATE_EXEC_MASK(mach);
3825 /* Todo: If CondMask==0, jump to ENDIF */
3826 }
3827 break;
3828
3829 case TGSI_OPCODE_ENDIF:
3830 /* pop CondMask */
3831 assert(mach->CondStackTop > 0);
3832 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3833 UPDATE_EXEC_MASK(mach);
3834 break;
3835
3836 case TGSI_OPCODE_END:
3837 /* make sure we end primitives which haven't
3838 * been explicitly emitted */
3839 conditional_emit_primitive(mach);
3840 /* halt execution */
3841 *pc = -1;
3842 break;
3843
3844 case TGSI_OPCODE_PUSHA:
3845 assert (0);
3846 break;
3847
3848 case TGSI_OPCODE_POPA:
3849 assert (0);
3850 break;
3851
3852 case TGSI_OPCODE_CEIL:
3853 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3854 break;
3855
3856 case TGSI_OPCODE_I2F:
3857 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3858 break;
3859
3860 case TGSI_OPCODE_NOT:
3861 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3862 break;
3863
3864 case TGSI_OPCODE_TRUNC:
3865 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3866 break;
3867
3868 case TGSI_OPCODE_SHL:
3869 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3870 break;
3871
3872 case TGSI_OPCODE_AND:
3873 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3874 break;
3875
3876 case TGSI_OPCODE_OR:
3877 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3878 break;
3879
3880 case TGSI_OPCODE_MOD:
3881 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3882 break;
3883
3884 case TGSI_OPCODE_XOR:
3885 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3886 break;
3887
3888 case TGSI_OPCODE_SAD:
3889 assert (0);
3890 break;
3891
3892 case TGSI_OPCODE_TXF:
3893 exec_txf(mach, inst);
3894 break;
3895
3896 case TGSI_OPCODE_TXQ:
3897 exec_txq(mach, inst);
3898 break;
3899
3900 case TGSI_OPCODE_EMIT:
3901 emit_vertex(mach);
3902 break;
3903
3904 case TGSI_OPCODE_ENDPRIM:
3905 emit_primitive(mach);
3906 break;
3907
3908 case TGSI_OPCODE_BGNLOOP:
3909 /* push LoopMask and ContMasks */
3910 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3911 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3912 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3913 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3914
3915 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3916 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3917 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3918 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3919 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3920 break;
3921
3922 case TGSI_OPCODE_ENDLOOP:
3923 /* Restore ContMask, but don't pop */
3924 assert(mach->ContStackTop > 0);
3925 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3926 UPDATE_EXEC_MASK(mach);
3927 if (mach->ExecMask) {
3928 /* repeat loop: jump to instruction just past BGNLOOP */
3929 assert(mach->LoopLabelStackTop > 0);
3930 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3931 }
3932 else {
3933 /* exit loop: pop LoopMask */
3934 assert(mach->LoopStackTop > 0);
3935 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3936 /* pop ContMask */
3937 assert(mach->ContStackTop > 0);
3938 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3939 assert(mach->LoopLabelStackTop > 0);
3940 --mach->LoopLabelStackTop;
3941
3942 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3943 }
3944 UPDATE_EXEC_MASK(mach);
3945 break;
3946
3947 case TGSI_OPCODE_BRK:
3948 exec_break(mach);
3949 break;
3950
3951 case TGSI_OPCODE_CONT:
3952 /* turn off cont channels for each enabled exec channel */
3953 mach->ContMask &= ~mach->ExecMask;
3954 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3955 UPDATE_EXEC_MASK(mach);
3956 break;
3957
3958 case TGSI_OPCODE_BGNSUB:
3959 /* no-op */
3960 break;
3961
3962 case TGSI_OPCODE_ENDSUB:
3963 /*
3964 * XXX: This really should be a no-op. We should never reach this opcode.
3965 */
3966
3967 assert(mach->CallStackTop > 0);
3968 mach->CallStackTop--;
3969
3970 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3971 mach->CondMask = mach->CondStack[mach->CondStackTop];
3972
3973 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3974 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3975
3976 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3977 mach->ContMask = mach->ContStack[mach->ContStackTop];
3978
3979 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3980 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3981
3982 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3983 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3984
3985 assert(mach->FuncStackTop > 0);
3986 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3987
3988 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3989
3990 UPDATE_EXEC_MASK(mach);
3991 break;
3992
3993 case TGSI_OPCODE_NOP:
3994 break;
3995
3996 case TGSI_OPCODE_BREAKC:
3997 FETCH(&r[0], 0, CHAN_X);
3998 /* update CondMask */
3999 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4000 mach->LoopMask &= ~0x1;
4001 }
4002 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4003 mach->LoopMask &= ~0x2;
4004 }
4005 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4006 mach->LoopMask &= ~0x4;
4007 }
4008 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4009 mach->LoopMask &= ~0x8;
4010 }
4011 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4012 UPDATE_EXEC_MASK(mach);
4013 break;
4014
4015 case TGSI_OPCODE_F2I:
4016 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4017 break;
4018
4019 case TGSI_OPCODE_IDIV:
4020 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4021 break;
4022
4023 case TGSI_OPCODE_IMAX:
4024 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4025 break;
4026
4027 case TGSI_OPCODE_IMIN:
4028 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4029 break;
4030
4031 case TGSI_OPCODE_INEG:
4032 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4033 break;
4034
4035 case TGSI_OPCODE_ISGE:
4036 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4037 break;
4038
4039 case TGSI_OPCODE_ISHR:
4040 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4041 break;
4042
4043 case TGSI_OPCODE_ISLT:
4044 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4045 break;
4046
4047 case TGSI_OPCODE_F2U:
4048 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4049 break;
4050
4051 case TGSI_OPCODE_U2F:
4052 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4053 break;
4054
4055 case TGSI_OPCODE_UADD:
4056 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4057 break;
4058
4059 case TGSI_OPCODE_UDIV:
4060 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4061 break;
4062
4063 case TGSI_OPCODE_UMAD:
4064 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4065 break;
4066
4067 case TGSI_OPCODE_UMAX:
4068 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4069 break;
4070
4071 case TGSI_OPCODE_UMIN:
4072 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4073 break;
4074
4075 case TGSI_OPCODE_UMOD:
4076 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4077 break;
4078
4079 case TGSI_OPCODE_UMUL:
4080 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4081 break;
4082
4083 case TGSI_OPCODE_USEQ:
4084 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4085 break;
4086
4087 case TGSI_OPCODE_USGE:
4088 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4089 break;
4090
4091 case TGSI_OPCODE_USHR:
4092 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4093 break;
4094
4095 case TGSI_OPCODE_USLT:
4096 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4097 break;
4098
4099 case TGSI_OPCODE_USNE:
4100 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4101 break;
4102
4103 case TGSI_OPCODE_SWITCH:
4104 exec_switch(mach, inst);
4105 break;
4106
4107 case TGSI_OPCODE_CASE:
4108 exec_case(mach, inst);
4109 break;
4110
4111 case TGSI_OPCODE_DEFAULT:
4112 exec_default(mach);
4113 break;
4114
4115 case TGSI_OPCODE_ENDSWITCH:
4116 exec_endswitch(mach);
4117 break;
4118
4119 case TGSI_OPCODE_LOAD:
4120 assert(0);
4121 break;
4122
4123 case TGSI_OPCODE_LOAD_MS:
4124 assert(0);
4125 break;
4126
4127 case TGSI_OPCODE_SAMPLE:
4128 exec_sample(mach, inst, TEX_MODIFIER_NONE);
4129 break;
4130
4131 case TGSI_OPCODE_SAMPLE_B:
4132 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS);
4133 break;
4134
4135 case TGSI_OPCODE_SAMPLE_C:
4136 exec_sample(mach, inst, TEX_MODIFIER_NONE);
4137 break;
4138
4139 case TGSI_OPCODE_SAMPLE_C_LZ:
4140 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS);
4141 break;
4142
4143 case TGSI_OPCODE_SAMPLE_D:
4144 exec_sample_d(mach, inst);
4145 break;
4146
4147 case TGSI_OPCODE_SAMPLE_L:
4148 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
4149 break;
4150
4151 case TGSI_OPCODE_GATHER4:
4152 assert(0);
4153 break;
4154
4155 case TGSI_OPCODE_RESINFO:
4156 assert(0);
4157 break;
4158
4159 case TGSI_OPCODE_SAMPLE_POS:
4160 assert(0);
4161 break;
4162
4163 case TGSI_OPCODE_SAMPLE_INFO:
4164 assert(0);
4165 break;
4166
4167 case TGSI_OPCODE_UARL:
4168 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4169 break;
4170
4171 case TGSI_OPCODE_UCMP:
4172 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4173 break;
4174
4175 default:
4176 assert( 0 );
4177 }
4178 }
4179
4180
4181 #define DEBUG_EXECUTION 0
4182
4183
4184 /**
4185 * Run TGSI interpreter.
4186 * \return bitmask of "alive" quad components
4187 */
4188 uint
4189 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4190 {
4191 uint i;
4192 int pc = 0;
4193
4194 mach->CondMask = 0xf;
4195 mach->LoopMask = 0xf;
4196 mach->ContMask = 0xf;
4197 mach->FuncMask = 0xf;
4198 mach->ExecMask = 0xf;
4199
4200 mach->Switch.mask = 0xf;
4201
4202 assert(mach->CondStackTop == 0);
4203 assert(mach->LoopStackTop == 0);
4204 assert(mach->ContStackTop == 0);
4205 assert(mach->SwitchStackTop == 0);
4206 assert(mach->BreakStackTop == 0);
4207 assert(mach->CallStackTop == 0);
4208
4209 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4210 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4211
4212 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4213 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4214 mach->Primitives[0] = 0;
4215 }
4216
4217 /* execute declarations (interpolants) */
4218 for (i = 0; i < mach->NumDeclarations; i++) {
4219 exec_declaration( mach, mach->Declarations+i );
4220 }
4221
4222 {
4223 #if DEBUG_EXECUTION
4224 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4225 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4226 uint inst = 1;
4227
4228 memcpy(temps, mach->Temps, sizeof(temps));
4229 memcpy(outputs, mach->Outputs, sizeof(outputs));
4230 #endif
4231
4232 /* execute instructions, until pc is set to -1 */
4233 while (pc != -1) {
4234
4235 #if DEBUG_EXECUTION
4236 uint i;
4237
4238 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4239 #endif
4240
4241 assert(pc < (int) mach->NumInstructions);
4242 exec_instruction(mach, mach->Instructions + pc, &pc);
4243
4244 #if DEBUG_EXECUTION
4245 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4246 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4247 uint j;
4248
4249 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4250 debug_printf("TEMP[%2u] = ", i);
4251 for (j = 0; j < 4; j++) {
4252 if (j > 0) {
4253 debug_printf(" ");
4254 }
4255 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4256 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4257 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4258 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4259 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4260 }
4261 }
4262 }
4263 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4264 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4265 uint j;
4266
4267 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4268 debug_printf("OUT[%2u] = ", i);
4269 for (j = 0; j < 4; j++) {
4270 if (j > 0) {
4271 debug_printf(" ");
4272 }
4273 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4274 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4275 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4276 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4277 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4278 }
4279 }
4280 }
4281 #endif
4282 }
4283 }
4284
4285 #if 0
4286 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4287 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4288 /*
4289 * Scale back depth component.
4290 */
4291 for (i = 0; i < 4; i++)
4292 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4293 }
4294 #endif
4295
4296 /* Strictly speaking, these assertions aren't really needed but they
4297 * can potentially catch some bugs in the control flow code.
4298 */
4299 assert(mach->CondStackTop == 0);
4300 assert(mach->LoopStackTop == 0);
4301 assert(mach->ContStackTop == 0);
4302 assert(mach->SwitchStackTop == 0);
4303 assert(mach->BreakStackTop == 0);
4304 assert(mach->CallStackTop == 0);
4305
4306 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4307 }