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tgsi: avoid returning pointer to local var, make it static
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define DEBUG_EXECUTION 0
66
67
68 #define FAST_MATH 0
69
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
74
75 union tgsi_double_channel {
76 double d[TGSI_QUAD_SIZE];
77 unsigned u[TGSI_QUAD_SIZE][2];
78 };
79
80 struct tgsi_double_vector {
81 union tgsi_double_channel xy;
82 union tgsi_double_channel zw;
83 };
84
85 static void
86 micro_abs(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
88 {
89 dst->f[0] = fabsf(src->f[0]);
90 dst->f[1] = fabsf(src->f[1]);
91 dst->f[2] = fabsf(src->f[2]);
92 dst->f[3] = fabsf(src->f[3]);
93 }
94
95 static void
96 micro_arl(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
98 {
99 dst->i[0] = (int)floorf(src->f[0]);
100 dst->i[1] = (int)floorf(src->f[1]);
101 dst->i[2] = (int)floorf(src->f[2]);
102 dst->i[3] = (int)floorf(src->f[3]);
103 }
104
105 static void
106 micro_arr(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
108 {
109 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
110 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
111 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
112 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
113 }
114
115 static void
116 micro_ceil(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src)
118 {
119 dst->f[0] = ceilf(src->f[0]);
120 dst->f[1] = ceilf(src->f[1]);
121 dst->f[2] = ceilf(src->f[2]);
122 dst->f[3] = ceilf(src->f[3]);
123 }
124
125 static void
126 micro_clamp(union tgsi_exec_channel *dst,
127 const union tgsi_exec_channel *src0,
128 const union tgsi_exec_channel *src1,
129 const union tgsi_exec_channel *src2)
130 {
131 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
132 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
133 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
134 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
135 }
136
137 static void
138 micro_cmp(union tgsi_exec_channel *dst,
139 const union tgsi_exec_channel *src0,
140 const union tgsi_exec_channel *src1,
141 const union tgsi_exec_channel *src2)
142 {
143 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
144 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
145 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
146 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
147 }
148
149 static void
150 micro_cos(union tgsi_exec_channel *dst,
151 const union tgsi_exec_channel *src)
152 {
153 dst->f[0] = cosf(src->f[0]);
154 dst->f[1] = cosf(src->f[1]);
155 dst->f[2] = cosf(src->f[2]);
156 dst->f[3] = cosf(src->f[3]);
157 }
158
159 static void
160 micro_d2f(union tgsi_exec_channel *dst,
161 const union tgsi_double_channel *src)
162 {
163 dst->f[0] = (float)src->d[0];
164 dst->f[1] = (float)src->d[1];
165 dst->f[2] = (float)src->d[2];
166 dst->f[3] = (float)src->d[3];
167 }
168
169 static void
170 micro_d2i(union tgsi_exec_channel *dst,
171 const union tgsi_double_channel *src)
172 {
173 dst->i[0] = (int)src->d[0];
174 dst->i[1] = (int)src->d[1];
175 dst->i[2] = (int)src->d[2];
176 dst->i[3] = (int)src->d[3];
177 }
178
179 static void
180 micro_d2u(union tgsi_exec_channel *dst,
181 const union tgsi_double_channel *src)
182 {
183 dst->u[0] = (unsigned)src->d[0];
184 dst->u[1] = (unsigned)src->d[1];
185 dst->u[2] = (unsigned)src->d[2];
186 dst->u[3] = (unsigned)src->d[3];
187 }
188 static void
189 micro_dabs(union tgsi_double_channel *dst,
190 const union tgsi_double_channel *src)
191 {
192 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
193 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
194 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
195 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
196 }
197
198 static void
199 micro_dadd(union tgsi_double_channel *dst,
200 const union tgsi_double_channel *src)
201 {
202 dst->d[0] = src[0].d[0] + src[1].d[0];
203 dst->d[1] = src[0].d[1] + src[1].d[1];
204 dst->d[2] = src[0].d[2] + src[1].d[2];
205 dst->d[3] = src[0].d[3] + src[1].d[3];
206 }
207
208 static void
209 micro_ddx(union tgsi_exec_channel *dst,
210 const union tgsi_exec_channel *src)
211 {
212 dst->f[0] =
213 dst->f[1] =
214 dst->f[2] =
215 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
216 }
217
218 static void
219 micro_ddy(union tgsi_exec_channel *dst,
220 const union tgsi_exec_channel *src)
221 {
222 dst->f[0] =
223 dst->f[1] =
224 dst->f[2] =
225 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
226 }
227
228 static void
229 micro_dmul(union tgsi_double_channel *dst,
230 const union tgsi_double_channel *src)
231 {
232 dst->d[0] = src[0].d[0] * src[1].d[0];
233 dst->d[1] = src[0].d[1] * src[1].d[1];
234 dst->d[2] = src[0].d[2] * src[1].d[2];
235 dst->d[3] = src[0].d[3] * src[1].d[3];
236 }
237
238 static void
239 micro_dmax(union tgsi_double_channel *dst,
240 const union tgsi_double_channel *src)
241 {
242 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
243 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
244 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
245 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
246 }
247
248 static void
249 micro_dmin(union tgsi_double_channel *dst,
250 const union tgsi_double_channel *src)
251 {
252 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
253 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
254 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
255 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
256 }
257
258 static void
259 micro_dneg(union tgsi_double_channel *dst,
260 const union tgsi_double_channel *src)
261 {
262 dst->d[0] = -src->d[0];
263 dst->d[1] = -src->d[1];
264 dst->d[2] = -src->d[2];
265 dst->d[3] = -src->d[3];
266 }
267
268 static void
269 micro_dslt(union tgsi_double_channel *dst,
270 const union tgsi_double_channel *src)
271 {
272 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
273 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
274 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
275 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
276 }
277
278 static void
279 micro_dsne(union tgsi_double_channel *dst,
280 const union tgsi_double_channel *src)
281 {
282 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
283 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
284 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
285 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
286 }
287
288 static void
289 micro_dsge(union tgsi_double_channel *dst,
290 const union tgsi_double_channel *src)
291 {
292 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
293 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
294 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
295 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
296 }
297
298 static void
299 micro_dseq(union tgsi_double_channel *dst,
300 const union tgsi_double_channel *src)
301 {
302 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
303 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
304 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
305 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
306 }
307
308 static void
309 micro_drcp(union tgsi_double_channel *dst,
310 const union tgsi_double_channel *src)
311 {
312 dst->d[0] = 1.0 / src->d[0];
313 dst->d[1] = 1.0 / src->d[1];
314 dst->d[2] = 1.0 / src->d[2];
315 dst->d[3] = 1.0 / src->d[3];
316 }
317
318 static void
319 micro_dsqrt(union tgsi_double_channel *dst,
320 const union tgsi_double_channel *src)
321 {
322 dst->d[0] = sqrt(src->d[0]);
323 dst->d[1] = sqrt(src->d[1]);
324 dst->d[2] = sqrt(src->d[2]);
325 dst->d[3] = sqrt(src->d[3]);
326 }
327
328 static void
329 micro_drsq(union tgsi_double_channel *dst,
330 const union tgsi_double_channel *src)
331 {
332 dst->d[0] = 1.0 / sqrt(src->d[0]);
333 dst->d[1] = 1.0 / sqrt(src->d[1]);
334 dst->d[2] = 1.0 / sqrt(src->d[2]);
335 dst->d[3] = 1.0 / sqrt(src->d[3]);
336 }
337
338 static void
339 micro_dmad(union tgsi_double_channel *dst,
340 const union tgsi_double_channel *src)
341 {
342 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
343 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
344 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
345 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
346 }
347
348 static void
349 micro_dfrac(union tgsi_double_channel *dst,
350 const union tgsi_double_channel *src)
351 {
352 dst->d[0] = src->d[0] - floor(src->d[0]);
353 dst->d[1] = src->d[1] - floor(src->d[1]);
354 dst->d[2] = src->d[2] - floor(src->d[2]);
355 dst->d[3] = src->d[3] - floor(src->d[3]);
356 }
357
358 static void
359 micro_dldexp(union tgsi_double_channel *dst,
360 const union tgsi_double_channel *src0,
361 union tgsi_exec_channel *src1)
362 {
363 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
364 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
365 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
366 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
367 }
368
369 static void
370 micro_dfracexp(union tgsi_double_channel *dst,
371 union tgsi_exec_channel *dst_exp,
372 const union tgsi_double_channel *src)
373 {
374 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
375 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
376 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
377 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
378 }
379
380 static void
381 micro_exp2(union tgsi_exec_channel *dst,
382 const union tgsi_exec_channel *src)
383 {
384 #if FAST_MATH
385 dst->f[0] = util_fast_exp2(src->f[0]);
386 dst->f[1] = util_fast_exp2(src->f[1]);
387 dst->f[2] = util_fast_exp2(src->f[2]);
388 dst->f[3] = util_fast_exp2(src->f[3]);
389 #else
390 #if DEBUG
391 /* Inf is okay for this instruction, so clamp it to silence assertions. */
392 uint i;
393 union tgsi_exec_channel clamped;
394
395 for (i = 0; i < 4; i++) {
396 if (src->f[i] > 127.99999f) {
397 clamped.f[i] = 127.99999f;
398 } else if (src->f[i] < -126.99999f) {
399 clamped.f[i] = -126.99999f;
400 } else {
401 clamped.f[i] = src->f[i];
402 }
403 }
404 src = &clamped;
405 #endif /* DEBUG */
406
407 dst->f[0] = powf(2.0f, src->f[0]);
408 dst->f[1] = powf(2.0f, src->f[1]);
409 dst->f[2] = powf(2.0f, src->f[2]);
410 dst->f[3] = powf(2.0f, src->f[3]);
411 #endif /* FAST_MATH */
412 }
413
414 static void
415 micro_f2d(union tgsi_double_channel *dst,
416 const union tgsi_exec_channel *src)
417 {
418 dst->d[0] = (double)src->f[0];
419 dst->d[1] = (double)src->f[1];
420 dst->d[2] = (double)src->f[2];
421 dst->d[3] = (double)src->f[3];
422 }
423
424 static void
425 micro_flr(union tgsi_exec_channel *dst,
426 const union tgsi_exec_channel *src)
427 {
428 dst->f[0] = floorf(src->f[0]);
429 dst->f[1] = floorf(src->f[1]);
430 dst->f[2] = floorf(src->f[2]);
431 dst->f[3] = floorf(src->f[3]);
432 }
433
434 static void
435 micro_frc(union tgsi_exec_channel *dst,
436 const union tgsi_exec_channel *src)
437 {
438 dst->f[0] = src->f[0] - floorf(src->f[0]);
439 dst->f[1] = src->f[1] - floorf(src->f[1]);
440 dst->f[2] = src->f[2] - floorf(src->f[2]);
441 dst->f[3] = src->f[3] - floorf(src->f[3]);
442 }
443
444 static void
445 micro_i2d(union tgsi_double_channel *dst,
446 const union tgsi_exec_channel *src)
447 {
448 dst->d[0] = (double)src->i[0];
449 dst->d[1] = (double)src->i[1];
450 dst->d[2] = (double)src->i[2];
451 dst->d[3] = (double)src->i[3];
452 }
453
454 static void
455 micro_iabs(union tgsi_exec_channel *dst,
456 const union tgsi_exec_channel *src)
457 {
458 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
459 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
460 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
461 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
462 }
463
464 static void
465 micro_ineg(union tgsi_exec_channel *dst,
466 const union tgsi_exec_channel *src)
467 {
468 dst->i[0] = -src->i[0];
469 dst->i[1] = -src->i[1];
470 dst->i[2] = -src->i[2];
471 dst->i[3] = -src->i[3];
472 }
473
474 static void
475 micro_lg2(union tgsi_exec_channel *dst,
476 const union tgsi_exec_channel *src)
477 {
478 #if FAST_MATH
479 dst->f[0] = util_fast_log2(src->f[0]);
480 dst->f[1] = util_fast_log2(src->f[1]);
481 dst->f[2] = util_fast_log2(src->f[2]);
482 dst->f[3] = util_fast_log2(src->f[3]);
483 #else
484 dst->f[0] = logf(src->f[0]) * 1.442695f;
485 dst->f[1] = logf(src->f[1]) * 1.442695f;
486 dst->f[2] = logf(src->f[2]) * 1.442695f;
487 dst->f[3] = logf(src->f[3]) * 1.442695f;
488 #endif
489 }
490
491 static void
492 micro_lrp(union tgsi_exec_channel *dst,
493 const union tgsi_exec_channel *src0,
494 const union tgsi_exec_channel *src1,
495 const union tgsi_exec_channel *src2)
496 {
497 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
498 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
499 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
500 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
501 }
502
503 static void
504 micro_mad(union tgsi_exec_channel *dst,
505 const union tgsi_exec_channel *src0,
506 const union tgsi_exec_channel *src1,
507 const union tgsi_exec_channel *src2)
508 {
509 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
510 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
511 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
512 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
513 }
514
515 static void
516 micro_mov(union tgsi_exec_channel *dst,
517 const union tgsi_exec_channel *src)
518 {
519 dst->u[0] = src->u[0];
520 dst->u[1] = src->u[1];
521 dst->u[2] = src->u[2];
522 dst->u[3] = src->u[3];
523 }
524
525 static void
526 micro_rcp(union tgsi_exec_channel *dst,
527 const union tgsi_exec_channel *src)
528 {
529 #if 0 /* for debugging */
530 assert(src->f[0] != 0.0f);
531 assert(src->f[1] != 0.0f);
532 assert(src->f[2] != 0.0f);
533 assert(src->f[3] != 0.0f);
534 #endif
535 dst->f[0] = 1.0f / src->f[0];
536 dst->f[1] = 1.0f / src->f[1];
537 dst->f[2] = 1.0f / src->f[2];
538 dst->f[3] = 1.0f / src->f[3];
539 }
540
541 static void
542 micro_rnd(union tgsi_exec_channel *dst,
543 const union tgsi_exec_channel *src)
544 {
545 dst->f[0] = floorf(src->f[0] + 0.5f);
546 dst->f[1] = floorf(src->f[1] + 0.5f);
547 dst->f[2] = floorf(src->f[2] + 0.5f);
548 dst->f[3] = floorf(src->f[3] + 0.5f);
549 }
550
551 static void
552 micro_rsq(union tgsi_exec_channel *dst,
553 const union tgsi_exec_channel *src)
554 {
555 #if 0 /* for debugging */
556 assert(src->f[0] != 0.0f);
557 assert(src->f[1] != 0.0f);
558 assert(src->f[2] != 0.0f);
559 assert(src->f[3] != 0.0f);
560 #endif
561 dst->f[0] = 1.0f / sqrtf(src->f[0]);
562 dst->f[1] = 1.0f / sqrtf(src->f[1]);
563 dst->f[2] = 1.0f / sqrtf(src->f[2]);
564 dst->f[3] = 1.0f / sqrtf(src->f[3]);
565 }
566
567 static void
568 micro_sqrt(union tgsi_exec_channel *dst,
569 const union tgsi_exec_channel *src)
570 {
571 dst->f[0] = sqrtf(src->f[0]);
572 dst->f[1] = sqrtf(src->f[1]);
573 dst->f[2] = sqrtf(src->f[2]);
574 dst->f[3] = sqrtf(src->f[3]);
575 }
576
577 static void
578 micro_seq(union tgsi_exec_channel *dst,
579 const union tgsi_exec_channel *src0,
580 const union tgsi_exec_channel *src1)
581 {
582 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
583 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
584 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
585 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
586 }
587
588 static void
589 micro_sge(union tgsi_exec_channel *dst,
590 const union tgsi_exec_channel *src0,
591 const union tgsi_exec_channel *src1)
592 {
593 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
594 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
595 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
596 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
597 }
598
599 static void
600 micro_sgn(union tgsi_exec_channel *dst,
601 const union tgsi_exec_channel *src)
602 {
603 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
604 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
605 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
606 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
607 }
608
609 static void
610 micro_isgn(union tgsi_exec_channel *dst,
611 const union tgsi_exec_channel *src)
612 {
613 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
614 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
615 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
616 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
617 }
618
619 static void
620 micro_sgt(union tgsi_exec_channel *dst,
621 const union tgsi_exec_channel *src0,
622 const union tgsi_exec_channel *src1)
623 {
624 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
625 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
626 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
627 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
628 }
629
630 static void
631 micro_sin(union tgsi_exec_channel *dst,
632 const union tgsi_exec_channel *src)
633 {
634 dst->f[0] = sinf(src->f[0]);
635 dst->f[1] = sinf(src->f[1]);
636 dst->f[2] = sinf(src->f[2]);
637 dst->f[3] = sinf(src->f[3]);
638 }
639
640 static void
641 micro_sle(union tgsi_exec_channel *dst,
642 const union tgsi_exec_channel *src0,
643 const union tgsi_exec_channel *src1)
644 {
645 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
646 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
647 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
648 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
649 }
650
651 static void
652 micro_slt(union tgsi_exec_channel *dst,
653 const union tgsi_exec_channel *src0,
654 const union tgsi_exec_channel *src1)
655 {
656 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
657 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
658 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
659 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
660 }
661
662 static void
663 micro_sne(union tgsi_exec_channel *dst,
664 const union tgsi_exec_channel *src0,
665 const union tgsi_exec_channel *src1)
666 {
667 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
668 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
669 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
670 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
671 }
672
673 static void
674 micro_trunc(union tgsi_exec_channel *dst,
675 const union tgsi_exec_channel *src)
676 {
677 dst->f[0] = (float)(int)src->f[0];
678 dst->f[1] = (float)(int)src->f[1];
679 dst->f[2] = (float)(int)src->f[2];
680 dst->f[3] = (float)(int)src->f[3];
681 }
682
683 static void
684 micro_u2d(union tgsi_double_channel *dst,
685 const union tgsi_exec_channel *src)
686 {
687 dst->d[0] = (double)src->u[0];
688 dst->d[1] = (double)src->u[1];
689 dst->d[2] = (double)src->u[2];
690 dst->d[3] = (double)src->u[3];
691 }
692
693 enum tgsi_exec_datatype {
694 TGSI_EXEC_DATA_FLOAT,
695 TGSI_EXEC_DATA_INT,
696 TGSI_EXEC_DATA_UINT,
697 TGSI_EXEC_DATA_DOUBLE
698 };
699
700 /*
701 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
702 */
703 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
704 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
705 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
706 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
707 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
708 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
709
710
711 /** The execution mask depends on the conditional mask and the loop mask */
712 #define UPDATE_EXEC_MASK(MACH) \
713 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
714
715
716 static const union tgsi_exec_channel ZeroVec =
717 { { 0.0, 0.0, 0.0, 0.0 } };
718
719 static const union tgsi_exec_channel OneVec = {
720 {1.0f, 1.0f, 1.0f, 1.0f}
721 };
722
723 static const union tgsi_exec_channel P128Vec = {
724 {128.0f, 128.0f, 128.0f, 128.0f}
725 };
726
727 static const union tgsi_exec_channel M128Vec = {
728 {-128.0f, -128.0f, -128.0f, -128.0f}
729 };
730
731
732 /**
733 * Assert that none of the float values in 'chan' are infinite or NaN.
734 * NaN and Inf may occur normally during program execution and should
735 * not lead to crashes, etc. But when debugging, it's helpful to catch
736 * them.
737 */
738 static INLINE void
739 check_inf_or_nan(const union tgsi_exec_channel *chan)
740 {
741 assert(!util_is_inf_or_nan((chan)->f[0]));
742 assert(!util_is_inf_or_nan((chan)->f[1]));
743 assert(!util_is_inf_or_nan((chan)->f[2]));
744 assert(!util_is_inf_or_nan((chan)->f[3]));
745 }
746
747
748 #ifdef DEBUG
749 static void
750 print_chan(const char *msg, const union tgsi_exec_channel *chan)
751 {
752 debug_printf("%s = {%f, %f, %f, %f}\n",
753 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
754 }
755 #endif
756
757
758 #ifdef DEBUG
759 static void
760 print_temp(const struct tgsi_exec_machine *mach, uint index)
761 {
762 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
763 int i;
764 debug_printf("Temp[%u] =\n", index);
765 for (i = 0; i < 4; i++) {
766 debug_printf(" %c: { %f, %f, %f, %f }\n",
767 "XYZW"[i],
768 tmp->xyzw[i].f[0],
769 tmp->xyzw[i].f[1],
770 tmp->xyzw[i].f[2],
771 tmp->xyzw[i].f[3]);
772 }
773 }
774 #endif
775
776
777 void
778 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
779 unsigned num_bufs,
780 const void **bufs,
781 const unsigned *buf_sizes)
782 {
783 unsigned i;
784
785 for (i = 0; i < num_bufs; i++) {
786 mach->Consts[i] = bufs[i];
787 mach->ConstsSize[i] = buf_sizes[i];
788 }
789 }
790
791
792 /**
793 * Check if there's a potential src/dst register data dependency when
794 * using SOA execution.
795 * Example:
796 * MOV T, T.yxwz;
797 * This would expand into:
798 * MOV t0, t1;
799 * MOV t1, t0;
800 * MOV t2, t3;
801 * MOV t3, t2;
802 * The second instruction will have the wrong value for t0 if executed as-is.
803 */
804 boolean
805 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
806 {
807 uint i, chan;
808
809 uint writemask = inst->Dst[0].Register.WriteMask;
810 if (writemask == TGSI_WRITEMASK_X ||
811 writemask == TGSI_WRITEMASK_Y ||
812 writemask == TGSI_WRITEMASK_Z ||
813 writemask == TGSI_WRITEMASK_W ||
814 writemask == TGSI_WRITEMASK_NONE) {
815 /* no chance of data dependency */
816 return FALSE;
817 }
818
819 /* loop over src regs */
820 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
821 if ((inst->Src[i].Register.File ==
822 inst->Dst[0].Register.File) &&
823 ((inst->Src[i].Register.Index ==
824 inst->Dst[0].Register.Index) ||
825 inst->Src[i].Register.Indirect ||
826 inst->Dst[0].Register.Indirect)) {
827 /* loop over dest channels */
828 uint channelsWritten = 0x0;
829 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
830 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
831 /* check if we're reading a channel that's been written */
832 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
833 if (channelsWritten & (1 << swizzle)) {
834 return TRUE;
835 }
836
837 channelsWritten |= (1 << chan);
838 }
839 }
840 }
841 }
842 return FALSE;
843 }
844
845
846 /**
847 * Initialize machine state by expanding tokens to full instructions,
848 * allocating temporary storage, setting up constants, etc.
849 * After this, we can call tgsi_exec_machine_run() many times.
850 */
851 void
852 tgsi_exec_machine_bind_shader(
853 struct tgsi_exec_machine *mach,
854 const struct tgsi_token *tokens,
855 struct tgsi_sampler *sampler)
856 {
857 uint k;
858 struct tgsi_parse_context parse;
859 struct tgsi_full_instruction *instructions;
860 struct tgsi_full_declaration *declarations;
861 uint maxInstructions = 10, numInstructions = 0;
862 uint maxDeclarations = 10, numDeclarations = 0;
863
864 #if 0
865 tgsi_dump(tokens, 0);
866 #endif
867
868 util_init_math();
869
870
871 mach->Tokens = tokens;
872 mach->Sampler = sampler;
873
874 if (!tokens) {
875 /* unbind and free all */
876 FREE(mach->Declarations);
877 mach->Declarations = NULL;
878 mach->NumDeclarations = 0;
879
880 FREE(mach->Instructions);
881 mach->Instructions = NULL;
882 mach->NumInstructions = 0;
883
884 return;
885 }
886
887 k = tgsi_parse_init (&parse, mach->Tokens);
888 if (k != TGSI_PARSE_OK) {
889 debug_printf( "Problem parsing!\n" );
890 return;
891 }
892
893 mach->Processor = parse.FullHeader.Processor.Processor;
894 mach->ImmLimit = 0;
895 mach->NumOutputs = 0;
896
897 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
898 !mach->UsedGeometryShader) {
899 struct tgsi_exec_vector *inputs;
900 struct tgsi_exec_vector *outputs;
901
902 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
903 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
904 16);
905
906 if (!inputs)
907 return;
908
909 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
910 TGSI_MAX_TOTAL_VERTICES, 16);
911
912 if (!outputs) {
913 align_free(inputs);
914 return;
915 }
916
917 align_free(mach->Inputs);
918 align_free(mach->Outputs);
919
920 mach->Inputs = inputs;
921 mach->Outputs = outputs;
922 mach->UsedGeometryShader = TRUE;
923 }
924
925 declarations = (struct tgsi_full_declaration *)
926 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
927
928 if (!declarations) {
929 return;
930 }
931
932 instructions = (struct tgsi_full_instruction *)
933 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
934
935 if (!instructions) {
936 FREE( declarations );
937 return;
938 }
939
940 while( !tgsi_parse_end_of_tokens( &parse ) ) {
941 uint i;
942
943 tgsi_parse_token( &parse );
944 switch( parse.FullToken.Token.Type ) {
945 case TGSI_TOKEN_TYPE_DECLARATION:
946 /* save expanded declaration */
947 if (numDeclarations == maxDeclarations) {
948 declarations = REALLOC(declarations,
949 maxDeclarations
950 * sizeof(struct tgsi_full_declaration),
951 (maxDeclarations + 10)
952 * sizeof(struct tgsi_full_declaration));
953 maxDeclarations += 10;
954 }
955 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
956 unsigned reg;
957 for (reg = parse.FullToken.FullDeclaration.Range.First;
958 reg <= parse.FullToken.FullDeclaration.Range.Last;
959 ++reg) {
960 ++mach->NumOutputs;
961 }
962 }
963 memcpy(declarations + numDeclarations,
964 &parse.FullToken.FullDeclaration,
965 sizeof(declarations[0]));
966 numDeclarations++;
967 break;
968
969 case TGSI_TOKEN_TYPE_IMMEDIATE:
970 {
971 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
972 assert( size <= 4 );
973 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
974
975 for( i = 0; i < size; i++ ) {
976 mach->Imms[mach->ImmLimit][i] =
977 parse.FullToken.FullImmediate.u[i].Float;
978 }
979 mach->ImmLimit += 1;
980 }
981 break;
982
983 case TGSI_TOKEN_TYPE_INSTRUCTION:
984
985 /* save expanded instruction */
986 if (numInstructions == maxInstructions) {
987 instructions = REALLOC(instructions,
988 maxInstructions
989 * sizeof(struct tgsi_full_instruction),
990 (maxInstructions + 10)
991 * sizeof(struct tgsi_full_instruction));
992 maxInstructions += 10;
993 }
994
995 memcpy(instructions + numInstructions,
996 &parse.FullToken.FullInstruction,
997 sizeof(instructions[0]));
998
999 numInstructions++;
1000 break;
1001
1002 case TGSI_TOKEN_TYPE_PROPERTY:
1003 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY) {
1004 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1005 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1006 }
1007 }
1008 break;
1009
1010 default:
1011 assert( 0 );
1012 }
1013 }
1014 tgsi_parse_free (&parse);
1015
1016 FREE(mach->Declarations);
1017 mach->Declarations = declarations;
1018 mach->NumDeclarations = numDeclarations;
1019
1020 FREE(mach->Instructions);
1021 mach->Instructions = instructions;
1022 mach->NumInstructions = numInstructions;
1023 }
1024
1025
1026 struct tgsi_exec_machine *
1027 tgsi_exec_machine_create( void )
1028 {
1029 struct tgsi_exec_machine *mach;
1030 uint i;
1031
1032 mach = align_malloc( sizeof *mach, 16 );
1033 if (!mach)
1034 goto fail;
1035
1036 memset(mach, 0, sizeof(*mach));
1037
1038 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1039 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1040 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
1041
1042 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1043 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1044 if (!mach->Inputs || !mach->Outputs)
1045 goto fail;
1046
1047 /* Setup constants needed by the SSE2 executor. */
1048 for( i = 0; i < 4; i++ ) {
1049 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1050 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1051 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1052 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1053 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1054 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1055 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1056 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1057 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1058 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1059 }
1060
1061 #ifdef DEBUG
1062 /* silence warnings */
1063 (void) print_chan;
1064 (void) print_temp;
1065 #endif
1066
1067 return mach;
1068
1069 fail:
1070 if (mach) {
1071 align_free(mach->Inputs);
1072 align_free(mach->Outputs);
1073 align_free(mach);
1074 }
1075 return NULL;
1076 }
1077
1078
1079 void
1080 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1081 {
1082 if (mach) {
1083 FREE(mach->Instructions);
1084 FREE(mach->Declarations);
1085
1086 align_free(mach->Inputs);
1087 align_free(mach->Outputs);
1088
1089 align_free(mach);
1090 }
1091 }
1092
1093 static void
1094 micro_add(union tgsi_exec_channel *dst,
1095 const union tgsi_exec_channel *src0,
1096 const union tgsi_exec_channel *src1)
1097 {
1098 dst->f[0] = src0->f[0] + src1->f[0];
1099 dst->f[1] = src0->f[1] + src1->f[1];
1100 dst->f[2] = src0->f[2] + src1->f[2];
1101 dst->f[3] = src0->f[3] + src1->f[3];
1102 }
1103
1104 static void
1105 micro_div(
1106 union tgsi_exec_channel *dst,
1107 const union tgsi_exec_channel *src0,
1108 const union tgsi_exec_channel *src1 )
1109 {
1110 if (src1->f[0] != 0) {
1111 dst->f[0] = src0->f[0] / src1->f[0];
1112 }
1113 if (src1->f[1] != 0) {
1114 dst->f[1] = src0->f[1] / src1->f[1];
1115 }
1116 if (src1->f[2] != 0) {
1117 dst->f[2] = src0->f[2] / src1->f[2];
1118 }
1119 if (src1->f[3] != 0) {
1120 dst->f[3] = src0->f[3] / src1->f[3];
1121 }
1122 }
1123
1124 static void
1125 micro_lt(
1126 union tgsi_exec_channel *dst,
1127 const union tgsi_exec_channel *src0,
1128 const union tgsi_exec_channel *src1,
1129 const union tgsi_exec_channel *src2,
1130 const union tgsi_exec_channel *src3 )
1131 {
1132 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1133 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1134 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1135 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1136 }
1137
1138 static void
1139 micro_max(union tgsi_exec_channel *dst,
1140 const union tgsi_exec_channel *src0,
1141 const union tgsi_exec_channel *src1)
1142 {
1143 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1144 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1145 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1146 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1147 }
1148
1149 static void
1150 micro_min(union tgsi_exec_channel *dst,
1151 const union tgsi_exec_channel *src0,
1152 const union tgsi_exec_channel *src1)
1153 {
1154 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1155 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1156 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1157 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1158 }
1159
1160 static void
1161 micro_mul(union tgsi_exec_channel *dst,
1162 const union tgsi_exec_channel *src0,
1163 const union tgsi_exec_channel *src1)
1164 {
1165 dst->f[0] = src0->f[0] * src1->f[0];
1166 dst->f[1] = src0->f[1] * src1->f[1];
1167 dst->f[2] = src0->f[2] * src1->f[2];
1168 dst->f[3] = src0->f[3] * src1->f[3];
1169 }
1170
1171 static void
1172 micro_neg(
1173 union tgsi_exec_channel *dst,
1174 const union tgsi_exec_channel *src )
1175 {
1176 dst->f[0] = -src->f[0];
1177 dst->f[1] = -src->f[1];
1178 dst->f[2] = -src->f[2];
1179 dst->f[3] = -src->f[3];
1180 }
1181
1182 static void
1183 micro_pow(
1184 union tgsi_exec_channel *dst,
1185 const union tgsi_exec_channel *src0,
1186 const union tgsi_exec_channel *src1 )
1187 {
1188 #if FAST_MATH
1189 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1190 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1191 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1192 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1193 #else
1194 dst->f[0] = powf( src0->f[0], src1->f[0] );
1195 dst->f[1] = powf( src0->f[1], src1->f[1] );
1196 dst->f[2] = powf( src0->f[2], src1->f[2] );
1197 dst->f[3] = powf( src0->f[3], src1->f[3] );
1198 #endif
1199 }
1200
1201 static void
1202 micro_sub(union tgsi_exec_channel *dst,
1203 const union tgsi_exec_channel *src0,
1204 const union tgsi_exec_channel *src1)
1205 {
1206 dst->f[0] = src0->f[0] - src1->f[0];
1207 dst->f[1] = src0->f[1] - src1->f[1];
1208 dst->f[2] = src0->f[2] - src1->f[2];
1209 dst->f[3] = src0->f[3] - src1->f[3];
1210 }
1211
1212 static void
1213 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1214 const uint chan_index,
1215 const uint file,
1216 const uint swizzle,
1217 const union tgsi_exec_channel *index,
1218 const union tgsi_exec_channel *index2D,
1219 union tgsi_exec_channel *chan)
1220 {
1221 uint i;
1222
1223 assert(swizzle < 4);
1224
1225 switch (file) {
1226 case TGSI_FILE_CONSTANT:
1227 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1228 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1229 assert(mach->Consts[index2D->i[i]]);
1230
1231 if (index->i[i] < 0) {
1232 chan->u[i] = 0;
1233 } else {
1234 /* NOTE: copying the const value as a uint instead of float */
1235 const uint constbuf = index2D->i[i];
1236 const uint *buf = (const uint *)mach->Consts[constbuf];
1237 const int pos = index->i[i] * 4 + swizzle;
1238 /* const buffer bounds check */
1239 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1240 if (0) {
1241 /* Debug: print warning */
1242 static int count = 0;
1243 if (count++ < 100)
1244 debug_printf("TGSI Exec: const buffer index %d"
1245 " out of bounds\n", pos);
1246 }
1247 chan->u[i] = 0;
1248 }
1249 else
1250 chan->u[i] = buf[pos];
1251 }
1252 }
1253 break;
1254
1255 case TGSI_FILE_INPUT:
1256 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1257 /*
1258 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1259 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1260 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1261 index2D->i[i], index->i[i]);
1262 }*/
1263 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1264 assert(pos >= 0);
1265 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1266 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1267 }
1268 break;
1269
1270 case TGSI_FILE_SYSTEM_VALUE:
1271 /* XXX no swizzling at this point. Will be needed if we put
1272 * gl_FragCoord, for example, in a sys value register.
1273 */
1274 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1275 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1276 }
1277 break;
1278
1279 case TGSI_FILE_TEMPORARY:
1280 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1281 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1282 assert(index2D->i[i] == 0);
1283
1284 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1285 }
1286 break;
1287
1288 case TGSI_FILE_IMMEDIATE:
1289 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1290 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1291 assert(index2D->i[i] == 0);
1292
1293 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1294 }
1295 break;
1296
1297 case TGSI_FILE_ADDRESS:
1298 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1299 assert(index->i[i] >= 0);
1300 assert(index2D->i[i] == 0);
1301
1302 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1303 }
1304 break;
1305
1306 case TGSI_FILE_PREDICATE:
1307 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1308 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1309 assert(index2D->i[i] == 0);
1310
1311 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1312 }
1313 break;
1314
1315 case TGSI_FILE_OUTPUT:
1316 /* vertex/fragment output vars can be read too */
1317 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1318 assert(index->i[i] >= 0);
1319 assert(index2D->i[i] == 0);
1320
1321 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1322 }
1323 break;
1324
1325 default:
1326 assert(0);
1327 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1328 chan->u[i] = 0;
1329 }
1330 }
1331 }
1332
1333 static void
1334 fetch_source_d(const struct tgsi_exec_machine *mach,
1335 union tgsi_exec_channel *chan,
1336 const struct tgsi_full_src_register *reg,
1337 const uint chan_index,
1338 enum tgsi_exec_datatype src_datatype)
1339 {
1340 union tgsi_exec_channel index;
1341 union tgsi_exec_channel index2D;
1342 uint swizzle;
1343
1344 /* We start with a direct index into a register file.
1345 *
1346 * file[1],
1347 * where:
1348 * file = Register.File
1349 * [1] = Register.Index
1350 */
1351 index.i[0] =
1352 index.i[1] =
1353 index.i[2] =
1354 index.i[3] = reg->Register.Index;
1355
1356 /* There is an extra source register that indirectly subscripts
1357 * a register file. The direct index now becomes an offset
1358 * that is being added to the indirect register.
1359 *
1360 * file[ind[2].x+1],
1361 * where:
1362 * ind = Indirect.File
1363 * [2] = Indirect.Index
1364 * .x = Indirect.SwizzleX
1365 */
1366 if (reg->Register.Indirect) {
1367 union tgsi_exec_channel index2;
1368 union tgsi_exec_channel indir_index;
1369 const uint execmask = mach->ExecMask;
1370 uint i;
1371
1372 /* which address register (always zero now) */
1373 index2.i[0] =
1374 index2.i[1] =
1375 index2.i[2] =
1376 index2.i[3] = reg->Indirect.Index;
1377 /* get current value of address register[swizzle] */
1378 swizzle = reg->Indirect.Swizzle;
1379 fetch_src_file_channel(mach,
1380 chan_index,
1381 reg->Indirect.File,
1382 swizzle,
1383 &index2,
1384 &ZeroVec,
1385 &indir_index);
1386
1387 /* add value of address register to the offset */
1388 index.i[0] += indir_index.i[0];
1389 index.i[1] += indir_index.i[1];
1390 index.i[2] += indir_index.i[2];
1391 index.i[3] += indir_index.i[3];
1392
1393 /* for disabled execution channels, zero-out the index to
1394 * avoid using a potential garbage value.
1395 */
1396 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1397 if ((execmask & (1 << i)) == 0)
1398 index.i[i] = 0;
1399 }
1400 }
1401
1402 /* There is an extra source register that is a second
1403 * subscript to a register file. Effectively it means that
1404 * the register file is actually a 2D array of registers.
1405 *
1406 * file[3][1],
1407 * where:
1408 * [3] = Dimension.Index
1409 */
1410 if (reg->Register.Dimension) {
1411 index2D.i[0] =
1412 index2D.i[1] =
1413 index2D.i[2] =
1414 index2D.i[3] = reg->Dimension.Index;
1415
1416 /* Again, the second subscript index can be addressed indirectly
1417 * identically to the first one.
1418 * Nothing stops us from indirectly addressing the indirect register,
1419 * but there is no need for that, so we won't exercise it.
1420 *
1421 * file[ind[4].y+3][1],
1422 * where:
1423 * ind = DimIndirect.File
1424 * [4] = DimIndirect.Index
1425 * .y = DimIndirect.SwizzleX
1426 */
1427 if (reg->Dimension.Indirect) {
1428 union tgsi_exec_channel index2;
1429 union tgsi_exec_channel indir_index;
1430 const uint execmask = mach->ExecMask;
1431 uint i;
1432
1433 index2.i[0] =
1434 index2.i[1] =
1435 index2.i[2] =
1436 index2.i[3] = reg->DimIndirect.Index;
1437
1438 swizzle = reg->DimIndirect.Swizzle;
1439 fetch_src_file_channel(mach,
1440 chan_index,
1441 reg->DimIndirect.File,
1442 swizzle,
1443 &index2,
1444 &ZeroVec,
1445 &indir_index);
1446
1447 index2D.i[0] += indir_index.i[0];
1448 index2D.i[1] += indir_index.i[1];
1449 index2D.i[2] += indir_index.i[2];
1450 index2D.i[3] += indir_index.i[3];
1451
1452 /* for disabled execution channels, zero-out the index to
1453 * avoid using a potential garbage value.
1454 */
1455 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1456 if ((execmask & (1 << i)) == 0) {
1457 index2D.i[i] = 0;
1458 }
1459 }
1460 }
1461
1462 /* If by any chance there was a need for a 3D array of register
1463 * files, we would have to check whether Dimension is followed
1464 * by a dimension register and continue the saga.
1465 */
1466 } else {
1467 index2D.i[0] =
1468 index2D.i[1] =
1469 index2D.i[2] =
1470 index2D.i[3] = 0;
1471 }
1472
1473 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1474 fetch_src_file_channel(mach,
1475 chan_index,
1476 reg->Register.File,
1477 swizzle,
1478 &index,
1479 &index2D,
1480 chan);
1481 }
1482
1483 static void
1484 fetch_source(const struct tgsi_exec_machine *mach,
1485 union tgsi_exec_channel *chan,
1486 const struct tgsi_full_src_register *reg,
1487 const uint chan_index,
1488 enum tgsi_exec_datatype src_datatype)
1489 {
1490 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1491
1492 if (reg->Register.Absolute) {
1493 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1494 micro_abs(chan, chan);
1495 } else {
1496 micro_iabs(chan, chan);
1497 }
1498 }
1499
1500 if (reg->Register.Negate) {
1501 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1502 micro_neg(chan, chan);
1503 } else {
1504 micro_ineg(chan, chan);
1505 }
1506 }
1507 }
1508
1509 static union tgsi_exec_channel *
1510 store_dest_dstret(struct tgsi_exec_machine *mach,
1511 const union tgsi_exec_channel *chan,
1512 const struct tgsi_full_dst_register *reg,
1513 const struct tgsi_full_instruction *inst,
1514 uint chan_index,
1515 enum tgsi_exec_datatype dst_datatype)
1516 {
1517 uint i;
1518 static union tgsi_exec_channel null;
1519 union tgsi_exec_channel *dst;
1520 union tgsi_exec_channel index2D;
1521 uint execmask = mach->ExecMask;
1522 int offset = 0; /* indirection offset */
1523 int index;
1524
1525 /* for debugging */
1526 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1527 check_inf_or_nan(chan);
1528 }
1529
1530 /* There is an extra source register that indirectly subscripts
1531 * a register file. The direct index now becomes an offset
1532 * that is being added to the indirect register.
1533 *
1534 * file[ind[2].x+1],
1535 * where:
1536 * ind = Indirect.File
1537 * [2] = Indirect.Index
1538 * .x = Indirect.SwizzleX
1539 */
1540 if (reg->Register.Indirect) {
1541 union tgsi_exec_channel index;
1542 union tgsi_exec_channel indir_index;
1543 uint swizzle;
1544
1545 /* which address register (always zero for now) */
1546 index.i[0] =
1547 index.i[1] =
1548 index.i[2] =
1549 index.i[3] = reg->Indirect.Index;
1550
1551 /* get current value of address register[swizzle] */
1552 swizzle = reg->Indirect.Swizzle;
1553
1554 /* fetch values from the address/indirection register */
1555 fetch_src_file_channel(mach,
1556 chan_index,
1557 reg->Indirect.File,
1558 swizzle,
1559 &index,
1560 &ZeroVec,
1561 &indir_index);
1562
1563 /* save indirection offset */
1564 offset = indir_index.i[0];
1565 }
1566
1567 /* There is an extra source register that is a second
1568 * subscript to a register file. Effectively it means that
1569 * the register file is actually a 2D array of registers.
1570 *
1571 * file[3][1],
1572 * where:
1573 * [3] = Dimension.Index
1574 */
1575 if (reg->Register.Dimension) {
1576 index2D.i[0] =
1577 index2D.i[1] =
1578 index2D.i[2] =
1579 index2D.i[3] = reg->Dimension.Index;
1580
1581 /* Again, the second subscript index can be addressed indirectly
1582 * identically to the first one.
1583 * Nothing stops us from indirectly addressing the indirect register,
1584 * but there is no need for that, so we won't exercise it.
1585 *
1586 * file[ind[4].y+3][1],
1587 * where:
1588 * ind = DimIndirect.File
1589 * [4] = DimIndirect.Index
1590 * .y = DimIndirect.SwizzleX
1591 */
1592 if (reg->Dimension.Indirect) {
1593 union tgsi_exec_channel index2;
1594 union tgsi_exec_channel indir_index;
1595 const uint execmask = mach->ExecMask;
1596 unsigned swizzle;
1597 uint i;
1598
1599 index2.i[0] =
1600 index2.i[1] =
1601 index2.i[2] =
1602 index2.i[3] = reg->DimIndirect.Index;
1603
1604 swizzle = reg->DimIndirect.Swizzle;
1605 fetch_src_file_channel(mach,
1606 chan_index,
1607 reg->DimIndirect.File,
1608 swizzle,
1609 &index2,
1610 &ZeroVec,
1611 &indir_index);
1612
1613 index2D.i[0] += indir_index.i[0];
1614 index2D.i[1] += indir_index.i[1];
1615 index2D.i[2] += indir_index.i[2];
1616 index2D.i[3] += indir_index.i[3];
1617
1618 /* for disabled execution channels, zero-out the index to
1619 * avoid using a potential garbage value.
1620 */
1621 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1622 if ((execmask & (1 << i)) == 0) {
1623 index2D.i[i] = 0;
1624 }
1625 }
1626 }
1627
1628 /* If by any chance there was a need for a 3D array of register
1629 * files, we would have to check whether Dimension is followed
1630 * by a dimension register and continue the saga.
1631 */
1632 } else {
1633 index2D.i[0] =
1634 index2D.i[1] =
1635 index2D.i[2] =
1636 index2D.i[3] = 0;
1637 }
1638
1639 switch (reg->Register.File) {
1640 case TGSI_FILE_NULL:
1641 dst = &null;
1642 break;
1643
1644 case TGSI_FILE_OUTPUT:
1645 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1646 + reg->Register.Index;
1647 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1648 #if 0
1649 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1650 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1651 reg->Register.Index);
1652 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1653 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1654 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1655 if (execmask & (1 << i))
1656 debug_printf("%f, ", chan->f[i]);
1657 debug_printf(")\n");
1658 }
1659 #endif
1660 break;
1661
1662 case TGSI_FILE_TEMPORARY:
1663 index = reg->Register.Index;
1664 assert( index < TGSI_EXEC_NUM_TEMPS );
1665 dst = &mach->Temps[offset + index].xyzw[chan_index];
1666 break;
1667
1668 case TGSI_FILE_ADDRESS:
1669 index = reg->Register.Index;
1670 dst = &mach->Addrs[index].xyzw[chan_index];
1671 break;
1672
1673 case TGSI_FILE_PREDICATE:
1674 index = reg->Register.Index;
1675 assert(index < TGSI_EXEC_NUM_PREDS);
1676 dst = &mach->Predicates[index].xyzw[chan_index];
1677 break;
1678
1679 default:
1680 assert( 0 );
1681 return NULL;
1682 }
1683
1684 if (inst->Instruction.Predicate) {
1685 uint swizzle;
1686 union tgsi_exec_channel *pred;
1687
1688 switch (chan_index) {
1689 case TGSI_CHAN_X:
1690 swizzle = inst->Predicate.SwizzleX;
1691 break;
1692 case TGSI_CHAN_Y:
1693 swizzle = inst->Predicate.SwizzleY;
1694 break;
1695 case TGSI_CHAN_Z:
1696 swizzle = inst->Predicate.SwizzleZ;
1697 break;
1698 case TGSI_CHAN_W:
1699 swizzle = inst->Predicate.SwizzleW;
1700 break;
1701 default:
1702 assert(0);
1703 return NULL;
1704 }
1705
1706 assert(inst->Predicate.Index == 0);
1707
1708 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1709
1710 if (inst->Predicate.Negate) {
1711 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1712 if (pred->u[i]) {
1713 execmask &= ~(1 << i);
1714 }
1715 }
1716 } else {
1717 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1718 if (!pred->u[i]) {
1719 execmask &= ~(1 << i);
1720 }
1721 }
1722 }
1723 }
1724
1725 return dst;
1726 }
1727
1728 static void
1729 store_dest_double(struct tgsi_exec_machine *mach,
1730 const union tgsi_exec_channel *chan,
1731 const struct tgsi_full_dst_register *reg,
1732 const struct tgsi_full_instruction *inst,
1733 uint chan_index,
1734 enum tgsi_exec_datatype dst_datatype)
1735 {
1736 union tgsi_exec_channel *dst;
1737 const uint execmask = mach->ExecMask;
1738 int i;
1739
1740 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1741 dst_datatype);
1742 if (!dst)
1743 return;
1744
1745 /* doubles path */
1746 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1747 if (execmask & (1 << i))
1748 dst->i[i] = chan->i[i];
1749 }
1750
1751 static void
1752 store_dest(struct tgsi_exec_machine *mach,
1753 const union tgsi_exec_channel *chan,
1754 const struct tgsi_full_dst_register *reg,
1755 const struct tgsi_full_instruction *inst,
1756 uint chan_index,
1757 enum tgsi_exec_datatype dst_datatype)
1758 {
1759 union tgsi_exec_channel *dst;
1760 const uint execmask = mach->ExecMask;
1761 int i;
1762
1763 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1764 dst_datatype);
1765 if (!dst)
1766 return;
1767
1768 switch (inst->Instruction.Saturate) {
1769 case TGSI_SAT_NONE:
1770 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1771 if (execmask & (1 << i))
1772 dst->i[i] = chan->i[i];
1773 break;
1774
1775 case TGSI_SAT_ZERO_ONE:
1776 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1777 if (execmask & (1 << i)) {
1778 if (chan->f[i] < 0.0f)
1779 dst->f[i] = 0.0f;
1780 else if (chan->f[i] > 1.0f)
1781 dst->f[i] = 1.0f;
1782 else
1783 dst->i[i] = chan->i[i];
1784 }
1785 break;
1786
1787 case TGSI_SAT_MINUS_PLUS_ONE:
1788 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1789 if (execmask & (1 << i)) {
1790 if (chan->f[i] < -1.0f)
1791 dst->f[i] = -1.0f;
1792 else if (chan->f[i] > 1.0f)
1793 dst->f[i] = 1.0f;
1794 else
1795 dst->i[i] = chan->i[i];
1796 }
1797 break;
1798
1799 default:
1800 assert( 0 );
1801 }
1802 }
1803
1804 #define FETCH(VAL,INDEX,CHAN)\
1805 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1806
1807 #define IFETCH(VAL,INDEX,CHAN)\
1808 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1809
1810
1811 /**
1812 * Execute ARB-style KIL which is predicated by a src register.
1813 * Kill fragment if any of the four values is less than zero.
1814 */
1815 static void
1816 exec_kill_if(struct tgsi_exec_machine *mach,
1817 const struct tgsi_full_instruction *inst)
1818 {
1819 uint uniquemask;
1820 uint chan_index;
1821 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1822 union tgsi_exec_channel r[1];
1823
1824 /* This mask stores component bits that were already tested. */
1825 uniquemask = 0;
1826
1827 for (chan_index = 0; chan_index < 4; chan_index++)
1828 {
1829 uint swizzle;
1830 uint i;
1831
1832 /* unswizzle channel */
1833 swizzle = tgsi_util_get_full_src_register_swizzle (
1834 &inst->Src[0],
1835 chan_index);
1836
1837 /* check if the component has not been already tested */
1838 if (uniquemask & (1 << swizzle))
1839 continue;
1840 uniquemask |= 1 << swizzle;
1841
1842 FETCH(&r[0], 0, chan_index);
1843 for (i = 0; i < 4; i++)
1844 if (r[0].f[i] < 0.0f)
1845 kilmask |= 1 << i;
1846 }
1847
1848 /* restrict to fragments currently executing */
1849 kilmask &= mach->ExecMask;
1850
1851 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1852 }
1853
1854 /**
1855 * Unconditional fragment kill/discard.
1856 */
1857 static void
1858 exec_kill(struct tgsi_exec_machine *mach,
1859 const struct tgsi_full_instruction *inst)
1860 {
1861 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1862
1863 /* kill fragment for all fragments currently executing */
1864 kilmask = mach->ExecMask;
1865 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1866 }
1867
1868 static void
1869 emit_vertex(struct tgsi_exec_machine *mach)
1870 {
1871 /* FIXME: check for exec mask correctly
1872 unsigned i;
1873 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1874 if ((mach->ExecMask & (1 << i)))
1875 */
1876 if (mach->ExecMask) {
1877 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1878 return;
1879
1880 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1881 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1882 }
1883 }
1884
1885 static void
1886 emit_primitive(struct tgsi_exec_machine *mach)
1887 {
1888 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1889 /* FIXME: check for exec mask correctly
1890 unsigned i;
1891 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1892 if ((mach->ExecMask & (1 << i)))
1893 */
1894 if (mach->ExecMask) {
1895 ++(*prim_count);
1896 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1897 mach->Primitives[*prim_count] = 0;
1898 }
1899 }
1900
1901 static void
1902 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1903 {
1904 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1905 int emitted_verts =
1906 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1907 if (emitted_verts) {
1908 emit_primitive(mach);
1909 }
1910 }
1911 }
1912
1913
1914 /*
1915 * Fetch four texture samples using STR texture coordinates.
1916 */
1917 static void
1918 fetch_texel( struct tgsi_sampler *sampler,
1919 const unsigned sview_idx,
1920 const unsigned sampler_idx,
1921 const union tgsi_exec_channel *s,
1922 const union tgsi_exec_channel *t,
1923 const union tgsi_exec_channel *p,
1924 const union tgsi_exec_channel *c0,
1925 const union tgsi_exec_channel *c1,
1926 float derivs[3][2][TGSI_QUAD_SIZE],
1927 const int8_t offset[3],
1928 enum tgsi_sampler_control control,
1929 union tgsi_exec_channel *r,
1930 union tgsi_exec_channel *g,
1931 union tgsi_exec_channel *b,
1932 union tgsi_exec_channel *a )
1933 {
1934 uint j;
1935 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1936
1937 /* FIXME: handle explicit derivs, offsets */
1938 sampler->get_samples(sampler, sview_idx, sampler_idx,
1939 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1940
1941 for (j = 0; j < 4; j++) {
1942 r->f[j] = rgba[0][j];
1943 g->f[j] = rgba[1][j];
1944 b->f[j] = rgba[2][j];
1945 a->f[j] = rgba[3][j];
1946 }
1947 }
1948
1949
1950 #define TEX_MODIFIER_NONE 0
1951 #define TEX_MODIFIER_PROJECTED 1
1952 #define TEX_MODIFIER_LOD_BIAS 2
1953 #define TEX_MODIFIER_EXPLICIT_LOD 3
1954 #define TEX_MODIFIER_LEVEL_ZERO 4
1955
1956
1957 /*
1958 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1959 */
1960 static void
1961 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1962 const struct tgsi_full_instruction *inst,
1963 int8_t offsets[3])
1964 {
1965 if (inst->Texture.NumOffsets == 1) {
1966 union tgsi_exec_channel index;
1967 union tgsi_exec_channel offset[3];
1968 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1969 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1970 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1971 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1972 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1973 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1974 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1975 offsets[0] = offset[0].i[0];
1976 offsets[1] = offset[1].i[0];
1977 offsets[2] = offset[2].i[0];
1978 } else {
1979 assert(inst->Texture.NumOffsets == 0);
1980 offsets[0] = offsets[1] = offsets[2] = 0;
1981 }
1982 }
1983
1984
1985 /*
1986 * Fetch dx and dy values for one channel (s, t or r).
1987 * Put dx values into one float array, dy values into another.
1988 */
1989 static void
1990 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1991 const struct tgsi_full_instruction *inst,
1992 unsigned regdsrcx,
1993 unsigned chan,
1994 float derivs[2][TGSI_QUAD_SIZE])
1995 {
1996 union tgsi_exec_channel d;
1997 FETCH(&d, regdsrcx, chan);
1998 derivs[0][0] = d.f[0];
1999 derivs[0][1] = d.f[1];
2000 derivs[0][2] = d.f[2];
2001 derivs[0][3] = d.f[3];
2002 FETCH(&d, regdsrcx + 1, chan);
2003 derivs[1][0] = d.f[0];
2004 derivs[1][1] = d.f[1];
2005 derivs[1][2] = d.f[2];
2006 derivs[1][3] = d.f[3];
2007 }
2008
2009
2010 /*
2011 * execute a texture instruction.
2012 *
2013 * modifier is used to control the channel routing for the\
2014 * instruction variants like proj, lod, and texture with lod bias.
2015 * sampler indicates which src register the sampler is contained in.
2016 */
2017 static void
2018 exec_tex(struct tgsi_exec_machine *mach,
2019 const struct tgsi_full_instruction *inst,
2020 uint modifier, uint sampler)
2021 {
2022 const uint unit = inst->Src[sampler].Register.Index;
2023 const union tgsi_exec_channel *args[5], *proj = NULL;
2024 union tgsi_exec_channel r[5];
2025 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2026 uint chan;
2027 int8_t offsets[3];
2028 int dim, shadow_ref, i;
2029
2030 /* always fetch all 3 offsets, overkill but keeps code simple */
2031 fetch_texel_offsets(mach, inst, offsets);
2032
2033 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2034 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2035
2036 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
2037
2038 assert(dim <= 4);
2039 if (shadow_ref >= 0)
2040 assert(shadow_ref >= dim && shadow_ref < Elements(args));
2041
2042 /* fetch modifier to the last argument */
2043 if (modifier != TEX_MODIFIER_NONE) {
2044 const int last = Elements(args) - 1;
2045
2046 /* fetch modifier from src0.w or src1.x */
2047 if (sampler == 1) {
2048 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2049 FETCH(&r[last], 0, TGSI_CHAN_W);
2050 }
2051 else {
2052 assert(shadow_ref != 4);
2053 FETCH(&r[last], 1, TGSI_CHAN_X);
2054 }
2055
2056 if (modifier != TEX_MODIFIER_PROJECTED) {
2057 args[last] = &r[last];
2058 }
2059 else {
2060 proj = &r[last];
2061 args[last] = &ZeroVec;
2062 }
2063
2064 /* point unused arguments to zero vector */
2065 for (i = dim; i < last; i++)
2066 args[i] = &ZeroVec;
2067
2068 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2069 control = tgsi_sampler_lod_explicit;
2070 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2071 control = tgsi_sampler_lod_bias;
2072 }
2073 else {
2074 for (i = dim; i < Elements(args); i++)
2075 args[i] = &ZeroVec;
2076 }
2077
2078 /* fetch coordinates */
2079 for (i = 0; i < dim; i++) {
2080 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2081
2082 if (proj)
2083 micro_div(&r[i], &r[i], proj);
2084
2085 args[i] = &r[i];
2086 }
2087
2088 /* fetch reference value */
2089 if (shadow_ref >= 0) {
2090 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2091
2092 if (proj)
2093 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2094
2095 args[shadow_ref] = &r[shadow_ref];
2096 }
2097
2098 fetch_texel(mach->Sampler, unit, unit,
2099 args[0], args[1], args[2], args[3], args[4],
2100 NULL, offsets, control,
2101 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2102
2103 #if 0
2104 debug_printf("fetch r: %g %g %g %g\n",
2105 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2106 debug_printf("fetch g: %g %g %g %g\n",
2107 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2108 debug_printf("fetch b: %g %g %g %g\n",
2109 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2110 debug_printf("fetch a: %g %g %g %g\n",
2111 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2112 #endif
2113
2114 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2115 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2116 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2117 }
2118 }
2119 }
2120
2121
2122 static void
2123 exec_txd(struct tgsi_exec_machine *mach,
2124 const struct tgsi_full_instruction *inst)
2125 {
2126 const uint unit = inst->Src[3].Register.Index;
2127 union tgsi_exec_channel r[4];
2128 float derivs[3][2][TGSI_QUAD_SIZE];
2129 uint chan;
2130 int8_t offsets[3];
2131
2132 /* always fetch all 3 offsets, overkill but keeps code simple */
2133 fetch_texel_offsets(mach, inst, offsets);
2134
2135 switch (inst->Texture.Texture) {
2136 case TGSI_TEXTURE_1D:
2137 FETCH(&r[0], 0, TGSI_CHAN_X);
2138
2139 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2140
2141 fetch_texel(mach->Sampler, unit, unit,
2142 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2143 derivs, offsets, tgsi_sampler_derivs_explicit,
2144 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2145 break;
2146
2147 case TGSI_TEXTURE_SHADOW1D:
2148 case TGSI_TEXTURE_1D_ARRAY:
2149 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2150 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2151 FETCH(&r[0], 0, TGSI_CHAN_X);
2152 FETCH(&r[1], 0, TGSI_CHAN_Y);
2153 FETCH(&r[2], 0, TGSI_CHAN_Z);
2154
2155 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2156
2157 fetch_texel(mach->Sampler, unit, unit,
2158 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2159 derivs, offsets, tgsi_sampler_derivs_explicit,
2160 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2161 break;
2162
2163 case TGSI_TEXTURE_2D:
2164 case TGSI_TEXTURE_RECT:
2165 FETCH(&r[0], 0, TGSI_CHAN_X);
2166 FETCH(&r[1], 0, TGSI_CHAN_Y);
2167
2168 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2169 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2170
2171 fetch_texel(mach->Sampler, unit, unit,
2172 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2173 derivs, offsets, tgsi_sampler_derivs_explicit,
2174 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2175 break;
2176
2177
2178 case TGSI_TEXTURE_SHADOW2D:
2179 case TGSI_TEXTURE_SHADOWRECT:
2180 case TGSI_TEXTURE_2D_ARRAY:
2181 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2182 /* only SHADOW2D_ARRAY actually needs W */
2183 FETCH(&r[0], 0, TGSI_CHAN_X);
2184 FETCH(&r[1], 0, TGSI_CHAN_Y);
2185 FETCH(&r[2], 0, TGSI_CHAN_Z);
2186 FETCH(&r[3], 0, TGSI_CHAN_W);
2187
2188 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2189 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2190
2191 fetch_texel(mach->Sampler, unit, unit,
2192 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2193 derivs, offsets, tgsi_sampler_derivs_explicit,
2194 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2195 break;
2196
2197 case TGSI_TEXTURE_3D:
2198 case TGSI_TEXTURE_CUBE:
2199 case TGSI_TEXTURE_CUBE_ARRAY:
2200 case TGSI_TEXTURE_SHADOWCUBE:
2201 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2202 FETCH(&r[0], 0, TGSI_CHAN_X);
2203 FETCH(&r[1], 0, TGSI_CHAN_Y);
2204 FETCH(&r[2], 0, TGSI_CHAN_Z);
2205 FETCH(&r[3], 0, TGSI_CHAN_W);
2206
2207 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2208 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2209 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2210
2211 fetch_texel(mach->Sampler, unit, unit,
2212 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2213 derivs, offsets, tgsi_sampler_derivs_explicit,
2214 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2215 break;
2216
2217 default:
2218 assert(0);
2219 }
2220
2221 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2222 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2223 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2224 }
2225 }
2226 }
2227
2228
2229 static void
2230 exec_txf(struct tgsi_exec_machine *mach,
2231 const struct tgsi_full_instruction *inst)
2232 {
2233 const uint unit = inst->Src[1].Register.Index;
2234 union tgsi_exec_channel r[4];
2235 uint chan;
2236 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2237 int j;
2238 int8_t offsets[3];
2239 unsigned target;
2240
2241 /* always fetch all 3 offsets, overkill but keeps code simple */
2242 fetch_texel_offsets(mach, inst, offsets);
2243
2244 IFETCH(&r[3], 0, TGSI_CHAN_W);
2245
2246 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2247 target = mach->SamplerViews[unit].Resource;
2248 }
2249 else {
2250 target = inst->Texture.Texture;
2251 }
2252 switch(target) {
2253 case TGSI_TEXTURE_3D:
2254 case TGSI_TEXTURE_2D_ARRAY:
2255 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2256 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2257 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2258 /* fallthrough */
2259 case TGSI_TEXTURE_2D:
2260 case TGSI_TEXTURE_RECT:
2261 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2262 case TGSI_TEXTURE_SHADOW2D:
2263 case TGSI_TEXTURE_SHADOWRECT:
2264 case TGSI_TEXTURE_1D_ARRAY:
2265 case TGSI_TEXTURE_2D_MSAA:
2266 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2267 /* fallthrough */
2268 case TGSI_TEXTURE_BUFFER:
2269 case TGSI_TEXTURE_1D:
2270 case TGSI_TEXTURE_SHADOW1D:
2271 IFETCH(&r[0], 0, TGSI_CHAN_X);
2272 break;
2273 default:
2274 assert(0);
2275 break;
2276 }
2277
2278 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2279 offsets, rgba);
2280
2281 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2282 r[0].f[j] = rgba[0][j];
2283 r[1].f[j] = rgba[1][j];
2284 r[2].f[j] = rgba[2][j];
2285 r[3].f[j] = rgba[3][j];
2286 }
2287
2288 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2289 unsigned char swizzles[4];
2290 swizzles[0] = inst->Src[1].Register.SwizzleX;
2291 swizzles[1] = inst->Src[1].Register.SwizzleY;
2292 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2293 swizzles[3] = inst->Src[1].Register.SwizzleW;
2294
2295 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2296 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2297 store_dest(mach, &r[swizzles[chan]],
2298 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2299 }
2300 }
2301 }
2302 else {
2303 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2304 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2305 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2306 }
2307 }
2308 }
2309 }
2310
2311 static void
2312 exec_txq(struct tgsi_exec_machine *mach,
2313 const struct tgsi_full_instruction *inst)
2314 {
2315 const uint unit = inst->Src[1].Register.Index;
2316 int result[4];
2317 union tgsi_exec_channel r[4], src;
2318 uint chan;
2319 int i,j;
2320
2321 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2322
2323 /* XXX: This interface can't return per-pixel values */
2324 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2325
2326 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2327 for (j = 0; j < 4; j++) {
2328 r[j].i[i] = result[j];
2329 }
2330 }
2331
2332 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2333 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2334 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2335 TGSI_EXEC_DATA_INT);
2336 }
2337 }
2338 }
2339
2340 static void
2341 exec_sample(struct tgsi_exec_machine *mach,
2342 const struct tgsi_full_instruction *inst,
2343 uint modifier, boolean compare)
2344 {
2345 const uint resource_unit = inst->Src[1].Register.Index;
2346 const uint sampler_unit = inst->Src[2].Register.Index;
2347 union tgsi_exec_channel r[4], c1;
2348 const union tgsi_exec_channel *lod = &ZeroVec;
2349 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2350 uint chan;
2351 unsigned char swizzles[4];
2352 int8_t offsets[3];
2353
2354 /* always fetch all 3 offsets, overkill but keeps code simple */
2355 fetch_texel_offsets(mach, inst, offsets);
2356
2357 assert(modifier != TEX_MODIFIER_PROJECTED);
2358
2359 if (modifier != TEX_MODIFIER_NONE) {
2360 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2361 FETCH(&c1, 3, TGSI_CHAN_X);
2362 lod = &c1;
2363 control = tgsi_sampler_lod_bias;
2364 }
2365 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2366 FETCH(&c1, 3, TGSI_CHAN_X);
2367 lod = &c1;
2368 control = tgsi_sampler_lod_explicit;
2369 }
2370 else {
2371 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2372 control = tgsi_sampler_lod_zero;
2373 }
2374 }
2375
2376 FETCH(&r[0], 0, TGSI_CHAN_X);
2377
2378 switch (mach->SamplerViews[resource_unit].Resource) {
2379 case TGSI_TEXTURE_1D:
2380 if (compare) {
2381 FETCH(&r[2], 3, TGSI_CHAN_X);
2382 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2383 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2384 NULL, offsets, control,
2385 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2386 }
2387 else {
2388 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2389 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2390 NULL, offsets, control,
2391 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2392 }
2393 break;
2394
2395 case TGSI_TEXTURE_1D_ARRAY:
2396 case TGSI_TEXTURE_2D:
2397 case TGSI_TEXTURE_RECT:
2398 FETCH(&r[1], 0, TGSI_CHAN_Y);
2399 if (compare) {
2400 FETCH(&r[2], 3, TGSI_CHAN_X);
2401 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2402 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2403 NULL, offsets, control,
2404 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2405 }
2406 else {
2407 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2408 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2409 NULL, offsets, control,
2410 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2411 }
2412 break;
2413
2414 case TGSI_TEXTURE_2D_ARRAY:
2415 case TGSI_TEXTURE_3D:
2416 case TGSI_TEXTURE_CUBE:
2417 FETCH(&r[1], 0, TGSI_CHAN_Y);
2418 FETCH(&r[2], 0, TGSI_CHAN_Z);
2419 if(compare) {
2420 FETCH(&r[3], 3, TGSI_CHAN_X);
2421 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2422 &r[0], &r[1], &r[2], &r[3], lod,
2423 NULL, offsets, control,
2424 &r[0], &r[1], &r[2], &r[3]);
2425 }
2426 else {
2427 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2428 &r[0], &r[1], &r[2], &ZeroVec, lod,
2429 NULL, offsets, control,
2430 &r[0], &r[1], &r[2], &r[3]);
2431 }
2432 break;
2433
2434 case TGSI_TEXTURE_CUBE_ARRAY:
2435 FETCH(&r[1], 0, TGSI_CHAN_Y);
2436 FETCH(&r[2], 0, TGSI_CHAN_Z);
2437 FETCH(&r[3], 0, TGSI_CHAN_W);
2438 if(compare) {
2439 FETCH(&r[4], 3, TGSI_CHAN_X);
2440 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2441 &r[0], &r[1], &r[2], &r[3], &r[4],
2442 NULL, offsets, control,
2443 &r[0], &r[1], &r[2], &r[3]);
2444 }
2445 else {
2446 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2447 &r[0], &r[1], &r[2], &r[3], lod,
2448 NULL, offsets, control,
2449 &r[0], &r[1], &r[2], &r[3]);
2450 }
2451 break;
2452
2453
2454 default:
2455 assert(0);
2456 }
2457
2458 swizzles[0] = inst->Src[1].Register.SwizzleX;
2459 swizzles[1] = inst->Src[1].Register.SwizzleY;
2460 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2461 swizzles[3] = inst->Src[1].Register.SwizzleW;
2462
2463 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2464 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2465 store_dest(mach, &r[swizzles[chan]],
2466 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2467 }
2468 }
2469 }
2470
2471 static void
2472 exec_sample_d(struct tgsi_exec_machine *mach,
2473 const struct tgsi_full_instruction *inst)
2474 {
2475 const uint resource_unit = inst->Src[1].Register.Index;
2476 const uint sampler_unit = inst->Src[2].Register.Index;
2477 union tgsi_exec_channel r[4];
2478 float derivs[3][2][TGSI_QUAD_SIZE];
2479 uint chan;
2480 unsigned char swizzles[4];
2481 int8_t offsets[3];
2482
2483 /* always fetch all 3 offsets, overkill but keeps code simple */
2484 fetch_texel_offsets(mach, inst, offsets);
2485
2486 FETCH(&r[0], 0, TGSI_CHAN_X);
2487
2488 switch (mach->SamplerViews[resource_unit].Resource) {
2489 case TGSI_TEXTURE_1D:
2490 case TGSI_TEXTURE_1D_ARRAY:
2491 /* only 1D array actually needs Y */
2492 FETCH(&r[1], 0, TGSI_CHAN_Y);
2493
2494 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2495
2496 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2497 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2498 derivs, offsets, tgsi_sampler_derivs_explicit,
2499 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2500 break;
2501
2502 case TGSI_TEXTURE_2D:
2503 case TGSI_TEXTURE_RECT:
2504 case TGSI_TEXTURE_2D_ARRAY:
2505 /* only 2D array actually needs Z */
2506 FETCH(&r[1], 0, TGSI_CHAN_Y);
2507 FETCH(&r[2], 0, TGSI_CHAN_Z);
2508
2509 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2510 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2511
2512 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2513 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2514 derivs, offsets, tgsi_sampler_derivs_explicit,
2515 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2516 break;
2517
2518 case TGSI_TEXTURE_3D:
2519 case TGSI_TEXTURE_CUBE:
2520 case TGSI_TEXTURE_CUBE_ARRAY:
2521 /* only cube array actually needs W */
2522 FETCH(&r[1], 0, TGSI_CHAN_Y);
2523 FETCH(&r[2], 0, TGSI_CHAN_Z);
2524 FETCH(&r[3], 0, TGSI_CHAN_W);
2525
2526 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2527 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2528 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2529
2530 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2531 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2532 derivs, offsets, tgsi_sampler_derivs_explicit,
2533 &r[0], &r[1], &r[2], &r[3]);
2534 break;
2535
2536 default:
2537 assert(0);
2538 }
2539
2540 swizzles[0] = inst->Src[1].Register.SwizzleX;
2541 swizzles[1] = inst->Src[1].Register.SwizzleY;
2542 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2543 swizzles[3] = inst->Src[1].Register.SwizzleW;
2544
2545 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2546 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2547 store_dest(mach, &r[swizzles[chan]],
2548 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2549 }
2550 }
2551 }
2552
2553
2554 /**
2555 * Evaluate a constant-valued coefficient at the position of the
2556 * current quad.
2557 */
2558 static void
2559 eval_constant_coef(
2560 struct tgsi_exec_machine *mach,
2561 unsigned attrib,
2562 unsigned chan )
2563 {
2564 unsigned i;
2565
2566 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2567 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2568 }
2569 }
2570
2571 /**
2572 * Evaluate a linear-valued coefficient at the position of the
2573 * current quad.
2574 */
2575 static void
2576 eval_linear_coef(
2577 struct tgsi_exec_machine *mach,
2578 unsigned attrib,
2579 unsigned chan )
2580 {
2581 const float x = mach->QuadPos.xyzw[0].f[0];
2582 const float y = mach->QuadPos.xyzw[1].f[0];
2583 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2584 const float dady = mach->InterpCoefs[attrib].dady[chan];
2585 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2586 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2587 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2588 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2589 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2590 }
2591
2592 /**
2593 * Evaluate a perspective-valued coefficient at the position of the
2594 * current quad.
2595 */
2596 static void
2597 eval_perspective_coef(
2598 struct tgsi_exec_machine *mach,
2599 unsigned attrib,
2600 unsigned chan )
2601 {
2602 const float x = mach->QuadPos.xyzw[0].f[0];
2603 const float y = mach->QuadPos.xyzw[1].f[0];
2604 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2605 const float dady = mach->InterpCoefs[attrib].dady[chan];
2606 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2607 const float *w = mach->QuadPos.xyzw[3].f;
2608 /* divide by W here */
2609 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2610 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2611 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2612 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2613 }
2614
2615
2616 typedef void (* eval_coef_func)(
2617 struct tgsi_exec_machine *mach,
2618 unsigned attrib,
2619 unsigned chan );
2620
2621 static void
2622 exec_declaration(struct tgsi_exec_machine *mach,
2623 const struct tgsi_full_declaration *decl)
2624 {
2625 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2626 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2627 return;
2628 }
2629
2630 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2631 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2632 uint first, last, mask;
2633
2634 first = decl->Range.First;
2635 last = decl->Range.Last;
2636 mask = decl->Declaration.UsageMask;
2637
2638 /* XXX we could remove this special-case code since
2639 * mach->InterpCoefs[first].a0 should already have the
2640 * front/back-face value. But we should first update the
2641 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2642 * Then, we could remove the tgsi_exec_machine::Face field.
2643 */
2644 /* XXX make FACE a system value */
2645 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2646 uint i;
2647
2648 assert(decl->Semantic.Index == 0);
2649 assert(first == last);
2650
2651 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2652 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2653 }
2654 } else {
2655 eval_coef_func eval;
2656 uint i, j;
2657
2658 switch (decl->Interp.Interpolate) {
2659 case TGSI_INTERPOLATE_CONSTANT:
2660 eval = eval_constant_coef;
2661 break;
2662
2663 case TGSI_INTERPOLATE_LINEAR:
2664 eval = eval_linear_coef;
2665 break;
2666
2667 case TGSI_INTERPOLATE_PERSPECTIVE:
2668 eval = eval_perspective_coef;
2669 break;
2670
2671 case TGSI_INTERPOLATE_COLOR:
2672 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2673 break;
2674
2675 default:
2676 assert(0);
2677 return;
2678 }
2679
2680 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2681 if (mask & (1 << j)) {
2682 for (i = first; i <= last; i++) {
2683 eval(mach, i, j);
2684 }
2685 }
2686 }
2687 }
2688
2689 if (DEBUG_EXECUTION) {
2690 uint i, j;
2691 for (i = first; i <= last; ++i) {
2692 debug_printf("IN[%2u] = ", i);
2693 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2694 if (j > 0) {
2695 debug_printf(" ");
2696 }
2697 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2698 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2699 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2700 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2701 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2702 }
2703 }
2704 }
2705 }
2706 }
2707
2708 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2709 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2710 }
2711 }
2712
2713 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2714 const union tgsi_exec_channel *src);
2715
2716 static void
2717 exec_scalar_unary(struct tgsi_exec_machine *mach,
2718 const struct tgsi_full_instruction *inst,
2719 micro_unary_op op,
2720 enum tgsi_exec_datatype dst_datatype,
2721 enum tgsi_exec_datatype src_datatype)
2722 {
2723 unsigned int chan;
2724 union tgsi_exec_channel src;
2725 union tgsi_exec_channel dst;
2726
2727 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2728 op(&dst, &src);
2729 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2730 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2731 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2732 }
2733 }
2734 }
2735
2736 static void
2737 exec_vector_unary(struct tgsi_exec_machine *mach,
2738 const struct tgsi_full_instruction *inst,
2739 micro_unary_op op,
2740 enum tgsi_exec_datatype dst_datatype,
2741 enum tgsi_exec_datatype src_datatype)
2742 {
2743 unsigned int chan;
2744 struct tgsi_exec_vector dst;
2745
2746 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2747 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2748 union tgsi_exec_channel src;
2749
2750 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2751 op(&dst.xyzw[chan], &src);
2752 }
2753 }
2754 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2755 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2756 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2757 }
2758 }
2759 }
2760
2761 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2762 const union tgsi_exec_channel *src0,
2763 const union tgsi_exec_channel *src1);
2764
2765 static void
2766 exec_scalar_binary(struct tgsi_exec_machine *mach,
2767 const struct tgsi_full_instruction *inst,
2768 micro_binary_op op,
2769 enum tgsi_exec_datatype dst_datatype,
2770 enum tgsi_exec_datatype src_datatype)
2771 {
2772 unsigned int chan;
2773 union tgsi_exec_channel src[2];
2774 union tgsi_exec_channel dst;
2775
2776 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2777 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2778 op(&dst, &src[0], &src[1]);
2779 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2780 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2781 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2782 }
2783 }
2784 }
2785
2786 static void
2787 exec_vector_binary(struct tgsi_exec_machine *mach,
2788 const struct tgsi_full_instruction *inst,
2789 micro_binary_op op,
2790 enum tgsi_exec_datatype dst_datatype,
2791 enum tgsi_exec_datatype src_datatype)
2792 {
2793 unsigned int chan;
2794 struct tgsi_exec_vector dst;
2795
2796 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2797 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2798 union tgsi_exec_channel src[2];
2799
2800 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2801 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2802 op(&dst.xyzw[chan], &src[0], &src[1]);
2803 }
2804 }
2805 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2806 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2807 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2808 }
2809 }
2810 }
2811
2812 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2813 const union tgsi_exec_channel *src0,
2814 const union tgsi_exec_channel *src1,
2815 const union tgsi_exec_channel *src2);
2816
2817 static void
2818 exec_vector_trinary(struct tgsi_exec_machine *mach,
2819 const struct tgsi_full_instruction *inst,
2820 micro_trinary_op op,
2821 enum tgsi_exec_datatype dst_datatype,
2822 enum tgsi_exec_datatype src_datatype)
2823 {
2824 unsigned int chan;
2825 struct tgsi_exec_vector dst;
2826
2827 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2828 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2829 union tgsi_exec_channel src[3];
2830
2831 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2832 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2833 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2834 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2835 }
2836 }
2837 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2838 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2839 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2840 }
2841 }
2842 }
2843
2844 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2845 const union tgsi_exec_channel *src0,
2846 const union tgsi_exec_channel *src1,
2847 const union tgsi_exec_channel *src2,
2848 const union tgsi_exec_channel *src3);
2849
2850 static void
2851 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2852 const struct tgsi_full_instruction *inst,
2853 micro_quaternary_op op,
2854 enum tgsi_exec_datatype dst_datatype,
2855 enum tgsi_exec_datatype src_datatype)
2856 {
2857 unsigned int chan;
2858 struct tgsi_exec_vector dst;
2859
2860 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2861 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2862 union tgsi_exec_channel src[4];
2863
2864 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2865 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2866 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2867 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2868 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2869 }
2870 }
2871 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2872 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2873 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2874 }
2875 }
2876 }
2877
2878 static void
2879 exec_dp3(struct tgsi_exec_machine *mach,
2880 const struct tgsi_full_instruction *inst)
2881 {
2882 unsigned int chan;
2883 union tgsi_exec_channel arg[3];
2884
2885 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2886 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2887 micro_mul(&arg[2], &arg[0], &arg[1]);
2888
2889 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2890 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2891 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2892 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2893 }
2894
2895 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2896 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2897 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2898 }
2899 }
2900 }
2901
2902 static void
2903 exec_dp4(struct tgsi_exec_machine *mach,
2904 const struct tgsi_full_instruction *inst)
2905 {
2906 unsigned int chan;
2907 union tgsi_exec_channel arg[3];
2908
2909 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2910 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2911 micro_mul(&arg[2], &arg[0], &arg[1]);
2912
2913 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2914 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2915 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2916 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2917 }
2918
2919 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2920 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2921 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2922 }
2923 }
2924 }
2925
2926 static void
2927 exec_dp2a(struct tgsi_exec_machine *mach,
2928 const struct tgsi_full_instruction *inst)
2929 {
2930 unsigned int chan;
2931 union tgsi_exec_channel arg[3];
2932
2933 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2934 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2935 micro_mul(&arg[2], &arg[0], &arg[1]);
2936
2937 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2938 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2939 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2940
2941 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2942 micro_add(&arg[0], &arg[0], &arg[1]);
2943
2944 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2945 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2946 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2947 }
2948 }
2949 }
2950
2951 static void
2952 exec_dph(struct tgsi_exec_machine *mach,
2953 const struct tgsi_full_instruction *inst)
2954 {
2955 unsigned int chan;
2956 union tgsi_exec_channel arg[3];
2957
2958 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2959 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2960 micro_mul(&arg[2], &arg[0], &arg[1]);
2961
2962 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2963 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2964 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2965
2966 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2967 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2968 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2969
2970 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2971 micro_add(&arg[0], &arg[0], &arg[1]);
2972
2973 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2974 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2975 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2976 }
2977 }
2978 }
2979
2980 static void
2981 exec_dp2(struct tgsi_exec_machine *mach,
2982 const struct tgsi_full_instruction *inst)
2983 {
2984 unsigned int chan;
2985 union tgsi_exec_channel arg[3];
2986
2987 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2988 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2989 micro_mul(&arg[2], &arg[0], &arg[1]);
2990
2991 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2992 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2993 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2994
2995 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2996 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2997 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2998 }
2999 }
3000 }
3001
3002 static void
3003 exec_scs(struct tgsi_exec_machine *mach,
3004 const struct tgsi_full_instruction *inst)
3005 {
3006 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
3007 union tgsi_exec_channel arg;
3008 union tgsi_exec_channel result;
3009
3010 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3011
3012 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3013 micro_cos(&result, &arg);
3014 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3015 }
3016 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3017 micro_sin(&result, &arg);
3018 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3019 }
3020 }
3021 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3022 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3023 }
3024 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3025 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3026 }
3027 }
3028
3029 static void
3030 exec_xpd(struct tgsi_exec_machine *mach,
3031 const struct tgsi_full_instruction *inst)
3032 {
3033 union tgsi_exec_channel r[6];
3034 union tgsi_exec_channel d[3];
3035
3036 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3037 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3038
3039 micro_mul(&r[2], &r[0], &r[1]);
3040
3041 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3042 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3043
3044 micro_mul(&r[5], &r[3], &r[4] );
3045 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
3046
3047 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3048
3049 micro_mul(&r[3], &r[3], &r[2]);
3050
3051 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3052
3053 micro_mul(&r[1], &r[1], &r[5]);
3054 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
3055
3056 micro_mul(&r[5], &r[5], &r[4]);
3057 micro_mul(&r[0], &r[0], &r[2]);
3058 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
3059
3060 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3061 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3062 }
3063 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3064 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3065 }
3066 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3067 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3068 }
3069 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3070 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3071 }
3072 }
3073
3074 static void
3075 exec_dst(struct tgsi_exec_machine *mach,
3076 const struct tgsi_full_instruction *inst)
3077 {
3078 union tgsi_exec_channel r[2];
3079 union tgsi_exec_channel d[4];
3080
3081 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3082 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3083 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3084 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3085 }
3086 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3087 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3088 }
3089 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3090 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3091 }
3092
3093 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3094 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3095 }
3096 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3097 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3098 }
3099 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3100 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3101 }
3102 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3103 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3104 }
3105 }
3106
3107 static void
3108 exec_log(struct tgsi_exec_machine *mach,
3109 const struct tgsi_full_instruction *inst)
3110 {
3111 union tgsi_exec_channel r[3];
3112
3113 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3114 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3115 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3116 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3117 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3118 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3119 }
3120 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3121 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3122 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3123 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3124 }
3125 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3126 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3127 }
3128 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3129 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3130 }
3131 }
3132
3133 static void
3134 exec_exp(struct tgsi_exec_machine *mach,
3135 const struct tgsi_full_instruction *inst)
3136 {
3137 union tgsi_exec_channel r[3];
3138
3139 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3140 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3141 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3142 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3143 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3144 }
3145 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3146 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3147 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3148 }
3149 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3150 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3151 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3152 }
3153 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3154 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3155 }
3156 }
3157
3158 static void
3159 exec_lit(struct tgsi_exec_machine *mach,
3160 const struct tgsi_full_instruction *inst)
3161 {
3162 union tgsi_exec_channel r[3];
3163 union tgsi_exec_channel d[3];
3164
3165 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3166 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3167 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3168 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3169 micro_max(&r[1], &r[1], &ZeroVec);
3170
3171 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3172 micro_min(&r[2], &r[2], &P128Vec);
3173 micro_max(&r[2], &r[2], &M128Vec);
3174 micro_pow(&r[1], &r[1], &r[2]);
3175 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3176 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3177 }
3178 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3179 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3180 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3181 }
3182 }
3183 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3184 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3185 }
3186
3187 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3188 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3189 }
3190 }
3191
3192 static void
3193 exec_break(struct tgsi_exec_machine *mach)
3194 {
3195 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3196 /* turn off loop channels for each enabled exec channel */
3197 mach->LoopMask &= ~mach->ExecMask;
3198 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3199 UPDATE_EXEC_MASK(mach);
3200 } else {
3201 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3202
3203 mach->Switch.mask = 0x0;
3204
3205 UPDATE_EXEC_MASK(mach);
3206 }
3207 }
3208
3209 static void
3210 exec_switch(struct tgsi_exec_machine *mach,
3211 const struct tgsi_full_instruction *inst)
3212 {
3213 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3214 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3215
3216 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3217 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3218 mach->Switch.mask = 0x0;
3219 mach->Switch.defaultMask = 0x0;
3220
3221 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3222 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3223
3224 UPDATE_EXEC_MASK(mach);
3225 }
3226
3227 static void
3228 exec_case(struct tgsi_exec_machine *mach,
3229 const struct tgsi_full_instruction *inst)
3230 {
3231 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3232 union tgsi_exec_channel src;
3233 uint mask = 0;
3234
3235 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3236
3237 if (mach->Switch.selector.u[0] == src.u[0]) {
3238 mask |= 0x1;
3239 }
3240 if (mach->Switch.selector.u[1] == src.u[1]) {
3241 mask |= 0x2;
3242 }
3243 if (mach->Switch.selector.u[2] == src.u[2]) {
3244 mask |= 0x4;
3245 }
3246 if (mach->Switch.selector.u[3] == src.u[3]) {
3247 mask |= 0x8;
3248 }
3249
3250 mach->Switch.defaultMask |= mask;
3251
3252 mach->Switch.mask |= mask & prevMask;
3253
3254 UPDATE_EXEC_MASK(mach);
3255 }
3256
3257 /* FIXME: this will only work if default is last */
3258 static void
3259 exec_default(struct tgsi_exec_machine *mach)
3260 {
3261 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3262
3263 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3264
3265 UPDATE_EXEC_MASK(mach);
3266 }
3267
3268 static void
3269 exec_endswitch(struct tgsi_exec_machine *mach)
3270 {
3271 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3272 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3273
3274 UPDATE_EXEC_MASK(mach);
3275 }
3276
3277 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3278 const union tgsi_double_channel *src);
3279
3280 static void
3281 fetch_double_channel(struct tgsi_exec_machine *mach,
3282 union tgsi_double_channel *chan,
3283 const struct tgsi_full_src_register *reg,
3284 uint chan_0,
3285 uint chan_1)
3286 {
3287 union tgsi_exec_channel src[2];
3288 uint i;
3289
3290 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3291 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3292
3293 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3294 chan->u[i][0] = src[0].u[i];
3295 chan->u[i][1] = src[1].u[i];
3296 }
3297 if (reg->Register.Absolute) {
3298 micro_dabs(chan, chan);
3299 }
3300 if (reg->Register.Negate) {
3301 micro_dneg(chan, chan);
3302 }
3303 }
3304
3305 static void
3306 store_double_channel(struct tgsi_exec_machine *mach,
3307 const union tgsi_double_channel *chan,
3308 const struct tgsi_full_dst_register *reg,
3309 const struct tgsi_full_instruction *inst,
3310 uint chan_0,
3311 uint chan_1)
3312 {
3313 union tgsi_exec_channel dst[2];
3314 uint i;
3315 union tgsi_double_channel temp;
3316 const uint execmask = mach->ExecMask;
3317
3318 switch (inst->Instruction.Saturate) {
3319 case TGSI_SAT_NONE:
3320 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3321 if (execmask & (1 << i)) {
3322 dst[0].u[i] = chan->u[i][0];
3323 dst[1].u[i] = chan->u[i][1];
3324 }
3325 break;
3326
3327 case TGSI_SAT_ZERO_ONE:
3328 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3329 if (execmask & (1 << i)) {
3330 if (chan->d[i] < 0.0)
3331 temp.d[i] = 0.0;
3332 else if (chan->d[i] > 1.0)
3333 temp.d[i] = 1.0;
3334 else
3335 temp.d[i] = chan->d[i];
3336
3337 dst[0].u[i] = temp.u[i][0];
3338 dst[1].u[i] = temp.u[i][1];
3339 }
3340 break;
3341
3342 case TGSI_SAT_MINUS_PLUS_ONE:
3343 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3344 if (execmask & (1 << i)) {
3345 if (chan->d[i] < -1.0)
3346 temp.d[i] = -1.0;
3347 else if (chan->d[i] > 1.0)
3348 temp.d[i] = 1.0;
3349 else
3350 temp.d[i] = chan->d[i];
3351
3352 dst[0].u[i] = temp.u[i][0];
3353 dst[1].u[i] = temp.u[i][1];
3354 }
3355 break;
3356
3357 default:
3358 assert( 0 );
3359 }
3360
3361 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3362 if (chan_1 != -1)
3363 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3364 }
3365
3366 static void
3367 exec_double_unary(struct tgsi_exec_machine *mach,
3368 const struct tgsi_full_instruction *inst,
3369 micro_dop op)
3370 {
3371 union tgsi_double_channel src;
3372 union tgsi_double_channel dst;
3373
3374 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3375 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3376 op(&dst, &src);
3377 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3378 }
3379 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3380 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3381 op(&dst, &src);
3382 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3383 }
3384 }
3385
3386 static void
3387 exec_double_binary(struct tgsi_exec_machine *mach,
3388 const struct tgsi_full_instruction *inst,
3389 micro_dop op,
3390 enum tgsi_exec_datatype dst_datatype)
3391 {
3392 union tgsi_double_channel src[2];
3393 union tgsi_double_channel dst;
3394 int first_dest_chan, second_dest_chan;
3395 int wmask;
3396
3397 wmask = inst->Dst[0].Register.WriteMask;
3398 /* these are & because of the way DSLT etc store their destinations */
3399 if (wmask & TGSI_WRITEMASK_XY) {
3400 first_dest_chan = TGSI_CHAN_X;
3401 second_dest_chan = TGSI_CHAN_Y;
3402 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3403 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3404 second_dest_chan = -1;
3405 }
3406
3407 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3408 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3409 op(&dst, src);
3410 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3411 }
3412
3413 if (wmask & TGSI_WRITEMASK_ZW) {
3414 first_dest_chan = TGSI_CHAN_Z;
3415 second_dest_chan = TGSI_CHAN_W;
3416 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3417 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3418 second_dest_chan = -1;
3419 }
3420
3421 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3422 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3423 op(&dst, src);
3424 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3425 }
3426 }
3427
3428 static void
3429 exec_double_trinary(struct tgsi_exec_machine *mach,
3430 const struct tgsi_full_instruction *inst,
3431 micro_dop op)
3432 {
3433 union tgsi_double_channel src[3];
3434 union tgsi_double_channel dst;
3435
3436 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3437 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3438 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3439 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3440 op(&dst, src);
3441 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3442 }
3443 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3444 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3445 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3446 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3447 op(&dst, src);
3448 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3449 }
3450 }
3451
3452 static void
3453 exec_f2d(struct tgsi_exec_machine *mach,
3454 const struct tgsi_full_instruction *inst)
3455 {
3456 union tgsi_exec_channel src;
3457 union tgsi_double_channel dst;
3458
3459 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3460 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3461 micro_f2d(&dst, &src);
3462 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3463 }
3464 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3465 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3466 micro_f2d(&dst, &src);
3467 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3468 }
3469 }
3470
3471 static void
3472 exec_d2f(struct tgsi_exec_machine *mach,
3473 const struct tgsi_full_instruction *inst)
3474 {
3475 union tgsi_double_channel src;
3476 union tgsi_exec_channel dst;
3477 int wm = inst->Dst[0].Register.WriteMask;
3478 int i;
3479 int bit;
3480 for (i = 0; i < 2; i++) {
3481 bit = ffs(wm);
3482 if (bit) {
3483 wm &= ~(1 << (bit - 1));
3484 if (i == 0)
3485 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3486 else
3487 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3488 micro_d2f(&dst, &src);
3489 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_FLOAT);
3490 }
3491 }
3492 }
3493
3494 static void
3495 exec_i2d(struct tgsi_exec_machine *mach,
3496 const struct tgsi_full_instruction *inst)
3497 {
3498 union tgsi_exec_channel src;
3499 union tgsi_double_channel dst;
3500
3501 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3502 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3503 micro_i2d(&dst, &src);
3504 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3505 }
3506 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3507 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_INT);
3508 micro_i2d(&dst, &src);
3509 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3510 }
3511 }
3512
3513 static void
3514 exec_d2i(struct tgsi_exec_machine *mach,
3515 const struct tgsi_full_instruction *inst)
3516 {
3517 union tgsi_double_channel src;
3518 union tgsi_exec_channel dst;
3519 int wm = inst->Dst[0].Register.WriteMask;
3520 int i;
3521 int bit;
3522 for (i = 0; i < 2; i++) {
3523 bit = ffs(wm);
3524 if (bit) {
3525 wm &= ~(1 << (bit - 1));
3526 if (i == 0)
3527 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3528 else
3529 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3530 micro_d2i(&dst, &src);
3531 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_INT);
3532 }
3533 }
3534 }
3535 static void
3536 exec_u2d(struct tgsi_exec_machine *mach,
3537 const struct tgsi_full_instruction *inst)
3538 {
3539 union tgsi_exec_channel src;
3540 union tgsi_double_channel dst;
3541
3542 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3543 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3544 micro_u2d(&dst, &src);
3545 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3546 }
3547 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3548 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_UINT);
3549 micro_u2d(&dst, &src);
3550 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3551 }
3552 }
3553
3554 static void
3555 exec_d2u(struct tgsi_exec_machine *mach,
3556 const struct tgsi_full_instruction *inst)
3557 {
3558 union tgsi_double_channel src;
3559 union tgsi_exec_channel dst;
3560 int wm = inst->Dst[0].Register.WriteMask;
3561 int i;
3562 int bit;
3563 for (i = 0; i < 2; i++) {
3564 bit = ffs(wm);
3565 if (bit) {
3566 wm &= ~(1 << (bit - 1));
3567 if (i == 0)
3568 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3569 else
3570 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3571 micro_d2u(&dst, &src);
3572 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_UINT);
3573 }
3574 }
3575 }
3576
3577 static void
3578 exec_dldexp(struct tgsi_exec_machine *mach,
3579 const struct tgsi_full_instruction *inst)
3580 {
3581 union tgsi_double_channel src0;
3582 union tgsi_exec_channel src1;
3583 union tgsi_double_channel dst;
3584 int wmask;
3585
3586 wmask = inst->Dst[0].Register.WriteMask;
3587 if (wmask & TGSI_WRITEMASK_XY) {
3588 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3589 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3590 micro_dldexp(&dst, &src0, &src1);
3591 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3592 }
3593
3594 if (wmask & TGSI_WRITEMASK_ZW) {
3595 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3596 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3597 micro_dldexp(&dst, &src0, &src1);
3598 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3599 }
3600 }
3601
3602 static void
3603 exec_dfracexp(struct tgsi_exec_machine *mach,
3604 const struct tgsi_full_instruction *inst)
3605 {
3606 union tgsi_double_channel src;
3607 union tgsi_double_channel dst;
3608 union tgsi_exec_channel dst_exp;
3609
3610 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)) {
3611 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3612 micro_dfracexp(&dst, &dst_exp, &src);
3613 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3614 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3615 }
3616 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)) {
3617 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3618 micro_dfracexp(&dst, &dst_exp, &src);
3619 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3620 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3621 }
3622 }
3623
3624
3625 static void
3626 micro_i2f(union tgsi_exec_channel *dst,
3627 const union tgsi_exec_channel *src)
3628 {
3629 dst->f[0] = (float)src->i[0];
3630 dst->f[1] = (float)src->i[1];
3631 dst->f[2] = (float)src->i[2];
3632 dst->f[3] = (float)src->i[3];
3633 }
3634
3635 static void
3636 micro_not(union tgsi_exec_channel *dst,
3637 const union tgsi_exec_channel *src)
3638 {
3639 dst->u[0] = ~src->u[0];
3640 dst->u[1] = ~src->u[1];
3641 dst->u[2] = ~src->u[2];
3642 dst->u[3] = ~src->u[3];
3643 }
3644
3645 static void
3646 micro_shl(union tgsi_exec_channel *dst,
3647 const union tgsi_exec_channel *src0,
3648 const union tgsi_exec_channel *src1)
3649 {
3650 unsigned masked_count;
3651 masked_count = src1->u[0] & 0x1f;
3652 dst->u[0] = src0->u[0] << masked_count;
3653 masked_count = src1->u[1] & 0x1f;
3654 dst->u[1] = src0->u[1] << masked_count;
3655 masked_count = src1->u[2] & 0x1f;
3656 dst->u[2] = src0->u[2] << masked_count;
3657 masked_count = src1->u[3] & 0x1f;
3658 dst->u[3] = src0->u[3] << masked_count;
3659 }
3660
3661 static void
3662 micro_and(union tgsi_exec_channel *dst,
3663 const union tgsi_exec_channel *src0,
3664 const union tgsi_exec_channel *src1)
3665 {
3666 dst->u[0] = src0->u[0] & src1->u[0];
3667 dst->u[1] = src0->u[1] & src1->u[1];
3668 dst->u[2] = src0->u[2] & src1->u[2];
3669 dst->u[3] = src0->u[3] & src1->u[3];
3670 }
3671
3672 static void
3673 micro_or(union tgsi_exec_channel *dst,
3674 const union tgsi_exec_channel *src0,
3675 const union tgsi_exec_channel *src1)
3676 {
3677 dst->u[0] = src0->u[0] | src1->u[0];
3678 dst->u[1] = src0->u[1] | src1->u[1];
3679 dst->u[2] = src0->u[2] | src1->u[2];
3680 dst->u[3] = src0->u[3] | src1->u[3];
3681 }
3682
3683 static void
3684 micro_xor(union tgsi_exec_channel *dst,
3685 const union tgsi_exec_channel *src0,
3686 const union tgsi_exec_channel *src1)
3687 {
3688 dst->u[0] = src0->u[0] ^ src1->u[0];
3689 dst->u[1] = src0->u[1] ^ src1->u[1];
3690 dst->u[2] = src0->u[2] ^ src1->u[2];
3691 dst->u[3] = src0->u[3] ^ src1->u[3];
3692 }
3693
3694 static void
3695 micro_mod(union tgsi_exec_channel *dst,
3696 const union tgsi_exec_channel *src0,
3697 const union tgsi_exec_channel *src1)
3698 {
3699 dst->i[0] = src0->i[0] % src1->i[0];
3700 dst->i[1] = src0->i[1] % src1->i[1];
3701 dst->i[2] = src0->i[2] % src1->i[2];
3702 dst->i[3] = src0->i[3] % src1->i[3];
3703 }
3704
3705 static void
3706 micro_f2i(union tgsi_exec_channel *dst,
3707 const union tgsi_exec_channel *src)
3708 {
3709 dst->i[0] = (int)src->f[0];
3710 dst->i[1] = (int)src->f[1];
3711 dst->i[2] = (int)src->f[2];
3712 dst->i[3] = (int)src->f[3];
3713 }
3714
3715 static void
3716 micro_fseq(union tgsi_exec_channel *dst,
3717 const union tgsi_exec_channel *src0,
3718 const union tgsi_exec_channel *src1)
3719 {
3720 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
3721 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
3722 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
3723 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
3724 }
3725
3726 static void
3727 micro_fsge(union tgsi_exec_channel *dst,
3728 const union tgsi_exec_channel *src0,
3729 const union tgsi_exec_channel *src1)
3730 {
3731 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
3732 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
3733 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
3734 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
3735 }
3736
3737 static void
3738 micro_fslt(union tgsi_exec_channel *dst,
3739 const union tgsi_exec_channel *src0,
3740 const union tgsi_exec_channel *src1)
3741 {
3742 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
3743 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
3744 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
3745 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
3746 }
3747
3748 static void
3749 micro_fsne(union tgsi_exec_channel *dst,
3750 const union tgsi_exec_channel *src0,
3751 const union tgsi_exec_channel *src1)
3752 {
3753 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
3754 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
3755 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
3756 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
3757 }
3758
3759 static void
3760 micro_idiv(union tgsi_exec_channel *dst,
3761 const union tgsi_exec_channel *src0,
3762 const union tgsi_exec_channel *src1)
3763 {
3764 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
3765 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
3766 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
3767 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
3768 }
3769
3770 static void
3771 micro_imax(union tgsi_exec_channel *dst,
3772 const union tgsi_exec_channel *src0,
3773 const union tgsi_exec_channel *src1)
3774 {
3775 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3776 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3777 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3778 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3779 }
3780
3781 static void
3782 micro_imin(union tgsi_exec_channel *dst,
3783 const union tgsi_exec_channel *src0,
3784 const union tgsi_exec_channel *src1)
3785 {
3786 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3787 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3788 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3789 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3790 }
3791
3792 static void
3793 micro_isge(union tgsi_exec_channel *dst,
3794 const union tgsi_exec_channel *src0,
3795 const union tgsi_exec_channel *src1)
3796 {
3797 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3798 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3799 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3800 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3801 }
3802
3803 static void
3804 micro_ishr(union tgsi_exec_channel *dst,
3805 const union tgsi_exec_channel *src0,
3806 const union tgsi_exec_channel *src1)
3807 {
3808 unsigned masked_count;
3809 masked_count = src1->i[0] & 0x1f;
3810 dst->i[0] = src0->i[0] >> masked_count;
3811 masked_count = src1->i[1] & 0x1f;
3812 dst->i[1] = src0->i[1] >> masked_count;
3813 masked_count = src1->i[2] & 0x1f;
3814 dst->i[2] = src0->i[2] >> masked_count;
3815 masked_count = src1->i[3] & 0x1f;
3816 dst->i[3] = src0->i[3] >> masked_count;
3817 }
3818
3819 static void
3820 micro_islt(union tgsi_exec_channel *dst,
3821 const union tgsi_exec_channel *src0,
3822 const union tgsi_exec_channel *src1)
3823 {
3824 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3825 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3826 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3827 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3828 }
3829
3830 static void
3831 micro_f2u(union tgsi_exec_channel *dst,
3832 const union tgsi_exec_channel *src)
3833 {
3834 dst->u[0] = (uint)src->f[0];
3835 dst->u[1] = (uint)src->f[1];
3836 dst->u[2] = (uint)src->f[2];
3837 dst->u[3] = (uint)src->f[3];
3838 }
3839
3840 static void
3841 micro_u2f(union tgsi_exec_channel *dst,
3842 const union tgsi_exec_channel *src)
3843 {
3844 dst->f[0] = (float)src->u[0];
3845 dst->f[1] = (float)src->u[1];
3846 dst->f[2] = (float)src->u[2];
3847 dst->f[3] = (float)src->u[3];
3848 }
3849
3850 static void
3851 micro_uadd(union tgsi_exec_channel *dst,
3852 const union tgsi_exec_channel *src0,
3853 const union tgsi_exec_channel *src1)
3854 {
3855 dst->u[0] = src0->u[0] + src1->u[0];
3856 dst->u[1] = src0->u[1] + src1->u[1];
3857 dst->u[2] = src0->u[2] + src1->u[2];
3858 dst->u[3] = src0->u[3] + src1->u[3];
3859 }
3860
3861 static void
3862 micro_udiv(union tgsi_exec_channel *dst,
3863 const union tgsi_exec_channel *src0,
3864 const union tgsi_exec_channel *src1)
3865 {
3866 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
3867 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
3868 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
3869 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
3870 }
3871
3872 static void
3873 micro_umad(union tgsi_exec_channel *dst,
3874 const union tgsi_exec_channel *src0,
3875 const union tgsi_exec_channel *src1,
3876 const union tgsi_exec_channel *src2)
3877 {
3878 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3879 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3880 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3881 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3882 }
3883
3884 static void
3885 micro_umax(union tgsi_exec_channel *dst,
3886 const union tgsi_exec_channel *src0,
3887 const union tgsi_exec_channel *src1)
3888 {
3889 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3890 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3891 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3892 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3893 }
3894
3895 static void
3896 micro_umin(union tgsi_exec_channel *dst,
3897 const union tgsi_exec_channel *src0,
3898 const union tgsi_exec_channel *src1)
3899 {
3900 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3901 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3902 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3903 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3904 }
3905
3906 static void
3907 micro_umod(union tgsi_exec_channel *dst,
3908 const union tgsi_exec_channel *src0,
3909 const union tgsi_exec_channel *src1)
3910 {
3911 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
3912 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
3913 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
3914 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
3915 }
3916
3917 static void
3918 micro_umul(union tgsi_exec_channel *dst,
3919 const union tgsi_exec_channel *src0,
3920 const union tgsi_exec_channel *src1)
3921 {
3922 dst->u[0] = src0->u[0] * src1->u[0];
3923 dst->u[1] = src0->u[1] * src1->u[1];
3924 dst->u[2] = src0->u[2] * src1->u[2];
3925 dst->u[3] = src0->u[3] * src1->u[3];
3926 }
3927
3928 static void
3929 micro_imul_hi(union tgsi_exec_channel *dst,
3930 const union tgsi_exec_channel *src0,
3931 const union tgsi_exec_channel *src1)
3932 {
3933 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3934 dst->i[0] = I64M(src0->i[0], src1->i[0]);
3935 dst->i[1] = I64M(src0->i[1], src1->i[1]);
3936 dst->i[2] = I64M(src0->i[2], src1->i[2]);
3937 dst->i[3] = I64M(src0->i[3], src1->i[3]);
3938 #undef I64M
3939 }
3940
3941 static void
3942 micro_umul_hi(union tgsi_exec_channel *dst,
3943 const union tgsi_exec_channel *src0,
3944 const union tgsi_exec_channel *src1)
3945 {
3946 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3947 dst->u[0] = U64M(src0->u[0], src1->u[0]);
3948 dst->u[1] = U64M(src0->u[1], src1->u[1]);
3949 dst->u[2] = U64M(src0->u[2], src1->u[2]);
3950 dst->u[3] = U64M(src0->u[3], src1->u[3]);
3951 #undef U64M
3952 }
3953
3954 static void
3955 micro_useq(union tgsi_exec_channel *dst,
3956 const union tgsi_exec_channel *src0,
3957 const union tgsi_exec_channel *src1)
3958 {
3959 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3960 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3961 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3962 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3963 }
3964
3965 static void
3966 micro_usge(union tgsi_exec_channel *dst,
3967 const union tgsi_exec_channel *src0,
3968 const union tgsi_exec_channel *src1)
3969 {
3970 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3971 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3972 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3973 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3974 }
3975
3976 static void
3977 micro_ushr(union tgsi_exec_channel *dst,
3978 const union tgsi_exec_channel *src0,
3979 const union tgsi_exec_channel *src1)
3980 {
3981 unsigned masked_count;
3982 masked_count = src1->u[0] & 0x1f;
3983 dst->u[0] = src0->u[0] >> masked_count;
3984 masked_count = src1->u[1] & 0x1f;
3985 dst->u[1] = src0->u[1] >> masked_count;
3986 masked_count = src1->u[2] & 0x1f;
3987 dst->u[2] = src0->u[2] >> masked_count;
3988 masked_count = src1->u[3] & 0x1f;
3989 dst->u[3] = src0->u[3] >> masked_count;
3990 }
3991
3992 static void
3993 micro_uslt(union tgsi_exec_channel *dst,
3994 const union tgsi_exec_channel *src0,
3995 const union tgsi_exec_channel *src1)
3996 {
3997 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3998 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3999 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
4000 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
4001 }
4002
4003 static void
4004 micro_usne(union tgsi_exec_channel *dst,
4005 const union tgsi_exec_channel *src0,
4006 const union tgsi_exec_channel *src1)
4007 {
4008 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
4009 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
4010 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
4011 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
4012 }
4013
4014 static void
4015 micro_uarl(union tgsi_exec_channel *dst,
4016 const union tgsi_exec_channel *src)
4017 {
4018 dst->i[0] = src->u[0];
4019 dst->i[1] = src->u[1];
4020 dst->i[2] = src->u[2];
4021 dst->i[3] = src->u[3];
4022 }
4023
4024 static void
4025 micro_ucmp(union tgsi_exec_channel *dst,
4026 const union tgsi_exec_channel *src0,
4027 const union tgsi_exec_channel *src1,
4028 const union tgsi_exec_channel *src2)
4029 {
4030 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
4031 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
4032 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
4033 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
4034 }
4035
4036 /**
4037 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4038 */
4039 static void
4040 micro_ibfe(union tgsi_exec_channel *dst,
4041 const union tgsi_exec_channel *src0,
4042 const union tgsi_exec_channel *src1,
4043 const union tgsi_exec_channel *src2)
4044 {
4045 int i;
4046 for (i = 0; i < 4; i++) {
4047 int width = src2->i[i] & 0x1f;
4048 int offset = src1->i[i] & 0x1f;
4049 if (width == 0)
4050 dst->i[i] = 0;
4051 else if (width + offset < 32)
4052 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
4053 else
4054 dst->i[i] = src0->i[i] >> offset;
4055 }
4056 }
4057
4058 /**
4059 * Unsigned bitfield extract
4060 */
4061 static void
4062 micro_ubfe(union tgsi_exec_channel *dst,
4063 const union tgsi_exec_channel *src0,
4064 const union tgsi_exec_channel *src1,
4065 const union tgsi_exec_channel *src2)
4066 {
4067 int i;
4068 for (i = 0; i < 4; i++) {
4069 int width = src2->u[i] & 0x1f;
4070 int offset = src1->u[i] & 0x1f;
4071 if (width == 0)
4072 dst->u[i] = 0;
4073 else if (width + offset < 32)
4074 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
4075 else
4076 dst->u[i] = src0->u[i] >> offset;
4077 }
4078 }
4079
4080 /**
4081 * Bitfield insert: copy low bits from src1 into a region of src0.
4082 */
4083 static void
4084 micro_bfi(union tgsi_exec_channel *dst,
4085 const union tgsi_exec_channel *src0,
4086 const union tgsi_exec_channel *src1,
4087 const union tgsi_exec_channel *src2,
4088 const union tgsi_exec_channel *src3)
4089 {
4090 int i;
4091 for (i = 0; i < 4; i++) {
4092 int width = src3->u[i] & 0x1f;
4093 int offset = src2->u[i] & 0x1f;
4094 int bitmask = ((1 << width) - 1) << offset;
4095 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
4096 }
4097 }
4098
4099 static void
4100 micro_brev(union tgsi_exec_channel *dst,
4101 const union tgsi_exec_channel *src)
4102 {
4103 dst->u[0] = util_bitreverse(src->u[0]);
4104 dst->u[1] = util_bitreverse(src->u[1]);
4105 dst->u[2] = util_bitreverse(src->u[2]);
4106 dst->u[3] = util_bitreverse(src->u[3]);
4107 }
4108
4109 static void
4110 micro_popc(union tgsi_exec_channel *dst,
4111 const union tgsi_exec_channel *src)
4112 {
4113 dst->u[0] = util_bitcount(src->u[0]);
4114 dst->u[1] = util_bitcount(src->u[1]);
4115 dst->u[2] = util_bitcount(src->u[2]);
4116 dst->u[3] = util_bitcount(src->u[3]);
4117 }
4118
4119 static void
4120 micro_lsb(union tgsi_exec_channel *dst,
4121 const union tgsi_exec_channel *src)
4122 {
4123 dst->i[0] = ffs(src->u[0]) - 1;
4124 dst->i[1] = ffs(src->u[1]) - 1;
4125 dst->i[2] = ffs(src->u[2]) - 1;
4126 dst->i[3] = ffs(src->u[3]) - 1;
4127 }
4128
4129 static void
4130 micro_imsb(union tgsi_exec_channel *dst,
4131 const union tgsi_exec_channel *src)
4132 {
4133 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
4134 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
4135 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
4136 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
4137 }
4138
4139 static void
4140 micro_umsb(union tgsi_exec_channel *dst,
4141 const union tgsi_exec_channel *src)
4142 {
4143 dst->i[0] = util_last_bit(src->u[0]) - 1;
4144 dst->i[1] = util_last_bit(src->u[1]) - 1;
4145 dst->i[2] = util_last_bit(src->u[2]) - 1;
4146 dst->i[3] = util_last_bit(src->u[3]) - 1;
4147 }
4148
4149 static void
4150 exec_instruction(
4151 struct tgsi_exec_machine *mach,
4152 const struct tgsi_full_instruction *inst,
4153 int *pc )
4154 {
4155 union tgsi_exec_channel r[10];
4156
4157 (*pc)++;
4158
4159 switch (inst->Instruction.Opcode) {
4160 case TGSI_OPCODE_ARL:
4161 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4162 break;
4163
4164 case TGSI_OPCODE_MOV:
4165 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4166 break;
4167
4168 case TGSI_OPCODE_LIT:
4169 exec_lit(mach, inst);
4170 break;
4171
4172 case TGSI_OPCODE_RCP:
4173 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4174 break;
4175
4176 case TGSI_OPCODE_RSQ:
4177 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4178 break;
4179
4180 case TGSI_OPCODE_EXP:
4181 exec_exp(mach, inst);
4182 break;
4183
4184 case TGSI_OPCODE_LOG:
4185 exec_log(mach, inst);
4186 break;
4187
4188 case TGSI_OPCODE_MUL:
4189 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4190 break;
4191
4192 case TGSI_OPCODE_ADD:
4193 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4194 break;
4195
4196 case TGSI_OPCODE_DP3:
4197 exec_dp3(mach, inst);
4198 break;
4199
4200 case TGSI_OPCODE_DP4:
4201 exec_dp4(mach, inst);
4202 break;
4203
4204 case TGSI_OPCODE_DST:
4205 exec_dst(mach, inst);
4206 break;
4207
4208 case TGSI_OPCODE_MIN:
4209 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4210 break;
4211
4212 case TGSI_OPCODE_MAX:
4213 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4214 break;
4215
4216 case TGSI_OPCODE_SLT:
4217 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4218 break;
4219
4220 case TGSI_OPCODE_SGE:
4221 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4222 break;
4223
4224 case TGSI_OPCODE_MAD:
4225 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4226 break;
4227
4228 case TGSI_OPCODE_SUB:
4229 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4230 break;
4231
4232 case TGSI_OPCODE_LRP:
4233 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4234 break;
4235
4236 case TGSI_OPCODE_SQRT:
4237 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4238 break;
4239
4240 case TGSI_OPCODE_DP2A:
4241 exec_dp2a(mach, inst);
4242 break;
4243
4244 case TGSI_OPCODE_FRC:
4245 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4246 break;
4247
4248 case TGSI_OPCODE_CLAMP:
4249 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4250 break;
4251
4252 case TGSI_OPCODE_FLR:
4253 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4254 break;
4255
4256 case TGSI_OPCODE_ROUND:
4257 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4258 break;
4259
4260 case TGSI_OPCODE_EX2:
4261 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4262 break;
4263
4264 case TGSI_OPCODE_LG2:
4265 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4266 break;
4267
4268 case TGSI_OPCODE_POW:
4269 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4270 break;
4271
4272 case TGSI_OPCODE_XPD:
4273 exec_xpd(mach, inst);
4274 break;
4275
4276 case TGSI_OPCODE_ABS:
4277 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4278 break;
4279
4280 case TGSI_OPCODE_DPH:
4281 exec_dph(mach, inst);
4282 break;
4283
4284 case TGSI_OPCODE_COS:
4285 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4286 break;
4287
4288 case TGSI_OPCODE_DDX:
4289 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4290 break;
4291
4292 case TGSI_OPCODE_DDY:
4293 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4294 break;
4295
4296 case TGSI_OPCODE_KILL:
4297 exec_kill (mach, inst);
4298 break;
4299
4300 case TGSI_OPCODE_KILL_IF:
4301 exec_kill_if (mach, inst);
4302 break;
4303
4304 case TGSI_OPCODE_PK2H:
4305 assert (0);
4306 break;
4307
4308 case TGSI_OPCODE_PK2US:
4309 assert (0);
4310 break;
4311
4312 case TGSI_OPCODE_PK4B:
4313 assert (0);
4314 break;
4315
4316 case TGSI_OPCODE_PK4UB:
4317 assert (0);
4318 break;
4319
4320 case TGSI_OPCODE_SEQ:
4321 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4322 break;
4323
4324 case TGSI_OPCODE_SGT:
4325 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4326 break;
4327
4328 case TGSI_OPCODE_SIN:
4329 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4330 break;
4331
4332 case TGSI_OPCODE_SLE:
4333 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4334 break;
4335
4336 case TGSI_OPCODE_SNE:
4337 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4338 break;
4339
4340 case TGSI_OPCODE_TEX:
4341 /* simple texture lookup */
4342 /* src[0] = texcoord */
4343 /* src[1] = sampler unit */
4344 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
4345 break;
4346
4347 case TGSI_OPCODE_TXB:
4348 /* Texture lookup with lod bias */
4349 /* src[0] = texcoord (src[0].w = LOD bias) */
4350 /* src[1] = sampler unit */
4351 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
4352 break;
4353
4354 case TGSI_OPCODE_TXD:
4355 /* Texture lookup with explict partial derivatives */
4356 /* src[0] = texcoord */
4357 /* src[1] = d[strq]/dx */
4358 /* src[2] = d[strq]/dy */
4359 /* src[3] = sampler unit */
4360 exec_txd(mach, inst);
4361 break;
4362
4363 case TGSI_OPCODE_TXL:
4364 /* Texture lookup with explit LOD */
4365 /* src[0] = texcoord (src[0].w = LOD) */
4366 /* src[1] = sampler unit */
4367 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
4368 break;
4369
4370 case TGSI_OPCODE_TXP:
4371 /* Texture lookup with projection */
4372 /* src[0] = texcoord (src[0].w = projection) */
4373 /* src[1] = sampler unit */
4374 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
4375 break;
4376
4377 case TGSI_OPCODE_UP2H:
4378 assert (0);
4379 break;
4380
4381 case TGSI_OPCODE_UP2US:
4382 assert (0);
4383 break;
4384
4385 case TGSI_OPCODE_UP4B:
4386 assert (0);
4387 break;
4388
4389 case TGSI_OPCODE_UP4UB:
4390 assert (0);
4391 break;
4392
4393 case TGSI_OPCODE_ARR:
4394 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4395 break;
4396
4397 case TGSI_OPCODE_CAL:
4398 /* skip the call if no execution channels are enabled */
4399 if (mach->ExecMask) {
4400 /* do the call */
4401
4402 /* First, record the depths of the execution stacks.
4403 * This is important for deeply nested/looped return statements.
4404 * We have to unwind the stacks by the correct amount. For a
4405 * real code generator, we could determine the number of entries
4406 * to pop off each stack with simple static analysis and avoid
4407 * implementing this data structure at run time.
4408 */
4409 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
4410 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
4411 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
4412 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
4413 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
4414 /* note that PC was already incremented above */
4415 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
4416
4417 mach->CallStackTop++;
4418
4419 /* Second, push the Cond, Loop, Cont, Func stacks */
4420 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4421 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4422 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4423 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
4424 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4425 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
4426
4427 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4428 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4429 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4430 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
4431 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4432 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
4433
4434 /* Finally, jump to the subroutine */
4435 *pc = inst->Label.Label;
4436 }
4437 break;
4438
4439 case TGSI_OPCODE_RET:
4440 mach->FuncMask &= ~mach->ExecMask;
4441 UPDATE_EXEC_MASK(mach);
4442
4443 if (mach->FuncMask == 0x0) {
4444 /* really return now (otherwise, keep executing */
4445
4446 if (mach->CallStackTop == 0) {
4447 /* returning from main() */
4448 mach->CondStackTop = 0;
4449 mach->LoopStackTop = 0;
4450 *pc = -1;
4451 return;
4452 }
4453
4454 assert(mach->CallStackTop > 0);
4455 mach->CallStackTop--;
4456
4457 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4458 mach->CondMask = mach->CondStack[mach->CondStackTop];
4459
4460 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4461 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4462
4463 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4464 mach->ContMask = mach->ContStack[mach->ContStackTop];
4465
4466 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4467 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4468
4469 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4470 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4471
4472 assert(mach->FuncStackTop > 0);
4473 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4474
4475 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4476
4477 UPDATE_EXEC_MASK(mach);
4478 }
4479 break;
4480
4481 case TGSI_OPCODE_SSG:
4482 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4483 break;
4484
4485 case TGSI_OPCODE_CMP:
4486 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4487 break;
4488
4489 case TGSI_OPCODE_SCS:
4490 exec_scs(mach, inst);
4491 break;
4492
4493 case TGSI_OPCODE_DIV:
4494 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4495 break;
4496
4497 case TGSI_OPCODE_DP2:
4498 exec_dp2(mach, inst);
4499 break;
4500
4501 case TGSI_OPCODE_IF:
4502 /* push CondMask */
4503 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4504 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4505 FETCH( &r[0], 0, TGSI_CHAN_X );
4506 /* update CondMask */
4507 if( ! r[0].f[0] ) {
4508 mach->CondMask &= ~0x1;
4509 }
4510 if( ! r[0].f[1] ) {
4511 mach->CondMask &= ~0x2;
4512 }
4513 if( ! r[0].f[2] ) {
4514 mach->CondMask &= ~0x4;
4515 }
4516 if( ! r[0].f[3] ) {
4517 mach->CondMask &= ~0x8;
4518 }
4519 UPDATE_EXEC_MASK(mach);
4520 /* Todo: If CondMask==0, jump to ELSE */
4521 break;
4522
4523 case TGSI_OPCODE_UIF:
4524 /* push CondMask */
4525 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4526 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4527 IFETCH( &r[0], 0, TGSI_CHAN_X );
4528 /* update CondMask */
4529 if( ! r[0].u[0] ) {
4530 mach->CondMask &= ~0x1;
4531 }
4532 if( ! r[0].u[1] ) {
4533 mach->CondMask &= ~0x2;
4534 }
4535 if( ! r[0].u[2] ) {
4536 mach->CondMask &= ~0x4;
4537 }
4538 if( ! r[0].u[3] ) {
4539 mach->CondMask &= ~0x8;
4540 }
4541 UPDATE_EXEC_MASK(mach);
4542 /* Todo: If CondMask==0, jump to ELSE */
4543 break;
4544
4545 case TGSI_OPCODE_ELSE:
4546 /* invert CondMask wrt previous mask */
4547 {
4548 uint prevMask;
4549 assert(mach->CondStackTop > 0);
4550 prevMask = mach->CondStack[mach->CondStackTop - 1];
4551 mach->CondMask = ~mach->CondMask & prevMask;
4552 UPDATE_EXEC_MASK(mach);
4553 /* Todo: If CondMask==0, jump to ENDIF */
4554 }
4555 break;
4556
4557 case TGSI_OPCODE_ENDIF:
4558 /* pop CondMask */
4559 assert(mach->CondStackTop > 0);
4560 mach->CondMask = mach->CondStack[--mach->CondStackTop];
4561 UPDATE_EXEC_MASK(mach);
4562 break;
4563
4564 case TGSI_OPCODE_END:
4565 /* make sure we end primitives which haven't
4566 * been explicitly emitted */
4567 conditional_emit_primitive(mach);
4568 /* halt execution */
4569 *pc = -1;
4570 break;
4571
4572 case TGSI_OPCODE_PUSHA:
4573 assert (0);
4574 break;
4575
4576 case TGSI_OPCODE_POPA:
4577 assert (0);
4578 break;
4579
4580 case TGSI_OPCODE_CEIL:
4581 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4582 break;
4583
4584 case TGSI_OPCODE_I2F:
4585 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
4586 break;
4587
4588 case TGSI_OPCODE_NOT:
4589 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4590 break;
4591
4592 case TGSI_OPCODE_TRUNC:
4593 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4594 break;
4595
4596 case TGSI_OPCODE_SHL:
4597 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4598 break;
4599
4600 case TGSI_OPCODE_AND:
4601 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4602 break;
4603
4604 case TGSI_OPCODE_OR:
4605 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4606 break;
4607
4608 case TGSI_OPCODE_MOD:
4609 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4610 break;
4611
4612 case TGSI_OPCODE_XOR:
4613 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4614 break;
4615
4616 case TGSI_OPCODE_SAD:
4617 assert (0);
4618 break;
4619
4620 case TGSI_OPCODE_TXF:
4621 exec_txf(mach, inst);
4622 break;
4623
4624 case TGSI_OPCODE_TXQ:
4625 exec_txq(mach, inst);
4626 break;
4627
4628 case TGSI_OPCODE_EMIT:
4629 emit_vertex(mach);
4630 break;
4631
4632 case TGSI_OPCODE_ENDPRIM:
4633 emit_primitive(mach);
4634 break;
4635
4636 case TGSI_OPCODE_BGNLOOP:
4637 /* push LoopMask and ContMasks */
4638 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4639 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4640 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4641 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4642
4643 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4644 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4645 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4646 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4647 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4648 break;
4649
4650 case TGSI_OPCODE_ENDLOOP:
4651 /* Restore ContMask, but don't pop */
4652 assert(mach->ContStackTop > 0);
4653 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4654 UPDATE_EXEC_MASK(mach);
4655 if (mach->ExecMask) {
4656 /* repeat loop: jump to instruction just past BGNLOOP */
4657 assert(mach->LoopLabelStackTop > 0);
4658 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4659 }
4660 else {
4661 /* exit loop: pop LoopMask */
4662 assert(mach->LoopStackTop > 0);
4663 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4664 /* pop ContMask */
4665 assert(mach->ContStackTop > 0);
4666 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4667 assert(mach->LoopLabelStackTop > 0);
4668 --mach->LoopLabelStackTop;
4669
4670 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4671 }
4672 UPDATE_EXEC_MASK(mach);
4673 break;
4674
4675 case TGSI_OPCODE_BRK:
4676 exec_break(mach);
4677 break;
4678
4679 case TGSI_OPCODE_CONT:
4680 /* turn off cont channels for each enabled exec channel */
4681 mach->ContMask &= ~mach->ExecMask;
4682 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4683 UPDATE_EXEC_MASK(mach);
4684 break;
4685
4686 case TGSI_OPCODE_BGNSUB:
4687 /* no-op */
4688 break;
4689
4690 case TGSI_OPCODE_ENDSUB:
4691 /*
4692 * XXX: This really should be a no-op. We should never reach this opcode.
4693 */
4694
4695 assert(mach->CallStackTop > 0);
4696 mach->CallStackTop--;
4697
4698 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4699 mach->CondMask = mach->CondStack[mach->CondStackTop];
4700
4701 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4702 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4703
4704 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4705 mach->ContMask = mach->ContStack[mach->ContStackTop];
4706
4707 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4708 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4709
4710 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4711 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4712
4713 assert(mach->FuncStackTop > 0);
4714 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4715
4716 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4717
4718 UPDATE_EXEC_MASK(mach);
4719 break;
4720
4721 case TGSI_OPCODE_NOP:
4722 break;
4723
4724 case TGSI_OPCODE_BREAKC:
4725 IFETCH(&r[0], 0, TGSI_CHAN_X);
4726 /* update CondMask */
4727 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4728 mach->LoopMask &= ~0x1;
4729 }
4730 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4731 mach->LoopMask &= ~0x2;
4732 }
4733 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4734 mach->LoopMask &= ~0x4;
4735 }
4736 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4737 mach->LoopMask &= ~0x8;
4738 }
4739 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4740 UPDATE_EXEC_MASK(mach);
4741 break;
4742
4743 case TGSI_OPCODE_F2I:
4744 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4745 break;
4746
4747 case TGSI_OPCODE_FSEQ:
4748 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4749 break;
4750
4751 case TGSI_OPCODE_FSGE:
4752 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4753 break;
4754
4755 case TGSI_OPCODE_FSLT:
4756 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4757 break;
4758
4759 case TGSI_OPCODE_FSNE:
4760 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4761 break;
4762
4763 case TGSI_OPCODE_IDIV:
4764 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4765 break;
4766
4767 case TGSI_OPCODE_IMAX:
4768 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4769 break;
4770
4771 case TGSI_OPCODE_IMIN:
4772 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4773 break;
4774
4775 case TGSI_OPCODE_INEG:
4776 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4777 break;
4778
4779 case TGSI_OPCODE_ISGE:
4780 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4781 break;
4782
4783 case TGSI_OPCODE_ISHR:
4784 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4785 break;
4786
4787 case TGSI_OPCODE_ISLT:
4788 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4789 break;
4790
4791 case TGSI_OPCODE_F2U:
4792 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4793 break;
4794
4795 case TGSI_OPCODE_U2F:
4796 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4797 break;
4798
4799 case TGSI_OPCODE_UADD:
4800 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4801 break;
4802
4803 case TGSI_OPCODE_UDIV:
4804 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4805 break;
4806
4807 case TGSI_OPCODE_UMAD:
4808 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4809 break;
4810
4811 case TGSI_OPCODE_UMAX:
4812 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4813 break;
4814
4815 case TGSI_OPCODE_UMIN:
4816 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4817 break;
4818
4819 case TGSI_OPCODE_UMOD:
4820 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4821 break;
4822
4823 case TGSI_OPCODE_UMUL:
4824 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4825 break;
4826
4827 case TGSI_OPCODE_IMUL_HI:
4828 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4829 break;
4830
4831 case TGSI_OPCODE_UMUL_HI:
4832 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4833 break;
4834
4835 case TGSI_OPCODE_USEQ:
4836 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4837 break;
4838
4839 case TGSI_OPCODE_USGE:
4840 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4841 break;
4842
4843 case TGSI_OPCODE_USHR:
4844 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4845 break;
4846
4847 case TGSI_OPCODE_USLT:
4848 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4849 break;
4850
4851 case TGSI_OPCODE_USNE:
4852 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4853 break;
4854
4855 case TGSI_OPCODE_SWITCH:
4856 exec_switch(mach, inst);
4857 break;
4858
4859 case TGSI_OPCODE_CASE:
4860 exec_case(mach, inst);
4861 break;
4862
4863 case TGSI_OPCODE_DEFAULT:
4864 exec_default(mach);
4865 break;
4866
4867 case TGSI_OPCODE_ENDSWITCH:
4868 exec_endswitch(mach);
4869 break;
4870
4871 case TGSI_OPCODE_SAMPLE_I:
4872 exec_txf(mach, inst);
4873 break;
4874
4875 case TGSI_OPCODE_SAMPLE_I_MS:
4876 assert(0);
4877 break;
4878
4879 case TGSI_OPCODE_SAMPLE:
4880 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4881 break;
4882
4883 case TGSI_OPCODE_SAMPLE_B:
4884 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4885 break;
4886
4887 case TGSI_OPCODE_SAMPLE_C:
4888 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4889 break;
4890
4891 case TGSI_OPCODE_SAMPLE_C_LZ:
4892 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4893 break;
4894
4895 case TGSI_OPCODE_SAMPLE_D:
4896 exec_sample_d(mach, inst);
4897 break;
4898
4899 case TGSI_OPCODE_SAMPLE_L:
4900 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4901 break;
4902
4903 case TGSI_OPCODE_GATHER4:
4904 assert(0);
4905 break;
4906
4907 case TGSI_OPCODE_SVIEWINFO:
4908 exec_txq(mach, inst);
4909 break;
4910
4911 case TGSI_OPCODE_SAMPLE_POS:
4912 assert(0);
4913 break;
4914
4915 case TGSI_OPCODE_SAMPLE_INFO:
4916 assert(0);
4917 break;
4918
4919 case TGSI_OPCODE_UARL:
4920 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4921 break;
4922
4923 case TGSI_OPCODE_UCMP:
4924 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4925 break;
4926
4927 case TGSI_OPCODE_IABS:
4928 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4929 break;
4930
4931 case TGSI_OPCODE_ISSG:
4932 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4933 break;
4934
4935 case TGSI_OPCODE_TEX2:
4936 /* simple texture lookup */
4937 /* src[0] = texcoord */
4938 /* src[1] = compare */
4939 /* src[2] = sampler unit */
4940 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4941 break;
4942 case TGSI_OPCODE_TXB2:
4943 /* simple texture lookup */
4944 /* src[0] = texcoord */
4945 /* src[1] = bias */
4946 /* src[2] = sampler unit */
4947 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4948 break;
4949 case TGSI_OPCODE_TXL2:
4950 /* simple texture lookup */
4951 /* src[0] = texcoord */
4952 /* src[1] = lod */
4953 /* src[2] = sampler unit */
4954 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4955 break;
4956
4957 case TGSI_OPCODE_IBFE:
4958 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4959 break;
4960 case TGSI_OPCODE_UBFE:
4961 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4962 break;
4963 case TGSI_OPCODE_BFI:
4964 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4965 break;
4966 case TGSI_OPCODE_BREV:
4967 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4968 break;
4969 case TGSI_OPCODE_POPC:
4970 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4971 break;
4972 case TGSI_OPCODE_LSB:
4973 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4974 break;
4975 case TGSI_OPCODE_IMSB:
4976 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4977 break;
4978 case TGSI_OPCODE_UMSB:
4979 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4980 break;
4981
4982 case TGSI_OPCODE_F2D:
4983 exec_f2d(mach, inst);
4984 break;
4985
4986 case TGSI_OPCODE_D2F:
4987 exec_d2f(mach, inst);
4988 break;
4989
4990 case TGSI_OPCODE_DABS:
4991 exec_double_unary(mach, inst, micro_dabs);
4992 break;
4993
4994 case TGSI_OPCODE_DNEG:
4995 exec_double_unary(mach, inst, micro_dneg);
4996 break;
4997
4998 case TGSI_OPCODE_DADD:
4999 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
5000 break;
5001
5002 case TGSI_OPCODE_DMUL:
5003 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
5004 break;
5005
5006 case TGSI_OPCODE_DMAX:
5007 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
5008 break;
5009
5010 case TGSI_OPCODE_DMIN:
5011 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
5012 break;
5013
5014 case TGSI_OPCODE_DSLT:
5015 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
5016 break;
5017
5018 case TGSI_OPCODE_DSGE:
5019 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
5020 break;
5021
5022 case TGSI_OPCODE_DSEQ:
5023 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
5024 break;
5025
5026 case TGSI_OPCODE_DSNE:
5027 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
5028 break;
5029
5030 case TGSI_OPCODE_DRCP:
5031 exec_double_unary(mach, inst, micro_drcp);
5032 break;
5033
5034 case TGSI_OPCODE_DSQRT:
5035 exec_double_unary(mach, inst, micro_dsqrt);
5036 break;
5037
5038 case TGSI_OPCODE_DRSQ:
5039 exec_double_unary(mach, inst, micro_drsq);
5040 break;
5041
5042 case TGSI_OPCODE_DMAD:
5043 exec_double_trinary(mach, inst, micro_dmad);
5044 break;
5045
5046 case TGSI_OPCODE_DFRAC:
5047 exec_double_unary(mach, inst, micro_dfrac);
5048 break;
5049
5050 case TGSI_OPCODE_DLDEXP:
5051 exec_dldexp(mach, inst);
5052 break;
5053
5054 case TGSI_OPCODE_DFRACEXP:
5055 exec_dfracexp(mach, inst);
5056 break;
5057
5058 case TGSI_OPCODE_I2D:
5059 exec_i2d(mach, inst);
5060 break;
5061
5062 case TGSI_OPCODE_D2I:
5063 exec_d2i(mach, inst);
5064 break;
5065
5066 case TGSI_OPCODE_U2D:
5067 exec_u2d(mach, inst);
5068 break;
5069
5070 case TGSI_OPCODE_D2U:
5071 exec_d2u(mach, inst);
5072 break;
5073 default:
5074 assert( 0 );
5075 }
5076 }
5077
5078
5079 /**
5080 * Run TGSI interpreter.
5081 * \return bitmask of "alive" quad components
5082 */
5083 uint
5084 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
5085 {
5086 uint i;
5087 int pc = 0;
5088 uint default_mask = 0xf;
5089
5090 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
5091 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
5092
5093 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
5094 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
5095 mach->Primitives[0] = 0;
5096 /* GS runs on a single primitive for now */
5097 default_mask = 0x1;
5098 }
5099
5100 mach->CondMask = default_mask;
5101 mach->LoopMask = default_mask;
5102 mach->ContMask = default_mask;
5103 mach->FuncMask = default_mask;
5104 mach->ExecMask = default_mask;
5105
5106 mach->Switch.mask = default_mask;
5107
5108 assert(mach->CondStackTop == 0);
5109 assert(mach->LoopStackTop == 0);
5110 assert(mach->ContStackTop == 0);
5111 assert(mach->SwitchStackTop == 0);
5112 assert(mach->BreakStackTop == 0);
5113 assert(mach->CallStackTop == 0);
5114
5115
5116 /* execute declarations (interpolants) */
5117 for (i = 0; i < mach->NumDeclarations; i++) {
5118 exec_declaration( mach, mach->Declarations+i );
5119 }
5120
5121 {
5122 #if DEBUG_EXECUTION
5123 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
5124 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
5125 uint inst = 1;
5126
5127 memset(mach->Temps, 0, sizeof(temps));
5128 memset(mach->Outputs, 0, sizeof(outputs));
5129 memset(temps, 0, sizeof(temps));
5130 memset(outputs, 0, sizeof(outputs));
5131 #endif
5132
5133 /* execute instructions, until pc is set to -1 */
5134 while (pc != -1) {
5135
5136 #if DEBUG_EXECUTION
5137 uint i;
5138
5139 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
5140 #endif
5141
5142 assert(pc < (int) mach->NumInstructions);
5143 exec_instruction(mach, mach->Instructions + pc, &pc);
5144
5145 #if DEBUG_EXECUTION
5146 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
5147 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
5148 uint j;
5149
5150 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
5151 debug_printf("TEMP[%2u] = ", i);
5152 for (j = 0; j < 4; j++) {
5153 if (j > 0) {
5154 debug_printf(" ");
5155 }
5156 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5157 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
5158 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
5159 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
5160 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
5161 }
5162 }
5163 }
5164 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
5165 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
5166 uint j;
5167
5168 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
5169 debug_printf("OUT[%2u] = ", i);
5170 for (j = 0; j < 4; j++) {
5171 if (j > 0) {
5172 debug_printf(" ");
5173 }
5174 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5175 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
5176 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
5177 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
5178 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
5179 }
5180 }
5181 }
5182 #endif
5183 }
5184 }
5185
5186 #if 0
5187 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5188 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
5189 /*
5190 * Scale back depth component.
5191 */
5192 for (i = 0; i < 4; i++)
5193 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
5194 }
5195 #endif
5196
5197 /* Strictly speaking, these assertions aren't really needed but they
5198 * can potentially catch some bugs in the control flow code.
5199 */
5200 assert(mach->CondStackTop == 0);
5201 assert(mach->LoopStackTop == 0);
5202 assert(mach->ContStackTop == 0);
5203 assert(mach->SwitchStackTop == 0);
5204 assert(mach->BreakStackTop == 0);
5205 assert(mach->CallStackTop == 0);
5206
5207 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
5208 }