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Merge remote branch 'origin/master' into pipe-video
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 1
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_clamp(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src0,
115 const union tgsi_exec_channel *src1,
116 const union tgsi_exec_channel *src2)
117 {
118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
122 }
123
124 static void
125 micro_cmp(union tgsi_exec_channel *dst,
126 const union tgsi_exec_channel *src0,
127 const union tgsi_exec_channel *src1,
128 const union tgsi_exec_channel *src2)
129 {
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
134 }
135
136 static void
137 micro_cnd(union tgsi_exec_channel *dst,
138 const union tgsi_exec_channel *src0,
139 const union tgsi_exec_channel *src1,
140 const union tgsi_exec_channel *src2)
141 {
142 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
143 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
144 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
145 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
146 }
147
148 static void
149 micro_cos(union tgsi_exec_channel *dst,
150 const union tgsi_exec_channel *src)
151 {
152 dst->f[0] = cosf(src->f[0]);
153 dst->f[1] = cosf(src->f[1]);
154 dst->f[2] = cosf(src->f[2]);
155 dst->f[3] = cosf(src->f[3]);
156 }
157
158 static void
159 micro_ddx(union tgsi_exec_channel *dst,
160 const union tgsi_exec_channel *src)
161 {
162 dst->f[0] =
163 dst->f[1] =
164 dst->f[2] =
165 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
166 }
167
168 static void
169 micro_ddy(union tgsi_exec_channel *dst,
170 const union tgsi_exec_channel *src)
171 {
172 dst->f[0] =
173 dst->f[1] =
174 dst->f[2] =
175 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
176 }
177
178 static void
179 micro_exp2(union tgsi_exec_channel *dst,
180 const union tgsi_exec_channel *src)
181 {
182 #if FAST_MATH
183 dst->f[0] = util_fast_exp2(src->f[0]);
184 dst->f[1] = util_fast_exp2(src->f[1]);
185 dst->f[2] = util_fast_exp2(src->f[2]);
186 dst->f[3] = util_fast_exp2(src->f[3]);
187 #else
188 #if DEBUG
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
190 uint i;
191 union tgsi_exec_channel clamped;
192
193 for (i = 0; i < 4; i++) {
194 if (src->f[i] > 127.99999f) {
195 clamped.f[i] = 127.99999f;
196 } else if (src->f[i] < -126.99999f) {
197 clamped.f[i] = -126.99999f;
198 } else {
199 clamped.f[i] = src->f[i];
200 }
201 }
202 src = &clamped;
203 #endif /* DEBUG */
204
205 dst->f[0] = powf(2.0f, src->f[0]);
206 dst->f[1] = powf(2.0f, src->f[1]);
207 dst->f[2] = powf(2.0f, src->f[2]);
208 dst->f[3] = powf(2.0f, src->f[3]);
209 #endif /* FAST_MATH */
210 }
211
212 static void
213 micro_flr(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
215 {
216 dst->f[0] = floorf(src->f[0]);
217 dst->f[1] = floorf(src->f[1]);
218 dst->f[2] = floorf(src->f[2]);
219 dst->f[3] = floorf(src->f[3]);
220 }
221
222 static void
223 micro_frc(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
225 {
226 dst->f[0] = src->f[0] - floorf(src->f[0]);
227 dst->f[1] = src->f[1] - floorf(src->f[1]);
228 dst->f[2] = src->f[2] - floorf(src->f[2]);
229 dst->f[3] = src->f[3] - floorf(src->f[3]);
230 }
231
232 static void
233 micro_iabs(union tgsi_exec_channel *dst,
234 const union tgsi_exec_channel *src)
235 {
236 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
237 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
238 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
239 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
240 }
241
242 static void
243 micro_ineg(union tgsi_exec_channel *dst,
244 const union tgsi_exec_channel *src)
245 {
246 dst->i[0] = -src->i[0];
247 dst->i[1] = -src->i[1];
248 dst->i[2] = -src->i[2];
249 dst->i[3] = -src->i[3];
250 }
251
252 static void
253 micro_lg2(union tgsi_exec_channel *dst,
254 const union tgsi_exec_channel *src)
255 {
256 #if FAST_MATH
257 dst->f[0] = util_fast_log2(src->f[0]);
258 dst->f[1] = util_fast_log2(src->f[1]);
259 dst->f[2] = util_fast_log2(src->f[2]);
260 dst->f[3] = util_fast_log2(src->f[3]);
261 #else
262 dst->f[0] = logf(src->f[0]) * 1.442695f;
263 dst->f[1] = logf(src->f[1]) * 1.442695f;
264 dst->f[2] = logf(src->f[2]) * 1.442695f;
265 dst->f[3] = logf(src->f[3]) * 1.442695f;
266 #endif
267 }
268
269 static void
270 micro_lrp(union tgsi_exec_channel *dst,
271 const union tgsi_exec_channel *src0,
272 const union tgsi_exec_channel *src1,
273 const union tgsi_exec_channel *src2)
274 {
275 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
276 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
277 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
278 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
279 }
280
281 static void
282 micro_mad(union tgsi_exec_channel *dst,
283 const union tgsi_exec_channel *src0,
284 const union tgsi_exec_channel *src1,
285 const union tgsi_exec_channel *src2)
286 {
287 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
288 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
289 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
290 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
291 }
292
293 static void
294 micro_mov(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 dst->u[0] = src->u[0];
298 dst->u[1] = src->u[1];
299 dst->u[2] = src->u[2];
300 dst->u[3] = src->u[3];
301 }
302
303 static void
304 micro_rcp(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
306 {
307 #if 0 /* for debugging */
308 assert(src->f[0] != 0.0f);
309 assert(src->f[1] != 0.0f);
310 assert(src->f[2] != 0.0f);
311 assert(src->f[3] != 0.0f);
312 #endif
313 dst->f[0] = 1.0f / src->f[0];
314 dst->f[1] = 1.0f / src->f[1];
315 dst->f[2] = 1.0f / src->f[2];
316 dst->f[3] = 1.0f / src->f[3];
317 }
318
319 static void
320 micro_rnd(union tgsi_exec_channel *dst,
321 const union tgsi_exec_channel *src)
322 {
323 dst->f[0] = floorf(src->f[0] + 0.5f);
324 dst->f[1] = floorf(src->f[1] + 0.5f);
325 dst->f[2] = floorf(src->f[2] + 0.5f);
326 dst->f[3] = floorf(src->f[3] + 0.5f);
327 }
328
329 static void
330 micro_rsq(union tgsi_exec_channel *dst,
331 const union tgsi_exec_channel *src)
332 {
333 #if 0 /* for debugging */
334 assert(src->f[0] != 0.0f);
335 assert(src->f[1] != 0.0f);
336 assert(src->f[2] != 0.0f);
337 assert(src->f[3] != 0.0f);
338 #endif
339 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
340 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
341 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
342 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
343 }
344
345 static void
346 micro_seq(union tgsi_exec_channel *dst,
347 const union tgsi_exec_channel *src0,
348 const union tgsi_exec_channel *src1)
349 {
350 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
351 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
352 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
353 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
354 }
355
356 static void
357 micro_sge(union tgsi_exec_channel *dst,
358 const union tgsi_exec_channel *src0,
359 const union tgsi_exec_channel *src1)
360 {
361 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
362 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
363 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
364 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
365 }
366
367 static void
368 micro_sgn(union tgsi_exec_channel *dst,
369 const union tgsi_exec_channel *src)
370 {
371 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
372 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
373 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
374 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
375 }
376
377 static void
378 micro_sgt(union tgsi_exec_channel *dst,
379 const union tgsi_exec_channel *src0,
380 const union tgsi_exec_channel *src1)
381 {
382 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
383 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
384 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
385 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
386 }
387
388 static void
389 micro_sin(union tgsi_exec_channel *dst,
390 const union tgsi_exec_channel *src)
391 {
392 dst->f[0] = sinf(src->f[0]);
393 dst->f[1] = sinf(src->f[1]);
394 dst->f[2] = sinf(src->f[2]);
395 dst->f[3] = sinf(src->f[3]);
396 }
397
398 static void
399 micro_sle(union tgsi_exec_channel *dst,
400 const union tgsi_exec_channel *src0,
401 const union tgsi_exec_channel *src1)
402 {
403 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
404 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
405 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
406 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
407 }
408
409 static void
410 micro_slt(union tgsi_exec_channel *dst,
411 const union tgsi_exec_channel *src0,
412 const union tgsi_exec_channel *src1)
413 {
414 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
415 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
416 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
417 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
418 }
419
420 static void
421 micro_sne(union tgsi_exec_channel *dst,
422 const union tgsi_exec_channel *src0,
423 const union tgsi_exec_channel *src1)
424 {
425 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
426 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
427 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
428 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
429 }
430
431 static void
432 micro_sfl(union tgsi_exec_channel *dst)
433 {
434 dst->f[0] = 0.0f;
435 dst->f[1] = 0.0f;
436 dst->f[2] = 0.0f;
437 dst->f[3] = 0.0f;
438 }
439
440 static void
441 micro_str(union tgsi_exec_channel *dst)
442 {
443 dst->f[0] = 1.0f;
444 dst->f[1] = 1.0f;
445 dst->f[2] = 1.0f;
446 dst->f[3] = 1.0f;
447 }
448
449 static void
450 micro_trunc(union tgsi_exec_channel *dst,
451 const union tgsi_exec_channel *src)
452 {
453 dst->f[0] = (float)(int)src->f[0];
454 dst->f[1] = (float)(int)src->f[1];
455 dst->f[2] = (float)(int)src->f[2];
456 dst->f[3] = (float)(int)src->f[3];
457 }
458
459
460 #define CHAN_X 0
461 #define CHAN_Y 1
462 #define CHAN_Z 2
463 #define CHAN_W 3
464
465 enum tgsi_exec_datatype {
466 TGSI_EXEC_DATA_FLOAT,
467 TGSI_EXEC_DATA_INT,
468 TGSI_EXEC_DATA_UINT
469 };
470
471 /*
472 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
473 */
474 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
475 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
476 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
477 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
478 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
479 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
480
481
482 /** The execution mask depends on the conditional mask and the loop mask */
483 #define UPDATE_EXEC_MASK(MACH) \
484 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
485
486
487 static const union tgsi_exec_channel ZeroVec =
488 { { 0.0, 0.0, 0.0, 0.0 } };
489
490 static const union tgsi_exec_channel OneVec = {
491 {1.0f, 1.0f, 1.0f, 1.0f}
492 };
493
494 static const union tgsi_exec_channel P128Vec = {
495 {128.0f, 128.0f, 128.0f, 128.0f}
496 };
497
498 static const union tgsi_exec_channel M128Vec = {
499 {-128.0f, -128.0f, -128.0f, -128.0f}
500 };
501
502
503 /**
504 * Assert that none of the float values in 'chan' are infinite or NaN.
505 * NaN and Inf may occur normally during program execution and should
506 * not lead to crashes, etc. But when debugging, it's helpful to catch
507 * them.
508 */
509 static INLINE void
510 check_inf_or_nan(const union tgsi_exec_channel *chan)
511 {
512 assert(!util_is_inf_or_nan((chan)->f[0]));
513 assert(!util_is_inf_or_nan((chan)->f[1]));
514 assert(!util_is_inf_or_nan((chan)->f[2]));
515 assert(!util_is_inf_or_nan((chan)->f[3]));
516 }
517
518
519 #ifdef DEBUG
520 static void
521 print_chan(const char *msg, const union tgsi_exec_channel *chan)
522 {
523 debug_printf("%s = {%f, %f, %f, %f}\n",
524 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
525 }
526 #endif
527
528
529 #ifdef DEBUG
530 static void
531 print_temp(const struct tgsi_exec_machine *mach, uint index)
532 {
533 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
534 int i;
535 debug_printf("Temp[%u] =\n", index);
536 for (i = 0; i < 4; i++) {
537 debug_printf(" %c: { %f, %f, %f, %f }\n",
538 "XYZW"[i],
539 tmp->xyzw[i].f[0],
540 tmp->xyzw[i].f[1],
541 tmp->xyzw[i].f[2],
542 tmp->xyzw[i].f[3]);
543 }
544 }
545 #endif
546
547
548 void
549 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
550 unsigned num_bufs,
551 const void **bufs,
552 const unsigned *buf_sizes)
553 {
554 unsigned i;
555
556 for (i = 0; i < num_bufs; i++) {
557 mach->Consts[i] = bufs[i];
558 mach->ConstsSize[i] = buf_sizes[i];
559 }
560 }
561
562
563 /**
564 * Check if there's a potential src/dst register data dependency when
565 * using SOA execution.
566 * Example:
567 * MOV T, T.yxwz;
568 * This would expand into:
569 * MOV t0, t1;
570 * MOV t1, t0;
571 * MOV t2, t3;
572 * MOV t3, t2;
573 * The second instruction will have the wrong value for t0 if executed as-is.
574 */
575 boolean
576 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
577 {
578 uint i, chan;
579
580 uint writemask = inst->Dst[0].Register.WriteMask;
581 if (writemask == TGSI_WRITEMASK_X ||
582 writemask == TGSI_WRITEMASK_Y ||
583 writemask == TGSI_WRITEMASK_Z ||
584 writemask == TGSI_WRITEMASK_W ||
585 writemask == TGSI_WRITEMASK_NONE) {
586 /* no chance of data dependency */
587 return FALSE;
588 }
589
590 /* loop over src regs */
591 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
592 if ((inst->Src[i].Register.File ==
593 inst->Dst[0].Register.File) &&
594 ((inst->Src[i].Register.Index ==
595 inst->Dst[0].Register.Index) ||
596 inst->Src[i].Register.Indirect ||
597 inst->Dst[0].Register.Indirect)) {
598 /* loop over dest channels */
599 uint channelsWritten = 0x0;
600 for (chan = 0; chan < NUM_CHANNELS; chan++) {
601 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
602 /* check if we're reading a channel that's been written */
603 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
604 if (channelsWritten & (1 << swizzle)) {
605 return TRUE;
606 }
607
608 channelsWritten |= (1 << chan);
609 }
610 }
611 }
612 }
613 return FALSE;
614 }
615
616
617 /**
618 * Initialize machine state by expanding tokens to full instructions,
619 * allocating temporary storage, setting up constants, etc.
620 * After this, we can call tgsi_exec_machine_run() many times.
621 */
622 void
623 tgsi_exec_machine_bind_shader(
624 struct tgsi_exec_machine *mach,
625 const struct tgsi_token *tokens,
626 uint numSamplers,
627 struct tgsi_sampler **samplers)
628 {
629 uint k;
630 struct tgsi_parse_context parse;
631 struct tgsi_full_instruction *instructions;
632 struct tgsi_full_declaration *declarations;
633 uint maxInstructions = 10, numInstructions = 0;
634 uint maxDeclarations = 10, numDeclarations = 0;
635
636 #if 0
637 tgsi_dump(tokens, 0);
638 #endif
639
640 util_init_math();
641
642 if (numSamplers) {
643 assert(samplers);
644 }
645
646 mach->Tokens = tokens;
647 mach->Samplers = samplers;
648
649 if (!tokens) {
650 /* unbind and free all */
651 if (mach->Declarations) {
652 FREE( mach->Declarations );
653 }
654 mach->Declarations = NULL;
655 mach->NumDeclarations = 0;
656
657 if (mach->Instructions) {
658 FREE( mach->Instructions );
659 }
660 mach->Instructions = NULL;
661 mach->NumInstructions = 0;
662
663 return;
664 }
665
666 k = tgsi_parse_init (&parse, mach->Tokens);
667 if (k != TGSI_PARSE_OK) {
668 debug_printf( "Problem parsing!\n" );
669 return;
670 }
671
672 mach->Processor = parse.FullHeader.Processor.Processor;
673 mach->ImmLimit = 0;
674
675 declarations = (struct tgsi_full_declaration *)
676 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
677
678 if (!declarations) {
679 return;
680 }
681
682 instructions = (struct tgsi_full_instruction *)
683 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
684
685 if (!instructions) {
686 FREE( declarations );
687 return;
688 }
689
690 while( !tgsi_parse_end_of_tokens( &parse ) ) {
691 uint i;
692
693 tgsi_parse_token( &parse );
694 switch( parse.FullToken.Token.Type ) {
695 case TGSI_TOKEN_TYPE_DECLARATION:
696 /* save expanded declaration */
697 if (numDeclarations == maxDeclarations) {
698 declarations = REALLOC(declarations,
699 maxDeclarations
700 * sizeof(struct tgsi_full_declaration),
701 (maxDeclarations + 10)
702 * sizeof(struct tgsi_full_declaration));
703 maxDeclarations += 10;
704 }
705 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
706 unsigned reg;
707 for (reg = parse.FullToken.FullDeclaration.Range.First;
708 reg <= parse.FullToken.FullDeclaration.Range.Last;
709 ++reg) {
710 ++mach->NumOutputs;
711 }
712 }
713 if (parse.FullToken.FullDeclaration.Declaration.File ==
714 TGSI_FILE_IMMEDIATE_ARRAY) {
715 unsigned reg;
716 struct tgsi_full_declaration *decl =
717 &parse.FullToken.FullDeclaration;
718 debug_assert(decl->Range.Last < TGSI_EXEC_NUM_IMMEDIATES);
719 for (reg = decl->Range.First; reg <= decl->Range.Last; ++reg) {
720 for( i = 0; i < 4; i++ ) {
721 int idx = reg * 4 + i;
722 mach->ImmArray[reg][i] = decl->ImmediateData.u[idx].Float;
723 }
724 }
725 }
726 memcpy(declarations + numDeclarations,
727 &parse.FullToken.FullDeclaration,
728 sizeof(declarations[0]));
729 numDeclarations++;
730 break;
731
732 case TGSI_TOKEN_TYPE_IMMEDIATE:
733 {
734 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
735 assert( size <= 4 );
736 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
737
738 for( i = 0; i < size; i++ ) {
739 mach->Imms[mach->ImmLimit][i] =
740 parse.FullToken.FullImmediate.u[i].Float;
741 }
742 mach->ImmLimit += 1;
743 }
744 break;
745
746 case TGSI_TOKEN_TYPE_INSTRUCTION:
747
748 /* save expanded instruction */
749 if (numInstructions == maxInstructions) {
750 instructions = REALLOC(instructions,
751 maxInstructions
752 * sizeof(struct tgsi_full_instruction),
753 (maxInstructions + 10)
754 * sizeof(struct tgsi_full_instruction));
755 maxInstructions += 10;
756 }
757
758 memcpy(instructions + numInstructions,
759 &parse.FullToken.FullInstruction,
760 sizeof(instructions[0]));
761
762 numInstructions++;
763 break;
764
765 case TGSI_TOKEN_TYPE_PROPERTY:
766 break;
767
768 default:
769 assert( 0 );
770 }
771 }
772 tgsi_parse_free (&parse);
773
774 if (mach->Declarations) {
775 FREE( mach->Declarations );
776 }
777 mach->Declarations = declarations;
778 mach->NumDeclarations = numDeclarations;
779
780 if (mach->Instructions) {
781 FREE( mach->Instructions );
782 }
783 mach->Instructions = instructions;
784 mach->NumInstructions = numInstructions;
785 }
786
787
788 struct tgsi_exec_machine *
789 tgsi_exec_machine_create( void )
790 {
791 struct tgsi_exec_machine *mach;
792 uint i;
793
794 mach = align_malloc( sizeof *mach, 16 );
795 if (!mach)
796 goto fail;
797
798 memset(mach, 0, sizeof(*mach));
799
800 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
801 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
802 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
803
804 /* Setup constants needed by the SSE2 executor. */
805 for( i = 0; i < 4; i++ ) {
806 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
807 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
808 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
809 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
810 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
811 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
812 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
813 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
814 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
815 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
816 }
817
818 #ifdef DEBUG
819 /* silence warnings */
820 (void) print_chan;
821 (void) print_temp;
822 #endif
823
824 return mach;
825
826 fail:
827 align_free(mach);
828 return NULL;
829 }
830
831
832 void
833 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
834 {
835 if (mach) {
836 if (mach->Instructions)
837 FREE(mach->Instructions);
838 if (mach->Declarations)
839 FREE(mach->Declarations);
840 }
841
842 align_free(mach);
843 }
844
845 static void
846 micro_add(union tgsi_exec_channel *dst,
847 const union tgsi_exec_channel *src0,
848 const union tgsi_exec_channel *src1)
849 {
850 dst->f[0] = src0->f[0] + src1->f[0];
851 dst->f[1] = src0->f[1] + src1->f[1];
852 dst->f[2] = src0->f[2] + src1->f[2];
853 dst->f[3] = src0->f[3] + src1->f[3];
854 }
855
856 static void
857 micro_div(
858 union tgsi_exec_channel *dst,
859 const union tgsi_exec_channel *src0,
860 const union tgsi_exec_channel *src1 )
861 {
862 if (src1->f[0] != 0) {
863 dst->f[0] = src0->f[0] / src1->f[0];
864 }
865 if (src1->f[1] != 0) {
866 dst->f[1] = src0->f[1] / src1->f[1];
867 }
868 if (src1->f[2] != 0) {
869 dst->f[2] = src0->f[2] / src1->f[2];
870 }
871 if (src1->f[3] != 0) {
872 dst->f[3] = src0->f[3] / src1->f[3];
873 }
874 }
875
876 static void
877 micro_rcc(union tgsi_exec_channel *dst,
878 const union tgsi_exec_channel *src)
879 {
880 uint i;
881
882 for (i = 0; i < 4; i++) {
883 float recip = 1.0f / src->f[i];
884
885 if (recip > 0.0f) {
886 if (recip > 1.884467e+019f) {
887 dst->f[i] = 1.884467e+019f;
888 }
889 else if (recip < 5.42101e-020f) {
890 dst->f[i] = 5.42101e-020f;
891 }
892 else {
893 dst->f[i] = recip;
894 }
895 }
896 else {
897 if (recip < -1.884467e+019f) {
898 dst->f[i] = -1.884467e+019f;
899 }
900 else if (recip > -5.42101e-020f) {
901 dst->f[i] = -5.42101e-020f;
902 }
903 else {
904 dst->f[i] = recip;
905 }
906 }
907 }
908 }
909
910 static void
911 micro_lt(
912 union tgsi_exec_channel *dst,
913 const union tgsi_exec_channel *src0,
914 const union tgsi_exec_channel *src1,
915 const union tgsi_exec_channel *src2,
916 const union tgsi_exec_channel *src3 )
917 {
918 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
919 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
920 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
921 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
922 }
923
924 static void
925 micro_max(union tgsi_exec_channel *dst,
926 const union tgsi_exec_channel *src0,
927 const union tgsi_exec_channel *src1)
928 {
929 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
930 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
931 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
932 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
933 }
934
935 static void
936 micro_min(union tgsi_exec_channel *dst,
937 const union tgsi_exec_channel *src0,
938 const union tgsi_exec_channel *src1)
939 {
940 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
941 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
942 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
943 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
944 }
945
946 static void
947 micro_mul(union tgsi_exec_channel *dst,
948 const union tgsi_exec_channel *src0,
949 const union tgsi_exec_channel *src1)
950 {
951 dst->f[0] = src0->f[0] * src1->f[0];
952 dst->f[1] = src0->f[1] * src1->f[1];
953 dst->f[2] = src0->f[2] * src1->f[2];
954 dst->f[3] = src0->f[3] * src1->f[3];
955 }
956
957 static void
958 micro_neg(
959 union tgsi_exec_channel *dst,
960 const union tgsi_exec_channel *src )
961 {
962 dst->f[0] = -src->f[0];
963 dst->f[1] = -src->f[1];
964 dst->f[2] = -src->f[2];
965 dst->f[3] = -src->f[3];
966 }
967
968 static void
969 micro_pow(
970 union tgsi_exec_channel *dst,
971 const union tgsi_exec_channel *src0,
972 const union tgsi_exec_channel *src1 )
973 {
974 #if FAST_MATH
975 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
976 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
977 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
978 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
979 #else
980 dst->f[0] = powf( src0->f[0], src1->f[0] );
981 dst->f[1] = powf( src0->f[1], src1->f[1] );
982 dst->f[2] = powf( src0->f[2], src1->f[2] );
983 dst->f[3] = powf( src0->f[3], src1->f[3] );
984 #endif
985 }
986
987 static void
988 micro_sub(union tgsi_exec_channel *dst,
989 const union tgsi_exec_channel *src0,
990 const union tgsi_exec_channel *src1)
991 {
992 dst->f[0] = src0->f[0] - src1->f[0];
993 dst->f[1] = src0->f[1] - src1->f[1];
994 dst->f[2] = src0->f[2] - src1->f[2];
995 dst->f[3] = src0->f[3] - src1->f[3];
996 }
997
998 static void
999 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1000 const uint file,
1001 const uint swizzle,
1002 const union tgsi_exec_channel *index,
1003 const union tgsi_exec_channel *index2D,
1004 union tgsi_exec_channel *chan)
1005 {
1006 uint i;
1007
1008 assert(swizzle < 4);
1009
1010 switch (file) {
1011 case TGSI_FILE_CONSTANT:
1012 for (i = 0; i < QUAD_SIZE; i++) {
1013 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1014 assert(mach->Consts[index2D->i[i]]);
1015
1016 if (index->i[i] < 0) {
1017 chan->u[i] = 0;
1018 } else {
1019 /* NOTE: copying the const value as a uint instead of float */
1020 const uint constbuf = index2D->i[i];
1021 const uint *buf = (const uint *)mach->Consts[constbuf];
1022 const int pos = index->i[i] * 4 + swizzle;
1023 /* const buffer bounds check */
1024 if (pos < 0 || pos >= mach->ConstsSize[constbuf]) {
1025 if (0) {
1026 /* Debug: print warning */
1027 static int count = 0;
1028 if (count++ < 100)
1029 debug_printf("TGSI Exec: const buffer index %d"
1030 " out of bounds\n", pos);
1031 }
1032 chan->u[i] = 0;
1033 }
1034 else
1035 chan->u[i] = buf[pos];
1036 }
1037 }
1038 break;
1039
1040 case TGSI_FILE_INPUT:
1041 case TGSI_FILE_SYSTEM_VALUE:
1042 for (i = 0; i < QUAD_SIZE; i++) {
1043 /*
1044 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1045 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1046 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1047 index2D->i[i], index->i[i]);
1048 }*/
1049 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1050 assert(pos >= 0);
1051 assert(pos < Elements(mach->Inputs));
1052 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1053 }
1054 break;
1055
1056 case TGSI_FILE_TEMPORARY:
1057 for (i = 0; i < QUAD_SIZE; i++) {
1058 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1059 assert(index2D->i[i] == 0);
1060
1061 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1062 }
1063 break;
1064
1065 case TGSI_FILE_TEMPORARY_ARRAY:
1066 for (i = 0; i < QUAD_SIZE; i++) {
1067 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1068 assert(index2D->i[i] < TGSI_EXEC_NUM_TEMP_ARRAYS);
1069
1070 chan->u[i] =
1071 mach->TempArray[index2D->i[i]][index->i[i]].xyzw[swizzle].u[i];
1072 }
1073 break;
1074
1075 case TGSI_FILE_IMMEDIATE:
1076 for (i = 0; i < QUAD_SIZE; i++) {
1077 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1078 assert(index2D->i[i] == 0);
1079
1080 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1081 }
1082 break;
1083
1084 case TGSI_FILE_IMMEDIATE_ARRAY:
1085 for (i = 0; i < QUAD_SIZE; i++) {
1086 assert(index2D->i[i] == 0);
1087
1088 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1089 }
1090 break;
1091
1092 case TGSI_FILE_ADDRESS:
1093 for (i = 0; i < QUAD_SIZE; i++) {
1094 assert(index->i[i] >= 0);
1095 assert(index2D->i[i] == 0);
1096
1097 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1098 }
1099 break;
1100
1101 case TGSI_FILE_PREDICATE:
1102 for (i = 0; i < QUAD_SIZE; i++) {
1103 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1104 assert(index2D->i[i] == 0);
1105
1106 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1107 }
1108 break;
1109
1110 case TGSI_FILE_OUTPUT:
1111 /* vertex/fragment output vars can be read too */
1112 for (i = 0; i < QUAD_SIZE; i++) {
1113 assert(index->i[i] >= 0);
1114 assert(index2D->i[i] == 0);
1115
1116 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1117 }
1118 break;
1119
1120 default:
1121 assert(0);
1122 for (i = 0; i < QUAD_SIZE; i++) {
1123 chan->u[i] = 0;
1124 }
1125 }
1126 }
1127
1128 static void
1129 fetch_source(const struct tgsi_exec_machine *mach,
1130 union tgsi_exec_channel *chan,
1131 const struct tgsi_full_src_register *reg,
1132 const uint chan_index,
1133 enum tgsi_exec_datatype src_datatype)
1134 {
1135 union tgsi_exec_channel index;
1136 union tgsi_exec_channel index2D;
1137 uint swizzle;
1138
1139 /* We start with a direct index into a register file.
1140 *
1141 * file[1],
1142 * where:
1143 * file = Register.File
1144 * [1] = Register.Index
1145 */
1146 index.i[0] =
1147 index.i[1] =
1148 index.i[2] =
1149 index.i[3] = reg->Register.Index;
1150
1151 /* There is an extra source register that indirectly subscripts
1152 * a register file. The direct index now becomes an offset
1153 * that is being added to the indirect register.
1154 *
1155 * file[ind[2].x+1],
1156 * where:
1157 * ind = Indirect.File
1158 * [2] = Indirect.Index
1159 * .x = Indirect.SwizzleX
1160 */
1161 if (reg->Register.Indirect) {
1162 union tgsi_exec_channel index2;
1163 union tgsi_exec_channel indir_index;
1164 const uint execmask = mach->ExecMask;
1165 uint i;
1166
1167 /* which address register (always zero now) */
1168 index2.i[0] =
1169 index2.i[1] =
1170 index2.i[2] =
1171 index2.i[3] = reg->Indirect.Index;
1172 assert(reg->Indirect.File == TGSI_FILE_ADDRESS);
1173 /* get current value of address register[swizzle] */
1174 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1175 fetch_src_file_channel(mach,
1176 reg->Indirect.File,
1177 swizzle,
1178 &index2,
1179 &ZeroVec,
1180 &indir_index);
1181
1182 /* add value of address register to the offset */
1183 index.i[0] += indir_index.i[0];
1184 index.i[1] += indir_index.i[1];
1185 index.i[2] += indir_index.i[2];
1186 index.i[3] += indir_index.i[3];
1187
1188 /* for disabled execution channels, zero-out the index to
1189 * avoid using a potential garbage value.
1190 */
1191 for (i = 0; i < QUAD_SIZE; i++) {
1192 if ((execmask & (1 << i)) == 0)
1193 index.i[i] = 0;
1194 }
1195 }
1196
1197 /* There is an extra source register that is a second
1198 * subscript to a register file. Effectively it means that
1199 * the register file is actually a 2D array of registers.
1200 *
1201 * file[3][1],
1202 * where:
1203 * [3] = Dimension.Index
1204 */
1205 if (reg->Register.Dimension) {
1206 index2D.i[0] =
1207 index2D.i[1] =
1208 index2D.i[2] =
1209 index2D.i[3] = reg->Dimension.Index;
1210
1211 /* Again, the second subscript index can be addressed indirectly
1212 * identically to the first one.
1213 * Nothing stops us from indirectly addressing the indirect register,
1214 * but there is no need for that, so we won't exercise it.
1215 *
1216 * file[ind[4].y+3][1],
1217 * where:
1218 * ind = DimIndirect.File
1219 * [4] = DimIndirect.Index
1220 * .y = DimIndirect.SwizzleX
1221 */
1222 if (reg->Dimension.Indirect) {
1223 union tgsi_exec_channel index2;
1224 union tgsi_exec_channel indir_index;
1225 const uint execmask = mach->ExecMask;
1226 uint i;
1227
1228 index2.i[0] =
1229 index2.i[1] =
1230 index2.i[2] =
1231 index2.i[3] = reg->DimIndirect.Index;
1232
1233 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1234 fetch_src_file_channel(mach,
1235 reg->DimIndirect.File,
1236 swizzle,
1237 &index2,
1238 &ZeroVec,
1239 &indir_index);
1240
1241 index2D.i[0] += indir_index.i[0];
1242 index2D.i[1] += indir_index.i[1];
1243 index2D.i[2] += indir_index.i[2];
1244 index2D.i[3] += indir_index.i[3];
1245
1246 /* for disabled execution channels, zero-out the index to
1247 * avoid using a potential garbage value.
1248 */
1249 for (i = 0; i < QUAD_SIZE; i++) {
1250 if ((execmask & (1 << i)) == 0) {
1251 index2D.i[i] = 0;
1252 }
1253 }
1254 }
1255
1256 /* If by any chance there was a need for a 3D array of register
1257 * files, we would have to check whether Dimension is followed
1258 * by a dimension register and continue the saga.
1259 */
1260 } else {
1261 index2D.i[0] =
1262 index2D.i[1] =
1263 index2D.i[2] =
1264 index2D.i[3] = 0;
1265 }
1266
1267 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1268 fetch_src_file_channel(mach,
1269 reg->Register.File,
1270 swizzle,
1271 &index,
1272 &index2D,
1273 chan);
1274
1275 if (reg->Register.Absolute) {
1276 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1277 micro_abs(chan, chan);
1278 } else {
1279 micro_iabs(chan, chan);
1280 }
1281 }
1282
1283 if (reg->Register.Negate) {
1284 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1285 micro_neg(chan, chan);
1286 } else {
1287 micro_ineg(chan, chan);
1288 }
1289 }
1290 }
1291
1292 static void
1293 store_dest(struct tgsi_exec_machine *mach,
1294 const union tgsi_exec_channel *chan,
1295 const struct tgsi_full_dst_register *reg,
1296 const struct tgsi_full_instruction *inst,
1297 uint chan_index,
1298 enum tgsi_exec_datatype dst_datatype)
1299 {
1300 uint i;
1301 union tgsi_exec_channel null;
1302 union tgsi_exec_channel *dst;
1303 union tgsi_exec_channel index2D;
1304 uint execmask = mach->ExecMask;
1305 int offset = 0; /* indirection offset */
1306 int index;
1307
1308 /* for debugging */
1309 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1310 check_inf_or_nan(chan);
1311 }
1312
1313 /* There is an extra source register that indirectly subscripts
1314 * a register file. The direct index now becomes an offset
1315 * that is being added to the indirect register.
1316 *
1317 * file[ind[2].x+1],
1318 * where:
1319 * ind = Indirect.File
1320 * [2] = Indirect.Index
1321 * .x = Indirect.SwizzleX
1322 */
1323 if (reg->Register.Indirect) {
1324 union tgsi_exec_channel index;
1325 union tgsi_exec_channel indir_index;
1326 uint swizzle;
1327
1328 /* which address register (always zero for now) */
1329 index.i[0] =
1330 index.i[1] =
1331 index.i[2] =
1332 index.i[3] = reg->Indirect.Index;
1333
1334 /* get current value of address register[swizzle] */
1335 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1336
1337 /* fetch values from the address/indirection register */
1338 fetch_src_file_channel(mach,
1339 reg->Indirect.File,
1340 swizzle,
1341 &index,
1342 &ZeroVec,
1343 &indir_index);
1344
1345 /* save indirection offset */
1346 offset = indir_index.i[0];
1347 }
1348
1349 /* There is an extra source register that is a second
1350 * subscript to a register file. Effectively it means that
1351 * the register file is actually a 2D array of registers.
1352 *
1353 * file[3][1],
1354 * where:
1355 * [3] = Dimension.Index
1356 */
1357 if (reg->Register.Dimension) {
1358 index2D.i[0] =
1359 index2D.i[1] =
1360 index2D.i[2] =
1361 index2D.i[3] = reg->Dimension.Index;
1362
1363 /* Again, the second subscript index can be addressed indirectly
1364 * identically to the first one.
1365 * Nothing stops us from indirectly addressing the indirect register,
1366 * but there is no need for that, so we won't exercise it.
1367 *
1368 * file[ind[4].y+3][1],
1369 * where:
1370 * ind = DimIndirect.File
1371 * [4] = DimIndirect.Index
1372 * .y = DimIndirect.SwizzleX
1373 */
1374 if (reg->Dimension.Indirect) {
1375 union tgsi_exec_channel index2;
1376 union tgsi_exec_channel indir_index;
1377 const uint execmask = mach->ExecMask;
1378 unsigned swizzle;
1379 uint i;
1380
1381 index2.i[0] =
1382 index2.i[1] =
1383 index2.i[2] =
1384 index2.i[3] = reg->DimIndirect.Index;
1385
1386 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1387 fetch_src_file_channel(mach,
1388 reg->DimIndirect.File,
1389 swizzle,
1390 &index2,
1391 &ZeroVec,
1392 &indir_index);
1393
1394 index2D.i[0] += indir_index.i[0];
1395 index2D.i[1] += indir_index.i[1];
1396 index2D.i[2] += indir_index.i[2];
1397 index2D.i[3] += indir_index.i[3];
1398
1399 /* for disabled execution channels, zero-out the index to
1400 * avoid using a potential garbage value.
1401 */
1402 for (i = 0; i < QUAD_SIZE; i++) {
1403 if ((execmask & (1 << i)) == 0) {
1404 index2D.i[i] = 0;
1405 }
1406 }
1407 }
1408
1409 /* If by any chance there was a need for a 3D array of register
1410 * files, we would have to check whether Dimension is followed
1411 * by a dimension register and continue the saga.
1412 */
1413 } else {
1414 index2D.i[0] =
1415 index2D.i[1] =
1416 index2D.i[2] =
1417 index2D.i[3] = 0;
1418 }
1419
1420 switch (reg->Register.File) {
1421 case TGSI_FILE_NULL:
1422 dst = &null;
1423 break;
1424
1425 case TGSI_FILE_OUTPUT:
1426 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1427 + reg->Register.Index;
1428 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1429 #if 0
1430 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1431 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1432 for (i = 0; i < QUAD_SIZE; i++)
1433 if (execmask & (1 << i))
1434 fprintf(stderr, "%f, ", chan->f[i]);
1435 fprintf(stderr, ")\n");
1436 }
1437 #endif
1438 break;
1439
1440 case TGSI_FILE_TEMPORARY:
1441 index = reg->Register.Index;
1442 assert( index < TGSI_EXEC_NUM_TEMPS );
1443 dst = &mach->Temps[offset + index].xyzw[chan_index];
1444 break;
1445
1446 case TGSI_FILE_TEMPORARY_ARRAY:
1447 index = reg->Register.Index;
1448 assert( index < TGSI_EXEC_NUM_TEMPS );
1449 assert( index2D.i[0] < TGSI_EXEC_NUM_TEMP_ARRAYS );
1450 /* XXX we use index2D.i[0] here but somehow we might
1451 * end up with someone trying to store indirectly in
1452 * different buffers */
1453 dst = &mach->TempArray[index2D.i[0]][offset + index].xyzw[chan_index];
1454 break;
1455
1456 case TGSI_FILE_ADDRESS:
1457 index = reg->Register.Index;
1458 dst = &mach->Addrs[index].xyzw[chan_index];
1459 break;
1460
1461 case TGSI_FILE_PREDICATE:
1462 index = reg->Register.Index;
1463 assert(index < TGSI_EXEC_NUM_PREDS);
1464 dst = &mach->Predicates[index].xyzw[chan_index];
1465 break;
1466
1467 default:
1468 assert( 0 );
1469 return;
1470 }
1471
1472 if (inst->Instruction.Predicate) {
1473 uint swizzle;
1474 union tgsi_exec_channel *pred;
1475
1476 switch (chan_index) {
1477 case CHAN_X:
1478 swizzle = inst->Predicate.SwizzleX;
1479 break;
1480 case CHAN_Y:
1481 swizzle = inst->Predicate.SwizzleY;
1482 break;
1483 case CHAN_Z:
1484 swizzle = inst->Predicate.SwizzleZ;
1485 break;
1486 case CHAN_W:
1487 swizzle = inst->Predicate.SwizzleW;
1488 break;
1489 default:
1490 assert(0);
1491 return;
1492 }
1493
1494 assert(inst->Predicate.Index == 0);
1495
1496 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1497
1498 if (inst->Predicate.Negate) {
1499 for (i = 0; i < QUAD_SIZE; i++) {
1500 if (pred->u[i]) {
1501 execmask &= ~(1 << i);
1502 }
1503 }
1504 } else {
1505 for (i = 0; i < QUAD_SIZE; i++) {
1506 if (!pred->u[i]) {
1507 execmask &= ~(1 << i);
1508 }
1509 }
1510 }
1511 }
1512
1513 switch (inst->Instruction.Saturate) {
1514 case TGSI_SAT_NONE:
1515 for (i = 0; i < QUAD_SIZE; i++)
1516 if (execmask & (1 << i))
1517 dst->i[i] = chan->i[i];
1518 break;
1519
1520 case TGSI_SAT_ZERO_ONE:
1521 for (i = 0; i < QUAD_SIZE; i++)
1522 if (execmask & (1 << i)) {
1523 if (chan->f[i] < 0.0f)
1524 dst->f[i] = 0.0f;
1525 else if (chan->f[i] > 1.0f)
1526 dst->f[i] = 1.0f;
1527 else
1528 dst->i[i] = chan->i[i];
1529 }
1530 break;
1531
1532 case TGSI_SAT_MINUS_PLUS_ONE:
1533 for (i = 0; i < QUAD_SIZE; i++)
1534 if (execmask & (1 << i)) {
1535 if (chan->f[i] < -1.0f)
1536 dst->f[i] = -1.0f;
1537 else if (chan->f[i] > 1.0f)
1538 dst->f[i] = 1.0f;
1539 else
1540 dst->i[i] = chan->i[i];
1541 }
1542 break;
1543
1544 default:
1545 assert( 0 );
1546 }
1547 }
1548
1549 #define FETCH(VAL,INDEX,CHAN)\
1550 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1551
1552
1553 /**
1554 * Execute ARB-style KIL which is predicated by a src register.
1555 * Kill fragment if any of the four values is less than zero.
1556 */
1557 static void
1558 exec_kil(struct tgsi_exec_machine *mach,
1559 const struct tgsi_full_instruction *inst)
1560 {
1561 uint uniquemask;
1562 uint chan_index;
1563 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1564 union tgsi_exec_channel r[1];
1565
1566 /* This mask stores component bits that were already tested. */
1567 uniquemask = 0;
1568
1569 for (chan_index = 0; chan_index < 4; chan_index++)
1570 {
1571 uint swizzle;
1572 uint i;
1573
1574 /* unswizzle channel */
1575 swizzle = tgsi_util_get_full_src_register_swizzle (
1576 &inst->Src[0],
1577 chan_index);
1578
1579 /* check if the component has not been already tested */
1580 if (uniquemask & (1 << swizzle))
1581 continue;
1582 uniquemask |= 1 << swizzle;
1583
1584 FETCH(&r[0], 0, chan_index);
1585 for (i = 0; i < 4; i++)
1586 if (r[0].f[i] < 0.0f)
1587 kilmask |= 1 << i;
1588 }
1589
1590 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1591 }
1592
1593 /**
1594 * Execute NVIDIA-style KIL which is predicated by a condition code.
1595 * Kill fragment if the condition code is TRUE.
1596 */
1597 static void
1598 exec_kilp(struct tgsi_exec_machine *mach,
1599 const struct tgsi_full_instruction *inst)
1600 {
1601 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1602
1603 /* "unconditional" kil */
1604 kilmask = mach->ExecMask;
1605 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1606 }
1607
1608 static void
1609 emit_vertex(struct tgsi_exec_machine *mach)
1610 {
1611 /* FIXME: check for exec mask correctly
1612 unsigned i;
1613 for (i = 0; i < QUAD_SIZE; ++i) {
1614 if ((mach->ExecMask & (1 << i)))
1615 */
1616 if (mach->ExecMask) {
1617 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1618 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1619 }
1620 }
1621
1622 static void
1623 emit_primitive(struct tgsi_exec_machine *mach)
1624 {
1625 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1626 /* FIXME: check for exec mask correctly
1627 unsigned i;
1628 for (i = 0; i < QUAD_SIZE; ++i) {
1629 if ((mach->ExecMask & (1 << i)))
1630 */
1631 if (mach->ExecMask) {
1632 ++(*prim_count);
1633 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1634 mach->Primitives[*prim_count] = 0;
1635 }
1636 }
1637
1638 static void
1639 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1640 {
1641 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1642 int emitted_verts =
1643 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1644 if (emitted_verts) {
1645 emit_primitive(mach);
1646 }
1647 }
1648 }
1649
1650
1651 /*
1652 * Fetch four texture samples using STR texture coordinates.
1653 */
1654 static void
1655 fetch_texel( struct tgsi_sampler *sampler,
1656 const union tgsi_exec_channel *s,
1657 const union tgsi_exec_channel *t,
1658 const union tgsi_exec_channel *p,
1659 const union tgsi_exec_channel *c0,
1660 enum tgsi_sampler_control control,
1661 union tgsi_exec_channel *r,
1662 union tgsi_exec_channel *g,
1663 union tgsi_exec_channel *b,
1664 union tgsi_exec_channel *a )
1665 {
1666 uint j;
1667 float rgba[NUM_CHANNELS][QUAD_SIZE];
1668
1669 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, control, rgba);
1670
1671 for (j = 0; j < 4; j++) {
1672 r->f[j] = rgba[0][j];
1673 g->f[j] = rgba[1][j];
1674 b->f[j] = rgba[2][j];
1675 a->f[j] = rgba[3][j];
1676 }
1677 }
1678
1679
1680 #define TEX_MODIFIER_NONE 0
1681 #define TEX_MODIFIER_PROJECTED 1
1682 #define TEX_MODIFIER_LOD_BIAS 2
1683 #define TEX_MODIFIER_EXPLICIT_LOD 3
1684
1685
1686 static void
1687 exec_tex(struct tgsi_exec_machine *mach,
1688 const struct tgsi_full_instruction *inst,
1689 uint modifier)
1690 {
1691 const uint unit = inst->Src[1].Register.Index;
1692 union tgsi_exec_channel r[4];
1693 const union tgsi_exec_channel *lod = &ZeroVec;
1694 enum tgsi_sampler_control control;
1695 uint chan;
1696
1697 if (modifier != TEX_MODIFIER_NONE) {
1698 FETCH(&r[3], 0, CHAN_W);
1699 if (modifier != TEX_MODIFIER_PROJECTED) {
1700 lod = &r[3];
1701 }
1702 }
1703
1704 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1705 control = tgsi_sampler_lod_explicit;
1706 } else {
1707 control = tgsi_sampler_lod_bias;
1708 }
1709
1710 switch (inst->Texture.Texture) {
1711 case TGSI_TEXTURE_1D:
1712 case TGSI_TEXTURE_SHADOW1D:
1713 FETCH(&r[0], 0, CHAN_X);
1714
1715 if (modifier == TEX_MODIFIER_PROJECTED) {
1716 micro_div(&r[0], &r[0], &r[3]);
1717 }
1718
1719 fetch_texel(mach->Samplers[unit],
1720 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1721 control,
1722 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1723 break;
1724
1725 case TGSI_TEXTURE_2D:
1726 case TGSI_TEXTURE_RECT:
1727 case TGSI_TEXTURE_SHADOW2D:
1728 case TGSI_TEXTURE_SHADOWRECT:
1729 FETCH(&r[0], 0, CHAN_X);
1730 FETCH(&r[1], 0, CHAN_Y);
1731 FETCH(&r[2], 0, CHAN_Z);
1732
1733 if (modifier == TEX_MODIFIER_PROJECTED) {
1734 micro_div(&r[0], &r[0], &r[3]);
1735 micro_div(&r[1], &r[1], &r[3]);
1736 micro_div(&r[2], &r[2], &r[3]);
1737 }
1738
1739 fetch_texel(mach->Samplers[unit],
1740 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1741 control,
1742 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1743 break;
1744
1745 case TGSI_TEXTURE_3D:
1746 case TGSI_TEXTURE_CUBE:
1747 FETCH(&r[0], 0, CHAN_X);
1748 FETCH(&r[1], 0, CHAN_Y);
1749 FETCH(&r[2], 0, CHAN_Z);
1750
1751 if (modifier == TEX_MODIFIER_PROJECTED) {
1752 micro_div(&r[0], &r[0], &r[3]);
1753 micro_div(&r[1], &r[1], &r[3]);
1754 micro_div(&r[2], &r[2], &r[3]);
1755 }
1756
1757 fetch_texel(mach->Samplers[unit],
1758 &r[0], &r[1], &r[2], lod,
1759 control,
1760 &r[0], &r[1], &r[2], &r[3]);
1761 break;
1762
1763 default:
1764 assert(0);
1765 }
1766
1767 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1768 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1769 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1770 }
1771 }
1772 }
1773
1774 static void
1775 exec_txd(struct tgsi_exec_machine *mach,
1776 const struct tgsi_full_instruction *inst)
1777 {
1778 const uint unit = inst->Src[3].Register.Index;
1779 union tgsi_exec_channel r[4];
1780 uint chan;
1781
1782 /*
1783 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1784 */
1785
1786 switch (inst->Texture.Texture) {
1787 case TGSI_TEXTURE_1D:
1788 case TGSI_TEXTURE_SHADOW1D:
1789
1790 FETCH(&r[0], 0, CHAN_X);
1791
1792 fetch_texel(mach->Samplers[unit],
1793 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1794 tgsi_sampler_lod_bias,
1795 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1796 break;
1797
1798 case TGSI_TEXTURE_2D:
1799 case TGSI_TEXTURE_RECT:
1800 case TGSI_TEXTURE_SHADOW2D:
1801 case TGSI_TEXTURE_SHADOWRECT:
1802
1803 FETCH(&r[0], 0, CHAN_X);
1804 FETCH(&r[1], 0, CHAN_Y);
1805 FETCH(&r[2], 0, CHAN_Z);
1806
1807 fetch_texel(mach->Samplers[unit],
1808 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
1809 tgsi_sampler_lod_bias,
1810 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1811 break;
1812
1813 case TGSI_TEXTURE_3D:
1814 case TGSI_TEXTURE_CUBE:
1815
1816 FETCH(&r[0], 0, CHAN_X);
1817 FETCH(&r[1], 0, CHAN_Y);
1818 FETCH(&r[2], 0, CHAN_Z);
1819
1820 fetch_texel(mach->Samplers[unit],
1821 &r[0], &r[1], &r[2], &ZeroVec,
1822 tgsi_sampler_lod_bias,
1823 &r[0], &r[1], &r[2], &r[3]);
1824 break;
1825
1826 default:
1827 assert(0);
1828 }
1829
1830 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1831 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1832 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1833 }
1834 }
1835 }
1836
1837
1838 /**
1839 * Evaluate a constant-valued coefficient at the position of the
1840 * current quad.
1841 */
1842 static void
1843 eval_constant_coef(
1844 struct tgsi_exec_machine *mach,
1845 unsigned attrib,
1846 unsigned chan )
1847 {
1848 unsigned i;
1849
1850 for( i = 0; i < QUAD_SIZE; i++ ) {
1851 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
1852 }
1853 }
1854
1855 /**
1856 * Evaluate a linear-valued coefficient at the position of the
1857 * current quad.
1858 */
1859 static void
1860 eval_linear_coef(
1861 struct tgsi_exec_machine *mach,
1862 unsigned attrib,
1863 unsigned chan )
1864 {
1865 const float x = mach->QuadPos.xyzw[0].f[0];
1866 const float y = mach->QuadPos.xyzw[1].f[0];
1867 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1868 const float dady = mach->InterpCoefs[attrib].dady[chan];
1869 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1870 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
1871 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
1872 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
1873 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
1874 }
1875
1876 /**
1877 * Evaluate a perspective-valued coefficient at the position of the
1878 * current quad.
1879 */
1880 static void
1881 eval_perspective_coef(
1882 struct tgsi_exec_machine *mach,
1883 unsigned attrib,
1884 unsigned chan )
1885 {
1886 const float x = mach->QuadPos.xyzw[0].f[0];
1887 const float y = mach->QuadPos.xyzw[1].f[0];
1888 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1889 const float dady = mach->InterpCoefs[attrib].dady[chan];
1890 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1891 const float *w = mach->QuadPos.xyzw[3].f;
1892 /* divide by W here */
1893 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
1894 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
1895 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
1896 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
1897 }
1898
1899
1900 typedef void (* eval_coef_func)(
1901 struct tgsi_exec_machine *mach,
1902 unsigned attrib,
1903 unsigned chan );
1904
1905 static void
1906 exec_declaration(struct tgsi_exec_machine *mach,
1907 const struct tgsi_full_declaration *decl)
1908 {
1909 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
1910 if (decl->Declaration.File == TGSI_FILE_INPUT ||
1911 decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1912 uint first, last, mask;
1913
1914 first = decl->Range.First;
1915 last = decl->Range.Last;
1916 mask = decl->Declaration.UsageMask;
1917
1918 /* XXX we could remove this special-case code since
1919 * mach->InterpCoefs[first].a0 should already have the
1920 * front/back-face value. But we should first update the
1921 * ureg code to emit the right UsageMask value (WRITEMASK_X).
1922 * Then, we could remove the tgsi_exec_machine::Face field.
1923 */
1924 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1925 uint i;
1926
1927 assert(decl->Semantic.Index == 0);
1928 assert(first == last);
1929
1930 for (i = 0; i < QUAD_SIZE; i++) {
1931 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
1932 }
1933 } else {
1934 eval_coef_func eval;
1935 uint i, j;
1936
1937 switch (decl->Declaration.Interpolate) {
1938 case TGSI_INTERPOLATE_CONSTANT:
1939 eval = eval_constant_coef;
1940 break;
1941
1942 case TGSI_INTERPOLATE_LINEAR:
1943 eval = eval_linear_coef;
1944 break;
1945
1946 case TGSI_INTERPOLATE_PERSPECTIVE:
1947 eval = eval_perspective_coef;
1948 break;
1949
1950 default:
1951 assert(0);
1952 return;
1953 }
1954
1955 for (j = 0; j < NUM_CHANNELS; j++) {
1956 if (mask & (1 << j)) {
1957 for (i = first; i <= last; i++) {
1958 eval(mach, i, j);
1959 }
1960 }
1961 }
1962 }
1963 }
1964 }
1965 }
1966
1967 typedef void (* micro_op)(union tgsi_exec_channel *dst);
1968
1969 static void
1970 exec_vector(struct tgsi_exec_machine *mach,
1971 const struct tgsi_full_instruction *inst,
1972 micro_op op,
1973 enum tgsi_exec_datatype dst_datatype)
1974 {
1975 unsigned int chan;
1976
1977 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1978 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1979 union tgsi_exec_channel dst;
1980
1981 op(&dst);
1982 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
1983 }
1984 }
1985 }
1986
1987 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
1988 const union tgsi_exec_channel *src);
1989
1990 static void
1991 exec_scalar_unary(struct tgsi_exec_machine *mach,
1992 const struct tgsi_full_instruction *inst,
1993 micro_unary_op op,
1994 enum tgsi_exec_datatype dst_datatype,
1995 enum tgsi_exec_datatype src_datatype)
1996 {
1997 unsigned int chan;
1998 union tgsi_exec_channel src;
1999 union tgsi_exec_channel dst;
2000
2001 fetch_source(mach, &src, &inst->Src[0], CHAN_X, src_datatype);
2002 op(&dst, &src);
2003 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2004 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2005 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2006 }
2007 }
2008 }
2009
2010 static void
2011 exec_vector_unary(struct tgsi_exec_machine *mach,
2012 const struct tgsi_full_instruction *inst,
2013 micro_unary_op op,
2014 enum tgsi_exec_datatype dst_datatype,
2015 enum tgsi_exec_datatype src_datatype)
2016 {
2017 unsigned int chan;
2018 struct tgsi_exec_vector dst;
2019
2020 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2021 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2022 union tgsi_exec_channel src;
2023
2024 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2025 op(&dst.xyzw[chan], &src);
2026 }
2027 }
2028 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2029 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2030 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2031 }
2032 }
2033 }
2034
2035 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2036 const union tgsi_exec_channel *src0,
2037 const union tgsi_exec_channel *src1);
2038
2039 static void
2040 exec_scalar_binary(struct tgsi_exec_machine *mach,
2041 const struct tgsi_full_instruction *inst,
2042 micro_binary_op op,
2043 enum tgsi_exec_datatype dst_datatype,
2044 enum tgsi_exec_datatype src_datatype)
2045 {
2046 unsigned int chan;
2047 union tgsi_exec_channel src[2];
2048 union tgsi_exec_channel dst;
2049
2050 fetch_source(mach, &src[0], &inst->Src[0], CHAN_X, src_datatype);
2051 fetch_source(mach, &src[1], &inst->Src[1], CHAN_Y, src_datatype);
2052 op(&dst, &src[0], &src[1]);
2053 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2054 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2055 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2056 }
2057 }
2058 }
2059
2060 static void
2061 exec_vector_binary(struct tgsi_exec_machine *mach,
2062 const struct tgsi_full_instruction *inst,
2063 micro_binary_op op,
2064 enum tgsi_exec_datatype dst_datatype,
2065 enum tgsi_exec_datatype src_datatype)
2066 {
2067 unsigned int chan;
2068 struct tgsi_exec_vector dst;
2069
2070 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2071 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2072 union tgsi_exec_channel src[2];
2073
2074 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2075 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2076 op(&dst.xyzw[chan], &src[0], &src[1]);
2077 }
2078 }
2079 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2080 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2081 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2082 }
2083 }
2084 }
2085
2086 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2087 const union tgsi_exec_channel *src0,
2088 const union tgsi_exec_channel *src1,
2089 const union tgsi_exec_channel *src2);
2090
2091 static void
2092 exec_vector_trinary(struct tgsi_exec_machine *mach,
2093 const struct tgsi_full_instruction *inst,
2094 micro_trinary_op op,
2095 enum tgsi_exec_datatype dst_datatype,
2096 enum tgsi_exec_datatype src_datatype)
2097 {
2098 unsigned int chan;
2099 struct tgsi_exec_vector dst;
2100
2101 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2102 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2103 union tgsi_exec_channel src[3];
2104
2105 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2106 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2107 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2108 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2109 }
2110 }
2111 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2112 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2113 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2114 }
2115 }
2116 }
2117
2118 static void
2119 exec_dp3(struct tgsi_exec_machine *mach,
2120 const struct tgsi_full_instruction *inst)
2121 {
2122 unsigned int chan;
2123 union tgsi_exec_channel arg[3];
2124
2125 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2126 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2127 micro_mul(&arg[2], &arg[0], &arg[1]);
2128
2129 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2130 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2131 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2132 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2133 }
2134
2135 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2136 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2137 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2138 }
2139 }
2140 }
2141
2142 static void
2143 exec_dp4(struct tgsi_exec_machine *mach,
2144 const struct tgsi_full_instruction *inst)
2145 {
2146 unsigned int chan;
2147 union tgsi_exec_channel arg[3];
2148
2149 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2150 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2151 micro_mul(&arg[2], &arg[0], &arg[1]);
2152
2153 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2154 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2155 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2156 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2157 }
2158
2159 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2160 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2161 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2162 }
2163 }
2164 }
2165
2166 static void
2167 exec_dp2a(struct tgsi_exec_machine *mach,
2168 const struct tgsi_full_instruction *inst)
2169 {
2170 unsigned int chan;
2171 union tgsi_exec_channel arg[3];
2172
2173 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2174 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2175 micro_mul(&arg[2], &arg[0], &arg[1]);
2176
2177 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2178 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2179 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2180
2181 fetch_source(mach, &arg[1], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2182 micro_add(&arg[0], &arg[0], &arg[1]);
2183
2184 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2185 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2186 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2187 }
2188 }
2189 }
2190
2191 static void
2192 exec_dph(struct tgsi_exec_machine *mach,
2193 const struct tgsi_full_instruction *inst)
2194 {
2195 unsigned int chan;
2196 union tgsi_exec_channel arg[3];
2197
2198 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2199 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2200 micro_mul(&arg[2], &arg[0], &arg[1]);
2201
2202 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2203 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2204 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2205
2206 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2207 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2208 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2209
2210 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2211 micro_add(&arg[0], &arg[0], &arg[1]);
2212
2213 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2214 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2215 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2216 }
2217 }
2218 }
2219
2220 static void
2221 exec_dp2(struct tgsi_exec_machine *mach,
2222 const struct tgsi_full_instruction *inst)
2223 {
2224 unsigned int chan;
2225 union tgsi_exec_channel arg[3];
2226
2227 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2228 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2229 micro_mul(&arg[2], &arg[0], &arg[1]);
2230
2231 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2232 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2233 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2234
2235 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2236 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2237 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2238 }
2239 }
2240 }
2241
2242 static void
2243 exec_nrm4(struct tgsi_exec_machine *mach,
2244 const struct tgsi_full_instruction *inst)
2245 {
2246 unsigned int chan;
2247 union tgsi_exec_channel arg[4];
2248 union tgsi_exec_channel scale;
2249
2250 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2251 micro_mul(&scale, &arg[0], &arg[0]);
2252
2253 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2254 union tgsi_exec_channel product;
2255
2256 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2257 micro_mul(&product, &arg[chan], &arg[chan]);
2258 micro_add(&scale, &scale, &product);
2259 }
2260
2261 micro_rsq(&scale, &scale);
2262
2263 for (chan = CHAN_X; chan <= CHAN_W; chan++) {
2264 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2265 micro_mul(&arg[chan], &arg[chan], &scale);
2266 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2267 }
2268 }
2269 }
2270
2271 static void
2272 exec_nrm3(struct tgsi_exec_machine *mach,
2273 const struct tgsi_full_instruction *inst)
2274 {
2275 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2276 unsigned int chan;
2277 union tgsi_exec_channel arg[3];
2278 union tgsi_exec_channel scale;
2279
2280 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2281 micro_mul(&scale, &arg[0], &arg[0]);
2282
2283 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2284 union tgsi_exec_channel product;
2285
2286 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2287 micro_mul(&product, &arg[chan], &arg[chan]);
2288 micro_add(&scale, &scale, &product);
2289 }
2290
2291 micro_rsq(&scale, &scale);
2292
2293 for (chan = CHAN_X; chan <= CHAN_Z; chan++) {
2294 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2295 micro_mul(&arg[chan], &arg[chan], &scale);
2296 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2297 }
2298 }
2299 }
2300
2301 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2302 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2303 }
2304 }
2305
2306 static void
2307 exec_scs(struct tgsi_exec_machine *mach,
2308 const struct tgsi_full_instruction *inst)
2309 {
2310 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2311 union tgsi_exec_channel arg;
2312 union tgsi_exec_channel result;
2313
2314 fetch_source(mach, &arg, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2315
2316 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2317 micro_cos(&result, &arg);
2318 store_dest(mach, &result, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2319 }
2320 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2321 micro_sin(&result, &arg);
2322 store_dest(mach, &result, &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2323 }
2324 }
2325 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2326 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2327 }
2328 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2329 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2330 }
2331 }
2332
2333 static void
2334 exec_x2d(struct tgsi_exec_machine *mach,
2335 const struct tgsi_full_instruction *inst)
2336 {
2337 union tgsi_exec_channel r[4];
2338 union tgsi_exec_channel d[2];
2339
2340 fetch_source(mach, &r[0], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2341 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2342 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2343 fetch_source(mach, &r[2], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2344 micro_mul(&r[2], &r[2], &r[0]);
2345 fetch_source(mach, &r[3], &inst->Src[2], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2346 micro_mul(&r[3], &r[3], &r[1]);
2347 micro_add(&r[2], &r[2], &r[3]);
2348 fetch_source(mach, &r[3], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2349 micro_add(&d[0], &r[2], &r[3]);
2350 }
2351 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2352 fetch_source(mach, &r[2], &inst->Src[2], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2353 micro_mul(&r[2], &r[2], &r[0]);
2354 fetch_source(mach, &r[3], &inst->Src[2], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2355 micro_mul(&r[3], &r[3], &r[1]);
2356 micro_add(&r[2], &r[2], &r[3]);
2357 fetch_source(mach, &r[3], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2358 micro_add(&d[1], &r[2], &r[3]);
2359 }
2360 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2361 store_dest(mach, &d[0], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2362 }
2363 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2364 store_dest(mach, &d[1], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2365 }
2366 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2367 store_dest(mach, &d[0], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2368 }
2369 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2370 store_dest(mach, &d[1], &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2371 }
2372 }
2373
2374 static void
2375 exec_rfl(struct tgsi_exec_machine *mach,
2376 const struct tgsi_full_instruction *inst)
2377 {
2378 union tgsi_exec_channel r[9];
2379
2380 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2381 /* r0 = dp3(src0, src0) */
2382 fetch_source(mach, &r[2], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2383 micro_mul(&r[0], &r[2], &r[2]);
2384 fetch_source(mach, &r[4], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2385 micro_mul(&r[8], &r[4], &r[4]);
2386 micro_add(&r[0], &r[0], &r[8]);
2387 fetch_source(mach, &r[6], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2388 micro_mul(&r[8], &r[6], &r[6]);
2389 micro_add(&r[0], &r[0], &r[8]);
2390
2391 /* r1 = dp3(src0, src1) */
2392 fetch_source(mach, &r[3], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2393 micro_mul(&r[1], &r[2], &r[3]);
2394 fetch_source(mach, &r[5], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2395 micro_mul(&r[8], &r[4], &r[5]);
2396 micro_add(&r[1], &r[1], &r[8]);
2397 fetch_source(mach, &r[7], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2398 micro_mul(&r[8], &r[6], &r[7]);
2399 micro_add(&r[1], &r[1], &r[8]);
2400
2401 /* r1 = 2 * r1 / r0 */
2402 micro_add(&r[1], &r[1], &r[1]);
2403 micro_div(&r[1], &r[1], &r[0]);
2404
2405 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2406 micro_mul(&r[2], &r[2], &r[1]);
2407 micro_sub(&r[2], &r[2], &r[3]);
2408 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2409 }
2410 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2411 micro_mul(&r[4], &r[4], &r[1]);
2412 micro_sub(&r[4], &r[4], &r[5]);
2413 store_dest(mach, &r[4], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2414 }
2415 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2416 micro_mul(&r[6], &r[6], &r[1]);
2417 micro_sub(&r[6], &r[6], &r[7]);
2418 store_dest(mach, &r[6], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2419 }
2420 }
2421 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2422 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2423 }
2424 }
2425
2426 static void
2427 exec_xpd(struct tgsi_exec_machine *mach,
2428 const struct tgsi_full_instruction *inst)
2429 {
2430 union tgsi_exec_channel r[6];
2431 union tgsi_exec_channel d[3];
2432
2433 fetch_source(mach, &r[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2434 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2435
2436 micro_mul(&r[2], &r[0], &r[1]);
2437
2438 fetch_source(mach, &r[3], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2439 fetch_source(mach, &r[4], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2440
2441 micro_mul(&r[5], &r[3], &r[4] );
2442 micro_sub(&d[CHAN_X], &r[2], &r[5]);
2443
2444 fetch_source(mach, &r[2], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2445
2446 micro_mul(&r[3], &r[3], &r[2]);
2447
2448 fetch_source(mach, &r[5], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2449
2450 micro_mul(&r[1], &r[1], &r[5]);
2451 micro_sub(&d[CHAN_Y], &r[3], &r[1]);
2452
2453 micro_mul(&r[5], &r[5], &r[4]);
2454 micro_mul(&r[0], &r[0], &r[2]);
2455 micro_sub(&d[CHAN_Z], &r[5], &r[0]);
2456
2457 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2458 store_dest(mach, &d[CHAN_X], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2459 }
2460 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2461 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2462 }
2463 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2464 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2465 }
2466 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2467 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2468 }
2469 }
2470
2471 static void
2472 exec_dst(struct tgsi_exec_machine *mach,
2473 const struct tgsi_full_instruction *inst)
2474 {
2475 union tgsi_exec_channel r[2];
2476 union tgsi_exec_channel d[4];
2477
2478 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2479 fetch_source(mach, &r[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2480 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2481 micro_mul(&d[CHAN_Y], &r[0], &r[1]);
2482 }
2483 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2484 fetch_source(mach, &d[CHAN_Z], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2485 }
2486 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2487 fetch_source(mach, &d[CHAN_W], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2488 }
2489
2490 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2491 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2492 }
2493 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2494 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2495 }
2496 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2497 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2498 }
2499 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2500 store_dest(mach, &d[CHAN_W], &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2501 }
2502 }
2503
2504 static void
2505 exec_log(struct tgsi_exec_machine *mach,
2506 const struct tgsi_full_instruction *inst)
2507 {
2508 union tgsi_exec_channel r[3];
2509
2510 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2511 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
2512 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
2513 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
2514 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2515 store_dest(mach, &r[0], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2516 }
2517 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2518 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
2519 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
2520 store_dest(mach, &r[0], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2521 }
2522 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2523 store_dest(mach, &r[1], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2524 }
2525 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2526 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2527 }
2528 }
2529
2530 static void
2531 exec_exp(struct tgsi_exec_machine *mach,
2532 const struct tgsi_full_instruction *inst)
2533 {
2534 union tgsi_exec_channel r[3];
2535
2536 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2537 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
2538 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2539 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
2540 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2541 }
2542 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2543 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
2544 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2545 }
2546 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2547 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
2548 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2549 }
2550 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2551 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2552 }
2553 }
2554
2555 static void
2556 exec_lit(struct tgsi_exec_machine *mach,
2557 const struct tgsi_full_instruction *inst)
2558 {
2559 union tgsi_exec_channel r[3];
2560 union tgsi_exec_channel d[3];
2561
2562 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2563 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2564 }
2565 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
2566 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2567 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2568 micro_max(&d[CHAN_Y], &r[0], &ZeroVec);
2569 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2570 }
2571
2572 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2573 fetch_source(mach, &r[1], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2574 micro_max(&r[1], &r[1], &ZeroVec);
2575
2576 fetch_source(mach, &r[2], &inst->Src[0], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2577 micro_min(&r[2], &r[2], &P128Vec);
2578 micro_max(&r[2], &r[2], &M128Vec);
2579 micro_pow(&r[1], &r[1], &r[2]);
2580 micro_lt(&d[CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
2581 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2582 }
2583 }
2584 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2585 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2586 }
2587 }
2588
2589 static void
2590 exec_break(struct tgsi_exec_machine *mach)
2591 {
2592 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
2593 /* turn off loop channels for each enabled exec channel */
2594 mach->LoopMask &= ~mach->ExecMask;
2595 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2596 UPDATE_EXEC_MASK(mach);
2597 } else {
2598 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
2599
2600 mach->Switch.mask = 0x0;
2601
2602 UPDATE_EXEC_MASK(mach);
2603 }
2604 }
2605
2606 static void
2607 exec_switch(struct tgsi_exec_machine *mach,
2608 const struct tgsi_full_instruction *inst)
2609 {
2610 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
2611 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
2612
2613 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
2614 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2615 mach->Switch.mask = 0x0;
2616 mach->Switch.defaultMask = 0x0;
2617
2618 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
2619 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
2620
2621 UPDATE_EXEC_MASK(mach);
2622 }
2623
2624 static void
2625 exec_case(struct tgsi_exec_machine *mach,
2626 const struct tgsi_full_instruction *inst)
2627 {
2628 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2629 union tgsi_exec_channel src;
2630 uint mask = 0;
2631
2632 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2633
2634 if (mach->Switch.selector.u[0] == src.u[0]) {
2635 mask |= 0x1;
2636 }
2637 if (mach->Switch.selector.u[1] == src.u[1]) {
2638 mask |= 0x2;
2639 }
2640 if (mach->Switch.selector.u[2] == src.u[2]) {
2641 mask |= 0x4;
2642 }
2643 if (mach->Switch.selector.u[3] == src.u[3]) {
2644 mask |= 0x8;
2645 }
2646
2647 mach->Switch.defaultMask |= mask;
2648
2649 mach->Switch.mask |= mask & prevMask;
2650
2651 UPDATE_EXEC_MASK(mach);
2652 }
2653
2654 static void
2655 exec_default(struct tgsi_exec_machine *mach)
2656 {
2657 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2658
2659 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
2660
2661 UPDATE_EXEC_MASK(mach);
2662 }
2663
2664 static void
2665 exec_endswitch(struct tgsi_exec_machine *mach)
2666 {
2667 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
2668 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
2669
2670 UPDATE_EXEC_MASK(mach);
2671 }
2672
2673 static void
2674 micro_i2f(union tgsi_exec_channel *dst,
2675 const union tgsi_exec_channel *src)
2676 {
2677 dst->f[0] = (float)src->i[0];
2678 dst->f[1] = (float)src->i[1];
2679 dst->f[2] = (float)src->i[2];
2680 dst->f[3] = (float)src->i[3];
2681 }
2682
2683 static void
2684 micro_not(union tgsi_exec_channel *dst,
2685 const union tgsi_exec_channel *src)
2686 {
2687 dst->u[0] = ~src->u[0];
2688 dst->u[1] = ~src->u[1];
2689 dst->u[2] = ~src->u[2];
2690 dst->u[3] = ~src->u[3];
2691 }
2692
2693 static void
2694 micro_shl(union tgsi_exec_channel *dst,
2695 const union tgsi_exec_channel *src0,
2696 const union tgsi_exec_channel *src1)
2697 {
2698 dst->u[0] = src0->u[0] << src1->u[0];
2699 dst->u[1] = src0->u[1] << src1->u[1];
2700 dst->u[2] = src0->u[2] << src1->u[2];
2701 dst->u[3] = src0->u[3] << src1->u[3];
2702 }
2703
2704 static void
2705 micro_and(union tgsi_exec_channel *dst,
2706 const union tgsi_exec_channel *src0,
2707 const union tgsi_exec_channel *src1)
2708 {
2709 dst->u[0] = src0->u[0] & src1->u[0];
2710 dst->u[1] = src0->u[1] & src1->u[1];
2711 dst->u[2] = src0->u[2] & src1->u[2];
2712 dst->u[3] = src0->u[3] & src1->u[3];
2713 }
2714
2715 static void
2716 micro_or(union tgsi_exec_channel *dst,
2717 const union tgsi_exec_channel *src0,
2718 const union tgsi_exec_channel *src1)
2719 {
2720 dst->u[0] = src0->u[0] | src1->u[0];
2721 dst->u[1] = src0->u[1] | src1->u[1];
2722 dst->u[2] = src0->u[2] | src1->u[2];
2723 dst->u[3] = src0->u[3] | src1->u[3];
2724 }
2725
2726 static void
2727 micro_xor(union tgsi_exec_channel *dst,
2728 const union tgsi_exec_channel *src0,
2729 const union tgsi_exec_channel *src1)
2730 {
2731 dst->u[0] = src0->u[0] ^ src1->u[0];
2732 dst->u[1] = src0->u[1] ^ src1->u[1];
2733 dst->u[2] = src0->u[2] ^ src1->u[2];
2734 dst->u[3] = src0->u[3] ^ src1->u[3];
2735 }
2736
2737 static void
2738 micro_f2i(union tgsi_exec_channel *dst,
2739 const union tgsi_exec_channel *src)
2740 {
2741 dst->i[0] = (int)src->f[0];
2742 dst->i[1] = (int)src->f[1];
2743 dst->i[2] = (int)src->f[2];
2744 dst->i[3] = (int)src->f[3];
2745 }
2746
2747 static void
2748 micro_idiv(union tgsi_exec_channel *dst,
2749 const union tgsi_exec_channel *src0,
2750 const union tgsi_exec_channel *src1)
2751 {
2752 dst->i[0] = src0->i[0] / src1->i[0];
2753 dst->i[1] = src0->i[1] / src1->i[1];
2754 dst->i[2] = src0->i[2] / src1->i[2];
2755 dst->i[3] = src0->i[3] / src1->i[3];
2756 }
2757
2758 static void
2759 micro_imax(union tgsi_exec_channel *dst,
2760 const union tgsi_exec_channel *src0,
2761 const union tgsi_exec_channel *src1)
2762 {
2763 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
2764 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
2765 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
2766 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
2767 }
2768
2769 static void
2770 micro_imin(union tgsi_exec_channel *dst,
2771 const union tgsi_exec_channel *src0,
2772 const union tgsi_exec_channel *src1)
2773 {
2774 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
2775 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
2776 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
2777 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
2778 }
2779
2780 static void
2781 micro_isge(union tgsi_exec_channel *dst,
2782 const union tgsi_exec_channel *src0,
2783 const union tgsi_exec_channel *src1)
2784 {
2785 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
2786 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
2787 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
2788 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
2789 }
2790
2791 static void
2792 micro_ishr(union tgsi_exec_channel *dst,
2793 const union tgsi_exec_channel *src0,
2794 const union tgsi_exec_channel *src1)
2795 {
2796 dst->i[0] = src0->i[0] >> src1->i[0];
2797 dst->i[1] = src0->i[1] >> src1->i[1];
2798 dst->i[2] = src0->i[2] >> src1->i[2];
2799 dst->i[3] = src0->i[3] >> src1->i[3];
2800 }
2801
2802 static void
2803 micro_islt(union tgsi_exec_channel *dst,
2804 const union tgsi_exec_channel *src0,
2805 const union tgsi_exec_channel *src1)
2806 {
2807 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
2808 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
2809 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
2810 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
2811 }
2812
2813 static void
2814 micro_f2u(union tgsi_exec_channel *dst,
2815 const union tgsi_exec_channel *src)
2816 {
2817 dst->u[0] = (uint)src->f[0];
2818 dst->u[1] = (uint)src->f[1];
2819 dst->u[2] = (uint)src->f[2];
2820 dst->u[3] = (uint)src->f[3];
2821 }
2822
2823 static void
2824 micro_u2f(union tgsi_exec_channel *dst,
2825 const union tgsi_exec_channel *src)
2826 {
2827 dst->f[0] = (float)src->u[0];
2828 dst->f[1] = (float)src->u[1];
2829 dst->f[2] = (float)src->u[2];
2830 dst->f[3] = (float)src->u[3];
2831 }
2832
2833 static void
2834 micro_uadd(union tgsi_exec_channel *dst,
2835 const union tgsi_exec_channel *src0,
2836 const union tgsi_exec_channel *src1)
2837 {
2838 dst->u[0] = src0->u[0] + src1->u[0];
2839 dst->u[1] = src0->u[1] + src1->u[1];
2840 dst->u[2] = src0->u[2] + src1->u[2];
2841 dst->u[3] = src0->u[3] + src1->u[3];
2842 }
2843
2844 static void
2845 micro_udiv(union tgsi_exec_channel *dst,
2846 const union tgsi_exec_channel *src0,
2847 const union tgsi_exec_channel *src1)
2848 {
2849 dst->u[0] = src0->u[0] / src1->u[0];
2850 dst->u[1] = src0->u[1] / src1->u[1];
2851 dst->u[2] = src0->u[2] / src1->u[2];
2852 dst->u[3] = src0->u[3] / src1->u[3];
2853 }
2854
2855 static void
2856 micro_umad(union tgsi_exec_channel *dst,
2857 const union tgsi_exec_channel *src0,
2858 const union tgsi_exec_channel *src1,
2859 const union tgsi_exec_channel *src2)
2860 {
2861 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
2862 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
2863 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
2864 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
2865 }
2866
2867 static void
2868 micro_umax(union tgsi_exec_channel *dst,
2869 const union tgsi_exec_channel *src0,
2870 const union tgsi_exec_channel *src1)
2871 {
2872 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
2873 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
2874 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
2875 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
2876 }
2877
2878 static void
2879 micro_umin(union tgsi_exec_channel *dst,
2880 const union tgsi_exec_channel *src0,
2881 const union tgsi_exec_channel *src1)
2882 {
2883 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
2884 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
2885 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
2886 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
2887 }
2888
2889 static void
2890 micro_umod(union tgsi_exec_channel *dst,
2891 const union tgsi_exec_channel *src0,
2892 const union tgsi_exec_channel *src1)
2893 {
2894 dst->u[0] = src0->u[0] % src1->u[0];
2895 dst->u[1] = src0->u[1] % src1->u[1];
2896 dst->u[2] = src0->u[2] % src1->u[2];
2897 dst->u[3] = src0->u[3] % src1->u[3];
2898 }
2899
2900 static void
2901 micro_umul(union tgsi_exec_channel *dst,
2902 const union tgsi_exec_channel *src0,
2903 const union tgsi_exec_channel *src1)
2904 {
2905 dst->u[0] = src0->u[0] * src1->u[0];
2906 dst->u[1] = src0->u[1] * src1->u[1];
2907 dst->u[2] = src0->u[2] * src1->u[2];
2908 dst->u[3] = src0->u[3] * src1->u[3];
2909 }
2910
2911 static void
2912 micro_useq(union tgsi_exec_channel *dst,
2913 const union tgsi_exec_channel *src0,
2914 const union tgsi_exec_channel *src1)
2915 {
2916 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
2917 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
2918 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
2919 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
2920 }
2921
2922 static void
2923 micro_usge(union tgsi_exec_channel *dst,
2924 const union tgsi_exec_channel *src0,
2925 const union tgsi_exec_channel *src1)
2926 {
2927 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
2928 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
2929 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
2930 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
2931 }
2932
2933 static void
2934 micro_ushr(union tgsi_exec_channel *dst,
2935 const union tgsi_exec_channel *src0,
2936 const union tgsi_exec_channel *src1)
2937 {
2938 dst->u[0] = src0->u[0] >> src1->u[0];
2939 dst->u[1] = src0->u[1] >> src1->u[1];
2940 dst->u[2] = src0->u[2] >> src1->u[2];
2941 dst->u[3] = src0->u[3] >> src1->u[3];
2942 }
2943
2944 static void
2945 micro_uslt(union tgsi_exec_channel *dst,
2946 const union tgsi_exec_channel *src0,
2947 const union tgsi_exec_channel *src1)
2948 {
2949 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
2950 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
2951 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
2952 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
2953 }
2954
2955 static void
2956 micro_usne(union tgsi_exec_channel *dst,
2957 const union tgsi_exec_channel *src0,
2958 const union tgsi_exec_channel *src1)
2959 {
2960 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
2961 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
2962 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
2963 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
2964 }
2965
2966 static void
2967 exec_instruction(
2968 struct tgsi_exec_machine *mach,
2969 const struct tgsi_full_instruction *inst,
2970 int *pc )
2971 {
2972 union tgsi_exec_channel r[10];
2973
2974 (*pc)++;
2975
2976 switch (inst->Instruction.Opcode) {
2977 case TGSI_OPCODE_ARL:
2978 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
2979 break;
2980
2981 case TGSI_OPCODE_MOV:
2982 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
2983 break;
2984
2985 case TGSI_OPCODE_LIT:
2986 exec_lit(mach, inst);
2987 break;
2988
2989 case TGSI_OPCODE_RCP:
2990 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2991 break;
2992
2993 case TGSI_OPCODE_RSQ:
2994 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2995 break;
2996
2997 case TGSI_OPCODE_EXP:
2998 exec_exp(mach, inst);
2999 break;
3000
3001 case TGSI_OPCODE_LOG:
3002 exec_log(mach, inst);
3003 break;
3004
3005 case TGSI_OPCODE_MUL:
3006 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3007 break;
3008
3009 case TGSI_OPCODE_ADD:
3010 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3011 break;
3012
3013 case TGSI_OPCODE_DP3:
3014 exec_dp3(mach, inst);
3015 break;
3016
3017 case TGSI_OPCODE_DP4:
3018 exec_dp4(mach, inst);
3019 break;
3020
3021 case TGSI_OPCODE_DST:
3022 exec_dst(mach, inst);
3023 break;
3024
3025 case TGSI_OPCODE_MIN:
3026 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3027 break;
3028
3029 case TGSI_OPCODE_MAX:
3030 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3031 break;
3032
3033 case TGSI_OPCODE_SLT:
3034 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3035 break;
3036
3037 case TGSI_OPCODE_SGE:
3038 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3039 break;
3040
3041 case TGSI_OPCODE_MAD:
3042 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3043 break;
3044
3045 case TGSI_OPCODE_SUB:
3046 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3047 break;
3048
3049 case TGSI_OPCODE_LRP:
3050 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3051 break;
3052
3053 case TGSI_OPCODE_CND:
3054 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3055 break;
3056
3057 case TGSI_OPCODE_DP2A:
3058 exec_dp2a(mach, inst);
3059 break;
3060
3061 case TGSI_OPCODE_FRC:
3062 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3063 break;
3064
3065 case TGSI_OPCODE_CLAMP:
3066 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3067 break;
3068
3069 case TGSI_OPCODE_FLR:
3070 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3071 break;
3072
3073 case TGSI_OPCODE_ROUND:
3074 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3075 break;
3076
3077 case TGSI_OPCODE_EX2:
3078 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3079 break;
3080
3081 case TGSI_OPCODE_LG2:
3082 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3083 break;
3084
3085 case TGSI_OPCODE_POW:
3086 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3087 break;
3088
3089 case TGSI_OPCODE_XPD:
3090 exec_xpd(mach, inst);
3091 break;
3092
3093 case TGSI_OPCODE_ABS:
3094 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3095 break;
3096
3097 case TGSI_OPCODE_RCC:
3098 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3099 break;
3100
3101 case TGSI_OPCODE_DPH:
3102 exec_dph(mach, inst);
3103 break;
3104
3105 case TGSI_OPCODE_COS:
3106 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3107 break;
3108
3109 case TGSI_OPCODE_DDX:
3110 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3111 break;
3112
3113 case TGSI_OPCODE_DDY:
3114 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3115 break;
3116
3117 case TGSI_OPCODE_KILP:
3118 exec_kilp (mach, inst);
3119 break;
3120
3121 case TGSI_OPCODE_KIL:
3122 exec_kil (mach, inst);
3123 break;
3124
3125 case TGSI_OPCODE_PK2H:
3126 assert (0);
3127 break;
3128
3129 case TGSI_OPCODE_PK2US:
3130 assert (0);
3131 break;
3132
3133 case TGSI_OPCODE_PK4B:
3134 assert (0);
3135 break;
3136
3137 case TGSI_OPCODE_PK4UB:
3138 assert (0);
3139 break;
3140
3141 case TGSI_OPCODE_RFL:
3142 exec_rfl(mach, inst);
3143 break;
3144
3145 case TGSI_OPCODE_SEQ:
3146 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3147 break;
3148
3149 case TGSI_OPCODE_SFL:
3150 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3151 break;
3152
3153 case TGSI_OPCODE_SGT:
3154 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3155 break;
3156
3157 case TGSI_OPCODE_SIN:
3158 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3159 break;
3160
3161 case TGSI_OPCODE_SLE:
3162 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3163 break;
3164
3165 case TGSI_OPCODE_SNE:
3166 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3167 break;
3168
3169 case TGSI_OPCODE_STR:
3170 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3171 break;
3172
3173 case TGSI_OPCODE_TEX:
3174 /* simple texture lookup */
3175 /* src[0] = texcoord */
3176 /* src[1] = sampler unit */
3177 exec_tex(mach, inst, TEX_MODIFIER_NONE);
3178 break;
3179
3180 case TGSI_OPCODE_TXB:
3181 /* Texture lookup with lod bias */
3182 /* src[0] = texcoord (src[0].w = LOD bias) */
3183 /* src[1] = sampler unit */
3184 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS);
3185 break;
3186
3187 case TGSI_OPCODE_TXD:
3188 /* Texture lookup with explict partial derivatives */
3189 /* src[0] = texcoord */
3190 /* src[1] = d[strq]/dx */
3191 /* src[2] = d[strq]/dy */
3192 /* src[3] = sampler unit */
3193 exec_txd(mach, inst);
3194 break;
3195
3196 case TGSI_OPCODE_TXL:
3197 /* Texture lookup with explit LOD */
3198 /* src[0] = texcoord (src[0].w = LOD) */
3199 /* src[1] = sampler unit */
3200 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
3201 break;
3202
3203 case TGSI_OPCODE_TXP:
3204 /* Texture lookup with projection */
3205 /* src[0] = texcoord (src[0].w = projection) */
3206 /* src[1] = sampler unit */
3207 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED);
3208 break;
3209
3210 case TGSI_OPCODE_UP2H:
3211 assert (0);
3212 break;
3213
3214 case TGSI_OPCODE_UP2US:
3215 assert (0);
3216 break;
3217
3218 case TGSI_OPCODE_UP4B:
3219 assert (0);
3220 break;
3221
3222 case TGSI_OPCODE_UP4UB:
3223 assert (0);
3224 break;
3225
3226 case TGSI_OPCODE_X2D:
3227 exec_x2d(mach, inst);
3228 break;
3229
3230 case TGSI_OPCODE_ARA:
3231 assert (0);
3232 break;
3233
3234 case TGSI_OPCODE_ARR:
3235 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3236 break;
3237
3238 case TGSI_OPCODE_BRA:
3239 assert (0);
3240 break;
3241
3242 case TGSI_OPCODE_CAL:
3243 /* skip the call if no execution channels are enabled */
3244 if (mach->ExecMask) {
3245 /* do the call */
3246
3247 /* First, record the depths of the execution stacks.
3248 * This is important for deeply nested/looped return statements.
3249 * We have to unwind the stacks by the correct amount. For a
3250 * real code generator, we could determine the number of entries
3251 * to pop off each stack with simple static analysis and avoid
3252 * implementing this data structure at run time.
3253 */
3254 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3255 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3256 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3257 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3258 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3259 /* note that PC was already incremented above */
3260 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3261
3262 mach->CallStackTop++;
3263
3264 /* Second, push the Cond, Loop, Cont, Func stacks */
3265 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3266 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3267 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3268 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3269 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3270 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3271
3272 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3273 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3274 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3275 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3276 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3277 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3278
3279 /* Finally, jump to the subroutine */
3280 *pc = inst->Label.Label;
3281 }
3282 break;
3283
3284 case TGSI_OPCODE_RET:
3285 mach->FuncMask &= ~mach->ExecMask;
3286 UPDATE_EXEC_MASK(mach);
3287
3288 if (mach->FuncMask == 0x0) {
3289 /* really return now (otherwise, keep executing */
3290
3291 if (mach->CallStackTop == 0) {
3292 /* returning from main() */
3293 mach->CondStackTop = 0;
3294 mach->LoopStackTop = 0;
3295 *pc = -1;
3296 return;
3297 }
3298
3299 assert(mach->CallStackTop > 0);
3300 mach->CallStackTop--;
3301
3302 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3303 mach->CondMask = mach->CondStack[mach->CondStackTop];
3304
3305 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3306 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3307
3308 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3309 mach->ContMask = mach->ContStack[mach->ContStackTop];
3310
3311 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3312 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3313
3314 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3315 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3316
3317 assert(mach->FuncStackTop > 0);
3318 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3319
3320 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3321
3322 UPDATE_EXEC_MASK(mach);
3323 }
3324 break;
3325
3326 case TGSI_OPCODE_SSG:
3327 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3328 break;
3329
3330 case TGSI_OPCODE_CMP:
3331 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3332 break;
3333
3334 case TGSI_OPCODE_SCS:
3335 exec_scs(mach, inst);
3336 break;
3337
3338 case TGSI_OPCODE_NRM:
3339 exec_nrm3(mach, inst);
3340 break;
3341
3342 case TGSI_OPCODE_NRM4:
3343 exec_nrm4(mach, inst);
3344 break;
3345
3346 case TGSI_OPCODE_DIV:
3347 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3348 break;
3349
3350 case TGSI_OPCODE_DP2:
3351 exec_dp2(mach, inst);
3352 break;
3353
3354 case TGSI_OPCODE_IF:
3355 /* push CondMask */
3356 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3357 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3358 FETCH( &r[0], 0, CHAN_X );
3359 /* update CondMask */
3360 if( ! r[0].u[0] ) {
3361 mach->CondMask &= ~0x1;
3362 }
3363 if( ! r[0].u[1] ) {
3364 mach->CondMask &= ~0x2;
3365 }
3366 if( ! r[0].u[2] ) {
3367 mach->CondMask &= ~0x4;
3368 }
3369 if( ! r[0].u[3] ) {
3370 mach->CondMask &= ~0x8;
3371 }
3372 UPDATE_EXEC_MASK(mach);
3373 /* Todo: If CondMask==0, jump to ELSE */
3374 break;
3375
3376 case TGSI_OPCODE_ELSE:
3377 /* invert CondMask wrt previous mask */
3378 {
3379 uint prevMask;
3380 assert(mach->CondStackTop > 0);
3381 prevMask = mach->CondStack[mach->CondStackTop - 1];
3382 mach->CondMask = ~mach->CondMask & prevMask;
3383 UPDATE_EXEC_MASK(mach);
3384 /* Todo: If CondMask==0, jump to ENDIF */
3385 }
3386 break;
3387
3388 case TGSI_OPCODE_ENDIF:
3389 /* pop CondMask */
3390 assert(mach->CondStackTop > 0);
3391 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3392 UPDATE_EXEC_MASK(mach);
3393 break;
3394
3395 case TGSI_OPCODE_END:
3396 /* make sure we end primitives which haven't
3397 * been explicitly emitted */
3398 conditional_emit_primitive(mach);
3399 /* halt execution */
3400 *pc = -1;
3401 break;
3402
3403 case TGSI_OPCODE_PUSHA:
3404 assert (0);
3405 break;
3406
3407 case TGSI_OPCODE_POPA:
3408 assert (0);
3409 break;
3410
3411 case TGSI_OPCODE_CEIL:
3412 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3413 break;
3414
3415 case TGSI_OPCODE_I2F:
3416 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3417 break;
3418
3419 case TGSI_OPCODE_NOT:
3420 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3421 break;
3422
3423 case TGSI_OPCODE_TRUNC:
3424 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3425 break;
3426
3427 case TGSI_OPCODE_SHL:
3428 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3429 break;
3430
3431 case TGSI_OPCODE_AND:
3432 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3433 break;
3434
3435 case TGSI_OPCODE_OR:
3436 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3437 break;
3438
3439 case TGSI_OPCODE_MOD:
3440 assert (0);
3441 break;
3442
3443 case TGSI_OPCODE_XOR:
3444 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3445 break;
3446
3447 case TGSI_OPCODE_SAD:
3448 assert (0);
3449 break;
3450
3451 case TGSI_OPCODE_TXF:
3452 assert (0);
3453 break;
3454
3455 case TGSI_OPCODE_TXQ:
3456 assert (0);
3457 break;
3458
3459 case TGSI_OPCODE_EMIT:
3460 emit_vertex(mach);
3461 break;
3462
3463 case TGSI_OPCODE_ENDPRIM:
3464 emit_primitive(mach);
3465 break;
3466
3467 case TGSI_OPCODE_BGNLOOP:
3468 /* push LoopMask and ContMasks */
3469 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3470 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3471 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3472 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3473
3474 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3475 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3476 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3477 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3478 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3479 break;
3480
3481 case TGSI_OPCODE_ENDLOOP:
3482 /* Restore ContMask, but don't pop */
3483 assert(mach->ContStackTop > 0);
3484 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3485 UPDATE_EXEC_MASK(mach);
3486 if (mach->ExecMask) {
3487 /* repeat loop: jump to instruction just past BGNLOOP */
3488 assert(mach->LoopLabelStackTop > 0);
3489 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3490 }
3491 else {
3492 /* exit loop: pop LoopMask */
3493 assert(mach->LoopStackTop > 0);
3494 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3495 /* pop ContMask */
3496 assert(mach->ContStackTop > 0);
3497 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3498 assert(mach->LoopLabelStackTop > 0);
3499 --mach->LoopLabelStackTop;
3500
3501 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3502 }
3503 UPDATE_EXEC_MASK(mach);
3504 break;
3505
3506 case TGSI_OPCODE_BRK:
3507 exec_break(mach);
3508 break;
3509
3510 case TGSI_OPCODE_CONT:
3511 /* turn off cont channels for each enabled exec channel */
3512 mach->ContMask &= ~mach->ExecMask;
3513 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3514 UPDATE_EXEC_MASK(mach);
3515 break;
3516
3517 case TGSI_OPCODE_BGNSUB:
3518 /* no-op */
3519 break;
3520
3521 case TGSI_OPCODE_ENDSUB:
3522 /*
3523 * XXX: This really should be a no-op. We should never reach this opcode.
3524 */
3525
3526 assert(mach->CallStackTop > 0);
3527 mach->CallStackTop--;
3528
3529 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3530 mach->CondMask = mach->CondStack[mach->CondStackTop];
3531
3532 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3533 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3534
3535 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3536 mach->ContMask = mach->ContStack[mach->ContStackTop];
3537
3538 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3539 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3540
3541 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3542 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3543
3544 assert(mach->FuncStackTop > 0);
3545 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3546
3547 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3548
3549 UPDATE_EXEC_MASK(mach);
3550 break;
3551
3552 case TGSI_OPCODE_NOP:
3553 break;
3554
3555 case TGSI_OPCODE_BREAKC:
3556 FETCH(&r[0], 0, CHAN_X);
3557 /* update CondMask */
3558 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
3559 mach->LoopMask &= ~0x1;
3560 }
3561 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
3562 mach->LoopMask &= ~0x2;
3563 }
3564 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
3565 mach->LoopMask &= ~0x4;
3566 }
3567 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
3568 mach->LoopMask &= ~0x8;
3569 }
3570 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3571 UPDATE_EXEC_MASK(mach);
3572 break;
3573
3574 case TGSI_OPCODE_F2I:
3575 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3576 break;
3577
3578 case TGSI_OPCODE_IDIV:
3579 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3580 break;
3581
3582 case TGSI_OPCODE_IMAX:
3583 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3584 break;
3585
3586 case TGSI_OPCODE_IMIN:
3587 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3588 break;
3589
3590 case TGSI_OPCODE_INEG:
3591 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3592 break;
3593
3594 case TGSI_OPCODE_ISGE:
3595 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3596 break;
3597
3598 case TGSI_OPCODE_ISHR:
3599 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3600 break;
3601
3602 case TGSI_OPCODE_ISLT:
3603 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3604 break;
3605
3606 case TGSI_OPCODE_F2U:
3607 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3608 break;
3609
3610 case TGSI_OPCODE_U2F:
3611 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
3612 break;
3613
3614 case TGSI_OPCODE_UADD:
3615 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3616 break;
3617
3618 case TGSI_OPCODE_UDIV:
3619 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3620 break;
3621
3622 case TGSI_OPCODE_UMAD:
3623 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3624 break;
3625
3626 case TGSI_OPCODE_UMAX:
3627 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3628 break;
3629
3630 case TGSI_OPCODE_UMIN:
3631 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3632 break;
3633
3634 case TGSI_OPCODE_UMOD:
3635 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3636 break;
3637
3638 case TGSI_OPCODE_UMUL:
3639 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3640 break;
3641
3642 case TGSI_OPCODE_USEQ:
3643 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3644 break;
3645
3646 case TGSI_OPCODE_USGE:
3647 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3648 break;
3649
3650 case TGSI_OPCODE_USHR:
3651 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3652 break;
3653
3654 case TGSI_OPCODE_USLT:
3655 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3656 break;
3657
3658 case TGSI_OPCODE_USNE:
3659 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3660 break;
3661
3662 case TGSI_OPCODE_SWITCH:
3663 exec_switch(mach, inst);
3664 break;
3665
3666 case TGSI_OPCODE_CASE:
3667 exec_case(mach, inst);
3668 break;
3669
3670 case TGSI_OPCODE_DEFAULT:
3671 exec_default(mach);
3672 break;
3673
3674 case TGSI_OPCODE_ENDSWITCH:
3675 exec_endswitch(mach);
3676 break;
3677
3678 default:
3679 assert( 0 );
3680 }
3681 }
3682
3683
3684 #define DEBUG_EXECUTION 0
3685
3686
3687 /**
3688 * Run TGSI interpreter.
3689 * \return bitmask of "alive" quad components
3690 */
3691 uint
3692 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
3693 {
3694 uint i;
3695 int pc = 0;
3696
3697 mach->CondMask = 0xf;
3698 mach->LoopMask = 0xf;
3699 mach->ContMask = 0xf;
3700 mach->FuncMask = 0xf;
3701 mach->ExecMask = 0xf;
3702
3703 mach->Switch.mask = 0xf;
3704
3705 assert(mach->CondStackTop == 0);
3706 assert(mach->LoopStackTop == 0);
3707 assert(mach->ContStackTop == 0);
3708 assert(mach->SwitchStackTop == 0);
3709 assert(mach->BreakStackTop == 0);
3710 assert(mach->CallStackTop == 0);
3711
3712 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
3713 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
3714
3715 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
3716 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
3717 mach->Primitives[0] = 0;
3718 }
3719
3720 /* execute declarations (interpolants) */
3721 for (i = 0; i < mach->NumDeclarations; i++) {
3722 exec_declaration( mach, mach->Declarations+i );
3723 }
3724
3725 {
3726 #if DEBUG_EXECUTION
3727 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
3728 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
3729 uint inst = 1;
3730
3731 memcpy(temps, mach->Temps, sizeof(temps));
3732 memcpy(outputs, mach->Outputs, sizeof(outputs));
3733 #endif
3734
3735 /* execute instructions, until pc is set to -1 */
3736 while (pc != -1) {
3737
3738 #if DEBUG_EXECUTION
3739 uint i;
3740
3741 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
3742 #endif
3743
3744 assert(pc < (int) mach->NumInstructions);
3745 exec_instruction(mach, mach->Instructions + pc, &pc);
3746
3747 #if DEBUG_EXECUTION
3748 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
3749 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
3750 uint j;
3751
3752 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
3753 debug_printf("TEMP[%2u] = ", i);
3754 for (j = 0; j < 4; j++) {
3755 if (j > 0) {
3756 debug_printf(" ");
3757 }
3758 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3759 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
3760 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
3761 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
3762 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
3763 }
3764 }
3765 }
3766 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
3767 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
3768 uint j;
3769
3770 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
3771 debug_printf("OUT[%2u] = ", i);
3772 for (j = 0; j < 4; j++) {
3773 if (j > 0) {
3774 debug_printf(" ");
3775 }
3776 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3777 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
3778 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
3779 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
3780 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
3781 }
3782 }
3783 }
3784 #endif
3785 }
3786 }
3787
3788 #if 0
3789 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
3790 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
3791 /*
3792 * Scale back depth component.
3793 */
3794 for (i = 0; i < 4; i++)
3795 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
3796 }
3797 #endif
3798
3799 /* Strictly speaking, these assertions aren't really needed but they
3800 * can potentially catch some bugs in the control flow code.
3801 */
3802 assert(mach->CondStackTop == 0);
3803 assert(mach->LoopStackTop == 0);
3804 assert(mach->ContStackTop == 0);
3805 assert(mach->SwitchStackTop == 0);
3806 assert(mach->BreakStackTop == 0);
3807 assert(mach->CallStackTop == 0);
3808
3809 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3810 }