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tgsi: silence MSVC signed/unsigned comparison warnings
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 0
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_clamp(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src0,
115 const union tgsi_exec_channel *src1,
116 const union tgsi_exec_channel *src2)
117 {
118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
122 }
123
124 static void
125 micro_cmp(union tgsi_exec_channel *dst,
126 const union tgsi_exec_channel *src0,
127 const union tgsi_exec_channel *src1,
128 const union tgsi_exec_channel *src2)
129 {
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
134 }
135
136 static void
137 micro_cnd(union tgsi_exec_channel *dst,
138 const union tgsi_exec_channel *src0,
139 const union tgsi_exec_channel *src1,
140 const union tgsi_exec_channel *src2)
141 {
142 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
143 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
144 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
145 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
146 }
147
148 static void
149 micro_cos(union tgsi_exec_channel *dst,
150 const union tgsi_exec_channel *src)
151 {
152 dst->f[0] = cosf(src->f[0]);
153 dst->f[1] = cosf(src->f[1]);
154 dst->f[2] = cosf(src->f[2]);
155 dst->f[3] = cosf(src->f[3]);
156 }
157
158 static void
159 micro_ddx(union tgsi_exec_channel *dst,
160 const union tgsi_exec_channel *src)
161 {
162 dst->f[0] =
163 dst->f[1] =
164 dst->f[2] =
165 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
166 }
167
168 static void
169 micro_ddy(union tgsi_exec_channel *dst,
170 const union tgsi_exec_channel *src)
171 {
172 dst->f[0] =
173 dst->f[1] =
174 dst->f[2] =
175 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
176 }
177
178 static void
179 micro_exp2(union tgsi_exec_channel *dst,
180 const union tgsi_exec_channel *src)
181 {
182 #if FAST_MATH
183 dst->f[0] = util_fast_exp2(src->f[0]);
184 dst->f[1] = util_fast_exp2(src->f[1]);
185 dst->f[2] = util_fast_exp2(src->f[2]);
186 dst->f[3] = util_fast_exp2(src->f[3]);
187 #else
188 #if DEBUG
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
190 uint i;
191 union tgsi_exec_channel clamped;
192
193 for (i = 0; i < 4; i++) {
194 if (src->f[i] > 127.99999f) {
195 clamped.f[i] = 127.99999f;
196 } else if (src->f[i] < -126.99999f) {
197 clamped.f[i] = -126.99999f;
198 } else {
199 clamped.f[i] = src->f[i];
200 }
201 }
202 src = &clamped;
203 #endif /* DEBUG */
204
205 dst->f[0] = powf(2.0f, src->f[0]);
206 dst->f[1] = powf(2.0f, src->f[1]);
207 dst->f[2] = powf(2.0f, src->f[2]);
208 dst->f[3] = powf(2.0f, src->f[3]);
209 #endif /* FAST_MATH */
210 }
211
212 static void
213 micro_flr(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
215 {
216 dst->f[0] = floorf(src->f[0]);
217 dst->f[1] = floorf(src->f[1]);
218 dst->f[2] = floorf(src->f[2]);
219 dst->f[3] = floorf(src->f[3]);
220 }
221
222 static void
223 micro_frc(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
225 {
226 dst->f[0] = src->f[0] - floorf(src->f[0]);
227 dst->f[1] = src->f[1] - floorf(src->f[1]);
228 dst->f[2] = src->f[2] - floorf(src->f[2]);
229 dst->f[3] = src->f[3] - floorf(src->f[3]);
230 }
231
232 static void
233 micro_iabs(union tgsi_exec_channel *dst,
234 const union tgsi_exec_channel *src)
235 {
236 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
237 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
238 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
239 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
240 }
241
242 static void
243 micro_ineg(union tgsi_exec_channel *dst,
244 const union tgsi_exec_channel *src)
245 {
246 dst->i[0] = -src->i[0];
247 dst->i[1] = -src->i[1];
248 dst->i[2] = -src->i[2];
249 dst->i[3] = -src->i[3];
250 }
251
252 static void
253 micro_lg2(union tgsi_exec_channel *dst,
254 const union tgsi_exec_channel *src)
255 {
256 #if FAST_MATH
257 dst->f[0] = util_fast_log2(src->f[0]);
258 dst->f[1] = util_fast_log2(src->f[1]);
259 dst->f[2] = util_fast_log2(src->f[2]);
260 dst->f[3] = util_fast_log2(src->f[3]);
261 #else
262 dst->f[0] = logf(src->f[0]) * 1.442695f;
263 dst->f[1] = logf(src->f[1]) * 1.442695f;
264 dst->f[2] = logf(src->f[2]) * 1.442695f;
265 dst->f[3] = logf(src->f[3]) * 1.442695f;
266 #endif
267 }
268
269 static void
270 micro_lrp(union tgsi_exec_channel *dst,
271 const union tgsi_exec_channel *src0,
272 const union tgsi_exec_channel *src1,
273 const union tgsi_exec_channel *src2)
274 {
275 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
276 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
277 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
278 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
279 }
280
281 static void
282 micro_mad(union tgsi_exec_channel *dst,
283 const union tgsi_exec_channel *src0,
284 const union tgsi_exec_channel *src1,
285 const union tgsi_exec_channel *src2)
286 {
287 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
288 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
289 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
290 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
291 }
292
293 static void
294 micro_mov(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 dst->u[0] = src->u[0];
298 dst->u[1] = src->u[1];
299 dst->u[2] = src->u[2];
300 dst->u[3] = src->u[3];
301 }
302
303 static void
304 micro_rcp(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
306 {
307 #if 0 /* for debugging */
308 assert(src->f[0] != 0.0f);
309 assert(src->f[1] != 0.0f);
310 assert(src->f[2] != 0.0f);
311 assert(src->f[3] != 0.0f);
312 #endif
313 dst->f[0] = 1.0f / src->f[0];
314 dst->f[1] = 1.0f / src->f[1];
315 dst->f[2] = 1.0f / src->f[2];
316 dst->f[3] = 1.0f / src->f[3];
317 }
318
319 static void
320 micro_rnd(union tgsi_exec_channel *dst,
321 const union tgsi_exec_channel *src)
322 {
323 dst->f[0] = floorf(src->f[0] + 0.5f);
324 dst->f[1] = floorf(src->f[1] + 0.5f);
325 dst->f[2] = floorf(src->f[2] + 0.5f);
326 dst->f[3] = floorf(src->f[3] + 0.5f);
327 }
328
329 static void
330 micro_rsq(union tgsi_exec_channel *dst,
331 const union tgsi_exec_channel *src)
332 {
333 #if 0 /* for debugging */
334 assert(src->f[0] != 0.0f);
335 assert(src->f[1] != 0.0f);
336 assert(src->f[2] != 0.0f);
337 assert(src->f[3] != 0.0f);
338 #endif
339 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
340 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
341 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
342 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
343 }
344
345 static void
346 micro_seq(union tgsi_exec_channel *dst,
347 const union tgsi_exec_channel *src0,
348 const union tgsi_exec_channel *src1)
349 {
350 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
351 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
352 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
353 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
354 }
355
356 static void
357 micro_sge(union tgsi_exec_channel *dst,
358 const union tgsi_exec_channel *src0,
359 const union tgsi_exec_channel *src1)
360 {
361 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
362 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
363 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
364 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
365 }
366
367 static void
368 micro_sgn(union tgsi_exec_channel *dst,
369 const union tgsi_exec_channel *src)
370 {
371 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
372 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
373 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
374 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
375 }
376
377 static void
378 micro_isgn(union tgsi_exec_channel *dst,
379 const union tgsi_exec_channel *src)
380 {
381 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
382 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
383 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
384 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
385 }
386
387 static void
388 micro_sgt(union tgsi_exec_channel *dst,
389 const union tgsi_exec_channel *src0,
390 const union tgsi_exec_channel *src1)
391 {
392 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
393 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
394 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
395 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
396 }
397
398 static void
399 micro_sin(union tgsi_exec_channel *dst,
400 const union tgsi_exec_channel *src)
401 {
402 dst->f[0] = sinf(src->f[0]);
403 dst->f[1] = sinf(src->f[1]);
404 dst->f[2] = sinf(src->f[2]);
405 dst->f[3] = sinf(src->f[3]);
406 }
407
408 static void
409 micro_sle(union tgsi_exec_channel *dst,
410 const union tgsi_exec_channel *src0,
411 const union tgsi_exec_channel *src1)
412 {
413 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
414 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
415 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
416 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
417 }
418
419 static void
420 micro_slt(union tgsi_exec_channel *dst,
421 const union tgsi_exec_channel *src0,
422 const union tgsi_exec_channel *src1)
423 {
424 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
425 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
426 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
427 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
428 }
429
430 static void
431 micro_sne(union tgsi_exec_channel *dst,
432 const union tgsi_exec_channel *src0,
433 const union tgsi_exec_channel *src1)
434 {
435 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
436 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
437 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
438 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
439 }
440
441 static void
442 micro_sfl(union tgsi_exec_channel *dst)
443 {
444 dst->f[0] = 0.0f;
445 dst->f[1] = 0.0f;
446 dst->f[2] = 0.0f;
447 dst->f[3] = 0.0f;
448 }
449
450 static void
451 micro_str(union tgsi_exec_channel *dst)
452 {
453 dst->f[0] = 1.0f;
454 dst->f[1] = 1.0f;
455 dst->f[2] = 1.0f;
456 dst->f[3] = 1.0f;
457 }
458
459 static void
460 micro_trunc(union tgsi_exec_channel *dst,
461 const union tgsi_exec_channel *src)
462 {
463 dst->f[0] = (float)(int)src->f[0];
464 dst->f[1] = (float)(int)src->f[1];
465 dst->f[2] = (float)(int)src->f[2];
466 dst->f[3] = (float)(int)src->f[3];
467 }
468
469
470 enum tgsi_exec_datatype {
471 TGSI_EXEC_DATA_FLOAT,
472 TGSI_EXEC_DATA_INT,
473 TGSI_EXEC_DATA_UINT
474 };
475
476 /*
477 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
478 */
479 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
480 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
481 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
482 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
483 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
484 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
485
486
487 /** The execution mask depends on the conditional mask and the loop mask */
488 #define UPDATE_EXEC_MASK(MACH) \
489 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
490
491
492 static const union tgsi_exec_channel ZeroVec =
493 { { 0.0, 0.0, 0.0, 0.0 } };
494
495 static const union tgsi_exec_channel OneVec = {
496 {1.0f, 1.0f, 1.0f, 1.0f}
497 };
498
499 static const union tgsi_exec_channel P128Vec = {
500 {128.0f, 128.0f, 128.0f, 128.0f}
501 };
502
503 static const union tgsi_exec_channel M128Vec = {
504 {-128.0f, -128.0f, -128.0f, -128.0f}
505 };
506
507
508 /**
509 * Assert that none of the float values in 'chan' are infinite or NaN.
510 * NaN and Inf may occur normally during program execution and should
511 * not lead to crashes, etc. But when debugging, it's helpful to catch
512 * them.
513 */
514 static INLINE void
515 check_inf_or_nan(const union tgsi_exec_channel *chan)
516 {
517 assert(!util_is_inf_or_nan((chan)->f[0]));
518 assert(!util_is_inf_or_nan((chan)->f[1]));
519 assert(!util_is_inf_or_nan((chan)->f[2]));
520 assert(!util_is_inf_or_nan((chan)->f[3]));
521 }
522
523
524 #ifdef DEBUG
525 static void
526 print_chan(const char *msg, const union tgsi_exec_channel *chan)
527 {
528 debug_printf("%s = {%f, %f, %f, %f}\n",
529 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
530 }
531 #endif
532
533
534 #ifdef DEBUG
535 static void
536 print_temp(const struct tgsi_exec_machine *mach, uint index)
537 {
538 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
539 int i;
540 debug_printf("Temp[%u] =\n", index);
541 for (i = 0; i < 4; i++) {
542 debug_printf(" %c: { %f, %f, %f, %f }\n",
543 "XYZW"[i],
544 tmp->xyzw[i].f[0],
545 tmp->xyzw[i].f[1],
546 tmp->xyzw[i].f[2],
547 tmp->xyzw[i].f[3]);
548 }
549 }
550 #endif
551
552
553 void
554 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
555 unsigned num_bufs,
556 const void **bufs,
557 const unsigned *buf_sizes)
558 {
559 unsigned i;
560
561 for (i = 0; i < num_bufs; i++) {
562 mach->Consts[i] = bufs[i];
563 mach->ConstsSize[i] = buf_sizes[i];
564 }
565 }
566
567
568 /**
569 * Check if there's a potential src/dst register data dependency when
570 * using SOA execution.
571 * Example:
572 * MOV T, T.yxwz;
573 * This would expand into:
574 * MOV t0, t1;
575 * MOV t1, t0;
576 * MOV t2, t3;
577 * MOV t3, t2;
578 * The second instruction will have the wrong value for t0 if executed as-is.
579 */
580 boolean
581 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
582 {
583 uint i, chan;
584
585 uint writemask = inst->Dst[0].Register.WriteMask;
586 if (writemask == TGSI_WRITEMASK_X ||
587 writemask == TGSI_WRITEMASK_Y ||
588 writemask == TGSI_WRITEMASK_Z ||
589 writemask == TGSI_WRITEMASK_W ||
590 writemask == TGSI_WRITEMASK_NONE) {
591 /* no chance of data dependency */
592 return FALSE;
593 }
594
595 /* loop over src regs */
596 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
597 if ((inst->Src[i].Register.File ==
598 inst->Dst[0].Register.File) &&
599 ((inst->Src[i].Register.Index ==
600 inst->Dst[0].Register.Index) ||
601 inst->Src[i].Register.Indirect ||
602 inst->Dst[0].Register.Indirect)) {
603 /* loop over dest channels */
604 uint channelsWritten = 0x0;
605 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
607 /* check if we're reading a channel that's been written */
608 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
609 if (channelsWritten & (1 << swizzle)) {
610 return TRUE;
611 }
612
613 channelsWritten |= (1 << chan);
614 }
615 }
616 }
617 }
618 return FALSE;
619 }
620
621
622 /**
623 * Initialize machine state by expanding tokens to full instructions,
624 * allocating temporary storage, setting up constants, etc.
625 * After this, we can call tgsi_exec_machine_run() many times.
626 */
627 void
628 tgsi_exec_machine_bind_shader(
629 struct tgsi_exec_machine *mach,
630 const struct tgsi_token *tokens,
631 uint numSamplers,
632 struct tgsi_sampler **samplers)
633 {
634 uint k;
635 struct tgsi_parse_context parse;
636 struct tgsi_full_instruction *instructions;
637 struct tgsi_full_declaration *declarations;
638 uint maxInstructions = 10, numInstructions = 0;
639 uint maxDeclarations = 10, numDeclarations = 0;
640
641 #if 0
642 tgsi_dump(tokens, 0);
643 #endif
644
645 util_init_math();
646
647 if (numSamplers) {
648 assert(samplers);
649 }
650
651 mach->Tokens = tokens;
652 mach->Samplers = samplers;
653
654 if (!tokens) {
655 /* unbind and free all */
656 FREE(mach->Declarations);
657 mach->Declarations = NULL;
658 mach->NumDeclarations = 0;
659
660 FREE(mach->Instructions);
661 mach->Instructions = NULL;
662 mach->NumInstructions = 0;
663
664 return;
665 }
666
667 k = tgsi_parse_init (&parse, mach->Tokens);
668 if (k != TGSI_PARSE_OK) {
669 debug_printf( "Problem parsing!\n" );
670 return;
671 }
672
673 mach->Processor = parse.FullHeader.Processor.Processor;
674 mach->ImmLimit = 0;
675
676 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
677 !mach->UsedGeometryShader) {
678 struct tgsi_exec_vector *inputs;
679 struct tgsi_exec_vector *outputs;
680
681 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
682 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS,
683 16);
684
685 if (!inputs)
686 return;
687
688 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
689 TGSI_MAX_TOTAL_VERTICES, 16);
690
691 if (!outputs) {
692 align_free(inputs);
693 return;
694 }
695
696 align_free(mach->Inputs);
697 align_free(mach->Outputs);
698
699 mach->Inputs = inputs;
700 mach->Outputs = outputs;
701 mach->UsedGeometryShader = TRUE;
702 }
703
704 declarations = (struct tgsi_full_declaration *)
705 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
706
707 if (!declarations) {
708 return;
709 }
710
711 instructions = (struct tgsi_full_instruction *)
712 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
713
714 if (!instructions) {
715 FREE( declarations );
716 return;
717 }
718
719 while( !tgsi_parse_end_of_tokens( &parse ) ) {
720 uint i;
721
722 tgsi_parse_token( &parse );
723 switch( parse.FullToken.Token.Type ) {
724 case TGSI_TOKEN_TYPE_DECLARATION:
725 /* save expanded declaration */
726 if (numDeclarations == maxDeclarations) {
727 declarations = REALLOC(declarations,
728 maxDeclarations
729 * sizeof(struct tgsi_full_declaration),
730 (maxDeclarations + 10)
731 * sizeof(struct tgsi_full_declaration));
732 maxDeclarations += 10;
733 }
734 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
735 unsigned reg;
736 for (reg = parse.FullToken.FullDeclaration.Range.First;
737 reg <= parse.FullToken.FullDeclaration.Range.Last;
738 ++reg) {
739 ++mach->NumOutputs;
740 }
741 }
742 if (parse.FullToken.FullDeclaration.Declaration.File ==
743 TGSI_FILE_IMMEDIATE_ARRAY) {
744 unsigned reg;
745 struct tgsi_full_declaration *decl =
746 &parse.FullToken.FullDeclaration;
747 debug_assert(decl->Range.Last < TGSI_EXEC_NUM_IMMEDIATES);
748 for (reg = decl->Range.First; reg <= decl->Range.Last; ++reg) {
749 for( i = 0; i < 4; i++ ) {
750 int idx = reg * 4 + i;
751 mach->ImmArray[reg][i] = decl->ImmediateData.u[idx].Float;
752 }
753 }
754 }
755 memcpy(declarations + numDeclarations,
756 &parse.FullToken.FullDeclaration,
757 sizeof(declarations[0]));
758 numDeclarations++;
759 break;
760
761 case TGSI_TOKEN_TYPE_IMMEDIATE:
762 {
763 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
764 assert( size <= 4 );
765 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
766
767 for( i = 0; i < size; i++ ) {
768 mach->Imms[mach->ImmLimit][i] =
769 parse.FullToken.FullImmediate.u[i].Float;
770 }
771 mach->ImmLimit += 1;
772 }
773 break;
774
775 case TGSI_TOKEN_TYPE_INSTRUCTION:
776
777 /* save expanded instruction */
778 if (numInstructions == maxInstructions) {
779 instructions = REALLOC(instructions,
780 maxInstructions
781 * sizeof(struct tgsi_full_instruction),
782 (maxInstructions + 10)
783 * sizeof(struct tgsi_full_instruction));
784 maxInstructions += 10;
785 }
786
787 memcpy(instructions + numInstructions,
788 &parse.FullToken.FullInstruction,
789 sizeof(instructions[0]));
790
791 numInstructions++;
792 break;
793
794 case TGSI_TOKEN_TYPE_PROPERTY:
795 break;
796
797 default:
798 assert( 0 );
799 }
800 }
801 tgsi_parse_free (&parse);
802
803 FREE(mach->Declarations);
804 mach->Declarations = declarations;
805 mach->NumDeclarations = numDeclarations;
806
807 FREE(mach->Instructions);
808 mach->Instructions = instructions;
809 mach->NumInstructions = numInstructions;
810 }
811
812
813 struct tgsi_exec_machine *
814 tgsi_exec_machine_create( void )
815 {
816 struct tgsi_exec_machine *mach;
817 uint i;
818
819 mach = align_malloc( sizeof *mach, 16 );
820 if (!mach)
821 goto fail;
822
823 memset(mach, 0, sizeof(*mach));
824
825 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
826 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
827 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
828
829 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
830 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
831 if (!mach->Inputs || !mach->Outputs)
832 goto fail;
833
834 /* Setup constants needed by the SSE2 executor. */
835 for( i = 0; i < 4; i++ ) {
836 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
837 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
838 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
839 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
840 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
841 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
842 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
843 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
844 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
845 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
846 }
847
848 #ifdef DEBUG
849 /* silence warnings */
850 (void) print_chan;
851 (void) print_temp;
852 #endif
853
854 return mach;
855
856 fail:
857 if (mach) {
858 align_free(mach->Inputs);
859 align_free(mach->Outputs);
860 align_free(mach);
861 }
862 return NULL;
863 }
864
865
866 void
867 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
868 {
869 if (mach) {
870 FREE(mach->Instructions);
871 FREE(mach->Declarations);
872
873 align_free(mach->Inputs);
874 align_free(mach->Outputs);
875
876 align_free(mach);
877 }
878 }
879
880 static void
881 micro_add(union tgsi_exec_channel *dst,
882 const union tgsi_exec_channel *src0,
883 const union tgsi_exec_channel *src1)
884 {
885 dst->f[0] = src0->f[0] + src1->f[0];
886 dst->f[1] = src0->f[1] + src1->f[1];
887 dst->f[2] = src0->f[2] + src1->f[2];
888 dst->f[3] = src0->f[3] + src1->f[3];
889 }
890
891 static void
892 micro_div(
893 union tgsi_exec_channel *dst,
894 const union tgsi_exec_channel *src0,
895 const union tgsi_exec_channel *src1 )
896 {
897 if (src1->f[0] != 0) {
898 dst->f[0] = src0->f[0] / src1->f[0];
899 }
900 if (src1->f[1] != 0) {
901 dst->f[1] = src0->f[1] / src1->f[1];
902 }
903 if (src1->f[2] != 0) {
904 dst->f[2] = src0->f[2] / src1->f[2];
905 }
906 if (src1->f[3] != 0) {
907 dst->f[3] = src0->f[3] / src1->f[3];
908 }
909 }
910
911 static void
912 micro_rcc(union tgsi_exec_channel *dst,
913 const union tgsi_exec_channel *src)
914 {
915 uint i;
916
917 for (i = 0; i < 4; i++) {
918 float recip = 1.0f / src->f[i];
919
920 if (recip > 0.0f) {
921 if (recip > 1.884467e+019f) {
922 dst->f[i] = 1.884467e+019f;
923 }
924 else if (recip < 5.42101e-020f) {
925 dst->f[i] = 5.42101e-020f;
926 }
927 else {
928 dst->f[i] = recip;
929 }
930 }
931 else {
932 if (recip < -1.884467e+019f) {
933 dst->f[i] = -1.884467e+019f;
934 }
935 else if (recip > -5.42101e-020f) {
936 dst->f[i] = -5.42101e-020f;
937 }
938 else {
939 dst->f[i] = recip;
940 }
941 }
942 }
943 }
944
945 static void
946 micro_lt(
947 union tgsi_exec_channel *dst,
948 const union tgsi_exec_channel *src0,
949 const union tgsi_exec_channel *src1,
950 const union tgsi_exec_channel *src2,
951 const union tgsi_exec_channel *src3 )
952 {
953 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
954 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
955 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
956 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
957 }
958
959 static void
960 micro_max(union tgsi_exec_channel *dst,
961 const union tgsi_exec_channel *src0,
962 const union tgsi_exec_channel *src1)
963 {
964 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
965 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
966 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
967 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
968 }
969
970 static void
971 micro_min(union tgsi_exec_channel *dst,
972 const union tgsi_exec_channel *src0,
973 const union tgsi_exec_channel *src1)
974 {
975 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
976 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
977 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
978 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
979 }
980
981 static void
982 micro_mul(union tgsi_exec_channel *dst,
983 const union tgsi_exec_channel *src0,
984 const union tgsi_exec_channel *src1)
985 {
986 dst->f[0] = src0->f[0] * src1->f[0];
987 dst->f[1] = src0->f[1] * src1->f[1];
988 dst->f[2] = src0->f[2] * src1->f[2];
989 dst->f[3] = src0->f[3] * src1->f[3];
990 }
991
992 static void
993 micro_neg(
994 union tgsi_exec_channel *dst,
995 const union tgsi_exec_channel *src )
996 {
997 dst->f[0] = -src->f[0];
998 dst->f[1] = -src->f[1];
999 dst->f[2] = -src->f[2];
1000 dst->f[3] = -src->f[3];
1001 }
1002
1003 static void
1004 micro_pow(
1005 union tgsi_exec_channel *dst,
1006 const union tgsi_exec_channel *src0,
1007 const union tgsi_exec_channel *src1 )
1008 {
1009 #if FAST_MATH
1010 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1011 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1012 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1013 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1014 #else
1015 dst->f[0] = powf( src0->f[0], src1->f[0] );
1016 dst->f[1] = powf( src0->f[1], src1->f[1] );
1017 dst->f[2] = powf( src0->f[2], src1->f[2] );
1018 dst->f[3] = powf( src0->f[3], src1->f[3] );
1019 #endif
1020 }
1021
1022 static void
1023 micro_sub(union tgsi_exec_channel *dst,
1024 const union tgsi_exec_channel *src0,
1025 const union tgsi_exec_channel *src1)
1026 {
1027 dst->f[0] = src0->f[0] - src1->f[0];
1028 dst->f[1] = src0->f[1] - src1->f[1];
1029 dst->f[2] = src0->f[2] - src1->f[2];
1030 dst->f[3] = src0->f[3] - src1->f[3];
1031 }
1032
1033 static void
1034 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1035 const uint chan_index,
1036 const uint file,
1037 const uint swizzle,
1038 const union tgsi_exec_channel *index,
1039 const union tgsi_exec_channel *index2D,
1040 union tgsi_exec_channel *chan)
1041 {
1042 uint i;
1043
1044 assert(swizzle < 4);
1045
1046 switch (file) {
1047 case TGSI_FILE_CONSTANT:
1048 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1049 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1050 assert(mach->Consts[index2D->i[i]]);
1051
1052 if (index->i[i] < 0) {
1053 chan->u[i] = 0;
1054 } else {
1055 /* NOTE: copying the const value as a uint instead of float */
1056 const uint constbuf = index2D->i[i];
1057 const uint *buf = (const uint *)mach->Consts[constbuf];
1058 const int pos = index->i[i] * 4 + swizzle;
1059 /* const buffer bounds check */
1060 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1061 if (0) {
1062 /* Debug: print warning */
1063 static int count = 0;
1064 if (count++ < 100)
1065 debug_printf("TGSI Exec: const buffer index %d"
1066 " out of bounds\n", pos);
1067 }
1068 chan->u[i] = 0;
1069 }
1070 else
1071 chan->u[i] = buf[pos];
1072 }
1073 }
1074 break;
1075
1076 case TGSI_FILE_INPUT:
1077 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1078 /*
1079 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1080 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1081 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1082 index2D->i[i], index->i[i]);
1083 }*/
1084 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1085 assert(pos >= 0);
1086 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1087 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1088 }
1089 break;
1090
1091 case TGSI_FILE_SYSTEM_VALUE:
1092 /* XXX no swizzling at this point. Will be needed if we put
1093 * gl_FragCoord, for example, in a sys value register.
1094 */
1095 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1096 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1097 }
1098 break;
1099
1100 case TGSI_FILE_TEMPORARY:
1101 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1102 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1103 assert(index2D->i[i] == 0);
1104
1105 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1106 }
1107 break;
1108
1109 case TGSI_FILE_TEMPORARY_ARRAY:
1110 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1111 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1112 assert(index2D->i[i] < TGSI_EXEC_NUM_TEMP_ARRAYS);
1113
1114 chan->u[i] =
1115 mach->TempArray[index2D->i[i]][index->i[i]].xyzw[swizzle].u[i];
1116 }
1117 break;
1118
1119 case TGSI_FILE_IMMEDIATE:
1120 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1121 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1122 assert(index2D->i[i] == 0);
1123
1124 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1125 }
1126 break;
1127
1128 case TGSI_FILE_IMMEDIATE_ARRAY:
1129 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1130 assert(index2D->i[i] == 0);
1131
1132 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1133 }
1134 break;
1135
1136 case TGSI_FILE_ADDRESS:
1137 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1138 assert(index->i[i] >= 0);
1139 assert(index2D->i[i] == 0);
1140
1141 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1142 }
1143 break;
1144
1145 case TGSI_FILE_PREDICATE:
1146 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1147 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1148 assert(index2D->i[i] == 0);
1149
1150 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1151 }
1152 break;
1153
1154 case TGSI_FILE_OUTPUT:
1155 /* vertex/fragment output vars can be read too */
1156 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1157 assert(index->i[i] >= 0);
1158 assert(index2D->i[i] == 0);
1159
1160 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1161 }
1162 break;
1163
1164 default:
1165 assert(0);
1166 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1167 chan->u[i] = 0;
1168 }
1169 }
1170 }
1171
1172 static void
1173 fetch_source(const struct tgsi_exec_machine *mach,
1174 union tgsi_exec_channel *chan,
1175 const struct tgsi_full_src_register *reg,
1176 const uint chan_index,
1177 enum tgsi_exec_datatype src_datatype)
1178 {
1179 union tgsi_exec_channel index;
1180 union tgsi_exec_channel index2D;
1181 uint swizzle;
1182
1183 /* We start with a direct index into a register file.
1184 *
1185 * file[1],
1186 * where:
1187 * file = Register.File
1188 * [1] = Register.Index
1189 */
1190 index.i[0] =
1191 index.i[1] =
1192 index.i[2] =
1193 index.i[3] = reg->Register.Index;
1194
1195 /* There is an extra source register that indirectly subscripts
1196 * a register file. The direct index now becomes an offset
1197 * that is being added to the indirect register.
1198 *
1199 * file[ind[2].x+1],
1200 * where:
1201 * ind = Indirect.File
1202 * [2] = Indirect.Index
1203 * .x = Indirect.SwizzleX
1204 */
1205 if (reg->Register.Indirect) {
1206 union tgsi_exec_channel index2;
1207 union tgsi_exec_channel indir_index;
1208 const uint execmask = mach->ExecMask;
1209 uint i;
1210
1211 /* which address register (always zero now) */
1212 index2.i[0] =
1213 index2.i[1] =
1214 index2.i[2] =
1215 index2.i[3] = reg->Indirect.Index;
1216 assert(reg->Indirect.File == TGSI_FILE_ADDRESS);
1217 /* get current value of address register[swizzle] */
1218 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, TGSI_CHAN_X );
1219 fetch_src_file_channel(mach,
1220 chan_index,
1221 reg->Indirect.File,
1222 swizzle,
1223 &index2,
1224 &ZeroVec,
1225 &indir_index);
1226
1227 /* add value of address register to the offset */
1228 index.i[0] += indir_index.i[0];
1229 index.i[1] += indir_index.i[1];
1230 index.i[2] += indir_index.i[2];
1231 index.i[3] += indir_index.i[3];
1232
1233 /* for disabled execution channels, zero-out the index to
1234 * avoid using a potential garbage value.
1235 */
1236 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1237 if ((execmask & (1 << i)) == 0)
1238 index.i[i] = 0;
1239 }
1240 }
1241
1242 /* There is an extra source register that is a second
1243 * subscript to a register file. Effectively it means that
1244 * the register file is actually a 2D array of registers.
1245 *
1246 * file[3][1],
1247 * where:
1248 * [3] = Dimension.Index
1249 */
1250 if (reg->Register.Dimension) {
1251 index2D.i[0] =
1252 index2D.i[1] =
1253 index2D.i[2] =
1254 index2D.i[3] = reg->Dimension.Index;
1255
1256 /* Again, the second subscript index can be addressed indirectly
1257 * identically to the first one.
1258 * Nothing stops us from indirectly addressing the indirect register,
1259 * but there is no need for that, so we won't exercise it.
1260 *
1261 * file[ind[4].y+3][1],
1262 * where:
1263 * ind = DimIndirect.File
1264 * [4] = DimIndirect.Index
1265 * .y = DimIndirect.SwizzleX
1266 */
1267 if (reg->Dimension.Indirect) {
1268 union tgsi_exec_channel index2;
1269 union tgsi_exec_channel indir_index;
1270 const uint execmask = mach->ExecMask;
1271 uint i;
1272
1273 index2.i[0] =
1274 index2.i[1] =
1275 index2.i[2] =
1276 index2.i[3] = reg->DimIndirect.Index;
1277
1278 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, TGSI_CHAN_X );
1279 fetch_src_file_channel(mach,
1280 chan_index,
1281 reg->DimIndirect.File,
1282 swizzle,
1283 &index2,
1284 &ZeroVec,
1285 &indir_index);
1286
1287 index2D.i[0] += indir_index.i[0];
1288 index2D.i[1] += indir_index.i[1];
1289 index2D.i[2] += indir_index.i[2];
1290 index2D.i[3] += indir_index.i[3];
1291
1292 /* for disabled execution channels, zero-out the index to
1293 * avoid using a potential garbage value.
1294 */
1295 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1296 if ((execmask & (1 << i)) == 0) {
1297 index2D.i[i] = 0;
1298 }
1299 }
1300 }
1301
1302 /* If by any chance there was a need for a 3D array of register
1303 * files, we would have to check whether Dimension is followed
1304 * by a dimension register and continue the saga.
1305 */
1306 } else {
1307 index2D.i[0] =
1308 index2D.i[1] =
1309 index2D.i[2] =
1310 index2D.i[3] = 0;
1311 }
1312
1313 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1314 fetch_src_file_channel(mach,
1315 chan_index,
1316 reg->Register.File,
1317 swizzle,
1318 &index,
1319 &index2D,
1320 chan);
1321
1322 if (reg->Register.Absolute) {
1323 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1324 micro_abs(chan, chan);
1325 } else {
1326 micro_iabs(chan, chan);
1327 }
1328 }
1329
1330 if (reg->Register.Negate) {
1331 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1332 micro_neg(chan, chan);
1333 } else {
1334 micro_ineg(chan, chan);
1335 }
1336 }
1337 }
1338
1339 static void
1340 store_dest(struct tgsi_exec_machine *mach,
1341 const union tgsi_exec_channel *chan,
1342 const struct tgsi_full_dst_register *reg,
1343 const struct tgsi_full_instruction *inst,
1344 uint chan_index,
1345 enum tgsi_exec_datatype dst_datatype)
1346 {
1347 uint i;
1348 union tgsi_exec_channel null;
1349 union tgsi_exec_channel *dst;
1350 union tgsi_exec_channel index2D;
1351 uint execmask = mach->ExecMask;
1352 int offset = 0; /* indirection offset */
1353 int index;
1354
1355 /* for debugging */
1356 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1357 check_inf_or_nan(chan);
1358 }
1359
1360 /* There is an extra source register that indirectly subscripts
1361 * a register file. The direct index now becomes an offset
1362 * that is being added to the indirect register.
1363 *
1364 * file[ind[2].x+1],
1365 * where:
1366 * ind = Indirect.File
1367 * [2] = Indirect.Index
1368 * .x = Indirect.SwizzleX
1369 */
1370 if (reg->Register.Indirect) {
1371 union tgsi_exec_channel index;
1372 union tgsi_exec_channel indir_index;
1373 uint swizzle;
1374
1375 /* which address register (always zero for now) */
1376 index.i[0] =
1377 index.i[1] =
1378 index.i[2] =
1379 index.i[3] = reg->Indirect.Index;
1380
1381 /* get current value of address register[swizzle] */
1382 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, TGSI_CHAN_X );
1383
1384 /* fetch values from the address/indirection register */
1385 fetch_src_file_channel(mach,
1386 chan_index,
1387 reg->Indirect.File,
1388 swizzle,
1389 &index,
1390 &ZeroVec,
1391 &indir_index);
1392
1393 /* save indirection offset */
1394 offset = indir_index.i[0];
1395 }
1396
1397 /* There is an extra source register that is a second
1398 * subscript to a register file. Effectively it means that
1399 * the register file is actually a 2D array of registers.
1400 *
1401 * file[3][1],
1402 * where:
1403 * [3] = Dimension.Index
1404 */
1405 if (reg->Register.Dimension) {
1406 index2D.i[0] =
1407 index2D.i[1] =
1408 index2D.i[2] =
1409 index2D.i[3] = reg->Dimension.Index;
1410
1411 /* Again, the second subscript index can be addressed indirectly
1412 * identically to the first one.
1413 * Nothing stops us from indirectly addressing the indirect register,
1414 * but there is no need for that, so we won't exercise it.
1415 *
1416 * file[ind[4].y+3][1],
1417 * where:
1418 * ind = DimIndirect.File
1419 * [4] = DimIndirect.Index
1420 * .y = DimIndirect.SwizzleX
1421 */
1422 if (reg->Dimension.Indirect) {
1423 union tgsi_exec_channel index2;
1424 union tgsi_exec_channel indir_index;
1425 const uint execmask = mach->ExecMask;
1426 unsigned swizzle;
1427 uint i;
1428
1429 index2.i[0] =
1430 index2.i[1] =
1431 index2.i[2] =
1432 index2.i[3] = reg->DimIndirect.Index;
1433
1434 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, TGSI_CHAN_X );
1435 fetch_src_file_channel(mach,
1436 chan_index,
1437 reg->DimIndirect.File,
1438 swizzle,
1439 &index2,
1440 &ZeroVec,
1441 &indir_index);
1442
1443 index2D.i[0] += indir_index.i[0];
1444 index2D.i[1] += indir_index.i[1];
1445 index2D.i[2] += indir_index.i[2];
1446 index2D.i[3] += indir_index.i[3];
1447
1448 /* for disabled execution channels, zero-out the index to
1449 * avoid using a potential garbage value.
1450 */
1451 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1452 if ((execmask & (1 << i)) == 0) {
1453 index2D.i[i] = 0;
1454 }
1455 }
1456 }
1457
1458 /* If by any chance there was a need for a 3D array of register
1459 * files, we would have to check whether Dimension is followed
1460 * by a dimension register and continue the saga.
1461 */
1462 } else {
1463 index2D.i[0] =
1464 index2D.i[1] =
1465 index2D.i[2] =
1466 index2D.i[3] = 0;
1467 }
1468
1469 switch (reg->Register.File) {
1470 case TGSI_FILE_NULL:
1471 dst = &null;
1472 break;
1473
1474 case TGSI_FILE_OUTPUT:
1475 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1476 + reg->Register.Index;
1477 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1478 #if 0
1479 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1480 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1481 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1482 if (execmask & (1 << i))
1483 fprintf(stderr, "%f, ", chan->f[i]);
1484 fprintf(stderr, ")\n");
1485 }
1486 #endif
1487 break;
1488
1489 case TGSI_FILE_TEMPORARY:
1490 index = reg->Register.Index;
1491 assert( index < TGSI_EXEC_NUM_TEMPS );
1492 dst = &mach->Temps[offset + index].xyzw[chan_index];
1493 break;
1494
1495 case TGSI_FILE_TEMPORARY_ARRAY:
1496 index = reg->Register.Index;
1497 assert( index < TGSI_EXEC_NUM_TEMPS );
1498 assert( index2D.i[0] < TGSI_EXEC_NUM_TEMP_ARRAYS );
1499 /* XXX we use index2D.i[0] here but somehow we might
1500 * end up with someone trying to store indirectly in
1501 * different buffers */
1502 dst = &mach->TempArray[index2D.i[0]][offset + index].xyzw[chan_index];
1503 break;
1504
1505 case TGSI_FILE_ADDRESS:
1506 index = reg->Register.Index;
1507 dst = &mach->Addrs[index].xyzw[chan_index];
1508 break;
1509
1510 case TGSI_FILE_PREDICATE:
1511 index = reg->Register.Index;
1512 assert(index < TGSI_EXEC_NUM_PREDS);
1513 dst = &mach->Predicates[index].xyzw[chan_index];
1514 break;
1515
1516 default:
1517 assert( 0 );
1518 return;
1519 }
1520
1521 if (inst->Instruction.Predicate) {
1522 uint swizzle;
1523 union tgsi_exec_channel *pred;
1524
1525 switch (chan_index) {
1526 case TGSI_CHAN_X:
1527 swizzle = inst->Predicate.SwizzleX;
1528 break;
1529 case TGSI_CHAN_Y:
1530 swizzle = inst->Predicate.SwizzleY;
1531 break;
1532 case TGSI_CHAN_Z:
1533 swizzle = inst->Predicate.SwizzleZ;
1534 break;
1535 case TGSI_CHAN_W:
1536 swizzle = inst->Predicate.SwizzleW;
1537 break;
1538 default:
1539 assert(0);
1540 return;
1541 }
1542
1543 assert(inst->Predicate.Index == 0);
1544
1545 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1546
1547 if (inst->Predicate.Negate) {
1548 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1549 if (pred->u[i]) {
1550 execmask &= ~(1 << i);
1551 }
1552 }
1553 } else {
1554 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1555 if (!pred->u[i]) {
1556 execmask &= ~(1 << i);
1557 }
1558 }
1559 }
1560 }
1561
1562 switch (inst->Instruction.Saturate) {
1563 case TGSI_SAT_NONE:
1564 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1565 if (execmask & (1 << i))
1566 dst->i[i] = chan->i[i];
1567 break;
1568
1569 case TGSI_SAT_ZERO_ONE:
1570 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1571 if (execmask & (1 << i)) {
1572 if (chan->f[i] < 0.0f)
1573 dst->f[i] = 0.0f;
1574 else if (chan->f[i] > 1.0f)
1575 dst->f[i] = 1.0f;
1576 else
1577 dst->i[i] = chan->i[i];
1578 }
1579 break;
1580
1581 case TGSI_SAT_MINUS_PLUS_ONE:
1582 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1583 if (execmask & (1 << i)) {
1584 if (chan->f[i] < -1.0f)
1585 dst->f[i] = -1.0f;
1586 else if (chan->f[i] > 1.0f)
1587 dst->f[i] = 1.0f;
1588 else
1589 dst->i[i] = chan->i[i];
1590 }
1591 break;
1592
1593 default:
1594 assert( 0 );
1595 }
1596 }
1597
1598 #define FETCH(VAL,INDEX,CHAN)\
1599 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1600
1601 #define IFETCH(VAL,INDEX,CHAN)\
1602 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1603
1604
1605 /**
1606 * Execute ARB-style KIL which is predicated by a src register.
1607 * Kill fragment if any of the four values is less than zero.
1608 */
1609 static void
1610 exec_kil(struct tgsi_exec_machine *mach,
1611 const struct tgsi_full_instruction *inst)
1612 {
1613 uint uniquemask;
1614 uint chan_index;
1615 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1616 union tgsi_exec_channel r[1];
1617
1618 /* This mask stores component bits that were already tested. */
1619 uniquemask = 0;
1620
1621 for (chan_index = 0; chan_index < 4; chan_index++)
1622 {
1623 uint swizzle;
1624 uint i;
1625
1626 /* unswizzle channel */
1627 swizzle = tgsi_util_get_full_src_register_swizzle (
1628 &inst->Src[0],
1629 chan_index);
1630
1631 /* check if the component has not been already tested */
1632 if (uniquemask & (1 << swizzle))
1633 continue;
1634 uniquemask |= 1 << swizzle;
1635
1636 FETCH(&r[0], 0, chan_index);
1637 for (i = 0; i < 4; i++)
1638 if (r[0].f[i] < 0.0f)
1639 kilmask |= 1 << i;
1640 }
1641
1642 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1643 }
1644
1645 /**
1646 * Execute NVIDIA-style KIL which is predicated by a condition code.
1647 * Kill fragment if the condition code is TRUE.
1648 */
1649 static void
1650 exec_kilp(struct tgsi_exec_machine *mach,
1651 const struct tgsi_full_instruction *inst)
1652 {
1653 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1654
1655 /* "unconditional" kil */
1656 kilmask = mach->ExecMask;
1657 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1658 }
1659
1660 static void
1661 emit_vertex(struct tgsi_exec_machine *mach)
1662 {
1663 /* FIXME: check for exec mask correctly
1664 unsigned i;
1665 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1666 if ((mach->ExecMask & (1 << i)))
1667 */
1668 if (mach->ExecMask) {
1669 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1670 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1671 }
1672 }
1673
1674 static void
1675 emit_primitive(struct tgsi_exec_machine *mach)
1676 {
1677 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1678 /* FIXME: check for exec mask correctly
1679 unsigned i;
1680 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1681 if ((mach->ExecMask & (1 << i)))
1682 */
1683 if (mach->ExecMask) {
1684 ++(*prim_count);
1685 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1686 mach->Primitives[*prim_count] = 0;
1687 }
1688 }
1689
1690 static void
1691 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1692 {
1693 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1694 int emitted_verts =
1695 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1696 if (emitted_verts) {
1697 emit_primitive(mach);
1698 }
1699 }
1700 }
1701
1702
1703 /*
1704 * Fetch four texture samples using STR texture coordinates.
1705 */
1706 static void
1707 fetch_texel( struct tgsi_sampler *sampler,
1708 const union tgsi_exec_channel *s,
1709 const union tgsi_exec_channel *t,
1710 const union tgsi_exec_channel *p,
1711 const union tgsi_exec_channel *c0,
1712 enum tgsi_sampler_control control,
1713 union tgsi_exec_channel *r,
1714 union tgsi_exec_channel *g,
1715 union tgsi_exec_channel *b,
1716 union tgsi_exec_channel *a )
1717 {
1718 uint j;
1719 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1720
1721 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, control, rgba);
1722
1723 for (j = 0; j < 4; j++) {
1724 r->f[j] = rgba[0][j];
1725 g->f[j] = rgba[1][j];
1726 b->f[j] = rgba[2][j];
1727 a->f[j] = rgba[3][j];
1728 }
1729 }
1730
1731
1732 #define TEX_MODIFIER_NONE 0
1733 #define TEX_MODIFIER_PROJECTED 1
1734 #define TEX_MODIFIER_LOD_BIAS 2
1735 #define TEX_MODIFIER_EXPLICIT_LOD 3
1736
1737
1738 static void
1739 exec_tex(struct tgsi_exec_machine *mach,
1740 const struct tgsi_full_instruction *inst,
1741 uint modifier)
1742 {
1743 const uint unit = inst->Src[1].Register.Index;
1744 union tgsi_exec_channel r[4];
1745 const union tgsi_exec_channel *lod = &ZeroVec;
1746 enum tgsi_sampler_control control;
1747 uint chan;
1748
1749 if (modifier != TEX_MODIFIER_NONE) {
1750 FETCH(&r[3], 0, TGSI_CHAN_W);
1751 if (modifier != TEX_MODIFIER_PROJECTED) {
1752 lod = &r[3];
1753 }
1754 }
1755
1756 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1757 control = tgsi_sampler_lod_explicit;
1758 } else {
1759 control = tgsi_sampler_lod_bias;
1760 }
1761
1762 switch (inst->Texture.Texture) {
1763 case TGSI_TEXTURE_1D:
1764 FETCH(&r[0], 0, TGSI_CHAN_X);
1765
1766 if (modifier == TEX_MODIFIER_PROJECTED) {
1767 micro_div(&r[0], &r[0], &r[3]);
1768 }
1769
1770 fetch_texel(mach->Samplers[unit],
1771 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1772 control,
1773 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1774 break;
1775 case TGSI_TEXTURE_SHADOW1D:
1776 FETCH(&r[0], 0, TGSI_CHAN_X);
1777 FETCH(&r[2], 0, TGSI_CHAN_Z);
1778
1779 if (modifier == TEX_MODIFIER_PROJECTED) {
1780 micro_div(&r[0], &r[0], &r[3]);
1781 }
1782
1783 fetch_texel(mach->Samplers[unit],
1784 &r[0], &ZeroVec, &r[2], lod, /* S, T, P, LOD */
1785 control,
1786 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1787 break;
1788
1789 case TGSI_TEXTURE_2D:
1790 case TGSI_TEXTURE_RECT:
1791 case TGSI_TEXTURE_SHADOW2D:
1792 case TGSI_TEXTURE_SHADOWRECT:
1793 FETCH(&r[0], 0, TGSI_CHAN_X);
1794 FETCH(&r[1], 0, TGSI_CHAN_Y);
1795 FETCH(&r[2], 0, TGSI_CHAN_Z);
1796
1797 if (modifier == TEX_MODIFIER_PROJECTED) {
1798 micro_div(&r[0], &r[0], &r[3]);
1799 micro_div(&r[1], &r[1], &r[3]);
1800 micro_div(&r[2], &r[2], &r[3]);
1801 }
1802
1803 fetch_texel(mach->Samplers[unit],
1804 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1805 control,
1806 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1807 break;
1808
1809 case TGSI_TEXTURE_1D_ARRAY:
1810 FETCH(&r[0], 0, TGSI_CHAN_X);
1811 FETCH(&r[1], 0, TGSI_CHAN_Y);
1812
1813 if (modifier == TEX_MODIFIER_PROJECTED) {
1814 micro_div(&r[0], &r[0], &r[3]);
1815 }
1816
1817 fetch_texel(mach->Samplers[unit],
1818 &r[0], &r[1], &ZeroVec, lod, /* S, T, P, LOD */
1819 control,
1820 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1821 break;
1822 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1823 FETCH(&r[0], 0, TGSI_CHAN_X);
1824 FETCH(&r[1], 0, TGSI_CHAN_Y);
1825 FETCH(&r[2], 0, TGSI_CHAN_Z);
1826
1827 if (modifier == TEX_MODIFIER_PROJECTED) {
1828 micro_div(&r[0], &r[0], &r[3]);
1829 }
1830
1831 fetch_texel(mach->Samplers[unit],
1832 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1833 control,
1834 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1835 break;
1836
1837 case TGSI_TEXTURE_2D_ARRAY:
1838 FETCH(&r[0], 0, TGSI_CHAN_X);
1839 FETCH(&r[1], 0, TGSI_CHAN_Y);
1840 FETCH(&r[2], 0, TGSI_CHAN_Z);
1841
1842 if (modifier == TEX_MODIFIER_PROJECTED) {
1843 micro_div(&r[0], &r[0], &r[3]);
1844 micro_div(&r[1], &r[1], &r[3]);
1845 }
1846
1847 fetch_texel(mach->Samplers[unit],
1848 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1849 control,
1850 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1851 break;
1852 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1853 case TGSI_TEXTURE_SHADOWCUBE:
1854 FETCH(&r[0], 0, TGSI_CHAN_X);
1855 FETCH(&r[1], 0, TGSI_CHAN_Y);
1856 FETCH(&r[2], 0, TGSI_CHAN_Z);
1857 FETCH(&r[3], 0, TGSI_CHAN_W);
1858
1859 fetch_texel(mach->Samplers[unit],
1860 &r[0], &r[1], &r[2], &r[3], /* S, T, P, LOD */
1861 control,
1862 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1863 break;
1864 case TGSI_TEXTURE_3D:
1865 case TGSI_TEXTURE_CUBE:
1866 FETCH(&r[0], 0, TGSI_CHAN_X);
1867 FETCH(&r[1], 0, TGSI_CHAN_Y);
1868 FETCH(&r[2], 0, TGSI_CHAN_Z);
1869
1870 if (modifier == TEX_MODIFIER_PROJECTED) {
1871 micro_div(&r[0], &r[0], &r[3]);
1872 micro_div(&r[1], &r[1], &r[3]);
1873 micro_div(&r[2], &r[2], &r[3]);
1874 }
1875
1876 fetch_texel(mach->Samplers[unit],
1877 &r[0], &r[1], &r[2], lod,
1878 control,
1879 &r[0], &r[1], &r[2], &r[3]);
1880 break;
1881
1882 default:
1883 assert(0);
1884 }
1885
1886 #if 0
1887 debug_printf("fetch r: %g %g %g %g\n",
1888 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1889 debug_printf("fetch g: %g %g %g %g\n",
1890 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1891 debug_printf("fetch b: %g %g %g %g\n",
1892 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1893 debug_printf("fetch a: %g %g %g %g\n",
1894 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1895 #endif
1896
1897 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1898 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1899 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1900 }
1901 }
1902 }
1903
1904 static void
1905 exec_txd(struct tgsi_exec_machine *mach,
1906 const struct tgsi_full_instruction *inst)
1907 {
1908 const uint unit = inst->Src[3].Register.Index;
1909 union tgsi_exec_channel r[4];
1910 uint chan;
1911
1912 /*
1913 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1914 */
1915
1916 switch (inst->Texture.Texture) {
1917 case TGSI_TEXTURE_1D:
1918 case TGSI_TEXTURE_SHADOW1D:
1919
1920 FETCH(&r[0], 0, TGSI_CHAN_X);
1921
1922 fetch_texel(mach->Samplers[unit],
1923 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1924 tgsi_sampler_lod_bias,
1925 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1926 break;
1927
1928 case TGSI_TEXTURE_1D_ARRAY:
1929 case TGSI_TEXTURE_2D:
1930 case TGSI_TEXTURE_RECT:
1931 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1932 case TGSI_TEXTURE_SHADOW2D:
1933 case TGSI_TEXTURE_SHADOWRECT:
1934
1935 FETCH(&r[0], 0, TGSI_CHAN_X);
1936 FETCH(&r[1], 0, TGSI_CHAN_Y);
1937 FETCH(&r[2], 0, TGSI_CHAN_Z);
1938
1939 fetch_texel(mach->Samplers[unit],
1940 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
1941 tgsi_sampler_lod_bias,
1942 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1943 break;
1944
1945 case TGSI_TEXTURE_2D_ARRAY:
1946 case TGSI_TEXTURE_3D:
1947 case TGSI_TEXTURE_CUBE:
1948
1949 FETCH(&r[0], 0, TGSI_CHAN_X);
1950 FETCH(&r[1], 0, TGSI_CHAN_Y);
1951 FETCH(&r[2], 0, TGSI_CHAN_Z);
1952
1953 fetch_texel(mach->Samplers[unit],
1954 &r[0], &r[1], &r[2], &ZeroVec,
1955 tgsi_sampler_lod_bias,
1956 &r[0], &r[1], &r[2], &r[3]);
1957 break;
1958
1959 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1960
1961 FETCH(&r[0], 0, TGSI_CHAN_X);
1962 FETCH(&r[1], 0, TGSI_CHAN_Y);
1963 FETCH(&r[2], 0, TGSI_CHAN_Z);
1964 FETCH(&r[3], 0, TGSI_CHAN_W);
1965
1966 fetch_texel(mach->Samplers[unit],
1967 &r[0], &r[1], &r[2], &r[3],
1968 tgsi_sampler_lod_bias,
1969 &r[0], &r[1], &r[2], &r[3]);
1970 break;
1971
1972 default:
1973 assert(0);
1974 }
1975
1976 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1977 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1978 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1979 }
1980 }
1981 }
1982
1983
1984 static void
1985 exec_txf(struct tgsi_exec_machine *mach,
1986 const struct tgsi_full_instruction *inst)
1987 {
1988 struct tgsi_sampler *sampler;
1989 const uint unit = inst->Src[2].Register.Index;
1990 union tgsi_exec_channel r[4];
1991 union tgsi_exec_channel offset[3];
1992 uint chan;
1993 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1994 int j;
1995 int8_t offsets[3];
1996
1997 if (inst->Texture.NumOffsets == 1) {
1998 union tgsi_exec_channel index;
1999 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
2000 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2001 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
2002 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2003 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
2004 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2005 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
2006 offsets[0] = offset[0].i[0];
2007 offsets[1] = offset[1].i[0];
2008 offsets[2] = offset[2].i[0];
2009 } else
2010 offsets[0] = offsets[1] = offsets[2] = 0;
2011
2012 IFETCH(&r[3], 0, TGSI_CHAN_W);
2013
2014 switch(inst->Texture.Texture) {
2015 case TGSI_TEXTURE_3D:
2016 case TGSI_TEXTURE_2D_ARRAY:
2017 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2018 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2019 /* fallthrough */
2020 case TGSI_TEXTURE_2D:
2021 case TGSI_TEXTURE_RECT:
2022 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2023 case TGSI_TEXTURE_SHADOW2D:
2024 case TGSI_TEXTURE_SHADOWRECT:
2025 case TGSI_TEXTURE_1D_ARRAY:
2026 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2027 /* fallthrough */
2028 case TGSI_TEXTURE_1D:
2029 case TGSI_TEXTURE_SHADOW1D:
2030 IFETCH(&r[0], 0, TGSI_CHAN_X);
2031 break;
2032 default:
2033 assert(0);
2034 break;
2035 }
2036
2037 sampler = mach->Samplers[unit];
2038 sampler->get_texel(sampler, r[0].i, r[1].i, r[2].i, r[3].i,
2039 offsets, rgba);
2040
2041 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2042 r[0].f[j] = rgba[0][j];
2043 r[1].f[j] = rgba[1][j];
2044 r[2].f[j] = rgba[2][j];
2045 r[3].f[j] = rgba[3][j];
2046 }
2047
2048 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2049 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2050 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2051 }
2052 }
2053 }
2054
2055 static void
2056 exec_txq(struct tgsi_exec_machine *mach,
2057 const struct tgsi_full_instruction *inst)
2058 {
2059 struct tgsi_sampler *sampler;
2060 const uint unit = inst->Src[1].Register.Index;
2061 int result[4];
2062 union tgsi_exec_channel r[4], src;
2063 uint chan;
2064 int i,j;
2065
2066 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2067 sampler = mach->Samplers[unit];
2068
2069 sampler->get_dims(sampler, src.i[0], result);
2070
2071 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2072 for (j = 0; j < 4; j++) {
2073 r[j].i[i] = result[j];
2074 }
2075 }
2076
2077 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2078 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2079 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2080 TGSI_EXEC_DATA_INT);
2081 }
2082 }
2083 }
2084
2085 static void
2086 exec_sample(struct tgsi_exec_machine *mach,
2087 const struct tgsi_full_instruction *inst,
2088 uint modifier)
2089 {
2090 const uint resource_unit = inst->Src[1].Register.Index;
2091 const uint sampler_unit = inst->Src[2].Register.Index;
2092 union tgsi_exec_channel r[4];
2093 const union tgsi_exec_channel *lod = &ZeroVec;
2094 enum tgsi_sampler_control control;
2095 uint chan;
2096
2097 if (modifier != TEX_MODIFIER_NONE) {
2098 if (modifier == TEX_MODIFIER_LOD_BIAS)
2099 FETCH(&r[3], 3, TGSI_CHAN_X);
2100 else /*TEX_MODIFIER_LOD*/
2101 FETCH(&r[3], 0, TGSI_CHAN_W);
2102
2103 if (modifier != TEX_MODIFIER_PROJECTED) {
2104 lod = &r[3];
2105 }
2106 }
2107
2108 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2109 control = tgsi_sampler_lod_explicit;
2110 } else {
2111 control = tgsi_sampler_lod_bias;
2112 }
2113
2114 switch (mach->SamplerViews[resource_unit].Resource) {
2115 case TGSI_TEXTURE_1D:
2116 case TGSI_TEXTURE_SHADOW1D:
2117 FETCH(&r[0], 0, TGSI_CHAN_X);
2118
2119 if (modifier == TEX_MODIFIER_PROJECTED) {
2120 micro_div(&r[0], &r[0], &r[3]);
2121 }
2122
2123 fetch_texel(mach->Samplers[sampler_unit],
2124 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
2125 control,
2126 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2127 break;
2128
2129 case TGSI_TEXTURE_1D_ARRAY:
2130 case TGSI_TEXTURE_2D:
2131 case TGSI_TEXTURE_RECT:
2132 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2133 case TGSI_TEXTURE_SHADOW2D:
2134 case TGSI_TEXTURE_SHADOWRECT:
2135 FETCH(&r[0], 0, TGSI_CHAN_X);
2136 FETCH(&r[1], 0, TGSI_CHAN_Y);
2137 FETCH(&r[2], 0, TGSI_CHAN_Z);
2138
2139 if (modifier == TEX_MODIFIER_PROJECTED) {
2140 micro_div(&r[0], &r[0], &r[3]);
2141 micro_div(&r[1], &r[1], &r[3]);
2142 micro_div(&r[2], &r[2], &r[3]);
2143 }
2144
2145 fetch_texel(mach->Samplers[sampler_unit],
2146 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
2147 control,
2148 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2149 break;
2150
2151 case TGSI_TEXTURE_2D_ARRAY:
2152 case TGSI_TEXTURE_3D:
2153 case TGSI_TEXTURE_CUBE:
2154 FETCH(&r[0], 0, TGSI_CHAN_X);
2155 FETCH(&r[1], 0, TGSI_CHAN_Y);
2156 FETCH(&r[2], 0, TGSI_CHAN_Z);
2157
2158 if (modifier == TEX_MODIFIER_PROJECTED) {
2159 micro_div(&r[0], &r[0], &r[3]);
2160 micro_div(&r[1], &r[1], &r[3]);
2161 micro_div(&r[2], &r[2], &r[3]);
2162 }
2163
2164 fetch_texel(mach->Samplers[sampler_unit],
2165 &r[0], &r[1], &r[2], lod,
2166 control,
2167 &r[0], &r[1], &r[2], &r[3]);
2168 break;
2169
2170 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2171 case TGSI_TEXTURE_SHADOWCUBE:
2172 FETCH(&r[0], 0, TGSI_CHAN_X);
2173 FETCH(&r[1], 0, TGSI_CHAN_Y);
2174 FETCH(&r[2], 0, TGSI_CHAN_Z);
2175 FETCH(&r[3], 0, TGSI_CHAN_W);
2176
2177 assert(modifier != TEX_MODIFIER_PROJECTED);
2178
2179 fetch_texel(mach->Samplers[sampler_unit],
2180 &r[0], &r[1], &r[2], &r[3],
2181 control,
2182 &r[0], &r[1], &r[2], &r[3]);
2183 break;
2184
2185 default:
2186 assert(0);
2187 }
2188
2189 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2190 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2191 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2192 }
2193 }
2194 }
2195
2196 static void
2197 exec_sample_d(struct tgsi_exec_machine *mach,
2198 const struct tgsi_full_instruction *inst)
2199 {
2200 const uint resource_unit = inst->Src[1].Register.Index;
2201 const uint sampler_unit = inst->Src[2].Register.Index;
2202 union tgsi_exec_channel r[4];
2203 uint chan;
2204 /*
2205 * XXX: This is fake SAMPLE_D -- the derivatives are not taken into account, yet.
2206 */
2207
2208 switch (mach->SamplerViews[resource_unit].Resource) {
2209 case TGSI_TEXTURE_1D:
2210 case TGSI_TEXTURE_SHADOW1D:
2211
2212 FETCH(&r[0], 0, TGSI_CHAN_X);
2213
2214 fetch_texel(mach->Samplers[sampler_unit],
2215 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
2216 tgsi_sampler_lod_bias,
2217 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2218 break;
2219
2220 case TGSI_TEXTURE_2D:
2221 case TGSI_TEXTURE_RECT:
2222 case TGSI_TEXTURE_SHADOW2D:
2223 case TGSI_TEXTURE_SHADOWRECT:
2224
2225 FETCH(&r[0], 0, TGSI_CHAN_X);
2226 FETCH(&r[1], 0, TGSI_CHAN_Y);
2227 FETCH(&r[2], 0, TGSI_CHAN_Z);
2228
2229 fetch_texel(mach->Samplers[sampler_unit],
2230 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
2231 tgsi_sampler_lod_bias,
2232 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2233 break;
2234
2235 case TGSI_TEXTURE_3D:
2236 case TGSI_TEXTURE_CUBE:
2237
2238 FETCH(&r[0], 0, TGSI_CHAN_X);
2239 FETCH(&r[1], 0, TGSI_CHAN_Y);
2240 FETCH(&r[2], 0, TGSI_CHAN_Z);
2241
2242 fetch_texel(mach->Samplers[sampler_unit],
2243 &r[0], &r[1], &r[2], &ZeroVec,
2244 tgsi_sampler_lod_bias,
2245 &r[0], &r[1], &r[2], &r[3]);
2246 break;
2247
2248 default:
2249 assert(0);
2250 }
2251
2252 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2253 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2254 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2255 }
2256 }
2257 }
2258
2259
2260 /**
2261 * Evaluate a constant-valued coefficient at the position of the
2262 * current quad.
2263 */
2264 static void
2265 eval_constant_coef(
2266 struct tgsi_exec_machine *mach,
2267 unsigned attrib,
2268 unsigned chan )
2269 {
2270 unsigned i;
2271
2272 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2273 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2274 }
2275 }
2276
2277 /**
2278 * Evaluate a linear-valued coefficient at the position of the
2279 * current quad.
2280 */
2281 static void
2282 eval_linear_coef(
2283 struct tgsi_exec_machine *mach,
2284 unsigned attrib,
2285 unsigned chan )
2286 {
2287 const float x = mach->QuadPos.xyzw[0].f[0];
2288 const float y = mach->QuadPos.xyzw[1].f[0];
2289 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2290 const float dady = mach->InterpCoefs[attrib].dady[chan];
2291 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2292 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2293 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2294 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2295 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2296 }
2297
2298 /**
2299 * Evaluate a perspective-valued coefficient at the position of the
2300 * current quad.
2301 */
2302 static void
2303 eval_perspective_coef(
2304 struct tgsi_exec_machine *mach,
2305 unsigned attrib,
2306 unsigned chan )
2307 {
2308 const float x = mach->QuadPos.xyzw[0].f[0];
2309 const float y = mach->QuadPos.xyzw[1].f[0];
2310 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2311 const float dady = mach->InterpCoefs[attrib].dady[chan];
2312 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2313 const float *w = mach->QuadPos.xyzw[3].f;
2314 /* divide by W here */
2315 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2316 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2317 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2318 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2319 }
2320
2321
2322 typedef void (* eval_coef_func)(
2323 struct tgsi_exec_machine *mach,
2324 unsigned attrib,
2325 unsigned chan );
2326
2327 static void
2328 exec_declaration(struct tgsi_exec_machine *mach,
2329 const struct tgsi_full_declaration *decl)
2330 {
2331 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2332 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2333 return;
2334 }
2335
2336 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2337 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2338 uint first, last, mask;
2339
2340 first = decl->Range.First;
2341 last = decl->Range.Last;
2342 mask = decl->Declaration.UsageMask;
2343
2344 /* XXX we could remove this special-case code since
2345 * mach->InterpCoefs[first].a0 should already have the
2346 * front/back-face value. But we should first update the
2347 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2348 * Then, we could remove the tgsi_exec_machine::Face field.
2349 */
2350 /* XXX make FACE a system value */
2351 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2352 uint i;
2353
2354 assert(decl->Semantic.Index == 0);
2355 assert(first == last);
2356
2357 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2358 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2359 }
2360 } else {
2361 eval_coef_func eval;
2362 uint i, j;
2363
2364 switch (decl->Interp.Interpolate) {
2365 case TGSI_INTERPOLATE_CONSTANT:
2366 eval = eval_constant_coef;
2367 break;
2368
2369 case TGSI_INTERPOLATE_LINEAR:
2370 eval = eval_linear_coef;
2371 break;
2372
2373 case TGSI_INTERPOLATE_PERSPECTIVE:
2374 eval = eval_perspective_coef;
2375 break;
2376
2377 case TGSI_INTERPOLATE_COLOR:
2378 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2379 break;
2380
2381 default:
2382 assert(0);
2383 return;
2384 }
2385
2386 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2387 if (mask & (1 << j)) {
2388 for (i = first; i <= last; i++) {
2389 eval(mach, i, j);
2390 }
2391 }
2392 }
2393 }
2394 }
2395 }
2396
2397 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2398 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2399 }
2400 }
2401
2402
2403 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2404
2405 static void
2406 exec_vector(struct tgsi_exec_machine *mach,
2407 const struct tgsi_full_instruction *inst,
2408 micro_op op,
2409 enum tgsi_exec_datatype dst_datatype)
2410 {
2411 unsigned int chan;
2412
2413 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2414 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2415 union tgsi_exec_channel dst;
2416
2417 op(&dst);
2418 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2419 }
2420 }
2421 }
2422
2423 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2424 const union tgsi_exec_channel *src);
2425
2426 static void
2427 exec_scalar_unary(struct tgsi_exec_machine *mach,
2428 const struct tgsi_full_instruction *inst,
2429 micro_unary_op op,
2430 enum tgsi_exec_datatype dst_datatype,
2431 enum tgsi_exec_datatype src_datatype)
2432 {
2433 unsigned int chan;
2434 union tgsi_exec_channel src;
2435 union tgsi_exec_channel dst;
2436
2437 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2438 op(&dst, &src);
2439 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2440 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2441 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2442 }
2443 }
2444 }
2445
2446 static void
2447 exec_vector_unary(struct tgsi_exec_machine *mach,
2448 const struct tgsi_full_instruction *inst,
2449 micro_unary_op op,
2450 enum tgsi_exec_datatype dst_datatype,
2451 enum tgsi_exec_datatype src_datatype)
2452 {
2453 unsigned int chan;
2454 struct tgsi_exec_vector dst;
2455
2456 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2457 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2458 union tgsi_exec_channel src;
2459
2460 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2461 op(&dst.xyzw[chan], &src);
2462 }
2463 }
2464 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2465 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2466 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2467 }
2468 }
2469 }
2470
2471 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2472 const union tgsi_exec_channel *src0,
2473 const union tgsi_exec_channel *src1);
2474
2475 static void
2476 exec_scalar_binary(struct tgsi_exec_machine *mach,
2477 const struct tgsi_full_instruction *inst,
2478 micro_binary_op op,
2479 enum tgsi_exec_datatype dst_datatype,
2480 enum tgsi_exec_datatype src_datatype)
2481 {
2482 unsigned int chan;
2483 union tgsi_exec_channel src[2];
2484 union tgsi_exec_channel dst;
2485
2486 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2487 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_Y, src_datatype);
2488 op(&dst, &src[0], &src[1]);
2489 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2490 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2491 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2492 }
2493 }
2494 }
2495
2496 static void
2497 exec_vector_binary(struct tgsi_exec_machine *mach,
2498 const struct tgsi_full_instruction *inst,
2499 micro_binary_op op,
2500 enum tgsi_exec_datatype dst_datatype,
2501 enum tgsi_exec_datatype src_datatype)
2502 {
2503 unsigned int chan;
2504 struct tgsi_exec_vector dst;
2505
2506 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2507 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2508 union tgsi_exec_channel src[2];
2509
2510 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2511 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2512 op(&dst.xyzw[chan], &src[0], &src[1]);
2513 }
2514 }
2515 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2516 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2517 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2518 }
2519 }
2520 }
2521
2522 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2523 const union tgsi_exec_channel *src0,
2524 const union tgsi_exec_channel *src1,
2525 const union tgsi_exec_channel *src2);
2526
2527 static void
2528 exec_vector_trinary(struct tgsi_exec_machine *mach,
2529 const struct tgsi_full_instruction *inst,
2530 micro_trinary_op op,
2531 enum tgsi_exec_datatype dst_datatype,
2532 enum tgsi_exec_datatype src_datatype)
2533 {
2534 unsigned int chan;
2535 struct tgsi_exec_vector dst;
2536
2537 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2538 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2539 union tgsi_exec_channel src[3];
2540
2541 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2542 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2543 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2544 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2545 }
2546 }
2547 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2548 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2549 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2550 }
2551 }
2552 }
2553
2554 static void
2555 exec_dp3(struct tgsi_exec_machine *mach,
2556 const struct tgsi_full_instruction *inst)
2557 {
2558 unsigned int chan;
2559 union tgsi_exec_channel arg[3];
2560
2561 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2562 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2563 micro_mul(&arg[2], &arg[0], &arg[1]);
2564
2565 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2566 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2567 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2568 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2569 }
2570
2571 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2572 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2573 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2574 }
2575 }
2576 }
2577
2578 static void
2579 exec_dp4(struct tgsi_exec_machine *mach,
2580 const struct tgsi_full_instruction *inst)
2581 {
2582 unsigned int chan;
2583 union tgsi_exec_channel arg[3];
2584
2585 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2586 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2587 micro_mul(&arg[2], &arg[0], &arg[1]);
2588
2589 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2590 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2591 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2592 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2593 }
2594
2595 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2596 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2597 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2598 }
2599 }
2600 }
2601
2602 static void
2603 exec_dp2a(struct tgsi_exec_machine *mach,
2604 const struct tgsi_full_instruction *inst)
2605 {
2606 unsigned int chan;
2607 union tgsi_exec_channel arg[3];
2608
2609 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2610 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2611 micro_mul(&arg[2], &arg[0], &arg[1]);
2612
2613 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2614 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2615 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2616
2617 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2618 micro_add(&arg[0], &arg[0], &arg[1]);
2619
2620 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2621 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2622 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2623 }
2624 }
2625 }
2626
2627 static void
2628 exec_dph(struct tgsi_exec_machine *mach,
2629 const struct tgsi_full_instruction *inst)
2630 {
2631 unsigned int chan;
2632 union tgsi_exec_channel arg[3];
2633
2634 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2635 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2636 micro_mul(&arg[2], &arg[0], &arg[1]);
2637
2638 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2639 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2640 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2641
2642 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2643 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2644 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2645
2646 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2647 micro_add(&arg[0], &arg[0], &arg[1]);
2648
2649 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2650 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2651 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2652 }
2653 }
2654 }
2655
2656 static void
2657 exec_dp2(struct tgsi_exec_machine *mach,
2658 const struct tgsi_full_instruction *inst)
2659 {
2660 unsigned int chan;
2661 union tgsi_exec_channel arg[3];
2662
2663 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2664 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2665 micro_mul(&arg[2], &arg[0], &arg[1]);
2666
2667 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2668 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2669 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2670
2671 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2672 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2673 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2674 }
2675 }
2676 }
2677
2678 static void
2679 exec_nrm4(struct tgsi_exec_machine *mach,
2680 const struct tgsi_full_instruction *inst)
2681 {
2682 unsigned int chan;
2683 union tgsi_exec_channel arg[4];
2684 union tgsi_exec_channel scale;
2685
2686 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2687 micro_mul(&scale, &arg[0], &arg[0]);
2688
2689 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2690 union tgsi_exec_channel product;
2691
2692 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2693 micro_mul(&product, &arg[chan], &arg[chan]);
2694 micro_add(&scale, &scale, &product);
2695 }
2696
2697 micro_rsq(&scale, &scale);
2698
2699 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_W; chan++) {
2700 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2701 micro_mul(&arg[chan], &arg[chan], &scale);
2702 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2703 }
2704 }
2705 }
2706
2707 static void
2708 exec_nrm3(struct tgsi_exec_machine *mach,
2709 const struct tgsi_full_instruction *inst)
2710 {
2711 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2712 unsigned int chan;
2713 union tgsi_exec_channel arg[3];
2714 union tgsi_exec_channel scale;
2715
2716 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2717 micro_mul(&scale, &arg[0], &arg[0]);
2718
2719 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2720 union tgsi_exec_channel product;
2721
2722 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2723 micro_mul(&product, &arg[chan], &arg[chan]);
2724 micro_add(&scale, &scale, &product);
2725 }
2726
2727 micro_rsq(&scale, &scale);
2728
2729 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_Z; chan++) {
2730 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2731 micro_mul(&arg[chan], &arg[chan], &scale);
2732 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2733 }
2734 }
2735 }
2736
2737 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2738 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2739 }
2740 }
2741
2742 static void
2743 exec_scs(struct tgsi_exec_machine *mach,
2744 const struct tgsi_full_instruction *inst)
2745 {
2746 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2747 union tgsi_exec_channel arg;
2748 union tgsi_exec_channel result;
2749
2750 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2751
2752 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2753 micro_cos(&result, &arg);
2754 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2755 }
2756 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2757 micro_sin(&result, &arg);
2758 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2759 }
2760 }
2761 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2762 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2763 }
2764 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2765 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2766 }
2767 }
2768
2769 static void
2770 exec_x2d(struct tgsi_exec_machine *mach,
2771 const struct tgsi_full_instruction *inst)
2772 {
2773 union tgsi_exec_channel r[4];
2774 union tgsi_exec_channel d[2];
2775
2776 fetch_source(mach, &r[0], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2777 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2778 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2779 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2780 micro_mul(&r[2], &r[2], &r[0]);
2781 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2782 micro_mul(&r[3], &r[3], &r[1]);
2783 micro_add(&r[2], &r[2], &r[3]);
2784 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2785 micro_add(&d[0], &r[2], &r[3]);
2786 }
2787 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2788 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2789 micro_mul(&r[2], &r[2], &r[0]);
2790 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2791 micro_mul(&r[3], &r[3], &r[1]);
2792 micro_add(&r[2], &r[2], &r[3]);
2793 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2794 micro_add(&d[1], &r[2], &r[3]);
2795 }
2796 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2797 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2798 }
2799 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2800 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2801 }
2802 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2803 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2804 }
2805 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2806 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2807 }
2808 }
2809
2810 static void
2811 exec_rfl(struct tgsi_exec_machine *mach,
2812 const struct tgsi_full_instruction *inst)
2813 {
2814 union tgsi_exec_channel r[9];
2815
2816 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2817 /* r0 = dp3(src0, src0) */
2818 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2819 micro_mul(&r[0], &r[2], &r[2]);
2820 fetch_source(mach, &r[4], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2821 micro_mul(&r[8], &r[4], &r[4]);
2822 micro_add(&r[0], &r[0], &r[8]);
2823 fetch_source(mach, &r[6], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2824 micro_mul(&r[8], &r[6], &r[6]);
2825 micro_add(&r[0], &r[0], &r[8]);
2826
2827 /* r1 = dp3(src0, src1) */
2828 fetch_source(mach, &r[3], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2829 micro_mul(&r[1], &r[2], &r[3]);
2830 fetch_source(mach, &r[5], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2831 micro_mul(&r[8], &r[4], &r[5]);
2832 micro_add(&r[1], &r[1], &r[8]);
2833 fetch_source(mach, &r[7], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2834 micro_mul(&r[8], &r[6], &r[7]);
2835 micro_add(&r[1], &r[1], &r[8]);
2836
2837 /* r1 = 2 * r1 / r0 */
2838 micro_add(&r[1], &r[1], &r[1]);
2839 micro_div(&r[1], &r[1], &r[0]);
2840
2841 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2842 micro_mul(&r[2], &r[2], &r[1]);
2843 micro_sub(&r[2], &r[2], &r[3]);
2844 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2845 }
2846 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2847 micro_mul(&r[4], &r[4], &r[1]);
2848 micro_sub(&r[4], &r[4], &r[5]);
2849 store_dest(mach, &r[4], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2850 }
2851 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2852 micro_mul(&r[6], &r[6], &r[1]);
2853 micro_sub(&r[6], &r[6], &r[7]);
2854 store_dest(mach, &r[6], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2855 }
2856 }
2857 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2858 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2859 }
2860 }
2861
2862 static void
2863 exec_xpd(struct tgsi_exec_machine *mach,
2864 const struct tgsi_full_instruction *inst)
2865 {
2866 union tgsi_exec_channel r[6];
2867 union tgsi_exec_channel d[3];
2868
2869 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2870 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2871
2872 micro_mul(&r[2], &r[0], &r[1]);
2873
2874 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2875 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2876
2877 micro_mul(&r[5], &r[3], &r[4] );
2878 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
2879
2880 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2881
2882 micro_mul(&r[3], &r[3], &r[2]);
2883
2884 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2885
2886 micro_mul(&r[1], &r[1], &r[5]);
2887 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
2888
2889 micro_mul(&r[5], &r[5], &r[4]);
2890 micro_mul(&r[0], &r[0], &r[2]);
2891 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
2892
2893 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2894 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2895 }
2896 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2897 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2898 }
2899 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2900 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2901 }
2902 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2903 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2904 }
2905 }
2906
2907 static void
2908 exec_dst(struct tgsi_exec_machine *mach,
2909 const struct tgsi_full_instruction *inst)
2910 {
2911 union tgsi_exec_channel r[2];
2912 union tgsi_exec_channel d[4];
2913
2914 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2915 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2916 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2917 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
2918 }
2919 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2920 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2921 }
2922 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2923 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2924 }
2925
2926 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2927 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2928 }
2929 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2930 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2931 }
2932 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2933 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2934 }
2935 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2936 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2937 }
2938 }
2939
2940 static void
2941 exec_log(struct tgsi_exec_machine *mach,
2942 const struct tgsi_full_instruction *inst)
2943 {
2944 union tgsi_exec_channel r[3];
2945
2946 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2947 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
2948 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
2949 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
2950 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2951 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2952 }
2953 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2954 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
2955 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
2956 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2957 }
2958 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2959 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2960 }
2961 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2962 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2963 }
2964 }
2965
2966 static void
2967 exec_exp(struct tgsi_exec_machine *mach,
2968 const struct tgsi_full_instruction *inst)
2969 {
2970 union tgsi_exec_channel r[3];
2971
2972 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2973 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
2974 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2975 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
2976 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2977 }
2978 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2979 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
2980 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2981 }
2982 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2983 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
2984 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2985 }
2986 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2987 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2988 }
2989 }
2990
2991 static void
2992 exec_lit(struct tgsi_exec_machine *mach,
2993 const struct tgsi_full_instruction *inst)
2994 {
2995 union tgsi_exec_channel r[3];
2996 union tgsi_exec_channel d[3];
2997
2998 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
2999 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3000 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3001 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3002 micro_max(&r[1], &r[1], &ZeroVec);
3003
3004 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3005 micro_min(&r[2], &r[2], &P128Vec);
3006 micro_max(&r[2], &r[2], &M128Vec);
3007 micro_pow(&r[1], &r[1], &r[2]);
3008 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3009 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3010 }
3011 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3012 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3013 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3014 }
3015 }
3016 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3017 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3018 }
3019
3020 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3021 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3022 }
3023 }
3024
3025 static void
3026 exec_break(struct tgsi_exec_machine *mach)
3027 {
3028 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3029 /* turn off loop channels for each enabled exec channel */
3030 mach->LoopMask &= ~mach->ExecMask;
3031 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3032 UPDATE_EXEC_MASK(mach);
3033 } else {
3034 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3035
3036 mach->Switch.mask = 0x0;
3037
3038 UPDATE_EXEC_MASK(mach);
3039 }
3040 }
3041
3042 static void
3043 exec_switch(struct tgsi_exec_machine *mach,
3044 const struct tgsi_full_instruction *inst)
3045 {
3046 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3047 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3048
3049 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3050 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3051 mach->Switch.mask = 0x0;
3052 mach->Switch.defaultMask = 0x0;
3053
3054 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3055 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3056
3057 UPDATE_EXEC_MASK(mach);
3058 }
3059
3060 static void
3061 exec_case(struct tgsi_exec_machine *mach,
3062 const struct tgsi_full_instruction *inst)
3063 {
3064 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3065 union tgsi_exec_channel src;
3066 uint mask = 0;
3067
3068 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3069
3070 if (mach->Switch.selector.u[0] == src.u[0]) {
3071 mask |= 0x1;
3072 }
3073 if (mach->Switch.selector.u[1] == src.u[1]) {
3074 mask |= 0x2;
3075 }
3076 if (mach->Switch.selector.u[2] == src.u[2]) {
3077 mask |= 0x4;
3078 }
3079 if (mach->Switch.selector.u[3] == src.u[3]) {
3080 mask |= 0x8;
3081 }
3082
3083 mach->Switch.defaultMask |= mask;
3084
3085 mach->Switch.mask |= mask & prevMask;
3086
3087 UPDATE_EXEC_MASK(mach);
3088 }
3089
3090 static void
3091 exec_default(struct tgsi_exec_machine *mach)
3092 {
3093 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3094
3095 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3096
3097 UPDATE_EXEC_MASK(mach);
3098 }
3099
3100 static void
3101 exec_endswitch(struct tgsi_exec_machine *mach)
3102 {
3103 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3104 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3105
3106 UPDATE_EXEC_MASK(mach);
3107 }
3108
3109 static void
3110 micro_i2f(union tgsi_exec_channel *dst,
3111 const union tgsi_exec_channel *src)
3112 {
3113 dst->f[0] = (float)src->i[0];
3114 dst->f[1] = (float)src->i[1];
3115 dst->f[2] = (float)src->i[2];
3116 dst->f[3] = (float)src->i[3];
3117 }
3118
3119 static void
3120 micro_not(union tgsi_exec_channel *dst,
3121 const union tgsi_exec_channel *src)
3122 {
3123 dst->u[0] = ~src->u[0];
3124 dst->u[1] = ~src->u[1];
3125 dst->u[2] = ~src->u[2];
3126 dst->u[3] = ~src->u[3];
3127 }
3128
3129 static void
3130 micro_shl(union tgsi_exec_channel *dst,
3131 const union tgsi_exec_channel *src0,
3132 const union tgsi_exec_channel *src1)
3133 {
3134 dst->u[0] = src0->u[0] << src1->u[0];
3135 dst->u[1] = src0->u[1] << src1->u[1];
3136 dst->u[2] = src0->u[2] << src1->u[2];
3137 dst->u[3] = src0->u[3] << src1->u[3];
3138 }
3139
3140 static void
3141 micro_and(union tgsi_exec_channel *dst,
3142 const union tgsi_exec_channel *src0,
3143 const union tgsi_exec_channel *src1)
3144 {
3145 dst->u[0] = src0->u[0] & src1->u[0];
3146 dst->u[1] = src0->u[1] & src1->u[1];
3147 dst->u[2] = src0->u[2] & src1->u[2];
3148 dst->u[3] = src0->u[3] & src1->u[3];
3149 }
3150
3151 static void
3152 micro_or(union tgsi_exec_channel *dst,
3153 const union tgsi_exec_channel *src0,
3154 const union tgsi_exec_channel *src1)
3155 {
3156 dst->u[0] = src0->u[0] | src1->u[0];
3157 dst->u[1] = src0->u[1] | src1->u[1];
3158 dst->u[2] = src0->u[2] | src1->u[2];
3159 dst->u[3] = src0->u[3] | src1->u[3];
3160 }
3161
3162 static void
3163 micro_xor(union tgsi_exec_channel *dst,
3164 const union tgsi_exec_channel *src0,
3165 const union tgsi_exec_channel *src1)
3166 {
3167 dst->u[0] = src0->u[0] ^ src1->u[0];
3168 dst->u[1] = src0->u[1] ^ src1->u[1];
3169 dst->u[2] = src0->u[2] ^ src1->u[2];
3170 dst->u[3] = src0->u[3] ^ src1->u[3];
3171 }
3172
3173 static void
3174 micro_mod(union tgsi_exec_channel *dst,
3175 const union tgsi_exec_channel *src0,
3176 const union tgsi_exec_channel *src1)
3177 {
3178 dst->i[0] = src0->i[0] % src1->i[0];
3179 dst->i[1] = src0->i[1] % src1->i[1];
3180 dst->i[2] = src0->i[2] % src1->i[2];
3181 dst->i[3] = src0->i[3] % src1->i[3];
3182 }
3183
3184 static void
3185 micro_f2i(union tgsi_exec_channel *dst,
3186 const union tgsi_exec_channel *src)
3187 {
3188 dst->i[0] = (int)src->f[0];
3189 dst->i[1] = (int)src->f[1];
3190 dst->i[2] = (int)src->f[2];
3191 dst->i[3] = (int)src->f[3];
3192 }
3193
3194 static void
3195 micro_idiv(union tgsi_exec_channel *dst,
3196 const union tgsi_exec_channel *src0,
3197 const union tgsi_exec_channel *src1)
3198 {
3199 dst->i[0] = src0->i[0] / src1->i[0];
3200 dst->i[1] = src0->i[1] / src1->i[1];
3201 dst->i[2] = src0->i[2] / src1->i[2];
3202 dst->i[3] = src0->i[3] / src1->i[3];
3203 }
3204
3205 static void
3206 micro_imax(union tgsi_exec_channel *dst,
3207 const union tgsi_exec_channel *src0,
3208 const union tgsi_exec_channel *src1)
3209 {
3210 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3211 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3212 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3213 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3214 }
3215
3216 static void
3217 micro_imin(union tgsi_exec_channel *dst,
3218 const union tgsi_exec_channel *src0,
3219 const union tgsi_exec_channel *src1)
3220 {
3221 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3222 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3223 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3224 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3225 }
3226
3227 static void
3228 micro_isge(union tgsi_exec_channel *dst,
3229 const union tgsi_exec_channel *src0,
3230 const union tgsi_exec_channel *src1)
3231 {
3232 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3233 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3234 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3235 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3236 }
3237
3238 static void
3239 micro_ishr(union tgsi_exec_channel *dst,
3240 const union tgsi_exec_channel *src0,
3241 const union tgsi_exec_channel *src1)
3242 {
3243 dst->i[0] = src0->i[0] >> src1->i[0];
3244 dst->i[1] = src0->i[1] >> src1->i[1];
3245 dst->i[2] = src0->i[2] >> src1->i[2];
3246 dst->i[3] = src0->i[3] >> src1->i[3];
3247 }
3248
3249 static void
3250 micro_islt(union tgsi_exec_channel *dst,
3251 const union tgsi_exec_channel *src0,
3252 const union tgsi_exec_channel *src1)
3253 {
3254 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3255 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3256 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3257 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3258 }
3259
3260 static void
3261 micro_f2u(union tgsi_exec_channel *dst,
3262 const union tgsi_exec_channel *src)
3263 {
3264 dst->u[0] = (uint)src->f[0];
3265 dst->u[1] = (uint)src->f[1];
3266 dst->u[2] = (uint)src->f[2];
3267 dst->u[3] = (uint)src->f[3];
3268 }
3269
3270 static void
3271 micro_u2f(union tgsi_exec_channel *dst,
3272 const union tgsi_exec_channel *src)
3273 {
3274 dst->f[0] = (float)src->u[0];
3275 dst->f[1] = (float)src->u[1];
3276 dst->f[2] = (float)src->u[2];
3277 dst->f[3] = (float)src->u[3];
3278 }
3279
3280 static void
3281 micro_uadd(union tgsi_exec_channel *dst,
3282 const union tgsi_exec_channel *src0,
3283 const union tgsi_exec_channel *src1)
3284 {
3285 dst->u[0] = src0->u[0] + src1->u[0];
3286 dst->u[1] = src0->u[1] + src1->u[1];
3287 dst->u[2] = src0->u[2] + src1->u[2];
3288 dst->u[3] = src0->u[3] + src1->u[3];
3289 }
3290
3291 static void
3292 micro_udiv(union tgsi_exec_channel *dst,
3293 const union tgsi_exec_channel *src0,
3294 const union tgsi_exec_channel *src1)
3295 {
3296 dst->u[0] = src0->u[0] / src1->u[0];
3297 dst->u[1] = src0->u[1] / src1->u[1];
3298 dst->u[2] = src0->u[2] / src1->u[2];
3299 dst->u[3] = src0->u[3] / src1->u[3];
3300 }
3301
3302 static void
3303 micro_umad(union tgsi_exec_channel *dst,
3304 const union tgsi_exec_channel *src0,
3305 const union tgsi_exec_channel *src1,
3306 const union tgsi_exec_channel *src2)
3307 {
3308 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3309 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3310 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3311 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3312 }
3313
3314 static void
3315 micro_umax(union tgsi_exec_channel *dst,
3316 const union tgsi_exec_channel *src0,
3317 const union tgsi_exec_channel *src1)
3318 {
3319 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3320 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3321 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3322 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3323 }
3324
3325 static void
3326 micro_umin(union tgsi_exec_channel *dst,
3327 const union tgsi_exec_channel *src0,
3328 const union tgsi_exec_channel *src1)
3329 {
3330 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3331 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3332 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3333 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3334 }
3335
3336 static void
3337 micro_umod(union tgsi_exec_channel *dst,
3338 const union tgsi_exec_channel *src0,
3339 const union tgsi_exec_channel *src1)
3340 {
3341 dst->u[0] = src0->u[0] % src1->u[0];
3342 dst->u[1] = src0->u[1] % src1->u[1];
3343 dst->u[2] = src0->u[2] % src1->u[2];
3344 dst->u[3] = src0->u[3] % src1->u[3];
3345 }
3346
3347 static void
3348 micro_umul(union tgsi_exec_channel *dst,
3349 const union tgsi_exec_channel *src0,
3350 const union tgsi_exec_channel *src1)
3351 {
3352 dst->u[0] = src0->u[0] * src1->u[0];
3353 dst->u[1] = src0->u[1] * src1->u[1];
3354 dst->u[2] = src0->u[2] * src1->u[2];
3355 dst->u[3] = src0->u[3] * src1->u[3];
3356 }
3357
3358 static void
3359 micro_useq(union tgsi_exec_channel *dst,
3360 const union tgsi_exec_channel *src0,
3361 const union tgsi_exec_channel *src1)
3362 {
3363 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3364 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3365 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3366 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3367 }
3368
3369 static void
3370 micro_usge(union tgsi_exec_channel *dst,
3371 const union tgsi_exec_channel *src0,
3372 const union tgsi_exec_channel *src1)
3373 {
3374 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3375 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3376 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3377 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3378 }
3379
3380 static void
3381 micro_ushr(union tgsi_exec_channel *dst,
3382 const union tgsi_exec_channel *src0,
3383 const union tgsi_exec_channel *src1)
3384 {
3385 dst->u[0] = src0->u[0] >> src1->u[0];
3386 dst->u[1] = src0->u[1] >> src1->u[1];
3387 dst->u[2] = src0->u[2] >> src1->u[2];
3388 dst->u[3] = src0->u[3] >> src1->u[3];
3389 }
3390
3391 static void
3392 micro_uslt(union tgsi_exec_channel *dst,
3393 const union tgsi_exec_channel *src0,
3394 const union tgsi_exec_channel *src1)
3395 {
3396 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3397 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3398 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3399 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3400 }
3401
3402 static void
3403 micro_usne(union tgsi_exec_channel *dst,
3404 const union tgsi_exec_channel *src0,
3405 const union tgsi_exec_channel *src1)
3406 {
3407 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3408 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3409 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3410 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3411 }
3412
3413 static void
3414 micro_uarl(union tgsi_exec_channel *dst,
3415 const union tgsi_exec_channel *src)
3416 {
3417 dst->i[0] = src->u[0];
3418 dst->i[1] = src->u[1];
3419 dst->i[2] = src->u[2];
3420 dst->i[3] = src->u[3];
3421 }
3422
3423 static void
3424 micro_ucmp(union tgsi_exec_channel *dst,
3425 const union tgsi_exec_channel *src0,
3426 const union tgsi_exec_channel *src1,
3427 const union tgsi_exec_channel *src2)
3428 {
3429 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3430 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3431 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3432 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3433 }
3434
3435 static void
3436 exec_instruction(
3437 struct tgsi_exec_machine *mach,
3438 const struct tgsi_full_instruction *inst,
3439 int *pc )
3440 {
3441 union tgsi_exec_channel r[10];
3442
3443 (*pc)++;
3444
3445 switch (inst->Instruction.Opcode) {
3446 case TGSI_OPCODE_ARL:
3447 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3448 break;
3449
3450 case TGSI_OPCODE_MOV:
3451 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3452 break;
3453
3454 case TGSI_OPCODE_LIT:
3455 exec_lit(mach, inst);
3456 break;
3457
3458 case TGSI_OPCODE_RCP:
3459 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3460 break;
3461
3462 case TGSI_OPCODE_RSQ:
3463 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3464 break;
3465
3466 case TGSI_OPCODE_EXP:
3467 exec_exp(mach, inst);
3468 break;
3469
3470 case TGSI_OPCODE_LOG:
3471 exec_log(mach, inst);
3472 break;
3473
3474 case TGSI_OPCODE_MUL:
3475 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3476 break;
3477
3478 case TGSI_OPCODE_ADD:
3479 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3480 break;
3481
3482 case TGSI_OPCODE_DP3:
3483 exec_dp3(mach, inst);
3484 break;
3485
3486 case TGSI_OPCODE_DP4:
3487 exec_dp4(mach, inst);
3488 break;
3489
3490 case TGSI_OPCODE_DST:
3491 exec_dst(mach, inst);
3492 break;
3493
3494 case TGSI_OPCODE_MIN:
3495 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3496 break;
3497
3498 case TGSI_OPCODE_MAX:
3499 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3500 break;
3501
3502 case TGSI_OPCODE_SLT:
3503 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3504 break;
3505
3506 case TGSI_OPCODE_SGE:
3507 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3508 break;
3509
3510 case TGSI_OPCODE_MAD:
3511 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3512 break;
3513
3514 case TGSI_OPCODE_SUB:
3515 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3516 break;
3517
3518 case TGSI_OPCODE_LRP:
3519 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3520 break;
3521
3522 case TGSI_OPCODE_CND:
3523 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3524 break;
3525
3526 case TGSI_OPCODE_DP2A:
3527 exec_dp2a(mach, inst);
3528 break;
3529
3530 case TGSI_OPCODE_FRC:
3531 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3532 break;
3533
3534 case TGSI_OPCODE_CLAMP:
3535 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3536 break;
3537
3538 case TGSI_OPCODE_FLR:
3539 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3540 break;
3541
3542 case TGSI_OPCODE_ROUND:
3543 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3544 break;
3545
3546 case TGSI_OPCODE_EX2:
3547 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3548 break;
3549
3550 case TGSI_OPCODE_LG2:
3551 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3552 break;
3553
3554 case TGSI_OPCODE_POW:
3555 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3556 break;
3557
3558 case TGSI_OPCODE_XPD:
3559 exec_xpd(mach, inst);
3560 break;
3561
3562 case TGSI_OPCODE_ABS:
3563 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3564 break;
3565
3566 case TGSI_OPCODE_RCC:
3567 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3568 break;
3569
3570 case TGSI_OPCODE_DPH:
3571 exec_dph(mach, inst);
3572 break;
3573
3574 case TGSI_OPCODE_COS:
3575 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3576 break;
3577
3578 case TGSI_OPCODE_DDX:
3579 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3580 break;
3581
3582 case TGSI_OPCODE_DDY:
3583 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3584 break;
3585
3586 case TGSI_OPCODE_KILP:
3587 exec_kilp (mach, inst);
3588 break;
3589
3590 case TGSI_OPCODE_KIL:
3591 exec_kil (mach, inst);
3592 break;
3593
3594 case TGSI_OPCODE_PK2H:
3595 assert (0);
3596 break;
3597
3598 case TGSI_OPCODE_PK2US:
3599 assert (0);
3600 break;
3601
3602 case TGSI_OPCODE_PK4B:
3603 assert (0);
3604 break;
3605
3606 case TGSI_OPCODE_PK4UB:
3607 assert (0);
3608 break;
3609
3610 case TGSI_OPCODE_RFL:
3611 exec_rfl(mach, inst);
3612 break;
3613
3614 case TGSI_OPCODE_SEQ:
3615 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3616 break;
3617
3618 case TGSI_OPCODE_SFL:
3619 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3620 break;
3621
3622 case TGSI_OPCODE_SGT:
3623 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3624 break;
3625
3626 case TGSI_OPCODE_SIN:
3627 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3628 break;
3629
3630 case TGSI_OPCODE_SLE:
3631 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3632 break;
3633
3634 case TGSI_OPCODE_SNE:
3635 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3636 break;
3637
3638 case TGSI_OPCODE_STR:
3639 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3640 break;
3641
3642 case TGSI_OPCODE_TEX:
3643 /* simple texture lookup */
3644 /* src[0] = texcoord */
3645 /* src[1] = sampler unit */
3646 exec_tex(mach, inst, TEX_MODIFIER_NONE);
3647 break;
3648
3649 case TGSI_OPCODE_TXB:
3650 /* Texture lookup with lod bias */
3651 /* src[0] = texcoord (src[0].w = LOD bias) */
3652 /* src[1] = sampler unit */
3653 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS);
3654 break;
3655
3656 case TGSI_OPCODE_TXD:
3657 /* Texture lookup with explict partial derivatives */
3658 /* src[0] = texcoord */
3659 /* src[1] = d[strq]/dx */
3660 /* src[2] = d[strq]/dy */
3661 /* src[3] = sampler unit */
3662 exec_txd(mach, inst);
3663 break;
3664
3665 case TGSI_OPCODE_TXL:
3666 /* Texture lookup with explit LOD */
3667 /* src[0] = texcoord (src[0].w = LOD) */
3668 /* src[1] = sampler unit */
3669 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
3670 break;
3671
3672 case TGSI_OPCODE_TXP:
3673 /* Texture lookup with projection */
3674 /* src[0] = texcoord (src[0].w = projection) */
3675 /* src[1] = sampler unit */
3676 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED);
3677 break;
3678
3679 case TGSI_OPCODE_UP2H:
3680 assert (0);
3681 break;
3682
3683 case TGSI_OPCODE_UP2US:
3684 assert (0);
3685 break;
3686
3687 case TGSI_OPCODE_UP4B:
3688 assert (0);
3689 break;
3690
3691 case TGSI_OPCODE_UP4UB:
3692 assert (0);
3693 break;
3694
3695 case TGSI_OPCODE_X2D:
3696 exec_x2d(mach, inst);
3697 break;
3698
3699 case TGSI_OPCODE_ARA:
3700 assert (0);
3701 break;
3702
3703 case TGSI_OPCODE_ARR:
3704 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3705 break;
3706
3707 case TGSI_OPCODE_BRA:
3708 assert (0);
3709 break;
3710
3711 case TGSI_OPCODE_CAL:
3712 /* skip the call if no execution channels are enabled */
3713 if (mach->ExecMask) {
3714 /* do the call */
3715
3716 /* First, record the depths of the execution stacks.
3717 * This is important for deeply nested/looped return statements.
3718 * We have to unwind the stacks by the correct amount. For a
3719 * real code generator, we could determine the number of entries
3720 * to pop off each stack with simple static analysis and avoid
3721 * implementing this data structure at run time.
3722 */
3723 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3724 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3725 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3726 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3727 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3728 /* note that PC was already incremented above */
3729 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3730
3731 mach->CallStackTop++;
3732
3733 /* Second, push the Cond, Loop, Cont, Func stacks */
3734 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3735 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3736 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3737 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3738 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3739 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3740
3741 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3742 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3743 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3744 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3745 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3746 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3747
3748 /* Finally, jump to the subroutine */
3749 *pc = inst->Label.Label;
3750 }
3751 break;
3752
3753 case TGSI_OPCODE_RET:
3754 mach->FuncMask &= ~mach->ExecMask;
3755 UPDATE_EXEC_MASK(mach);
3756
3757 if (mach->FuncMask == 0x0) {
3758 /* really return now (otherwise, keep executing */
3759
3760 if (mach->CallStackTop == 0) {
3761 /* returning from main() */
3762 mach->CondStackTop = 0;
3763 mach->LoopStackTop = 0;
3764 *pc = -1;
3765 return;
3766 }
3767
3768 assert(mach->CallStackTop > 0);
3769 mach->CallStackTop--;
3770
3771 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3772 mach->CondMask = mach->CondStack[mach->CondStackTop];
3773
3774 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3775 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3776
3777 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3778 mach->ContMask = mach->ContStack[mach->ContStackTop];
3779
3780 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3781 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3782
3783 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3784 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3785
3786 assert(mach->FuncStackTop > 0);
3787 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3788
3789 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3790
3791 UPDATE_EXEC_MASK(mach);
3792 }
3793 break;
3794
3795 case TGSI_OPCODE_SSG:
3796 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3797 break;
3798
3799 case TGSI_OPCODE_CMP:
3800 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3801 break;
3802
3803 case TGSI_OPCODE_SCS:
3804 exec_scs(mach, inst);
3805 break;
3806
3807 case TGSI_OPCODE_NRM:
3808 exec_nrm3(mach, inst);
3809 break;
3810
3811 case TGSI_OPCODE_NRM4:
3812 exec_nrm4(mach, inst);
3813 break;
3814
3815 case TGSI_OPCODE_DIV:
3816 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3817 break;
3818
3819 case TGSI_OPCODE_DP2:
3820 exec_dp2(mach, inst);
3821 break;
3822
3823 case TGSI_OPCODE_IF:
3824 /* push CondMask */
3825 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3826 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3827 FETCH( &r[0], 0, TGSI_CHAN_X );
3828 /* update CondMask */
3829 if( ! r[0].u[0] ) {
3830 mach->CondMask &= ~0x1;
3831 }
3832 if( ! r[0].u[1] ) {
3833 mach->CondMask &= ~0x2;
3834 }
3835 if( ! r[0].u[2] ) {
3836 mach->CondMask &= ~0x4;
3837 }
3838 if( ! r[0].u[3] ) {
3839 mach->CondMask &= ~0x8;
3840 }
3841 UPDATE_EXEC_MASK(mach);
3842 /* Todo: If CondMask==0, jump to ELSE */
3843 break;
3844
3845 case TGSI_OPCODE_ELSE:
3846 /* invert CondMask wrt previous mask */
3847 {
3848 uint prevMask;
3849 assert(mach->CondStackTop > 0);
3850 prevMask = mach->CondStack[mach->CondStackTop - 1];
3851 mach->CondMask = ~mach->CondMask & prevMask;
3852 UPDATE_EXEC_MASK(mach);
3853 /* Todo: If CondMask==0, jump to ENDIF */
3854 }
3855 break;
3856
3857 case TGSI_OPCODE_ENDIF:
3858 /* pop CondMask */
3859 assert(mach->CondStackTop > 0);
3860 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3861 UPDATE_EXEC_MASK(mach);
3862 break;
3863
3864 case TGSI_OPCODE_END:
3865 /* make sure we end primitives which haven't
3866 * been explicitly emitted */
3867 conditional_emit_primitive(mach);
3868 /* halt execution */
3869 *pc = -1;
3870 break;
3871
3872 case TGSI_OPCODE_PUSHA:
3873 assert (0);
3874 break;
3875
3876 case TGSI_OPCODE_POPA:
3877 assert (0);
3878 break;
3879
3880 case TGSI_OPCODE_CEIL:
3881 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3882 break;
3883
3884 case TGSI_OPCODE_I2F:
3885 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3886 break;
3887
3888 case TGSI_OPCODE_NOT:
3889 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3890 break;
3891
3892 case TGSI_OPCODE_TRUNC:
3893 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3894 break;
3895
3896 case TGSI_OPCODE_SHL:
3897 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3898 break;
3899
3900 case TGSI_OPCODE_AND:
3901 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3902 break;
3903
3904 case TGSI_OPCODE_OR:
3905 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3906 break;
3907
3908 case TGSI_OPCODE_MOD:
3909 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3910 break;
3911
3912 case TGSI_OPCODE_XOR:
3913 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3914 break;
3915
3916 case TGSI_OPCODE_SAD:
3917 assert (0);
3918 break;
3919
3920 case TGSI_OPCODE_TXF:
3921 exec_txf(mach, inst);
3922 break;
3923
3924 case TGSI_OPCODE_TXQ:
3925 exec_txq(mach, inst);
3926 break;
3927
3928 case TGSI_OPCODE_EMIT:
3929 emit_vertex(mach);
3930 break;
3931
3932 case TGSI_OPCODE_ENDPRIM:
3933 emit_primitive(mach);
3934 break;
3935
3936 case TGSI_OPCODE_BGNLOOP:
3937 /* push LoopMask and ContMasks */
3938 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3939 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3940 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3941 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3942
3943 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3944 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3945 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3946 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3947 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3948 break;
3949
3950 case TGSI_OPCODE_ENDLOOP:
3951 /* Restore ContMask, but don't pop */
3952 assert(mach->ContStackTop > 0);
3953 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3954 UPDATE_EXEC_MASK(mach);
3955 if (mach->ExecMask) {
3956 /* repeat loop: jump to instruction just past BGNLOOP */
3957 assert(mach->LoopLabelStackTop > 0);
3958 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3959 }
3960 else {
3961 /* exit loop: pop LoopMask */
3962 assert(mach->LoopStackTop > 0);
3963 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3964 /* pop ContMask */
3965 assert(mach->ContStackTop > 0);
3966 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3967 assert(mach->LoopLabelStackTop > 0);
3968 --mach->LoopLabelStackTop;
3969
3970 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3971 }
3972 UPDATE_EXEC_MASK(mach);
3973 break;
3974
3975 case TGSI_OPCODE_BRK:
3976 exec_break(mach);
3977 break;
3978
3979 case TGSI_OPCODE_CONT:
3980 /* turn off cont channels for each enabled exec channel */
3981 mach->ContMask &= ~mach->ExecMask;
3982 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3983 UPDATE_EXEC_MASK(mach);
3984 break;
3985
3986 case TGSI_OPCODE_BGNSUB:
3987 /* no-op */
3988 break;
3989
3990 case TGSI_OPCODE_ENDSUB:
3991 /*
3992 * XXX: This really should be a no-op. We should never reach this opcode.
3993 */
3994
3995 assert(mach->CallStackTop > 0);
3996 mach->CallStackTop--;
3997
3998 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3999 mach->CondMask = mach->CondStack[mach->CondStackTop];
4000
4001 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4002 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4003
4004 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4005 mach->ContMask = mach->ContStack[mach->ContStackTop];
4006
4007 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4008 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4009
4010 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4011 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4012
4013 assert(mach->FuncStackTop > 0);
4014 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4015
4016 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4017
4018 UPDATE_EXEC_MASK(mach);
4019 break;
4020
4021 case TGSI_OPCODE_NOP:
4022 break;
4023
4024 case TGSI_OPCODE_BREAKC:
4025 FETCH(&r[0], 0, TGSI_CHAN_X);
4026 /* update CondMask */
4027 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4028 mach->LoopMask &= ~0x1;
4029 }
4030 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4031 mach->LoopMask &= ~0x2;
4032 }
4033 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4034 mach->LoopMask &= ~0x4;
4035 }
4036 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4037 mach->LoopMask &= ~0x8;
4038 }
4039 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4040 UPDATE_EXEC_MASK(mach);
4041 break;
4042
4043 case TGSI_OPCODE_F2I:
4044 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4045 break;
4046
4047 case TGSI_OPCODE_IDIV:
4048 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4049 break;
4050
4051 case TGSI_OPCODE_IMAX:
4052 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4053 break;
4054
4055 case TGSI_OPCODE_IMIN:
4056 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4057 break;
4058
4059 case TGSI_OPCODE_INEG:
4060 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4061 break;
4062
4063 case TGSI_OPCODE_ISGE:
4064 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4065 break;
4066
4067 case TGSI_OPCODE_ISHR:
4068 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4069 break;
4070
4071 case TGSI_OPCODE_ISLT:
4072 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4073 break;
4074
4075 case TGSI_OPCODE_F2U:
4076 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4077 break;
4078
4079 case TGSI_OPCODE_U2F:
4080 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4081 break;
4082
4083 case TGSI_OPCODE_UADD:
4084 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4085 break;
4086
4087 case TGSI_OPCODE_UDIV:
4088 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4089 break;
4090
4091 case TGSI_OPCODE_UMAD:
4092 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4093 break;
4094
4095 case TGSI_OPCODE_UMAX:
4096 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4097 break;
4098
4099 case TGSI_OPCODE_UMIN:
4100 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4101 break;
4102
4103 case TGSI_OPCODE_UMOD:
4104 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4105 break;
4106
4107 case TGSI_OPCODE_UMUL:
4108 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4109 break;
4110
4111 case TGSI_OPCODE_USEQ:
4112 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4113 break;
4114
4115 case TGSI_OPCODE_USGE:
4116 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4117 break;
4118
4119 case TGSI_OPCODE_USHR:
4120 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4121 break;
4122
4123 case TGSI_OPCODE_USLT:
4124 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4125 break;
4126
4127 case TGSI_OPCODE_USNE:
4128 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4129 break;
4130
4131 case TGSI_OPCODE_SWITCH:
4132 exec_switch(mach, inst);
4133 break;
4134
4135 case TGSI_OPCODE_CASE:
4136 exec_case(mach, inst);
4137 break;
4138
4139 case TGSI_OPCODE_DEFAULT:
4140 exec_default(mach);
4141 break;
4142
4143 case TGSI_OPCODE_ENDSWITCH:
4144 exec_endswitch(mach);
4145 break;
4146
4147 case TGSI_OPCODE_SAMPLE_I:
4148 assert(0);
4149 break;
4150
4151 case TGSI_OPCODE_SAMPLE_I_MS:
4152 assert(0);
4153 break;
4154
4155 case TGSI_OPCODE_SAMPLE:
4156 exec_sample(mach, inst, TEX_MODIFIER_NONE);
4157 break;
4158
4159 case TGSI_OPCODE_SAMPLE_B:
4160 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS);
4161 break;
4162
4163 case TGSI_OPCODE_SAMPLE_C:
4164 exec_sample(mach, inst, TEX_MODIFIER_NONE);
4165 break;
4166
4167 case TGSI_OPCODE_SAMPLE_C_LZ:
4168 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS);
4169 break;
4170
4171 case TGSI_OPCODE_SAMPLE_D:
4172 exec_sample_d(mach, inst);
4173 break;
4174
4175 case TGSI_OPCODE_SAMPLE_L:
4176 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
4177 break;
4178
4179 case TGSI_OPCODE_GATHER4:
4180 assert(0);
4181 break;
4182
4183 case TGSI_OPCODE_SVIEWINFO:
4184 assert(0);
4185 break;
4186
4187 case TGSI_OPCODE_SAMPLE_POS:
4188 assert(0);
4189 break;
4190
4191 case TGSI_OPCODE_SAMPLE_INFO:
4192 assert(0);
4193 break;
4194
4195 case TGSI_OPCODE_UARL:
4196 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4197 break;
4198
4199 case TGSI_OPCODE_UCMP:
4200 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4201 break;
4202
4203 case TGSI_OPCODE_IABS:
4204 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4205 break;
4206
4207 case TGSI_OPCODE_ISSG:
4208 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4209 break;
4210
4211 default:
4212 assert( 0 );
4213 }
4214 }
4215
4216
4217 #define DEBUG_EXECUTION 0
4218
4219
4220 /**
4221 * Run TGSI interpreter.
4222 * \return bitmask of "alive" quad components
4223 */
4224 uint
4225 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4226 {
4227 uint i;
4228 int pc = 0;
4229
4230 mach->CondMask = 0xf;
4231 mach->LoopMask = 0xf;
4232 mach->ContMask = 0xf;
4233 mach->FuncMask = 0xf;
4234 mach->ExecMask = 0xf;
4235
4236 mach->Switch.mask = 0xf;
4237
4238 assert(mach->CondStackTop == 0);
4239 assert(mach->LoopStackTop == 0);
4240 assert(mach->ContStackTop == 0);
4241 assert(mach->SwitchStackTop == 0);
4242 assert(mach->BreakStackTop == 0);
4243 assert(mach->CallStackTop == 0);
4244
4245 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4246 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4247
4248 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4249 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4250 mach->Primitives[0] = 0;
4251 }
4252
4253 /* execute declarations (interpolants) */
4254 for (i = 0; i < mach->NumDeclarations; i++) {
4255 exec_declaration( mach, mach->Declarations+i );
4256 }
4257
4258 {
4259 #if DEBUG_EXECUTION
4260 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4261 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4262 uint inst = 1;
4263
4264 memcpy(temps, mach->Temps, sizeof(temps));
4265 memcpy(outputs, mach->Outputs, sizeof(outputs));
4266 #endif
4267
4268 /* execute instructions, until pc is set to -1 */
4269 while (pc != -1) {
4270
4271 #if DEBUG_EXECUTION
4272 uint i;
4273
4274 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4275 #endif
4276
4277 assert(pc < (int) mach->NumInstructions);
4278 exec_instruction(mach, mach->Instructions + pc, &pc);
4279
4280 #if DEBUG_EXECUTION
4281 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4282 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4283 uint j;
4284
4285 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4286 debug_printf("TEMP[%2u] = ", i);
4287 for (j = 0; j < 4; j++) {
4288 if (j > 0) {
4289 debug_printf(" ");
4290 }
4291 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4292 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4293 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4294 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4295 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4296 }
4297 }
4298 }
4299 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4300 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4301 uint j;
4302
4303 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4304 debug_printf("OUT[%2u] = ", i);
4305 for (j = 0; j < 4; j++) {
4306 if (j > 0) {
4307 debug_printf(" ");
4308 }
4309 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4310 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4311 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4312 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4313 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4314 }
4315 }
4316 }
4317 #endif
4318 }
4319 }
4320
4321 #if 0
4322 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4323 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4324 /*
4325 * Scale back depth component.
4326 */
4327 for (i = 0; i < 4; i++)
4328 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4329 }
4330 #endif
4331
4332 /* Strictly speaking, these assertions aren't really needed but they
4333 * can potentially catch some bugs in the control flow code.
4334 */
4335 assert(mach->CondStackTop == 0);
4336 assert(mach->LoopStackTop == 0);
4337 assert(mach->ContStackTop == 0);
4338 assert(mach->SwitchStackTop == 0);
4339 assert(mach->BreakStackTop == 0);
4340 assert(mach->CallStackTop == 0);
4341
4342 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4343 }