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tgsi: add tgsi_exec support for new bit manipulation opcodes
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define DEBUG_EXECUTION 0
66
67
68 #define FAST_MATH 0
69
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
74
75 static void
76 micro_abs(union tgsi_exec_channel *dst,
77 const union tgsi_exec_channel *src)
78 {
79 dst->f[0] = fabsf(src->f[0]);
80 dst->f[1] = fabsf(src->f[1]);
81 dst->f[2] = fabsf(src->f[2]);
82 dst->f[3] = fabsf(src->f[3]);
83 }
84
85 static void
86 micro_arl(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
88 {
89 dst->i[0] = (int)floorf(src->f[0]);
90 dst->i[1] = (int)floorf(src->f[1]);
91 dst->i[2] = (int)floorf(src->f[2]);
92 dst->i[3] = (int)floorf(src->f[3]);
93 }
94
95 static void
96 micro_arr(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
98 {
99 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
100 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
101 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
102 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
103 }
104
105 static void
106 micro_ceil(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
108 {
109 dst->f[0] = ceilf(src->f[0]);
110 dst->f[1] = ceilf(src->f[1]);
111 dst->f[2] = ceilf(src->f[2]);
112 dst->f[3] = ceilf(src->f[3]);
113 }
114
115 static void
116 micro_clamp(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src0,
118 const union tgsi_exec_channel *src1,
119 const union tgsi_exec_channel *src2)
120 {
121 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
122 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
123 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
124 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
125 }
126
127 static void
128 micro_cmp(union tgsi_exec_channel *dst,
129 const union tgsi_exec_channel *src0,
130 const union tgsi_exec_channel *src1,
131 const union tgsi_exec_channel *src2)
132 {
133 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
134 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
135 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
136 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
137 }
138
139 static void
140 micro_cnd(union tgsi_exec_channel *dst,
141 const union tgsi_exec_channel *src0,
142 const union tgsi_exec_channel *src1,
143 const union tgsi_exec_channel *src2)
144 {
145 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
146 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
147 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
148 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
149 }
150
151 static void
152 micro_cos(union tgsi_exec_channel *dst,
153 const union tgsi_exec_channel *src)
154 {
155 dst->f[0] = cosf(src->f[0]);
156 dst->f[1] = cosf(src->f[1]);
157 dst->f[2] = cosf(src->f[2]);
158 dst->f[3] = cosf(src->f[3]);
159 }
160
161 static void
162 micro_ddx(union tgsi_exec_channel *dst,
163 const union tgsi_exec_channel *src)
164 {
165 dst->f[0] =
166 dst->f[1] =
167 dst->f[2] =
168 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
169 }
170
171 static void
172 micro_ddy(union tgsi_exec_channel *dst,
173 const union tgsi_exec_channel *src)
174 {
175 dst->f[0] =
176 dst->f[1] =
177 dst->f[2] =
178 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
179 }
180
181 static void
182 micro_exp2(union tgsi_exec_channel *dst,
183 const union tgsi_exec_channel *src)
184 {
185 #if FAST_MATH
186 dst->f[0] = util_fast_exp2(src->f[0]);
187 dst->f[1] = util_fast_exp2(src->f[1]);
188 dst->f[2] = util_fast_exp2(src->f[2]);
189 dst->f[3] = util_fast_exp2(src->f[3]);
190 #else
191 #if DEBUG
192 /* Inf is okay for this instruction, so clamp it to silence assertions. */
193 uint i;
194 union tgsi_exec_channel clamped;
195
196 for (i = 0; i < 4; i++) {
197 if (src->f[i] > 127.99999f) {
198 clamped.f[i] = 127.99999f;
199 } else if (src->f[i] < -126.99999f) {
200 clamped.f[i] = -126.99999f;
201 } else {
202 clamped.f[i] = src->f[i];
203 }
204 }
205 src = &clamped;
206 #endif /* DEBUG */
207
208 dst->f[0] = powf(2.0f, src->f[0]);
209 dst->f[1] = powf(2.0f, src->f[1]);
210 dst->f[2] = powf(2.0f, src->f[2]);
211 dst->f[3] = powf(2.0f, src->f[3]);
212 #endif /* FAST_MATH */
213 }
214
215 static void
216 micro_flr(union tgsi_exec_channel *dst,
217 const union tgsi_exec_channel *src)
218 {
219 dst->f[0] = floorf(src->f[0]);
220 dst->f[1] = floorf(src->f[1]);
221 dst->f[2] = floorf(src->f[2]);
222 dst->f[3] = floorf(src->f[3]);
223 }
224
225 static void
226 micro_frc(union tgsi_exec_channel *dst,
227 const union tgsi_exec_channel *src)
228 {
229 dst->f[0] = src->f[0] - floorf(src->f[0]);
230 dst->f[1] = src->f[1] - floorf(src->f[1]);
231 dst->f[2] = src->f[2] - floorf(src->f[2]);
232 dst->f[3] = src->f[3] - floorf(src->f[3]);
233 }
234
235 static void
236 micro_iabs(union tgsi_exec_channel *dst,
237 const union tgsi_exec_channel *src)
238 {
239 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
240 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
241 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
242 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
243 }
244
245 static void
246 micro_ineg(union tgsi_exec_channel *dst,
247 const union tgsi_exec_channel *src)
248 {
249 dst->i[0] = -src->i[0];
250 dst->i[1] = -src->i[1];
251 dst->i[2] = -src->i[2];
252 dst->i[3] = -src->i[3];
253 }
254
255 static void
256 micro_lg2(union tgsi_exec_channel *dst,
257 const union tgsi_exec_channel *src)
258 {
259 #if FAST_MATH
260 dst->f[0] = util_fast_log2(src->f[0]);
261 dst->f[1] = util_fast_log2(src->f[1]);
262 dst->f[2] = util_fast_log2(src->f[2]);
263 dst->f[3] = util_fast_log2(src->f[3]);
264 #else
265 dst->f[0] = logf(src->f[0]) * 1.442695f;
266 dst->f[1] = logf(src->f[1]) * 1.442695f;
267 dst->f[2] = logf(src->f[2]) * 1.442695f;
268 dst->f[3] = logf(src->f[3]) * 1.442695f;
269 #endif
270 }
271
272 static void
273 micro_lrp(union tgsi_exec_channel *dst,
274 const union tgsi_exec_channel *src0,
275 const union tgsi_exec_channel *src1,
276 const union tgsi_exec_channel *src2)
277 {
278 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
279 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
280 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
281 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
282 }
283
284 static void
285 micro_mad(union tgsi_exec_channel *dst,
286 const union tgsi_exec_channel *src0,
287 const union tgsi_exec_channel *src1,
288 const union tgsi_exec_channel *src2)
289 {
290 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
291 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
292 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
293 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
294 }
295
296 static void
297 micro_mov(union tgsi_exec_channel *dst,
298 const union tgsi_exec_channel *src)
299 {
300 dst->u[0] = src->u[0];
301 dst->u[1] = src->u[1];
302 dst->u[2] = src->u[2];
303 dst->u[3] = src->u[3];
304 }
305
306 static void
307 micro_rcp(union tgsi_exec_channel *dst,
308 const union tgsi_exec_channel *src)
309 {
310 #if 0 /* for debugging */
311 assert(src->f[0] != 0.0f);
312 assert(src->f[1] != 0.0f);
313 assert(src->f[2] != 0.0f);
314 assert(src->f[3] != 0.0f);
315 #endif
316 dst->f[0] = 1.0f / src->f[0];
317 dst->f[1] = 1.0f / src->f[1];
318 dst->f[2] = 1.0f / src->f[2];
319 dst->f[3] = 1.0f / src->f[3];
320 }
321
322 static void
323 micro_rnd(union tgsi_exec_channel *dst,
324 const union tgsi_exec_channel *src)
325 {
326 dst->f[0] = floorf(src->f[0] + 0.5f);
327 dst->f[1] = floorf(src->f[1] + 0.5f);
328 dst->f[2] = floorf(src->f[2] + 0.5f);
329 dst->f[3] = floorf(src->f[3] + 0.5f);
330 }
331
332 static void
333 micro_rsq(union tgsi_exec_channel *dst,
334 const union tgsi_exec_channel *src)
335 {
336 #if 0 /* for debugging */
337 assert(src->f[0] != 0.0f);
338 assert(src->f[1] != 0.0f);
339 assert(src->f[2] != 0.0f);
340 assert(src->f[3] != 0.0f);
341 #endif
342 dst->f[0] = 1.0f / sqrtf(src->f[0]);
343 dst->f[1] = 1.0f / sqrtf(src->f[1]);
344 dst->f[2] = 1.0f / sqrtf(src->f[2]);
345 dst->f[3] = 1.0f / sqrtf(src->f[3]);
346 }
347
348 static void
349 micro_sqrt(union tgsi_exec_channel *dst,
350 const union tgsi_exec_channel *src)
351 {
352 dst->f[0] = sqrtf(src->f[0]);
353 dst->f[1] = sqrtf(src->f[1]);
354 dst->f[2] = sqrtf(src->f[2]);
355 dst->f[3] = sqrtf(src->f[3]);
356 }
357
358 static void
359 micro_seq(union tgsi_exec_channel *dst,
360 const union tgsi_exec_channel *src0,
361 const union tgsi_exec_channel *src1)
362 {
363 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
364 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
365 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
366 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
367 }
368
369 static void
370 micro_sge(union tgsi_exec_channel *dst,
371 const union tgsi_exec_channel *src0,
372 const union tgsi_exec_channel *src1)
373 {
374 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
375 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
376 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
377 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
378 }
379
380 static void
381 micro_sgn(union tgsi_exec_channel *dst,
382 const union tgsi_exec_channel *src)
383 {
384 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
385 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
386 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
387 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
388 }
389
390 static void
391 micro_isgn(union tgsi_exec_channel *dst,
392 const union tgsi_exec_channel *src)
393 {
394 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
395 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
396 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
397 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
398 }
399
400 static void
401 micro_sgt(union tgsi_exec_channel *dst,
402 const union tgsi_exec_channel *src0,
403 const union tgsi_exec_channel *src1)
404 {
405 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
406 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
407 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
408 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
409 }
410
411 static void
412 micro_sin(union tgsi_exec_channel *dst,
413 const union tgsi_exec_channel *src)
414 {
415 dst->f[0] = sinf(src->f[0]);
416 dst->f[1] = sinf(src->f[1]);
417 dst->f[2] = sinf(src->f[2]);
418 dst->f[3] = sinf(src->f[3]);
419 }
420
421 static void
422 micro_sle(union tgsi_exec_channel *dst,
423 const union tgsi_exec_channel *src0,
424 const union tgsi_exec_channel *src1)
425 {
426 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
427 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
428 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
429 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
430 }
431
432 static void
433 micro_slt(union tgsi_exec_channel *dst,
434 const union tgsi_exec_channel *src0,
435 const union tgsi_exec_channel *src1)
436 {
437 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
438 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
439 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
440 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
441 }
442
443 static void
444 micro_sne(union tgsi_exec_channel *dst,
445 const union tgsi_exec_channel *src0,
446 const union tgsi_exec_channel *src1)
447 {
448 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
449 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
450 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
451 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
452 }
453
454 static void
455 micro_sfl(union tgsi_exec_channel *dst)
456 {
457 dst->f[0] = 0.0f;
458 dst->f[1] = 0.0f;
459 dst->f[2] = 0.0f;
460 dst->f[3] = 0.0f;
461 }
462
463 static void
464 micro_str(union tgsi_exec_channel *dst)
465 {
466 dst->f[0] = 1.0f;
467 dst->f[1] = 1.0f;
468 dst->f[2] = 1.0f;
469 dst->f[3] = 1.0f;
470 }
471
472 static void
473 micro_trunc(union tgsi_exec_channel *dst,
474 const union tgsi_exec_channel *src)
475 {
476 dst->f[0] = (float)(int)src->f[0];
477 dst->f[1] = (float)(int)src->f[1];
478 dst->f[2] = (float)(int)src->f[2];
479 dst->f[3] = (float)(int)src->f[3];
480 }
481
482
483 enum tgsi_exec_datatype {
484 TGSI_EXEC_DATA_FLOAT,
485 TGSI_EXEC_DATA_INT,
486 TGSI_EXEC_DATA_UINT
487 };
488
489 /*
490 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
491 */
492 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
493 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
494 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
495 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
496 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
497 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
498
499
500 /** The execution mask depends on the conditional mask and the loop mask */
501 #define UPDATE_EXEC_MASK(MACH) \
502 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
503
504
505 static const union tgsi_exec_channel ZeroVec =
506 { { 0.0, 0.0, 0.0, 0.0 } };
507
508 static const union tgsi_exec_channel OneVec = {
509 {1.0f, 1.0f, 1.0f, 1.0f}
510 };
511
512 static const union tgsi_exec_channel P128Vec = {
513 {128.0f, 128.0f, 128.0f, 128.0f}
514 };
515
516 static const union tgsi_exec_channel M128Vec = {
517 {-128.0f, -128.0f, -128.0f, -128.0f}
518 };
519
520
521 /**
522 * Assert that none of the float values in 'chan' are infinite or NaN.
523 * NaN and Inf may occur normally during program execution and should
524 * not lead to crashes, etc. But when debugging, it's helpful to catch
525 * them.
526 */
527 static INLINE void
528 check_inf_or_nan(const union tgsi_exec_channel *chan)
529 {
530 assert(!util_is_inf_or_nan((chan)->f[0]));
531 assert(!util_is_inf_or_nan((chan)->f[1]));
532 assert(!util_is_inf_or_nan((chan)->f[2]));
533 assert(!util_is_inf_or_nan((chan)->f[3]));
534 }
535
536
537 #ifdef DEBUG
538 static void
539 print_chan(const char *msg, const union tgsi_exec_channel *chan)
540 {
541 debug_printf("%s = {%f, %f, %f, %f}\n",
542 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
543 }
544 #endif
545
546
547 #ifdef DEBUG
548 static void
549 print_temp(const struct tgsi_exec_machine *mach, uint index)
550 {
551 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
552 int i;
553 debug_printf("Temp[%u] =\n", index);
554 for (i = 0; i < 4; i++) {
555 debug_printf(" %c: { %f, %f, %f, %f }\n",
556 "XYZW"[i],
557 tmp->xyzw[i].f[0],
558 tmp->xyzw[i].f[1],
559 tmp->xyzw[i].f[2],
560 tmp->xyzw[i].f[3]);
561 }
562 }
563 #endif
564
565
566 void
567 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
568 unsigned num_bufs,
569 const void **bufs,
570 const unsigned *buf_sizes)
571 {
572 unsigned i;
573
574 for (i = 0; i < num_bufs; i++) {
575 mach->Consts[i] = bufs[i];
576 mach->ConstsSize[i] = buf_sizes[i];
577 }
578 }
579
580
581 /**
582 * Check if there's a potential src/dst register data dependency when
583 * using SOA execution.
584 * Example:
585 * MOV T, T.yxwz;
586 * This would expand into:
587 * MOV t0, t1;
588 * MOV t1, t0;
589 * MOV t2, t3;
590 * MOV t3, t2;
591 * The second instruction will have the wrong value for t0 if executed as-is.
592 */
593 boolean
594 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
595 {
596 uint i, chan;
597
598 uint writemask = inst->Dst[0].Register.WriteMask;
599 if (writemask == TGSI_WRITEMASK_X ||
600 writemask == TGSI_WRITEMASK_Y ||
601 writemask == TGSI_WRITEMASK_Z ||
602 writemask == TGSI_WRITEMASK_W ||
603 writemask == TGSI_WRITEMASK_NONE) {
604 /* no chance of data dependency */
605 return FALSE;
606 }
607
608 /* loop over src regs */
609 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
610 if ((inst->Src[i].Register.File ==
611 inst->Dst[0].Register.File) &&
612 ((inst->Src[i].Register.Index ==
613 inst->Dst[0].Register.Index) ||
614 inst->Src[i].Register.Indirect ||
615 inst->Dst[0].Register.Indirect)) {
616 /* loop over dest channels */
617 uint channelsWritten = 0x0;
618 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
619 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
620 /* check if we're reading a channel that's been written */
621 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
622 if (channelsWritten & (1 << swizzle)) {
623 return TRUE;
624 }
625
626 channelsWritten |= (1 << chan);
627 }
628 }
629 }
630 }
631 return FALSE;
632 }
633
634
635 /**
636 * Initialize machine state by expanding tokens to full instructions,
637 * allocating temporary storage, setting up constants, etc.
638 * After this, we can call tgsi_exec_machine_run() many times.
639 */
640 void
641 tgsi_exec_machine_bind_shader(
642 struct tgsi_exec_machine *mach,
643 const struct tgsi_token *tokens,
644 struct tgsi_sampler *sampler)
645 {
646 uint k;
647 struct tgsi_parse_context parse;
648 struct tgsi_full_instruction *instructions;
649 struct tgsi_full_declaration *declarations;
650 uint maxInstructions = 10, numInstructions = 0;
651 uint maxDeclarations = 10, numDeclarations = 0;
652
653 #if 0
654 tgsi_dump(tokens, 0);
655 #endif
656
657 util_init_math();
658
659
660 mach->Tokens = tokens;
661 mach->Sampler = sampler;
662
663 if (!tokens) {
664 /* unbind and free all */
665 FREE(mach->Declarations);
666 mach->Declarations = NULL;
667 mach->NumDeclarations = 0;
668
669 FREE(mach->Instructions);
670 mach->Instructions = NULL;
671 mach->NumInstructions = 0;
672
673 return;
674 }
675
676 k = tgsi_parse_init (&parse, mach->Tokens);
677 if (k != TGSI_PARSE_OK) {
678 debug_printf( "Problem parsing!\n" );
679 return;
680 }
681
682 mach->Processor = parse.FullHeader.Processor.Processor;
683 mach->ImmLimit = 0;
684 mach->NumOutputs = 0;
685
686 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
687 !mach->UsedGeometryShader) {
688 struct tgsi_exec_vector *inputs;
689 struct tgsi_exec_vector *outputs;
690
691 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
692 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS,
693 16);
694
695 if (!inputs)
696 return;
697
698 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
699 TGSI_MAX_TOTAL_VERTICES, 16);
700
701 if (!outputs) {
702 align_free(inputs);
703 return;
704 }
705
706 align_free(mach->Inputs);
707 align_free(mach->Outputs);
708
709 mach->Inputs = inputs;
710 mach->Outputs = outputs;
711 mach->UsedGeometryShader = TRUE;
712 }
713
714 declarations = (struct tgsi_full_declaration *)
715 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
716
717 if (!declarations) {
718 return;
719 }
720
721 instructions = (struct tgsi_full_instruction *)
722 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
723
724 if (!instructions) {
725 FREE( declarations );
726 return;
727 }
728
729 while( !tgsi_parse_end_of_tokens( &parse ) ) {
730 uint i;
731
732 tgsi_parse_token( &parse );
733 switch( parse.FullToken.Token.Type ) {
734 case TGSI_TOKEN_TYPE_DECLARATION:
735 /* save expanded declaration */
736 if (numDeclarations == maxDeclarations) {
737 declarations = REALLOC(declarations,
738 maxDeclarations
739 * sizeof(struct tgsi_full_declaration),
740 (maxDeclarations + 10)
741 * sizeof(struct tgsi_full_declaration));
742 maxDeclarations += 10;
743 }
744 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
745 unsigned reg;
746 for (reg = parse.FullToken.FullDeclaration.Range.First;
747 reg <= parse.FullToken.FullDeclaration.Range.Last;
748 ++reg) {
749 ++mach->NumOutputs;
750 }
751 }
752 memcpy(declarations + numDeclarations,
753 &parse.FullToken.FullDeclaration,
754 sizeof(declarations[0]));
755 numDeclarations++;
756 break;
757
758 case TGSI_TOKEN_TYPE_IMMEDIATE:
759 {
760 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
761 assert( size <= 4 );
762 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
763
764 for( i = 0; i < size; i++ ) {
765 mach->Imms[mach->ImmLimit][i] =
766 parse.FullToken.FullImmediate.u[i].Float;
767 }
768 mach->ImmLimit += 1;
769 }
770 break;
771
772 case TGSI_TOKEN_TYPE_INSTRUCTION:
773
774 /* save expanded instruction */
775 if (numInstructions == maxInstructions) {
776 instructions = REALLOC(instructions,
777 maxInstructions
778 * sizeof(struct tgsi_full_instruction),
779 (maxInstructions + 10)
780 * sizeof(struct tgsi_full_instruction));
781 maxInstructions += 10;
782 }
783
784 memcpy(instructions + numInstructions,
785 &parse.FullToken.FullInstruction,
786 sizeof(instructions[0]));
787
788 numInstructions++;
789 break;
790
791 case TGSI_TOKEN_TYPE_PROPERTY:
792 break;
793
794 default:
795 assert( 0 );
796 }
797 }
798 tgsi_parse_free (&parse);
799
800 FREE(mach->Declarations);
801 mach->Declarations = declarations;
802 mach->NumDeclarations = numDeclarations;
803
804 FREE(mach->Instructions);
805 mach->Instructions = instructions;
806 mach->NumInstructions = numInstructions;
807 }
808
809
810 struct tgsi_exec_machine *
811 tgsi_exec_machine_create( void )
812 {
813 struct tgsi_exec_machine *mach;
814 uint i;
815
816 mach = align_malloc( sizeof *mach, 16 );
817 if (!mach)
818 goto fail;
819
820 memset(mach, 0, sizeof(*mach));
821
822 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
823 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
824 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
825
826 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
827 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
828 if (!mach->Inputs || !mach->Outputs)
829 goto fail;
830
831 /* Setup constants needed by the SSE2 executor. */
832 for( i = 0; i < 4; i++ ) {
833 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
834 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
835 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
836 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
837 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
838 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
839 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
840 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
841 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
842 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
843 }
844
845 #ifdef DEBUG
846 /* silence warnings */
847 (void) print_chan;
848 (void) print_temp;
849 #endif
850
851 return mach;
852
853 fail:
854 if (mach) {
855 align_free(mach->Inputs);
856 align_free(mach->Outputs);
857 align_free(mach);
858 }
859 return NULL;
860 }
861
862
863 void
864 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
865 {
866 if (mach) {
867 FREE(mach->Instructions);
868 FREE(mach->Declarations);
869
870 align_free(mach->Inputs);
871 align_free(mach->Outputs);
872
873 align_free(mach);
874 }
875 }
876
877 static void
878 micro_add(union tgsi_exec_channel *dst,
879 const union tgsi_exec_channel *src0,
880 const union tgsi_exec_channel *src1)
881 {
882 dst->f[0] = src0->f[0] + src1->f[0];
883 dst->f[1] = src0->f[1] + src1->f[1];
884 dst->f[2] = src0->f[2] + src1->f[2];
885 dst->f[3] = src0->f[3] + src1->f[3];
886 }
887
888 static void
889 micro_div(
890 union tgsi_exec_channel *dst,
891 const union tgsi_exec_channel *src0,
892 const union tgsi_exec_channel *src1 )
893 {
894 if (src1->f[0] != 0) {
895 dst->f[0] = src0->f[0] / src1->f[0];
896 }
897 if (src1->f[1] != 0) {
898 dst->f[1] = src0->f[1] / src1->f[1];
899 }
900 if (src1->f[2] != 0) {
901 dst->f[2] = src0->f[2] / src1->f[2];
902 }
903 if (src1->f[3] != 0) {
904 dst->f[3] = src0->f[3] / src1->f[3];
905 }
906 }
907
908 static void
909 micro_rcc(union tgsi_exec_channel *dst,
910 const union tgsi_exec_channel *src)
911 {
912 uint i;
913
914 for (i = 0; i < 4; i++) {
915 float recip = 1.0f / src->f[i];
916
917 if (recip > 0.0f)
918 dst->f[i] = CLAMP(recip, 5.42101e-020f, 1.84467e+019f);
919 else
920 dst->f[i] = CLAMP(recip, -1.84467e+019f, -5.42101e-020f);
921 }
922 }
923
924 static void
925 micro_lt(
926 union tgsi_exec_channel *dst,
927 const union tgsi_exec_channel *src0,
928 const union tgsi_exec_channel *src1,
929 const union tgsi_exec_channel *src2,
930 const union tgsi_exec_channel *src3 )
931 {
932 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
933 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
934 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
935 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
936 }
937
938 static void
939 micro_max(union tgsi_exec_channel *dst,
940 const union tgsi_exec_channel *src0,
941 const union tgsi_exec_channel *src1)
942 {
943 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
944 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
945 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
946 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
947 }
948
949 static void
950 micro_min(union tgsi_exec_channel *dst,
951 const union tgsi_exec_channel *src0,
952 const union tgsi_exec_channel *src1)
953 {
954 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
955 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
956 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
957 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
958 }
959
960 static void
961 micro_mul(union tgsi_exec_channel *dst,
962 const union tgsi_exec_channel *src0,
963 const union tgsi_exec_channel *src1)
964 {
965 dst->f[0] = src0->f[0] * src1->f[0];
966 dst->f[1] = src0->f[1] * src1->f[1];
967 dst->f[2] = src0->f[2] * src1->f[2];
968 dst->f[3] = src0->f[3] * src1->f[3];
969 }
970
971 static void
972 micro_neg(
973 union tgsi_exec_channel *dst,
974 const union tgsi_exec_channel *src )
975 {
976 dst->f[0] = -src->f[0];
977 dst->f[1] = -src->f[1];
978 dst->f[2] = -src->f[2];
979 dst->f[3] = -src->f[3];
980 }
981
982 static void
983 micro_pow(
984 union tgsi_exec_channel *dst,
985 const union tgsi_exec_channel *src0,
986 const union tgsi_exec_channel *src1 )
987 {
988 #if FAST_MATH
989 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
990 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
991 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
992 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
993 #else
994 dst->f[0] = powf( src0->f[0], src1->f[0] );
995 dst->f[1] = powf( src0->f[1], src1->f[1] );
996 dst->f[2] = powf( src0->f[2], src1->f[2] );
997 dst->f[3] = powf( src0->f[3], src1->f[3] );
998 #endif
999 }
1000
1001 static void
1002 micro_sub(union tgsi_exec_channel *dst,
1003 const union tgsi_exec_channel *src0,
1004 const union tgsi_exec_channel *src1)
1005 {
1006 dst->f[0] = src0->f[0] - src1->f[0];
1007 dst->f[1] = src0->f[1] - src1->f[1];
1008 dst->f[2] = src0->f[2] - src1->f[2];
1009 dst->f[3] = src0->f[3] - src1->f[3];
1010 }
1011
1012 static void
1013 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1014 const uint chan_index,
1015 const uint file,
1016 const uint swizzle,
1017 const union tgsi_exec_channel *index,
1018 const union tgsi_exec_channel *index2D,
1019 union tgsi_exec_channel *chan)
1020 {
1021 uint i;
1022
1023 assert(swizzle < 4);
1024
1025 switch (file) {
1026 case TGSI_FILE_CONSTANT:
1027 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1028 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1029 assert(mach->Consts[index2D->i[i]]);
1030
1031 if (index->i[i] < 0) {
1032 chan->u[i] = 0;
1033 } else {
1034 /* NOTE: copying the const value as a uint instead of float */
1035 const uint constbuf = index2D->i[i];
1036 const uint *buf = (const uint *)mach->Consts[constbuf];
1037 const int pos = index->i[i] * 4 + swizzle;
1038 /* const buffer bounds check */
1039 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1040 if (0) {
1041 /* Debug: print warning */
1042 static int count = 0;
1043 if (count++ < 100)
1044 debug_printf("TGSI Exec: const buffer index %d"
1045 " out of bounds\n", pos);
1046 }
1047 chan->u[i] = 0;
1048 }
1049 else
1050 chan->u[i] = buf[pos];
1051 }
1052 }
1053 break;
1054
1055 case TGSI_FILE_INPUT:
1056 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1057 /*
1058 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1059 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1060 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1061 index2D->i[i], index->i[i]);
1062 }*/
1063 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1064 assert(pos >= 0);
1065 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1066 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1067 }
1068 break;
1069
1070 case TGSI_FILE_SYSTEM_VALUE:
1071 /* XXX no swizzling at this point. Will be needed if we put
1072 * gl_FragCoord, for example, in a sys value register.
1073 */
1074 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1075 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1076 }
1077 break;
1078
1079 case TGSI_FILE_TEMPORARY:
1080 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1081 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1082 assert(index2D->i[i] == 0);
1083
1084 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1085 }
1086 break;
1087
1088 case TGSI_FILE_IMMEDIATE:
1089 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1090 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1091 assert(index2D->i[i] == 0);
1092
1093 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1094 }
1095 break;
1096
1097 case TGSI_FILE_ADDRESS:
1098 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1099 assert(index->i[i] >= 0);
1100 assert(index2D->i[i] == 0);
1101
1102 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1103 }
1104 break;
1105
1106 case TGSI_FILE_PREDICATE:
1107 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1108 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1109 assert(index2D->i[i] == 0);
1110
1111 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1112 }
1113 break;
1114
1115 case TGSI_FILE_OUTPUT:
1116 /* vertex/fragment output vars can be read too */
1117 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1118 assert(index->i[i] >= 0);
1119 assert(index2D->i[i] == 0);
1120
1121 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1122 }
1123 break;
1124
1125 default:
1126 assert(0);
1127 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1128 chan->u[i] = 0;
1129 }
1130 }
1131 }
1132
1133 static void
1134 fetch_source(const struct tgsi_exec_machine *mach,
1135 union tgsi_exec_channel *chan,
1136 const struct tgsi_full_src_register *reg,
1137 const uint chan_index,
1138 enum tgsi_exec_datatype src_datatype)
1139 {
1140 union tgsi_exec_channel index;
1141 union tgsi_exec_channel index2D;
1142 uint swizzle;
1143
1144 /* We start with a direct index into a register file.
1145 *
1146 * file[1],
1147 * where:
1148 * file = Register.File
1149 * [1] = Register.Index
1150 */
1151 index.i[0] =
1152 index.i[1] =
1153 index.i[2] =
1154 index.i[3] = reg->Register.Index;
1155
1156 /* There is an extra source register that indirectly subscripts
1157 * a register file. The direct index now becomes an offset
1158 * that is being added to the indirect register.
1159 *
1160 * file[ind[2].x+1],
1161 * where:
1162 * ind = Indirect.File
1163 * [2] = Indirect.Index
1164 * .x = Indirect.SwizzleX
1165 */
1166 if (reg->Register.Indirect) {
1167 union tgsi_exec_channel index2;
1168 union tgsi_exec_channel indir_index;
1169 const uint execmask = mach->ExecMask;
1170 uint i;
1171
1172 /* which address register (always zero now) */
1173 index2.i[0] =
1174 index2.i[1] =
1175 index2.i[2] =
1176 index2.i[3] = reg->Indirect.Index;
1177 /* get current value of address register[swizzle] */
1178 swizzle = reg->Indirect.Swizzle;
1179 fetch_src_file_channel(mach,
1180 chan_index,
1181 reg->Indirect.File,
1182 swizzle,
1183 &index2,
1184 &ZeroVec,
1185 &indir_index);
1186
1187 /* add value of address register to the offset */
1188 index.i[0] += indir_index.i[0];
1189 index.i[1] += indir_index.i[1];
1190 index.i[2] += indir_index.i[2];
1191 index.i[3] += indir_index.i[3];
1192
1193 /* for disabled execution channels, zero-out the index to
1194 * avoid using a potential garbage value.
1195 */
1196 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1197 if ((execmask & (1 << i)) == 0)
1198 index.i[i] = 0;
1199 }
1200 }
1201
1202 /* There is an extra source register that is a second
1203 * subscript to a register file. Effectively it means that
1204 * the register file is actually a 2D array of registers.
1205 *
1206 * file[3][1],
1207 * where:
1208 * [3] = Dimension.Index
1209 */
1210 if (reg->Register.Dimension) {
1211 index2D.i[0] =
1212 index2D.i[1] =
1213 index2D.i[2] =
1214 index2D.i[3] = reg->Dimension.Index;
1215
1216 /* Again, the second subscript index can be addressed indirectly
1217 * identically to the first one.
1218 * Nothing stops us from indirectly addressing the indirect register,
1219 * but there is no need for that, so we won't exercise it.
1220 *
1221 * file[ind[4].y+3][1],
1222 * where:
1223 * ind = DimIndirect.File
1224 * [4] = DimIndirect.Index
1225 * .y = DimIndirect.SwizzleX
1226 */
1227 if (reg->Dimension.Indirect) {
1228 union tgsi_exec_channel index2;
1229 union tgsi_exec_channel indir_index;
1230 const uint execmask = mach->ExecMask;
1231 uint i;
1232
1233 index2.i[0] =
1234 index2.i[1] =
1235 index2.i[2] =
1236 index2.i[3] = reg->DimIndirect.Index;
1237
1238 swizzle = reg->DimIndirect.Swizzle;
1239 fetch_src_file_channel(mach,
1240 chan_index,
1241 reg->DimIndirect.File,
1242 swizzle,
1243 &index2,
1244 &ZeroVec,
1245 &indir_index);
1246
1247 index2D.i[0] += indir_index.i[0];
1248 index2D.i[1] += indir_index.i[1];
1249 index2D.i[2] += indir_index.i[2];
1250 index2D.i[3] += indir_index.i[3];
1251
1252 /* for disabled execution channels, zero-out the index to
1253 * avoid using a potential garbage value.
1254 */
1255 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1256 if ((execmask & (1 << i)) == 0) {
1257 index2D.i[i] = 0;
1258 }
1259 }
1260 }
1261
1262 /* If by any chance there was a need for a 3D array of register
1263 * files, we would have to check whether Dimension is followed
1264 * by a dimension register and continue the saga.
1265 */
1266 } else {
1267 index2D.i[0] =
1268 index2D.i[1] =
1269 index2D.i[2] =
1270 index2D.i[3] = 0;
1271 }
1272
1273 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1274 fetch_src_file_channel(mach,
1275 chan_index,
1276 reg->Register.File,
1277 swizzle,
1278 &index,
1279 &index2D,
1280 chan);
1281
1282 if (reg->Register.Absolute) {
1283 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1284 micro_abs(chan, chan);
1285 } else {
1286 micro_iabs(chan, chan);
1287 }
1288 }
1289
1290 if (reg->Register.Negate) {
1291 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1292 micro_neg(chan, chan);
1293 } else {
1294 micro_ineg(chan, chan);
1295 }
1296 }
1297 }
1298
1299 static void
1300 store_dest(struct tgsi_exec_machine *mach,
1301 const union tgsi_exec_channel *chan,
1302 const struct tgsi_full_dst_register *reg,
1303 const struct tgsi_full_instruction *inst,
1304 uint chan_index,
1305 enum tgsi_exec_datatype dst_datatype)
1306 {
1307 uint i;
1308 union tgsi_exec_channel null;
1309 union tgsi_exec_channel *dst;
1310 union tgsi_exec_channel index2D;
1311 uint execmask = mach->ExecMask;
1312 int offset = 0; /* indirection offset */
1313 int index;
1314
1315 /* for debugging */
1316 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1317 check_inf_or_nan(chan);
1318 }
1319
1320 /* There is an extra source register that indirectly subscripts
1321 * a register file. The direct index now becomes an offset
1322 * that is being added to the indirect register.
1323 *
1324 * file[ind[2].x+1],
1325 * where:
1326 * ind = Indirect.File
1327 * [2] = Indirect.Index
1328 * .x = Indirect.SwizzleX
1329 */
1330 if (reg->Register.Indirect) {
1331 union tgsi_exec_channel index;
1332 union tgsi_exec_channel indir_index;
1333 uint swizzle;
1334
1335 /* which address register (always zero for now) */
1336 index.i[0] =
1337 index.i[1] =
1338 index.i[2] =
1339 index.i[3] = reg->Indirect.Index;
1340
1341 /* get current value of address register[swizzle] */
1342 swizzle = reg->Indirect.Swizzle;
1343
1344 /* fetch values from the address/indirection register */
1345 fetch_src_file_channel(mach,
1346 chan_index,
1347 reg->Indirect.File,
1348 swizzle,
1349 &index,
1350 &ZeroVec,
1351 &indir_index);
1352
1353 /* save indirection offset */
1354 offset = indir_index.i[0];
1355 }
1356
1357 /* There is an extra source register that is a second
1358 * subscript to a register file. Effectively it means that
1359 * the register file is actually a 2D array of registers.
1360 *
1361 * file[3][1],
1362 * where:
1363 * [3] = Dimension.Index
1364 */
1365 if (reg->Register.Dimension) {
1366 index2D.i[0] =
1367 index2D.i[1] =
1368 index2D.i[2] =
1369 index2D.i[3] = reg->Dimension.Index;
1370
1371 /* Again, the second subscript index can be addressed indirectly
1372 * identically to the first one.
1373 * Nothing stops us from indirectly addressing the indirect register,
1374 * but there is no need for that, so we won't exercise it.
1375 *
1376 * file[ind[4].y+3][1],
1377 * where:
1378 * ind = DimIndirect.File
1379 * [4] = DimIndirect.Index
1380 * .y = DimIndirect.SwizzleX
1381 */
1382 if (reg->Dimension.Indirect) {
1383 union tgsi_exec_channel index2;
1384 union tgsi_exec_channel indir_index;
1385 const uint execmask = mach->ExecMask;
1386 unsigned swizzle;
1387 uint i;
1388
1389 index2.i[0] =
1390 index2.i[1] =
1391 index2.i[2] =
1392 index2.i[3] = reg->DimIndirect.Index;
1393
1394 swizzle = reg->DimIndirect.Swizzle;
1395 fetch_src_file_channel(mach,
1396 chan_index,
1397 reg->DimIndirect.File,
1398 swizzle,
1399 &index2,
1400 &ZeroVec,
1401 &indir_index);
1402
1403 index2D.i[0] += indir_index.i[0];
1404 index2D.i[1] += indir_index.i[1];
1405 index2D.i[2] += indir_index.i[2];
1406 index2D.i[3] += indir_index.i[3];
1407
1408 /* for disabled execution channels, zero-out the index to
1409 * avoid using a potential garbage value.
1410 */
1411 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1412 if ((execmask & (1 << i)) == 0) {
1413 index2D.i[i] = 0;
1414 }
1415 }
1416 }
1417
1418 /* If by any chance there was a need for a 3D array of register
1419 * files, we would have to check whether Dimension is followed
1420 * by a dimension register and continue the saga.
1421 */
1422 } else {
1423 index2D.i[0] =
1424 index2D.i[1] =
1425 index2D.i[2] =
1426 index2D.i[3] = 0;
1427 }
1428
1429 switch (reg->Register.File) {
1430 case TGSI_FILE_NULL:
1431 dst = &null;
1432 break;
1433
1434 case TGSI_FILE_OUTPUT:
1435 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1436 + reg->Register.Index;
1437 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1438 #if 0
1439 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1440 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1441 reg->Register.Index);
1442 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1443 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1444 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1445 if (execmask & (1 << i))
1446 debug_printf("%f, ", chan->f[i]);
1447 debug_printf(")\n");
1448 }
1449 #endif
1450 break;
1451
1452 case TGSI_FILE_TEMPORARY:
1453 index = reg->Register.Index;
1454 assert( index < TGSI_EXEC_NUM_TEMPS );
1455 dst = &mach->Temps[offset + index].xyzw[chan_index];
1456 break;
1457
1458 case TGSI_FILE_ADDRESS:
1459 index = reg->Register.Index;
1460 dst = &mach->Addrs[index].xyzw[chan_index];
1461 break;
1462
1463 case TGSI_FILE_PREDICATE:
1464 index = reg->Register.Index;
1465 assert(index < TGSI_EXEC_NUM_PREDS);
1466 dst = &mach->Predicates[index].xyzw[chan_index];
1467 break;
1468
1469 default:
1470 assert( 0 );
1471 return;
1472 }
1473
1474 if (inst->Instruction.Predicate) {
1475 uint swizzle;
1476 union tgsi_exec_channel *pred;
1477
1478 switch (chan_index) {
1479 case TGSI_CHAN_X:
1480 swizzle = inst->Predicate.SwizzleX;
1481 break;
1482 case TGSI_CHAN_Y:
1483 swizzle = inst->Predicate.SwizzleY;
1484 break;
1485 case TGSI_CHAN_Z:
1486 swizzle = inst->Predicate.SwizzleZ;
1487 break;
1488 case TGSI_CHAN_W:
1489 swizzle = inst->Predicate.SwizzleW;
1490 break;
1491 default:
1492 assert(0);
1493 return;
1494 }
1495
1496 assert(inst->Predicate.Index == 0);
1497
1498 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1499
1500 if (inst->Predicate.Negate) {
1501 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1502 if (pred->u[i]) {
1503 execmask &= ~(1 << i);
1504 }
1505 }
1506 } else {
1507 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1508 if (!pred->u[i]) {
1509 execmask &= ~(1 << i);
1510 }
1511 }
1512 }
1513 }
1514
1515 switch (inst->Instruction.Saturate) {
1516 case TGSI_SAT_NONE:
1517 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1518 if (execmask & (1 << i))
1519 dst->i[i] = chan->i[i];
1520 break;
1521
1522 case TGSI_SAT_ZERO_ONE:
1523 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1524 if (execmask & (1 << i)) {
1525 if (chan->f[i] < 0.0f)
1526 dst->f[i] = 0.0f;
1527 else if (chan->f[i] > 1.0f)
1528 dst->f[i] = 1.0f;
1529 else
1530 dst->i[i] = chan->i[i];
1531 }
1532 break;
1533
1534 case TGSI_SAT_MINUS_PLUS_ONE:
1535 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1536 if (execmask & (1 << i)) {
1537 if (chan->f[i] < -1.0f)
1538 dst->f[i] = -1.0f;
1539 else if (chan->f[i] > 1.0f)
1540 dst->f[i] = 1.0f;
1541 else
1542 dst->i[i] = chan->i[i];
1543 }
1544 break;
1545
1546 default:
1547 assert( 0 );
1548 }
1549 }
1550
1551 #define FETCH(VAL,INDEX,CHAN)\
1552 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1553
1554 #define IFETCH(VAL,INDEX,CHAN)\
1555 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1556
1557
1558 /**
1559 * Execute ARB-style KIL which is predicated by a src register.
1560 * Kill fragment if any of the four values is less than zero.
1561 */
1562 static void
1563 exec_kill_if(struct tgsi_exec_machine *mach,
1564 const struct tgsi_full_instruction *inst)
1565 {
1566 uint uniquemask;
1567 uint chan_index;
1568 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1569 union tgsi_exec_channel r[1];
1570
1571 /* This mask stores component bits that were already tested. */
1572 uniquemask = 0;
1573
1574 for (chan_index = 0; chan_index < 4; chan_index++)
1575 {
1576 uint swizzle;
1577 uint i;
1578
1579 /* unswizzle channel */
1580 swizzle = tgsi_util_get_full_src_register_swizzle (
1581 &inst->Src[0],
1582 chan_index);
1583
1584 /* check if the component has not been already tested */
1585 if (uniquemask & (1 << swizzle))
1586 continue;
1587 uniquemask |= 1 << swizzle;
1588
1589 FETCH(&r[0], 0, chan_index);
1590 for (i = 0; i < 4; i++)
1591 if (r[0].f[i] < 0.0f)
1592 kilmask |= 1 << i;
1593 }
1594
1595 /* restrict to fragments currently executing */
1596 kilmask &= mach->ExecMask;
1597
1598 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1599 }
1600
1601 /**
1602 * Unconditional fragment kill/discard.
1603 */
1604 static void
1605 exec_kill(struct tgsi_exec_machine *mach,
1606 const struct tgsi_full_instruction *inst)
1607 {
1608 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1609
1610 /* kill fragment for all fragments currently executing */
1611 kilmask = mach->ExecMask;
1612 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1613 }
1614
1615 static void
1616 emit_vertex(struct tgsi_exec_machine *mach)
1617 {
1618 /* FIXME: check for exec mask correctly
1619 unsigned i;
1620 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1621 if ((mach->ExecMask & (1 << i)))
1622 */
1623 if (mach->ExecMask) {
1624 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1625 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1626 }
1627 }
1628
1629 static void
1630 emit_primitive(struct tgsi_exec_machine *mach)
1631 {
1632 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1633 /* FIXME: check for exec mask correctly
1634 unsigned i;
1635 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1636 if ((mach->ExecMask & (1 << i)))
1637 */
1638 if (mach->ExecMask) {
1639 ++(*prim_count);
1640 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1641 mach->Primitives[*prim_count] = 0;
1642 }
1643 }
1644
1645 static void
1646 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1647 {
1648 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1649 int emitted_verts =
1650 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1651 if (emitted_verts) {
1652 emit_primitive(mach);
1653 }
1654 }
1655 }
1656
1657
1658 /*
1659 * Fetch four texture samples using STR texture coordinates.
1660 */
1661 static void
1662 fetch_texel( struct tgsi_sampler *sampler,
1663 const unsigned sview_idx,
1664 const unsigned sampler_idx,
1665 const union tgsi_exec_channel *s,
1666 const union tgsi_exec_channel *t,
1667 const union tgsi_exec_channel *p,
1668 const union tgsi_exec_channel *c0,
1669 const union tgsi_exec_channel *c1,
1670 float derivs[3][2][TGSI_QUAD_SIZE],
1671 const int8_t offset[3],
1672 enum tgsi_sampler_control control,
1673 union tgsi_exec_channel *r,
1674 union tgsi_exec_channel *g,
1675 union tgsi_exec_channel *b,
1676 union tgsi_exec_channel *a )
1677 {
1678 uint j;
1679 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1680
1681 /* FIXME: handle explicit derivs, offsets */
1682 sampler->get_samples(sampler, sview_idx, sampler_idx,
1683 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1684
1685 for (j = 0; j < 4; j++) {
1686 r->f[j] = rgba[0][j];
1687 g->f[j] = rgba[1][j];
1688 b->f[j] = rgba[2][j];
1689 a->f[j] = rgba[3][j];
1690 }
1691 }
1692
1693
1694 #define TEX_MODIFIER_NONE 0
1695 #define TEX_MODIFIER_PROJECTED 1
1696 #define TEX_MODIFIER_LOD_BIAS 2
1697 #define TEX_MODIFIER_EXPLICIT_LOD 3
1698 #define TEX_MODIFIER_LEVEL_ZERO 4
1699
1700
1701 /*
1702 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1703 */
1704 static void
1705 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1706 const struct tgsi_full_instruction *inst,
1707 int8_t offsets[3])
1708 {
1709 if (inst->Texture.NumOffsets == 1) {
1710 union tgsi_exec_channel index;
1711 union tgsi_exec_channel offset[3];
1712 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1713 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1714 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1715 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1716 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1717 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1718 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1719 offsets[0] = offset[0].i[0];
1720 offsets[1] = offset[1].i[0];
1721 offsets[2] = offset[2].i[0];
1722 } else {
1723 assert(inst->Texture.NumOffsets == 0);
1724 offsets[0] = offsets[1] = offsets[2] = 0;
1725 }
1726 }
1727
1728
1729 /*
1730 * Fetch dx and dy values for one channel (s, t or r).
1731 * Put dx values into one float array, dy values into another.
1732 */
1733 static void
1734 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1735 const struct tgsi_full_instruction *inst,
1736 unsigned regdsrcx,
1737 unsigned chan,
1738 float derivs[2][TGSI_QUAD_SIZE])
1739 {
1740 union tgsi_exec_channel d;
1741 FETCH(&d, regdsrcx, chan);
1742 derivs[0][0] = d.f[0];
1743 derivs[0][1] = d.f[1];
1744 derivs[0][2] = d.f[2];
1745 derivs[0][3] = d.f[3];
1746 FETCH(&d, regdsrcx + 1, chan);
1747 derivs[1][0] = d.f[0];
1748 derivs[1][1] = d.f[1];
1749 derivs[1][2] = d.f[2];
1750 derivs[1][3] = d.f[3];
1751 }
1752
1753
1754 /*
1755 * execute a texture instruction.
1756 *
1757 * modifier is used to control the channel routing for the\
1758 * instruction variants like proj, lod, and texture with lod bias.
1759 * sampler indicates which src register the sampler is contained in.
1760 */
1761 static void
1762 exec_tex(struct tgsi_exec_machine *mach,
1763 const struct tgsi_full_instruction *inst,
1764 uint modifier, uint sampler)
1765 {
1766 const uint unit = inst->Src[sampler].Register.Index;
1767 const union tgsi_exec_channel *args[5], *proj = NULL;
1768 union tgsi_exec_channel r[5];
1769 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
1770 uint chan;
1771 int8_t offsets[3];
1772 int dim, shadow_ref, i;
1773
1774 /* always fetch all 3 offsets, overkill but keeps code simple */
1775 fetch_texel_offsets(mach, inst, offsets);
1776
1777 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
1778 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
1779
1780 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
1781
1782 assert(dim <= 4);
1783 if (shadow_ref >= 0)
1784 assert(shadow_ref >= dim && shadow_ref < Elements(args));
1785
1786 /* fetch modifier to the last argument */
1787 if (modifier != TEX_MODIFIER_NONE) {
1788 const int last = Elements(args) - 1;
1789
1790 /* fetch modifier from src0.w or src1.x */
1791 if (sampler == 1) {
1792 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
1793 FETCH(&r[last], 0, TGSI_CHAN_W);
1794 }
1795 else {
1796 assert(shadow_ref != 4);
1797 FETCH(&r[last], 1, TGSI_CHAN_X);
1798 }
1799
1800 if (modifier != TEX_MODIFIER_PROJECTED) {
1801 args[last] = &r[last];
1802 }
1803 else {
1804 proj = &r[last];
1805 args[last] = &ZeroVec;
1806 }
1807
1808 /* point unused arguments to zero vector */
1809 for (i = dim; i < last; i++)
1810 args[i] = &ZeroVec;
1811
1812 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
1813 control = tgsi_sampler_lod_explicit;
1814 else if (modifier == TEX_MODIFIER_LOD_BIAS)
1815 control = tgsi_sampler_lod_bias;
1816 }
1817 else {
1818 for (i = dim; i < Elements(args); i++)
1819 args[i] = &ZeroVec;
1820 }
1821
1822 /* fetch coordinates */
1823 for (i = 0; i < dim; i++) {
1824 FETCH(&r[i], 0, TGSI_CHAN_X + i);
1825
1826 if (proj)
1827 micro_div(&r[i], &r[i], proj);
1828
1829 args[i] = &r[i];
1830 }
1831
1832 /* fetch reference value */
1833 if (shadow_ref >= 0) {
1834 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
1835
1836 if (proj)
1837 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
1838
1839 args[shadow_ref] = &r[shadow_ref];
1840 }
1841
1842 fetch_texel(mach->Sampler, unit, unit,
1843 args[0], args[1], args[2], args[3], args[4],
1844 NULL, offsets, control,
1845 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1846
1847 #if 0
1848 debug_printf("fetch r: %g %g %g %g\n",
1849 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1850 debug_printf("fetch g: %g %g %g %g\n",
1851 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1852 debug_printf("fetch b: %g %g %g %g\n",
1853 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1854 debug_printf("fetch a: %g %g %g %g\n",
1855 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1856 #endif
1857
1858 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1859 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1860 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1861 }
1862 }
1863 }
1864
1865
1866 static void
1867 exec_txd(struct tgsi_exec_machine *mach,
1868 const struct tgsi_full_instruction *inst)
1869 {
1870 const uint unit = inst->Src[3].Register.Index;
1871 union tgsi_exec_channel r[4];
1872 float derivs[3][2][TGSI_QUAD_SIZE];
1873 uint chan;
1874 int8_t offsets[3];
1875
1876 /* always fetch all 3 offsets, overkill but keeps code simple */
1877 fetch_texel_offsets(mach, inst, offsets);
1878
1879 switch (inst->Texture.Texture) {
1880 case TGSI_TEXTURE_1D:
1881 FETCH(&r[0], 0, TGSI_CHAN_X);
1882
1883 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1884
1885 fetch_texel(mach->Sampler, unit, unit,
1886 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1887 derivs, offsets, tgsi_sampler_derivs_explicit,
1888 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1889 break;
1890
1891 case TGSI_TEXTURE_SHADOW1D:
1892 case TGSI_TEXTURE_1D_ARRAY:
1893 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1894 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
1895 FETCH(&r[0], 0, TGSI_CHAN_X);
1896 FETCH(&r[1], 0, TGSI_CHAN_Y);
1897 FETCH(&r[2], 0, TGSI_CHAN_Z);
1898
1899 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1900
1901 fetch_texel(mach->Sampler, unit, unit,
1902 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1903 derivs, offsets, tgsi_sampler_derivs_explicit,
1904 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1905 break;
1906
1907 case TGSI_TEXTURE_2D:
1908 case TGSI_TEXTURE_RECT:
1909 FETCH(&r[0], 0, TGSI_CHAN_X);
1910 FETCH(&r[1], 0, TGSI_CHAN_Y);
1911
1912 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1913 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1914
1915 fetch_texel(mach->Sampler, unit, unit,
1916 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1917 derivs, offsets, tgsi_sampler_derivs_explicit,
1918 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1919 break;
1920
1921
1922 case TGSI_TEXTURE_SHADOW2D:
1923 case TGSI_TEXTURE_SHADOWRECT:
1924 case TGSI_TEXTURE_2D_ARRAY:
1925 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1926 /* only SHADOW2D_ARRAY actually needs W */
1927 FETCH(&r[0], 0, TGSI_CHAN_X);
1928 FETCH(&r[1], 0, TGSI_CHAN_Y);
1929 FETCH(&r[2], 0, TGSI_CHAN_Z);
1930 FETCH(&r[3], 0, TGSI_CHAN_W);
1931
1932 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1933 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1934
1935 fetch_texel(mach->Sampler, unit, unit,
1936 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1937 derivs, offsets, tgsi_sampler_derivs_explicit,
1938 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1939 break;
1940
1941 case TGSI_TEXTURE_3D:
1942 case TGSI_TEXTURE_CUBE:
1943 case TGSI_TEXTURE_CUBE_ARRAY:
1944 /* only TEXTURE_CUBE_ARRAY actually needs W */
1945 FETCH(&r[0], 0, TGSI_CHAN_X);
1946 FETCH(&r[1], 0, TGSI_CHAN_Y);
1947 FETCH(&r[2], 0, TGSI_CHAN_Z);
1948 FETCH(&r[3], 0, TGSI_CHAN_W);
1949
1950 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1951 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1952 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
1953
1954 fetch_texel(mach->Sampler, unit, unit,
1955 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1956 derivs, offsets, tgsi_sampler_derivs_explicit,
1957 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1958 break;
1959
1960 default:
1961 assert(0);
1962 }
1963
1964 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1965 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1966 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1967 }
1968 }
1969 }
1970
1971
1972 static void
1973 exec_txf(struct tgsi_exec_machine *mach,
1974 const struct tgsi_full_instruction *inst)
1975 {
1976 const uint unit = inst->Src[1].Register.Index;
1977 union tgsi_exec_channel r[4];
1978 uint chan;
1979 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1980 int j;
1981 int8_t offsets[3];
1982 unsigned target;
1983
1984 /* always fetch all 3 offsets, overkill but keeps code simple */
1985 fetch_texel_offsets(mach, inst, offsets);
1986
1987 IFETCH(&r[3], 0, TGSI_CHAN_W);
1988
1989 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
1990 target = mach->SamplerViews[unit].Resource;
1991 }
1992 else {
1993 target = inst->Texture.Texture;
1994 }
1995 switch(target) {
1996 case TGSI_TEXTURE_3D:
1997 case TGSI_TEXTURE_2D_ARRAY:
1998 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1999 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2000 /* fallthrough */
2001 case TGSI_TEXTURE_2D:
2002 case TGSI_TEXTURE_RECT:
2003 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2004 case TGSI_TEXTURE_SHADOW2D:
2005 case TGSI_TEXTURE_SHADOWRECT:
2006 case TGSI_TEXTURE_1D_ARRAY:
2007 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2008 /* fallthrough */
2009 case TGSI_TEXTURE_BUFFER:
2010 case TGSI_TEXTURE_1D:
2011 case TGSI_TEXTURE_SHADOW1D:
2012 IFETCH(&r[0], 0, TGSI_CHAN_X);
2013 break;
2014 default:
2015 assert(0);
2016 break;
2017 }
2018
2019 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2020 offsets, rgba);
2021
2022 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2023 r[0].f[j] = rgba[0][j];
2024 r[1].f[j] = rgba[1][j];
2025 r[2].f[j] = rgba[2][j];
2026 r[3].f[j] = rgba[3][j];
2027 }
2028
2029 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2030 unsigned char swizzles[4];
2031 swizzles[0] = inst->Src[1].Register.SwizzleX;
2032 swizzles[1] = inst->Src[1].Register.SwizzleY;
2033 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2034 swizzles[3] = inst->Src[1].Register.SwizzleW;
2035
2036 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2037 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2038 store_dest(mach, &r[swizzles[chan]],
2039 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2040 }
2041 }
2042 }
2043 else {
2044 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2045 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2046 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2047 }
2048 }
2049 }
2050 }
2051
2052 static void
2053 exec_txq(struct tgsi_exec_machine *mach,
2054 const struct tgsi_full_instruction *inst)
2055 {
2056 const uint unit = inst->Src[1].Register.Index;
2057 int result[4];
2058 union tgsi_exec_channel r[4], src;
2059 uint chan;
2060 int i,j;
2061
2062 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2063
2064 /* XXX: This interface can't return per-pixel values */
2065 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2066
2067 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2068 for (j = 0; j < 4; j++) {
2069 r[j].i[i] = result[j];
2070 }
2071 }
2072
2073 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2074 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2075 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2076 TGSI_EXEC_DATA_INT);
2077 }
2078 }
2079 }
2080
2081 static void
2082 exec_sample(struct tgsi_exec_machine *mach,
2083 const struct tgsi_full_instruction *inst,
2084 uint modifier, boolean compare)
2085 {
2086 const uint resource_unit = inst->Src[1].Register.Index;
2087 const uint sampler_unit = inst->Src[2].Register.Index;
2088 union tgsi_exec_channel r[4], c1;
2089 const union tgsi_exec_channel *lod = &ZeroVec;
2090 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2091 uint chan;
2092 unsigned char swizzles[4];
2093 int8_t offsets[3];
2094
2095 /* always fetch all 3 offsets, overkill but keeps code simple */
2096 fetch_texel_offsets(mach, inst, offsets);
2097
2098 assert(modifier != TEX_MODIFIER_PROJECTED);
2099
2100 if (modifier != TEX_MODIFIER_NONE) {
2101 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2102 FETCH(&c1, 3, TGSI_CHAN_X);
2103 lod = &c1;
2104 control = tgsi_sampler_lod_bias;
2105 }
2106 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2107 FETCH(&c1, 3, TGSI_CHAN_X);
2108 lod = &c1;
2109 control = tgsi_sampler_lod_explicit;
2110 }
2111 else {
2112 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2113 control = tgsi_sampler_lod_zero;
2114 }
2115 }
2116
2117 FETCH(&r[0], 0, TGSI_CHAN_X);
2118
2119 switch (mach->SamplerViews[resource_unit].Resource) {
2120 case TGSI_TEXTURE_1D:
2121 if (compare) {
2122 FETCH(&r[2], 3, TGSI_CHAN_X);
2123 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2124 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2125 NULL, offsets, control,
2126 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2127 }
2128 else {
2129 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2130 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2131 NULL, offsets, control,
2132 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2133 }
2134 break;
2135
2136 case TGSI_TEXTURE_1D_ARRAY:
2137 case TGSI_TEXTURE_2D:
2138 case TGSI_TEXTURE_RECT:
2139 FETCH(&r[1], 0, TGSI_CHAN_Y);
2140 if (compare) {
2141 FETCH(&r[2], 3, TGSI_CHAN_X);
2142 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2143 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2144 NULL, offsets, control,
2145 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2146 }
2147 else {
2148 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2149 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2150 NULL, offsets, control,
2151 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2152 }
2153 break;
2154
2155 case TGSI_TEXTURE_2D_ARRAY:
2156 case TGSI_TEXTURE_3D:
2157 case TGSI_TEXTURE_CUBE:
2158 FETCH(&r[1], 0, TGSI_CHAN_Y);
2159 FETCH(&r[2], 0, TGSI_CHAN_Z);
2160 if(compare) {
2161 FETCH(&r[3], 3, TGSI_CHAN_X);
2162 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2163 &r[0], &r[1], &r[2], &r[3], lod,
2164 NULL, offsets, control,
2165 &r[0], &r[1], &r[2], &r[3]);
2166 }
2167 else {
2168 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2169 &r[0], &r[1], &r[2], &ZeroVec, lod,
2170 NULL, offsets, control,
2171 &r[0], &r[1], &r[2], &r[3]);
2172 }
2173 break;
2174
2175 case TGSI_TEXTURE_CUBE_ARRAY:
2176 FETCH(&r[1], 0, TGSI_CHAN_Y);
2177 FETCH(&r[2], 0, TGSI_CHAN_Z);
2178 FETCH(&r[3], 0, TGSI_CHAN_W);
2179 if(compare) {
2180 FETCH(&r[4], 3, TGSI_CHAN_X);
2181 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2182 &r[0], &r[1], &r[2], &r[3], &r[4],
2183 NULL, offsets, control,
2184 &r[0], &r[1], &r[2], &r[3]);
2185 }
2186 else {
2187 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2188 &r[0], &r[1], &r[2], &r[3], lod,
2189 NULL, offsets, control,
2190 &r[0], &r[1], &r[2], &r[3]);
2191 }
2192 break;
2193
2194
2195 default:
2196 assert(0);
2197 }
2198
2199 swizzles[0] = inst->Src[1].Register.SwizzleX;
2200 swizzles[1] = inst->Src[1].Register.SwizzleY;
2201 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2202 swizzles[3] = inst->Src[1].Register.SwizzleW;
2203
2204 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2205 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2206 store_dest(mach, &r[swizzles[chan]],
2207 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2208 }
2209 }
2210 }
2211
2212 static void
2213 exec_sample_d(struct tgsi_exec_machine *mach,
2214 const struct tgsi_full_instruction *inst)
2215 {
2216 const uint resource_unit = inst->Src[1].Register.Index;
2217 const uint sampler_unit = inst->Src[2].Register.Index;
2218 union tgsi_exec_channel r[4];
2219 float derivs[3][2][TGSI_QUAD_SIZE];
2220 uint chan;
2221 unsigned char swizzles[4];
2222 int8_t offsets[3];
2223
2224 /* always fetch all 3 offsets, overkill but keeps code simple */
2225 fetch_texel_offsets(mach, inst, offsets);
2226
2227 FETCH(&r[0], 0, TGSI_CHAN_X);
2228
2229 switch (mach->SamplerViews[resource_unit].Resource) {
2230 case TGSI_TEXTURE_1D:
2231 case TGSI_TEXTURE_1D_ARRAY:
2232 /* only 1D array actually needs Y */
2233 FETCH(&r[1], 0, TGSI_CHAN_Y);
2234
2235 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2236
2237 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2238 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2239 derivs, offsets, tgsi_sampler_derivs_explicit,
2240 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2241 break;
2242
2243 case TGSI_TEXTURE_2D:
2244 case TGSI_TEXTURE_RECT:
2245 case TGSI_TEXTURE_2D_ARRAY:
2246 /* only 2D array actually needs Z */
2247 FETCH(&r[1], 0, TGSI_CHAN_Y);
2248 FETCH(&r[2], 0, TGSI_CHAN_Z);
2249
2250 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2251 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2252
2253 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2254 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2255 derivs, offsets, tgsi_sampler_derivs_explicit,
2256 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2257 break;
2258
2259 case TGSI_TEXTURE_3D:
2260 case TGSI_TEXTURE_CUBE:
2261 case TGSI_TEXTURE_CUBE_ARRAY:
2262 /* only cube array actually needs W */
2263 FETCH(&r[1], 0, TGSI_CHAN_Y);
2264 FETCH(&r[2], 0, TGSI_CHAN_Z);
2265 FETCH(&r[3], 0, TGSI_CHAN_W);
2266
2267 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2268 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2269 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2270
2271 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2272 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2273 derivs, offsets, tgsi_sampler_derivs_explicit,
2274 &r[0], &r[1], &r[2], &r[3]);
2275 break;
2276
2277 default:
2278 assert(0);
2279 }
2280
2281 swizzles[0] = inst->Src[1].Register.SwizzleX;
2282 swizzles[1] = inst->Src[1].Register.SwizzleY;
2283 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2284 swizzles[3] = inst->Src[1].Register.SwizzleW;
2285
2286 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2287 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2288 store_dest(mach, &r[swizzles[chan]],
2289 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2290 }
2291 }
2292 }
2293
2294
2295 /**
2296 * Evaluate a constant-valued coefficient at the position of the
2297 * current quad.
2298 */
2299 static void
2300 eval_constant_coef(
2301 struct tgsi_exec_machine *mach,
2302 unsigned attrib,
2303 unsigned chan )
2304 {
2305 unsigned i;
2306
2307 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2308 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2309 }
2310 }
2311
2312 /**
2313 * Evaluate a linear-valued coefficient at the position of the
2314 * current quad.
2315 */
2316 static void
2317 eval_linear_coef(
2318 struct tgsi_exec_machine *mach,
2319 unsigned attrib,
2320 unsigned chan )
2321 {
2322 const float x = mach->QuadPos.xyzw[0].f[0];
2323 const float y = mach->QuadPos.xyzw[1].f[0];
2324 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2325 const float dady = mach->InterpCoefs[attrib].dady[chan];
2326 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2327 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2328 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2329 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2330 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2331 }
2332
2333 /**
2334 * Evaluate a perspective-valued coefficient at the position of the
2335 * current quad.
2336 */
2337 static void
2338 eval_perspective_coef(
2339 struct tgsi_exec_machine *mach,
2340 unsigned attrib,
2341 unsigned chan )
2342 {
2343 const float x = mach->QuadPos.xyzw[0].f[0];
2344 const float y = mach->QuadPos.xyzw[1].f[0];
2345 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2346 const float dady = mach->InterpCoefs[attrib].dady[chan];
2347 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2348 const float *w = mach->QuadPos.xyzw[3].f;
2349 /* divide by W here */
2350 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2351 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2352 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2353 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2354 }
2355
2356
2357 typedef void (* eval_coef_func)(
2358 struct tgsi_exec_machine *mach,
2359 unsigned attrib,
2360 unsigned chan );
2361
2362 static void
2363 exec_declaration(struct tgsi_exec_machine *mach,
2364 const struct tgsi_full_declaration *decl)
2365 {
2366 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2367 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2368 return;
2369 }
2370
2371 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2372 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2373 uint first, last, mask;
2374
2375 first = decl->Range.First;
2376 last = decl->Range.Last;
2377 mask = decl->Declaration.UsageMask;
2378
2379 /* XXX we could remove this special-case code since
2380 * mach->InterpCoefs[first].a0 should already have the
2381 * front/back-face value. But we should first update the
2382 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2383 * Then, we could remove the tgsi_exec_machine::Face field.
2384 */
2385 /* XXX make FACE a system value */
2386 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2387 uint i;
2388
2389 assert(decl->Semantic.Index == 0);
2390 assert(first == last);
2391
2392 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2393 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2394 }
2395 } else {
2396 eval_coef_func eval;
2397 uint i, j;
2398
2399 switch (decl->Interp.Interpolate) {
2400 case TGSI_INTERPOLATE_CONSTANT:
2401 eval = eval_constant_coef;
2402 break;
2403
2404 case TGSI_INTERPOLATE_LINEAR:
2405 eval = eval_linear_coef;
2406 break;
2407
2408 case TGSI_INTERPOLATE_PERSPECTIVE:
2409 eval = eval_perspective_coef;
2410 break;
2411
2412 case TGSI_INTERPOLATE_COLOR:
2413 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2414 break;
2415
2416 default:
2417 assert(0);
2418 return;
2419 }
2420
2421 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2422 if (mask & (1 << j)) {
2423 for (i = first; i <= last; i++) {
2424 eval(mach, i, j);
2425 }
2426 }
2427 }
2428 }
2429
2430 if (DEBUG_EXECUTION) {
2431 uint i, j;
2432 for (i = first; i <= last; ++i) {
2433 debug_printf("IN[%2u] = ", i);
2434 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2435 if (j > 0) {
2436 debug_printf(" ");
2437 }
2438 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2439 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2440 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2441 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2442 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2443 }
2444 }
2445 }
2446 }
2447 }
2448
2449 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2450 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2451 }
2452 }
2453
2454
2455 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2456
2457 static void
2458 exec_vector(struct tgsi_exec_machine *mach,
2459 const struct tgsi_full_instruction *inst,
2460 micro_op op,
2461 enum tgsi_exec_datatype dst_datatype)
2462 {
2463 unsigned int chan;
2464
2465 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2466 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2467 union tgsi_exec_channel dst;
2468
2469 op(&dst);
2470 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2471 }
2472 }
2473 }
2474
2475 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2476 const union tgsi_exec_channel *src);
2477
2478 static void
2479 exec_scalar_unary(struct tgsi_exec_machine *mach,
2480 const struct tgsi_full_instruction *inst,
2481 micro_unary_op op,
2482 enum tgsi_exec_datatype dst_datatype,
2483 enum tgsi_exec_datatype src_datatype)
2484 {
2485 unsigned int chan;
2486 union tgsi_exec_channel src;
2487 union tgsi_exec_channel dst;
2488
2489 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2490 op(&dst, &src);
2491 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2492 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2493 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2494 }
2495 }
2496 }
2497
2498 static void
2499 exec_vector_unary(struct tgsi_exec_machine *mach,
2500 const struct tgsi_full_instruction *inst,
2501 micro_unary_op op,
2502 enum tgsi_exec_datatype dst_datatype,
2503 enum tgsi_exec_datatype src_datatype)
2504 {
2505 unsigned int chan;
2506 struct tgsi_exec_vector dst;
2507
2508 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2509 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2510 union tgsi_exec_channel src;
2511
2512 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2513 op(&dst.xyzw[chan], &src);
2514 }
2515 }
2516 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2517 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2518 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2519 }
2520 }
2521 }
2522
2523 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2524 const union tgsi_exec_channel *src0,
2525 const union tgsi_exec_channel *src1);
2526
2527 static void
2528 exec_scalar_binary(struct tgsi_exec_machine *mach,
2529 const struct tgsi_full_instruction *inst,
2530 micro_binary_op op,
2531 enum tgsi_exec_datatype dst_datatype,
2532 enum tgsi_exec_datatype src_datatype)
2533 {
2534 unsigned int chan;
2535 union tgsi_exec_channel src[2];
2536 union tgsi_exec_channel dst;
2537
2538 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2539 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2540 op(&dst, &src[0], &src[1]);
2541 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2542 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2543 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2544 }
2545 }
2546 }
2547
2548 static void
2549 exec_vector_binary(struct tgsi_exec_machine *mach,
2550 const struct tgsi_full_instruction *inst,
2551 micro_binary_op op,
2552 enum tgsi_exec_datatype dst_datatype,
2553 enum tgsi_exec_datatype src_datatype)
2554 {
2555 unsigned int chan;
2556 struct tgsi_exec_vector dst;
2557
2558 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2559 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2560 union tgsi_exec_channel src[2];
2561
2562 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2563 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2564 op(&dst.xyzw[chan], &src[0], &src[1]);
2565 }
2566 }
2567 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2568 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2569 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2570 }
2571 }
2572 }
2573
2574 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2575 const union tgsi_exec_channel *src0,
2576 const union tgsi_exec_channel *src1,
2577 const union tgsi_exec_channel *src2);
2578
2579 static void
2580 exec_vector_trinary(struct tgsi_exec_machine *mach,
2581 const struct tgsi_full_instruction *inst,
2582 micro_trinary_op op,
2583 enum tgsi_exec_datatype dst_datatype,
2584 enum tgsi_exec_datatype src_datatype)
2585 {
2586 unsigned int chan;
2587 struct tgsi_exec_vector dst;
2588
2589 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2590 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2591 union tgsi_exec_channel src[3];
2592
2593 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2594 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2595 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2596 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2597 }
2598 }
2599 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2600 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2601 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2602 }
2603 }
2604 }
2605
2606 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2607 const union tgsi_exec_channel *src0,
2608 const union tgsi_exec_channel *src1,
2609 const union tgsi_exec_channel *src2,
2610 const union tgsi_exec_channel *src3);
2611
2612 static void
2613 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2614 const struct tgsi_full_instruction *inst,
2615 micro_quaternary_op op,
2616 enum tgsi_exec_datatype dst_datatype,
2617 enum tgsi_exec_datatype src_datatype)
2618 {
2619 unsigned int chan;
2620 struct tgsi_exec_vector dst;
2621
2622 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2623 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2624 union tgsi_exec_channel src[4];
2625
2626 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2627 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2628 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2629 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2630 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2631 }
2632 }
2633 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2634 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2635 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2636 }
2637 }
2638 }
2639
2640 static void
2641 exec_dp3(struct tgsi_exec_machine *mach,
2642 const struct tgsi_full_instruction *inst)
2643 {
2644 unsigned int chan;
2645 union tgsi_exec_channel arg[3];
2646
2647 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2648 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2649 micro_mul(&arg[2], &arg[0], &arg[1]);
2650
2651 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2652 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2653 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2654 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2655 }
2656
2657 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2658 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2659 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2660 }
2661 }
2662 }
2663
2664 static void
2665 exec_dp4(struct tgsi_exec_machine *mach,
2666 const struct tgsi_full_instruction *inst)
2667 {
2668 unsigned int chan;
2669 union tgsi_exec_channel arg[3];
2670
2671 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2672 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2673 micro_mul(&arg[2], &arg[0], &arg[1]);
2674
2675 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2676 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2677 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2678 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2679 }
2680
2681 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2682 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2683 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2684 }
2685 }
2686 }
2687
2688 static void
2689 exec_dp2a(struct tgsi_exec_machine *mach,
2690 const struct tgsi_full_instruction *inst)
2691 {
2692 unsigned int chan;
2693 union tgsi_exec_channel arg[3];
2694
2695 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2696 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2697 micro_mul(&arg[2], &arg[0], &arg[1]);
2698
2699 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2700 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2701 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2702
2703 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2704 micro_add(&arg[0], &arg[0], &arg[1]);
2705
2706 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2707 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2708 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2709 }
2710 }
2711 }
2712
2713 static void
2714 exec_dph(struct tgsi_exec_machine *mach,
2715 const struct tgsi_full_instruction *inst)
2716 {
2717 unsigned int chan;
2718 union tgsi_exec_channel arg[3];
2719
2720 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2721 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2722 micro_mul(&arg[2], &arg[0], &arg[1]);
2723
2724 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2725 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2726 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2727
2728 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2729 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2730 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2731
2732 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2733 micro_add(&arg[0], &arg[0], &arg[1]);
2734
2735 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2736 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2737 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2738 }
2739 }
2740 }
2741
2742 static void
2743 exec_dp2(struct tgsi_exec_machine *mach,
2744 const struct tgsi_full_instruction *inst)
2745 {
2746 unsigned int chan;
2747 union tgsi_exec_channel arg[3];
2748
2749 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2750 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2751 micro_mul(&arg[2], &arg[0], &arg[1]);
2752
2753 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2754 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2755 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2756
2757 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2758 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2759 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2760 }
2761 }
2762 }
2763
2764 static void
2765 exec_nrm4(struct tgsi_exec_machine *mach,
2766 const struct tgsi_full_instruction *inst)
2767 {
2768 unsigned int chan;
2769 union tgsi_exec_channel arg[4];
2770 union tgsi_exec_channel scale;
2771
2772 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2773 micro_mul(&scale, &arg[0], &arg[0]);
2774
2775 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2776 union tgsi_exec_channel product;
2777
2778 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2779 micro_mul(&product, &arg[chan], &arg[chan]);
2780 micro_add(&scale, &scale, &product);
2781 }
2782
2783 micro_rsq(&scale, &scale);
2784
2785 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_W; chan++) {
2786 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2787 micro_mul(&arg[chan], &arg[chan], &scale);
2788 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2789 }
2790 }
2791 }
2792
2793 static void
2794 exec_nrm3(struct tgsi_exec_machine *mach,
2795 const struct tgsi_full_instruction *inst)
2796 {
2797 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2798 unsigned int chan;
2799 union tgsi_exec_channel arg[3];
2800 union tgsi_exec_channel scale;
2801
2802 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2803 micro_mul(&scale, &arg[0], &arg[0]);
2804
2805 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2806 union tgsi_exec_channel product;
2807
2808 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2809 micro_mul(&product, &arg[chan], &arg[chan]);
2810 micro_add(&scale, &scale, &product);
2811 }
2812
2813 micro_rsq(&scale, &scale);
2814
2815 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_Z; chan++) {
2816 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2817 micro_mul(&arg[chan], &arg[chan], &scale);
2818 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2819 }
2820 }
2821 }
2822
2823 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2824 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2825 }
2826 }
2827
2828 static void
2829 exec_scs(struct tgsi_exec_machine *mach,
2830 const struct tgsi_full_instruction *inst)
2831 {
2832 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2833 union tgsi_exec_channel arg;
2834 union tgsi_exec_channel result;
2835
2836 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2837
2838 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2839 micro_cos(&result, &arg);
2840 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2841 }
2842 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2843 micro_sin(&result, &arg);
2844 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2845 }
2846 }
2847 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2848 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2849 }
2850 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2851 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2852 }
2853 }
2854
2855 static void
2856 exec_x2d(struct tgsi_exec_machine *mach,
2857 const struct tgsi_full_instruction *inst)
2858 {
2859 union tgsi_exec_channel r[4];
2860 union tgsi_exec_channel d[2];
2861
2862 fetch_source(mach, &r[0], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2863 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2864 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2865 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2866 micro_mul(&r[2], &r[2], &r[0]);
2867 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2868 micro_mul(&r[3], &r[3], &r[1]);
2869 micro_add(&r[2], &r[2], &r[3]);
2870 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2871 micro_add(&d[0], &r[2], &r[3]);
2872 }
2873 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2874 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2875 micro_mul(&r[2], &r[2], &r[0]);
2876 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2877 micro_mul(&r[3], &r[3], &r[1]);
2878 micro_add(&r[2], &r[2], &r[3]);
2879 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2880 micro_add(&d[1], &r[2], &r[3]);
2881 }
2882 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2883 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2884 }
2885 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2886 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2887 }
2888 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2889 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2890 }
2891 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2892 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2893 }
2894 }
2895
2896 static void
2897 exec_rfl(struct tgsi_exec_machine *mach,
2898 const struct tgsi_full_instruction *inst)
2899 {
2900 union tgsi_exec_channel r[9];
2901
2902 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2903 /* r0 = dp3(src0, src0) */
2904 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2905 micro_mul(&r[0], &r[2], &r[2]);
2906 fetch_source(mach, &r[4], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2907 micro_mul(&r[8], &r[4], &r[4]);
2908 micro_add(&r[0], &r[0], &r[8]);
2909 fetch_source(mach, &r[6], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2910 micro_mul(&r[8], &r[6], &r[6]);
2911 micro_add(&r[0], &r[0], &r[8]);
2912
2913 /* r1 = dp3(src0, src1) */
2914 fetch_source(mach, &r[3], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2915 micro_mul(&r[1], &r[2], &r[3]);
2916 fetch_source(mach, &r[5], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2917 micro_mul(&r[8], &r[4], &r[5]);
2918 micro_add(&r[1], &r[1], &r[8]);
2919 fetch_source(mach, &r[7], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2920 micro_mul(&r[8], &r[6], &r[7]);
2921 micro_add(&r[1], &r[1], &r[8]);
2922
2923 /* r1 = 2 * r1 / r0 */
2924 micro_add(&r[1], &r[1], &r[1]);
2925 micro_div(&r[1], &r[1], &r[0]);
2926
2927 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2928 micro_mul(&r[2], &r[2], &r[1]);
2929 micro_sub(&r[2], &r[2], &r[3]);
2930 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2931 }
2932 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2933 micro_mul(&r[4], &r[4], &r[1]);
2934 micro_sub(&r[4], &r[4], &r[5]);
2935 store_dest(mach, &r[4], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2936 }
2937 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2938 micro_mul(&r[6], &r[6], &r[1]);
2939 micro_sub(&r[6], &r[6], &r[7]);
2940 store_dest(mach, &r[6], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2941 }
2942 }
2943 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2944 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2945 }
2946 }
2947
2948 static void
2949 exec_xpd(struct tgsi_exec_machine *mach,
2950 const struct tgsi_full_instruction *inst)
2951 {
2952 union tgsi_exec_channel r[6];
2953 union tgsi_exec_channel d[3];
2954
2955 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2956 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2957
2958 micro_mul(&r[2], &r[0], &r[1]);
2959
2960 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2961 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2962
2963 micro_mul(&r[5], &r[3], &r[4] );
2964 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
2965
2966 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2967
2968 micro_mul(&r[3], &r[3], &r[2]);
2969
2970 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2971
2972 micro_mul(&r[1], &r[1], &r[5]);
2973 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
2974
2975 micro_mul(&r[5], &r[5], &r[4]);
2976 micro_mul(&r[0], &r[0], &r[2]);
2977 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
2978
2979 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2980 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2981 }
2982 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2983 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2984 }
2985 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2986 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2987 }
2988 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2989 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2990 }
2991 }
2992
2993 static void
2994 exec_dst(struct tgsi_exec_machine *mach,
2995 const struct tgsi_full_instruction *inst)
2996 {
2997 union tgsi_exec_channel r[2];
2998 union tgsi_exec_channel d[4];
2999
3000 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3001 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3002 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3003 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3004 }
3005 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3006 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3007 }
3008 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3009 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3010 }
3011
3012 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3013 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3014 }
3015 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3016 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3017 }
3018 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3019 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3020 }
3021 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3022 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3023 }
3024 }
3025
3026 static void
3027 exec_log(struct tgsi_exec_machine *mach,
3028 const struct tgsi_full_instruction *inst)
3029 {
3030 union tgsi_exec_channel r[3];
3031
3032 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3033 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3034 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3035 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3036 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3037 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3038 }
3039 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3040 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3041 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3042 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3043 }
3044 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3045 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3046 }
3047 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3048 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3049 }
3050 }
3051
3052 static void
3053 exec_exp(struct tgsi_exec_machine *mach,
3054 const struct tgsi_full_instruction *inst)
3055 {
3056 union tgsi_exec_channel r[3];
3057
3058 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3059 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3060 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3061 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3062 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3063 }
3064 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3065 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3066 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3067 }
3068 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3069 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3070 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3071 }
3072 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3073 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3074 }
3075 }
3076
3077 static void
3078 exec_lit(struct tgsi_exec_machine *mach,
3079 const struct tgsi_full_instruction *inst)
3080 {
3081 union tgsi_exec_channel r[3];
3082 union tgsi_exec_channel d[3];
3083
3084 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3085 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3086 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3087 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3088 micro_max(&r[1], &r[1], &ZeroVec);
3089
3090 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3091 micro_min(&r[2], &r[2], &P128Vec);
3092 micro_max(&r[2], &r[2], &M128Vec);
3093 micro_pow(&r[1], &r[1], &r[2]);
3094 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3095 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3096 }
3097 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3098 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3099 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3100 }
3101 }
3102 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3103 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3104 }
3105
3106 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3107 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3108 }
3109 }
3110
3111 static void
3112 exec_break(struct tgsi_exec_machine *mach)
3113 {
3114 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3115 /* turn off loop channels for each enabled exec channel */
3116 mach->LoopMask &= ~mach->ExecMask;
3117 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3118 UPDATE_EXEC_MASK(mach);
3119 } else {
3120 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3121
3122 mach->Switch.mask = 0x0;
3123
3124 UPDATE_EXEC_MASK(mach);
3125 }
3126 }
3127
3128 static void
3129 exec_switch(struct tgsi_exec_machine *mach,
3130 const struct tgsi_full_instruction *inst)
3131 {
3132 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3133 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3134
3135 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3136 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3137 mach->Switch.mask = 0x0;
3138 mach->Switch.defaultMask = 0x0;
3139
3140 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3141 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3142
3143 UPDATE_EXEC_MASK(mach);
3144 }
3145
3146 static void
3147 exec_case(struct tgsi_exec_machine *mach,
3148 const struct tgsi_full_instruction *inst)
3149 {
3150 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3151 union tgsi_exec_channel src;
3152 uint mask = 0;
3153
3154 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3155
3156 if (mach->Switch.selector.u[0] == src.u[0]) {
3157 mask |= 0x1;
3158 }
3159 if (mach->Switch.selector.u[1] == src.u[1]) {
3160 mask |= 0x2;
3161 }
3162 if (mach->Switch.selector.u[2] == src.u[2]) {
3163 mask |= 0x4;
3164 }
3165 if (mach->Switch.selector.u[3] == src.u[3]) {
3166 mask |= 0x8;
3167 }
3168
3169 mach->Switch.defaultMask |= mask;
3170
3171 mach->Switch.mask |= mask & prevMask;
3172
3173 UPDATE_EXEC_MASK(mach);
3174 }
3175
3176 /* FIXME: this will only work if default is last */
3177 static void
3178 exec_default(struct tgsi_exec_machine *mach)
3179 {
3180 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3181
3182 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3183
3184 UPDATE_EXEC_MASK(mach);
3185 }
3186
3187 static void
3188 exec_endswitch(struct tgsi_exec_machine *mach)
3189 {
3190 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3191 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3192
3193 UPDATE_EXEC_MASK(mach);
3194 }
3195
3196 static void
3197 micro_i2f(union tgsi_exec_channel *dst,
3198 const union tgsi_exec_channel *src)
3199 {
3200 dst->f[0] = (float)src->i[0];
3201 dst->f[1] = (float)src->i[1];
3202 dst->f[2] = (float)src->i[2];
3203 dst->f[3] = (float)src->i[3];
3204 }
3205
3206 static void
3207 micro_not(union tgsi_exec_channel *dst,
3208 const union tgsi_exec_channel *src)
3209 {
3210 dst->u[0] = ~src->u[0];
3211 dst->u[1] = ~src->u[1];
3212 dst->u[2] = ~src->u[2];
3213 dst->u[3] = ~src->u[3];
3214 }
3215
3216 static void
3217 micro_shl(union tgsi_exec_channel *dst,
3218 const union tgsi_exec_channel *src0,
3219 const union tgsi_exec_channel *src1)
3220 {
3221 unsigned masked_count;
3222 masked_count = src1->u[0] & 0x1f;
3223 dst->u[0] = src0->u[0] << masked_count;
3224 masked_count = src1->u[1] & 0x1f;
3225 dst->u[1] = src0->u[1] << masked_count;
3226 masked_count = src1->u[2] & 0x1f;
3227 dst->u[2] = src0->u[2] << masked_count;
3228 masked_count = src1->u[3] & 0x1f;
3229 dst->u[3] = src0->u[3] << masked_count;
3230 }
3231
3232 static void
3233 micro_and(union tgsi_exec_channel *dst,
3234 const union tgsi_exec_channel *src0,
3235 const union tgsi_exec_channel *src1)
3236 {
3237 dst->u[0] = src0->u[0] & src1->u[0];
3238 dst->u[1] = src0->u[1] & src1->u[1];
3239 dst->u[2] = src0->u[2] & src1->u[2];
3240 dst->u[3] = src0->u[3] & src1->u[3];
3241 }
3242
3243 static void
3244 micro_or(union tgsi_exec_channel *dst,
3245 const union tgsi_exec_channel *src0,
3246 const union tgsi_exec_channel *src1)
3247 {
3248 dst->u[0] = src0->u[0] | src1->u[0];
3249 dst->u[1] = src0->u[1] | src1->u[1];
3250 dst->u[2] = src0->u[2] | src1->u[2];
3251 dst->u[3] = src0->u[3] | src1->u[3];
3252 }
3253
3254 static void
3255 micro_xor(union tgsi_exec_channel *dst,
3256 const union tgsi_exec_channel *src0,
3257 const union tgsi_exec_channel *src1)
3258 {
3259 dst->u[0] = src0->u[0] ^ src1->u[0];
3260 dst->u[1] = src0->u[1] ^ src1->u[1];
3261 dst->u[2] = src0->u[2] ^ src1->u[2];
3262 dst->u[3] = src0->u[3] ^ src1->u[3];
3263 }
3264
3265 static void
3266 micro_mod(union tgsi_exec_channel *dst,
3267 const union tgsi_exec_channel *src0,
3268 const union tgsi_exec_channel *src1)
3269 {
3270 dst->i[0] = src0->i[0] % src1->i[0];
3271 dst->i[1] = src0->i[1] % src1->i[1];
3272 dst->i[2] = src0->i[2] % src1->i[2];
3273 dst->i[3] = src0->i[3] % src1->i[3];
3274 }
3275
3276 static void
3277 micro_f2i(union tgsi_exec_channel *dst,
3278 const union tgsi_exec_channel *src)
3279 {
3280 dst->i[0] = (int)src->f[0];
3281 dst->i[1] = (int)src->f[1];
3282 dst->i[2] = (int)src->f[2];
3283 dst->i[3] = (int)src->f[3];
3284 }
3285
3286 static void
3287 micro_fseq(union tgsi_exec_channel *dst,
3288 const union tgsi_exec_channel *src0,
3289 const union tgsi_exec_channel *src1)
3290 {
3291 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
3292 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
3293 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
3294 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
3295 }
3296
3297 static void
3298 micro_fsge(union tgsi_exec_channel *dst,
3299 const union tgsi_exec_channel *src0,
3300 const union tgsi_exec_channel *src1)
3301 {
3302 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
3303 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
3304 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
3305 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
3306 }
3307
3308 static void
3309 micro_fslt(union tgsi_exec_channel *dst,
3310 const union tgsi_exec_channel *src0,
3311 const union tgsi_exec_channel *src1)
3312 {
3313 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
3314 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
3315 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
3316 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
3317 }
3318
3319 static void
3320 micro_fsne(union tgsi_exec_channel *dst,
3321 const union tgsi_exec_channel *src0,
3322 const union tgsi_exec_channel *src1)
3323 {
3324 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
3325 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
3326 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
3327 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
3328 }
3329
3330 static void
3331 micro_idiv(union tgsi_exec_channel *dst,
3332 const union tgsi_exec_channel *src0,
3333 const union tgsi_exec_channel *src1)
3334 {
3335 dst->i[0] = src0->i[0] / src1->i[0];
3336 dst->i[1] = src0->i[1] / src1->i[1];
3337 dst->i[2] = src0->i[2] / src1->i[2];
3338 dst->i[3] = src0->i[3] / src1->i[3];
3339 }
3340
3341 static void
3342 micro_imax(union tgsi_exec_channel *dst,
3343 const union tgsi_exec_channel *src0,
3344 const union tgsi_exec_channel *src1)
3345 {
3346 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3347 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3348 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3349 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3350 }
3351
3352 static void
3353 micro_imin(union tgsi_exec_channel *dst,
3354 const union tgsi_exec_channel *src0,
3355 const union tgsi_exec_channel *src1)
3356 {
3357 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3358 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3359 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3360 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3361 }
3362
3363 static void
3364 micro_isge(union tgsi_exec_channel *dst,
3365 const union tgsi_exec_channel *src0,
3366 const union tgsi_exec_channel *src1)
3367 {
3368 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3369 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3370 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3371 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3372 }
3373
3374 static void
3375 micro_ishr(union tgsi_exec_channel *dst,
3376 const union tgsi_exec_channel *src0,
3377 const union tgsi_exec_channel *src1)
3378 {
3379 unsigned masked_count;
3380 masked_count = src1->i[0] & 0x1f;
3381 dst->i[0] = src0->i[0] >> masked_count;
3382 masked_count = src1->i[1] & 0x1f;
3383 dst->i[1] = src0->i[1] >> masked_count;
3384 masked_count = src1->i[2] & 0x1f;
3385 dst->i[2] = src0->i[2] >> masked_count;
3386 masked_count = src1->i[3] & 0x1f;
3387 dst->i[3] = src0->i[3] >> masked_count;
3388 }
3389
3390 static void
3391 micro_islt(union tgsi_exec_channel *dst,
3392 const union tgsi_exec_channel *src0,
3393 const union tgsi_exec_channel *src1)
3394 {
3395 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3396 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3397 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3398 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3399 }
3400
3401 static void
3402 micro_f2u(union tgsi_exec_channel *dst,
3403 const union tgsi_exec_channel *src)
3404 {
3405 dst->u[0] = (uint)src->f[0];
3406 dst->u[1] = (uint)src->f[1];
3407 dst->u[2] = (uint)src->f[2];
3408 dst->u[3] = (uint)src->f[3];
3409 }
3410
3411 static void
3412 micro_u2f(union tgsi_exec_channel *dst,
3413 const union tgsi_exec_channel *src)
3414 {
3415 dst->f[0] = (float)src->u[0];
3416 dst->f[1] = (float)src->u[1];
3417 dst->f[2] = (float)src->u[2];
3418 dst->f[3] = (float)src->u[3];
3419 }
3420
3421 static void
3422 micro_uadd(union tgsi_exec_channel *dst,
3423 const union tgsi_exec_channel *src0,
3424 const union tgsi_exec_channel *src1)
3425 {
3426 dst->u[0] = src0->u[0] + src1->u[0];
3427 dst->u[1] = src0->u[1] + src1->u[1];
3428 dst->u[2] = src0->u[2] + src1->u[2];
3429 dst->u[3] = src0->u[3] + src1->u[3];
3430 }
3431
3432 static void
3433 micro_udiv(union tgsi_exec_channel *dst,
3434 const union tgsi_exec_channel *src0,
3435 const union tgsi_exec_channel *src1)
3436 {
3437 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
3438 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
3439 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
3440 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
3441 }
3442
3443 static void
3444 micro_umad(union tgsi_exec_channel *dst,
3445 const union tgsi_exec_channel *src0,
3446 const union tgsi_exec_channel *src1,
3447 const union tgsi_exec_channel *src2)
3448 {
3449 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3450 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3451 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3452 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3453 }
3454
3455 static void
3456 micro_umax(union tgsi_exec_channel *dst,
3457 const union tgsi_exec_channel *src0,
3458 const union tgsi_exec_channel *src1)
3459 {
3460 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3461 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3462 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3463 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3464 }
3465
3466 static void
3467 micro_umin(union tgsi_exec_channel *dst,
3468 const union tgsi_exec_channel *src0,
3469 const union tgsi_exec_channel *src1)
3470 {
3471 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3472 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3473 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3474 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3475 }
3476
3477 static void
3478 micro_umod(union tgsi_exec_channel *dst,
3479 const union tgsi_exec_channel *src0,
3480 const union tgsi_exec_channel *src1)
3481 {
3482 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
3483 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
3484 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
3485 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
3486 }
3487
3488 static void
3489 micro_umul(union tgsi_exec_channel *dst,
3490 const union tgsi_exec_channel *src0,
3491 const union tgsi_exec_channel *src1)
3492 {
3493 dst->u[0] = src0->u[0] * src1->u[0];
3494 dst->u[1] = src0->u[1] * src1->u[1];
3495 dst->u[2] = src0->u[2] * src1->u[2];
3496 dst->u[3] = src0->u[3] * src1->u[3];
3497 }
3498
3499 static void
3500 micro_imul_hi(union tgsi_exec_channel *dst,
3501 const union tgsi_exec_channel *src0,
3502 const union tgsi_exec_channel *src1)
3503 {
3504 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3505 dst->i[0] = I64M(src0->i[0], src1->i[0]);
3506 dst->i[1] = I64M(src0->i[1], src1->i[1]);
3507 dst->i[2] = I64M(src0->i[2], src1->i[2]);
3508 dst->i[3] = I64M(src0->i[3], src1->i[3]);
3509 #undef I64M
3510 }
3511
3512 static void
3513 micro_umul_hi(union tgsi_exec_channel *dst,
3514 const union tgsi_exec_channel *src0,
3515 const union tgsi_exec_channel *src1)
3516 {
3517 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3518 dst->u[0] = U64M(src0->u[0], src1->u[0]);
3519 dst->u[1] = U64M(src0->u[1], src1->u[1]);
3520 dst->u[2] = U64M(src0->u[2], src1->u[2]);
3521 dst->u[3] = U64M(src0->u[3], src1->u[3]);
3522 #undef U64M
3523 }
3524
3525 static void
3526 micro_useq(union tgsi_exec_channel *dst,
3527 const union tgsi_exec_channel *src0,
3528 const union tgsi_exec_channel *src1)
3529 {
3530 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3531 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3532 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3533 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3534 }
3535
3536 static void
3537 micro_usge(union tgsi_exec_channel *dst,
3538 const union tgsi_exec_channel *src0,
3539 const union tgsi_exec_channel *src1)
3540 {
3541 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3542 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3543 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3544 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3545 }
3546
3547 static void
3548 micro_ushr(union tgsi_exec_channel *dst,
3549 const union tgsi_exec_channel *src0,
3550 const union tgsi_exec_channel *src1)
3551 {
3552 unsigned masked_count;
3553 masked_count = src1->u[0] & 0x1f;
3554 dst->u[0] = src0->u[0] >> masked_count;
3555 masked_count = src1->u[1] & 0x1f;
3556 dst->u[1] = src0->u[1] >> masked_count;
3557 masked_count = src1->u[2] & 0x1f;
3558 dst->u[2] = src0->u[2] >> masked_count;
3559 masked_count = src1->u[3] & 0x1f;
3560 dst->u[3] = src0->u[3] >> masked_count;
3561 }
3562
3563 static void
3564 micro_uslt(union tgsi_exec_channel *dst,
3565 const union tgsi_exec_channel *src0,
3566 const union tgsi_exec_channel *src1)
3567 {
3568 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3569 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3570 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3571 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3572 }
3573
3574 static void
3575 micro_usne(union tgsi_exec_channel *dst,
3576 const union tgsi_exec_channel *src0,
3577 const union tgsi_exec_channel *src1)
3578 {
3579 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3580 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3581 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3582 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3583 }
3584
3585 static void
3586 micro_uarl(union tgsi_exec_channel *dst,
3587 const union tgsi_exec_channel *src)
3588 {
3589 dst->i[0] = src->u[0];
3590 dst->i[1] = src->u[1];
3591 dst->i[2] = src->u[2];
3592 dst->i[3] = src->u[3];
3593 }
3594
3595 static void
3596 micro_ucmp(union tgsi_exec_channel *dst,
3597 const union tgsi_exec_channel *src0,
3598 const union tgsi_exec_channel *src1,
3599 const union tgsi_exec_channel *src2)
3600 {
3601 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3602 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3603 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3604 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3605 }
3606
3607 /**
3608 * Signed bitfield extract (i.e. sign-extend the extracted bits)
3609 */
3610 static void
3611 micro_ibfe(union tgsi_exec_channel *dst,
3612 const union tgsi_exec_channel *src0,
3613 const union tgsi_exec_channel *src1,
3614 const union tgsi_exec_channel *src2)
3615 {
3616 int i;
3617 for (i = 0; i < 4; i++) {
3618 int width = src2->i[i] & 0x1f;
3619 int offset = src1->i[i] & 0x1f;
3620 if (width == 0)
3621 dst->i[i] = 0;
3622 else if (width + offset < 32)
3623 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
3624 else
3625 dst->i[i] = src0->i[i] >> offset;
3626 }
3627 }
3628
3629 /**
3630 * Unsigned bitfield extract
3631 */
3632 static void
3633 micro_ubfe(union tgsi_exec_channel *dst,
3634 const union tgsi_exec_channel *src0,
3635 const union tgsi_exec_channel *src1,
3636 const union tgsi_exec_channel *src2)
3637 {
3638 int i;
3639 for (i = 0; i < 4; i++) {
3640 int width = src2->u[i] & 0x1f;
3641 int offset = src1->u[i] & 0x1f;
3642 if (width == 0)
3643 dst->u[i] = 0;
3644 else if (width + offset < 32)
3645 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
3646 else
3647 dst->u[i] = src0->u[i] >> offset;
3648 }
3649 }
3650
3651 /**
3652 * Bitfield insert: copy low bits from src1 into a region of src0.
3653 */
3654 static void
3655 micro_bfi(union tgsi_exec_channel *dst,
3656 const union tgsi_exec_channel *src0,
3657 const union tgsi_exec_channel *src1,
3658 const union tgsi_exec_channel *src2,
3659 const union tgsi_exec_channel *src3)
3660 {
3661 int i;
3662 for (i = 0; i < 4; i++) {
3663 int width = src3->u[i] & 0x1f;
3664 int offset = src2->u[i] & 0x1f;
3665 int bitmask = ((1 << width) - 1) << offset;
3666 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
3667 }
3668 }
3669
3670 static void
3671 micro_brev(union tgsi_exec_channel *dst,
3672 const union tgsi_exec_channel *src)
3673 {
3674 dst->u[0] = util_bitreverse(src->u[0]);
3675 dst->u[1] = util_bitreverse(src->u[1]);
3676 dst->u[2] = util_bitreverse(src->u[2]);
3677 dst->u[3] = util_bitreverse(src->u[3]);
3678 }
3679
3680 static void
3681 micro_popc(union tgsi_exec_channel *dst,
3682 const union tgsi_exec_channel *src)
3683 {
3684 dst->u[0] = util_bitcount(src->u[0]);
3685 dst->u[1] = util_bitcount(src->u[1]);
3686 dst->u[2] = util_bitcount(src->u[2]);
3687 dst->u[3] = util_bitcount(src->u[3]);
3688 }
3689
3690 static void
3691 micro_lsb(union tgsi_exec_channel *dst,
3692 const union tgsi_exec_channel *src)
3693 {
3694 dst->i[0] = ffs(src->u[0]) - 1;
3695 dst->i[1] = ffs(src->u[1]) - 1;
3696 dst->i[2] = ffs(src->u[2]) - 1;
3697 dst->i[3] = ffs(src->u[3]) - 1;
3698 }
3699
3700 static void
3701 micro_imsb(union tgsi_exec_channel *dst,
3702 const union tgsi_exec_channel *src)
3703 {
3704 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
3705 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
3706 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
3707 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
3708 }
3709
3710 static void
3711 micro_umsb(union tgsi_exec_channel *dst,
3712 const union tgsi_exec_channel *src)
3713 {
3714 dst->i[0] = util_last_bit(src->u[0]) - 1;
3715 dst->i[1] = util_last_bit(src->u[1]) - 1;
3716 dst->i[2] = util_last_bit(src->u[2]) - 1;
3717 dst->i[3] = util_last_bit(src->u[3]) - 1;
3718 }
3719
3720 static void
3721 exec_instruction(
3722 struct tgsi_exec_machine *mach,
3723 const struct tgsi_full_instruction *inst,
3724 int *pc )
3725 {
3726 union tgsi_exec_channel r[10];
3727
3728 (*pc)++;
3729
3730 switch (inst->Instruction.Opcode) {
3731 case TGSI_OPCODE_ARL:
3732 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3733 break;
3734
3735 case TGSI_OPCODE_MOV:
3736 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3737 break;
3738
3739 case TGSI_OPCODE_LIT:
3740 exec_lit(mach, inst);
3741 break;
3742
3743 case TGSI_OPCODE_RCP:
3744 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3745 break;
3746
3747 case TGSI_OPCODE_RSQ:
3748 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3749 break;
3750
3751 case TGSI_OPCODE_EXP:
3752 exec_exp(mach, inst);
3753 break;
3754
3755 case TGSI_OPCODE_LOG:
3756 exec_log(mach, inst);
3757 break;
3758
3759 case TGSI_OPCODE_MUL:
3760 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3761 break;
3762
3763 case TGSI_OPCODE_ADD:
3764 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3765 break;
3766
3767 case TGSI_OPCODE_DP3:
3768 exec_dp3(mach, inst);
3769 break;
3770
3771 case TGSI_OPCODE_DP4:
3772 exec_dp4(mach, inst);
3773 break;
3774
3775 case TGSI_OPCODE_DST:
3776 exec_dst(mach, inst);
3777 break;
3778
3779 case TGSI_OPCODE_MIN:
3780 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3781 break;
3782
3783 case TGSI_OPCODE_MAX:
3784 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3785 break;
3786
3787 case TGSI_OPCODE_SLT:
3788 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3789 break;
3790
3791 case TGSI_OPCODE_SGE:
3792 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3793 break;
3794
3795 case TGSI_OPCODE_MAD:
3796 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3797 break;
3798
3799 case TGSI_OPCODE_SUB:
3800 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3801 break;
3802
3803 case TGSI_OPCODE_LRP:
3804 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3805 break;
3806
3807 case TGSI_OPCODE_CND:
3808 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3809 break;
3810
3811 case TGSI_OPCODE_SQRT:
3812 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3813 break;
3814
3815 case TGSI_OPCODE_DP2A:
3816 exec_dp2a(mach, inst);
3817 break;
3818
3819 case TGSI_OPCODE_FRC:
3820 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3821 break;
3822
3823 case TGSI_OPCODE_CLAMP:
3824 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3825 break;
3826
3827 case TGSI_OPCODE_FLR:
3828 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3829 break;
3830
3831 case TGSI_OPCODE_ROUND:
3832 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3833 break;
3834
3835 case TGSI_OPCODE_EX2:
3836 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3837 break;
3838
3839 case TGSI_OPCODE_LG2:
3840 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3841 break;
3842
3843 case TGSI_OPCODE_POW:
3844 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3845 break;
3846
3847 case TGSI_OPCODE_XPD:
3848 exec_xpd(mach, inst);
3849 break;
3850
3851 case TGSI_OPCODE_ABS:
3852 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3853 break;
3854
3855 case TGSI_OPCODE_RCC:
3856 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3857 break;
3858
3859 case TGSI_OPCODE_DPH:
3860 exec_dph(mach, inst);
3861 break;
3862
3863 case TGSI_OPCODE_COS:
3864 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3865 break;
3866
3867 case TGSI_OPCODE_DDX:
3868 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3869 break;
3870
3871 case TGSI_OPCODE_DDY:
3872 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3873 break;
3874
3875 case TGSI_OPCODE_KILL:
3876 exec_kill (mach, inst);
3877 break;
3878
3879 case TGSI_OPCODE_KILL_IF:
3880 exec_kill_if (mach, inst);
3881 break;
3882
3883 case TGSI_OPCODE_PK2H:
3884 assert (0);
3885 break;
3886
3887 case TGSI_OPCODE_PK2US:
3888 assert (0);
3889 break;
3890
3891 case TGSI_OPCODE_PK4B:
3892 assert (0);
3893 break;
3894
3895 case TGSI_OPCODE_PK4UB:
3896 assert (0);
3897 break;
3898
3899 case TGSI_OPCODE_RFL:
3900 exec_rfl(mach, inst);
3901 break;
3902
3903 case TGSI_OPCODE_SEQ:
3904 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3905 break;
3906
3907 case TGSI_OPCODE_SFL:
3908 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3909 break;
3910
3911 case TGSI_OPCODE_SGT:
3912 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3913 break;
3914
3915 case TGSI_OPCODE_SIN:
3916 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3917 break;
3918
3919 case TGSI_OPCODE_SLE:
3920 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3921 break;
3922
3923 case TGSI_OPCODE_SNE:
3924 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3925 break;
3926
3927 case TGSI_OPCODE_STR:
3928 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3929 break;
3930
3931 case TGSI_OPCODE_TEX:
3932 /* simple texture lookup */
3933 /* src[0] = texcoord */
3934 /* src[1] = sampler unit */
3935 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
3936 break;
3937
3938 case TGSI_OPCODE_TXB:
3939 /* Texture lookup with lod bias */
3940 /* src[0] = texcoord (src[0].w = LOD bias) */
3941 /* src[1] = sampler unit */
3942 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
3943 break;
3944
3945 case TGSI_OPCODE_TXD:
3946 /* Texture lookup with explict partial derivatives */
3947 /* src[0] = texcoord */
3948 /* src[1] = d[strq]/dx */
3949 /* src[2] = d[strq]/dy */
3950 /* src[3] = sampler unit */
3951 exec_txd(mach, inst);
3952 break;
3953
3954 case TGSI_OPCODE_TXL:
3955 /* Texture lookup with explit LOD */
3956 /* src[0] = texcoord (src[0].w = LOD) */
3957 /* src[1] = sampler unit */
3958 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
3959 break;
3960
3961 case TGSI_OPCODE_TXP:
3962 /* Texture lookup with projection */
3963 /* src[0] = texcoord (src[0].w = projection) */
3964 /* src[1] = sampler unit */
3965 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
3966 break;
3967
3968 case TGSI_OPCODE_UP2H:
3969 assert (0);
3970 break;
3971
3972 case TGSI_OPCODE_UP2US:
3973 assert (0);
3974 break;
3975
3976 case TGSI_OPCODE_UP4B:
3977 assert (0);
3978 break;
3979
3980 case TGSI_OPCODE_UP4UB:
3981 assert (0);
3982 break;
3983
3984 case TGSI_OPCODE_X2D:
3985 exec_x2d(mach, inst);
3986 break;
3987
3988 case TGSI_OPCODE_ARA:
3989 assert (0);
3990 break;
3991
3992 case TGSI_OPCODE_ARR:
3993 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3994 break;
3995
3996 case TGSI_OPCODE_BRA:
3997 assert (0);
3998 break;
3999
4000 case TGSI_OPCODE_CAL:
4001 /* skip the call if no execution channels are enabled */
4002 if (mach->ExecMask) {
4003 /* do the call */
4004
4005 /* First, record the depths of the execution stacks.
4006 * This is important for deeply nested/looped return statements.
4007 * We have to unwind the stacks by the correct amount. For a
4008 * real code generator, we could determine the number of entries
4009 * to pop off each stack with simple static analysis and avoid
4010 * implementing this data structure at run time.
4011 */
4012 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
4013 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
4014 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
4015 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
4016 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
4017 /* note that PC was already incremented above */
4018 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
4019
4020 mach->CallStackTop++;
4021
4022 /* Second, push the Cond, Loop, Cont, Func stacks */
4023 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4024 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4025 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4026 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
4027 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4028 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
4029
4030 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4031 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4032 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4033 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
4034 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4035 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
4036
4037 /* Finally, jump to the subroutine */
4038 *pc = inst->Label.Label;
4039 }
4040 break;
4041
4042 case TGSI_OPCODE_RET:
4043 mach->FuncMask &= ~mach->ExecMask;
4044 UPDATE_EXEC_MASK(mach);
4045
4046 if (mach->FuncMask == 0x0) {
4047 /* really return now (otherwise, keep executing */
4048
4049 if (mach->CallStackTop == 0) {
4050 /* returning from main() */
4051 mach->CondStackTop = 0;
4052 mach->LoopStackTop = 0;
4053 *pc = -1;
4054 return;
4055 }
4056
4057 assert(mach->CallStackTop > 0);
4058 mach->CallStackTop--;
4059
4060 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4061 mach->CondMask = mach->CondStack[mach->CondStackTop];
4062
4063 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4064 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4065
4066 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4067 mach->ContMask = mach->ContStack[mach->ContStackTop];
4068
4069 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4070 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4071
4072 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4073 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4074
4075 assert(mach->FuncStackTop > 0);
4076 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4077
4078 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4079
4080 UPDATE_EXEC_MASK(mach);
4081 }
4082 break;
4083
4084 case TGSI_OPCODE_SSG:
4085 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4086 break;
4087
4088 case TGSI_OPCODE_CMP:
4089 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4090 break;
4091
4092 case TGSI_OPCODE_SCS:
4093 exec_scs(mach, inst);
4094 break;
4095
4096 case TGSI_OPCODE_NRM:
4097 exec_nrm3(mach, inst);
4098 break;
4099
4100 case TGSI_OPCODE_NRM4:
4101 exec_nrm4(mach, inst);
4102 break;
4103
4104 case TGSI_OPCODE_DIV:
4105 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4106 break;
4107
4108 case TGSI_OPCODE_DP2:
4109 exec_dp2(mach, inst);
4110 break;
4111
4112 case TGSI_OPCODE_IF:
4113 /* push CondMask */
4114 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4115 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4116 FETCH( &r[0], 0, TGSI_CHAN_X );
4117 /* update CondMask */
4118 if( ! r[0].f[0] ) {
4119 mach->CondMask &= ~0x1;
4120 }
4121 if( ! r[0].f[1] ) {
4122 mach->CondMask &= ~0x2;
4123 }
4124 if( ! r[0].f[2] ) {
4125 mach->CondMask &= ~0x4;
4126 }
4127 if( ! r[0].f[3] ) {
4128 mach->CondMask &= ~0x8;
4129 }
4130 UPDATE_EXEC_MASK(mach);
4131 /* Todo: If CondMask==0, jump to ELSE */
4132 break;
4133
4134 case TGSI_OPCODE_UIF:
4135 /* push CondMask */
4136 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4137 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4138 IFETCH( &r[0], 0, TGSI_CHAN_X );
4139 /* update CondMask */
4140 if( ! r[0].u[0] ) {
4141 mach->CondMask &= ~0x1;
4142 }
4143 if( ! r[0].u[1] ) {
4144 mach->CondMask &= ~0x2;
4145 }
4146 if( ! r[0].u[2] ) {
4147 mach->CondMask &= ~0x4;
4148 }
4149 if( ! r[0].u[3] ) {
4150 mach->CondMask &= ~0x8;
4151 }
4152 UPDATE_EXEC_MASK(mach);
4153 /* Todo: If CondMask==0, jump to ELSE */
4154 break;
4155
4156 case TGSI_OPCODE_ELSE:
4157 /* invert CondMask wrt previous mask */
4158 {
4159 uint prevMask;
4160 assert(mach->CondStackTop > 0);
4161 prevMask = mach->CondStack[mach->CondStackTop - 1];
4162 mach->CondMask = ~mach->CondMask & prevMask;
4163 UPDATE_EXEC_MASK(mach);
4164 /* Todo: If CondMask==0, jump to ENDIF */
4165 }
4166 break;
4167
4168 case TGSI_OPCODE_ENDIF:
4169 /* pop CondMask */
4170 assert(mach->CondStackTop > 0);
4171 mach->CondMask = mach->CondStack[--mach->CondStackTop];
4172 UPDATE_EXEC_MASK(mach);
4173 break;
4174
4175 case TGSI_OPCODE_END:
4176 /* make sure we end primitives which haven't
4177 * been explicitly emitted */
4178 conditional_emit_primitive(mach);
4179 /* halt execution */
4180 *pc = -1;
4181 break;
4182
4183 case TGSI_OPCODE_PUSHA:
4184 assert (0);
4185 break;
4186
4187 case TGSI_OPCODE_POPA:
4188 assert (0);
4189 break;
4190
4191 case TGSI_OPCODE_CEIL:
4192 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4193 break;
4194
4195 case TGSI_OPCODE_I2F:
4196 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
4197 break;
4198
4199 case TGSI_OPCODE_NOT:
4200 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4201 break;
4202
4203 case TGSI_OPCODE_TRUNC:
4204 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4205 break;
4206
4207 case TGSI_OPCODE_SHL:
4208 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4209 break;
4210
4211 case TGSI_OPCODE_AND:
4212 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4213 break;
4214
4215 case TGSI_OPCODE_OR:
4216 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4217 break;
4218
4219 case TGSI_OPCODE_MOD:
4220 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4221 break;
4222
4223 case TGSI_OPCODE_XOR:
4224 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4225 break;
4226
4227 case TGSI_OPCODE_SAD:
4228 assert (0);
4229 break;
4230
4231 case TGSI_OPCODE_TXF:
4232 exec_txf(mach, inst);
4233 break;
4234
4235 case TGSI_OPCODE_TXQ:
4236 exec_txq(mach, inst);
4237 break;
4238
4239 case TGSI_OPCODE_EMIT:
4240 emit_vertex(mach);
4241 break;
4242
4243 case TGSI_OPCODE_ENDPRIM:
4244 emit_primitive(mach);
4245 break;
4246
4247 case TGSI_OPCODE_BGNLOOP:
4248 /* push LoopMask and ContMasks */
4249 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4250 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4251 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4252 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4253
4254 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4255 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4256 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4257 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4258 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4259 break;
4260
4261 case TGSI_OPCODE_ENDLOOP:
4262 /* Restore ContMask, but don't pop */
4263 assert(mach->ContStackTop > 0);
4264 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4265 UPDATE_EXEC_MASK(mach);
4266 if (mach->ExecMask) {
4267 /* repeat loop: jump to instruction just past BGNLOOP */
4268 assert(mach->LoopLabelStackTop > 0);
4269 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4270 }
4271 else {
4272 /* exit loop: pop LoopMask */
4273 assert(mach->LoopStackTop > 0);
4274 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4275 /* pop ContMask */
4276 assert(mach->ContStackTop > 0);
4277 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4278 assert(mach->LoopLabelStackTop > 0);
4279 --mach->LoopLabelStackTop;
4280
4281 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4282 }
4283 UPDATE_EXEC_MASK(mach);
4284 break;
4285
4286 case TGSI_OPCODE_BRK:
4287 exec_break(mach);
4288 break;
4289
4290 case TGSI_OPCODE_CONT:
4291 /* turn off cont channels for each enabled exec channel */
4292 mach->ContMask &= ~mach->ExecMask;
4293 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4294 UPDATE_EXEC_MASK(mach);
4295 break;
4296
4297 case TGSI_OPCODE_BGNSUB:
4298 /* no-op */
4299 break;
4300
4301 case TGSI_OPCODE_ENDSUB:
4302 /*
4303 * XXX: This really should be a no-op. We should never reach this opcode.
4304 */
4305
4306 assert(mach->CallStackTop > 0);
4307 mach->CallStackTop--;
4308
4309 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4310 mach->CondMask = mach->CondStack[mach->CondStackTop];
4311
4312 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4313 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4314
4315 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4316 mach->ContMask = mach->ContStack[mach->ContStackTop];
4317
4318 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4319 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4320
4321 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4322 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4323
4324 assert(mach->FuncStackTop > 0);
4325 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4326
4327 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4328
4329 UPDATE_EXEC_MASK(mach);
4330 break;
4331
4332 case TGSI_OPCODE_NOP:
4333 break;
4334
4335 case TGSI_OPCODE_BREAKC:
4336 IFETCH(&r[0], 0, TGSI_CHAN_X);
4337 /* update CondMask */
4338 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4339 mach->LoopMask &= ~0x1;
4340 }
4341 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4342 mach->LoopMask &= ~0x2;
4343 }
4344 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4345 mach->LoopMask &= ~0x4;
4346 }
4347 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4348 mach->LoopMask &= ~0x8;
4349 }
4350 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4351 UPDATE_EXEC_MASK(mach);
4352 break;
4353
4354 case TGSI_OPCODE_F2I:
4355 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4356 break;
4357
4358 case TGSI_OPCODE_FSEQ:
4359 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4360 break;
4361
4362 case TGSI_OPCODE_FSGE:
4363 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4364 break;
4365
4366 case TGSI_OPCODE_FSLT:
4367 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4368 break;
4369
4370 case TGSI_OPCODE_FSNE:
4371 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4372 break;
4373
4374 case TGSI_OPCODE_IDIV:
4375 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4376 break;
4377
4378 case TGSI_OPCODE_IMAX:
4379 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4380 break;
4381
4382 case TGSI_OPCODE_IMIN:
4383 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4384 break;
4385
4386 case TGSI_OPCODE_INEG:
4387 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4388 break;
4389
4390 case TGSI_OPCODE_ISGE:
4391 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4392 break;
4393
4394 case TGSI_OPCODE_ISHR:
4395 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4396 break;
4397
4398 case TGSI_OPCODE_ISLT:
4399 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4400 break;
4401
4402 case TGSI_OPCODE_F2U:
4403 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4404 break;
4405
4406 case TGSI_OPCODE_U2F:
4407 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4408 break;
4409
4410 case TGSI_OPCODE_UADD:
4411 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4412 break;
4413
4414 case TGSI_OPCODE_UDIV:
4415 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4416 break;
4417
4418 case TGSI_OPCODE_UMAD:
4419 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4420 break;
4421
4422 case TGSI_OPCODE_UMAX:
4423 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4424 break;
4425
4426 case TGSI_OPCODE_UMIN:
4427 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4428 break;
4429
4430 case TGSI_OPCODE_UMOD:
4431 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4432 break;
4433
4434 case TGSI_OPCODE_UMUL:
4435 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4436 break;
4437
4438 case TGSI_OPCODE_IMUL_HI:
4439 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4440 break;
4441
4442 case TGSI_OPCODE_UMUL_HI:
4443 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4444 break;
4445
4446 case TGSI_OPCODE_USEQ:
4447 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4448 break;
4449
4450 case TGSI_OPCODE_USGE:
4451 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4452 break;
4453
4454 case TGSI_OPCODE_USHR:
4455 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4456 break;
4457
4458 case TGSI_OPCODE_USLT:
4459 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4460 break;
4461
4462 case TGSI_OPCODE_USNE:
4463 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4464 break;
4465
4466 case TGSI_OPCODE_SWITCH:
4467 exec_switch(mach, inst);
4468 break;
4469
4470 case TGSI_OPCODE_CASE:
4471 exec_case(mach, inst);
4472 break;
4473
4474 case TGSI_OPCODE_DEFAULT:
4475 exec_default(mach);
4476 break;
4477
4478 case TGSI_OPCODE_ENDSWITCH:
4479 exec_endswitch(mach);
4480 break;
4481
4482 case TGSI_OPCODE_SAMPLE_I:
4483 exec_txf(mach, inst);
4484 break;
4485
4486 case TGSI_OPCODE_SAMPLE_I_MS:
4487 assert(0);
4488 break;
4489
4490 case TGSI_OPCODE_SAMPLE:
4491 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4492 break;
4493
4494 case TGSI_OPCODE_SAMPLE_B:
4495 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4496 break;
4497
4498 case TGSI_OPCODE_SAMPLE_C:
4499 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4500 break;
4501
4502 case TGSI_OPCODE_SAMPLE_C_LZ:
4503 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4504 break;
4505
4506 case TGSI_OPCODE_SAMPLE_D:
4507 exec_sample_d(mach, inst);
4508 break;
4509
4510 case TGSI_OPCODE_SAMPLE_L:
4511 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4512 break;
4513
4514 case TGSI_OPCODE_GATHER4:
4515 assert(0);
4516 break;
4517
4518 case TGSI_OPCODE_SVIEWINFO:
4519 exec_txq(mach, inst);
4520 break;
4521
4522 case TGSI_OPCODE_SAMPLE_POS:
4523 assert(0);
4524 break;
4525
4526 case TGSI_OPCODE_SAMPLE_INFO:
4527 assert(0);
4528 break;
4529
4530 case TGSI_OPCODE_UARL:
4531 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4532 break;
4533
4534 case TGSI_OPCODE_UCMP:
4535 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4536 break;
4537
4538 case TGSI_OPCODE_IABS:
4539 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4540 break;
4541
4542 case TGSI_OPCODE_ISSG:
4543 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4544 break;
4545
4546 case TGSI_OPCODE_TEX2:
4547 /* simple texture lookup */
4548 /* src[0] = texcoord */
4549 /* src[1] = compare */
4550 /* src[2] = sampler unit */
4551 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4552 break;
4553 case TGSI_OPCODE_TXB2:
4554 /* simple texture lookup */
4555 /* src[0] = texcoord */
4556 /* src[1] = bias */
4557 /* src[2] = sampler unit */
4558 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4559 break;
4560 case TGSI_OPCODE_TXL2:
4561 /* simple texture lookup */
4562 /* src[0] = texcoord */
4563 /* src[1] = lod */
4564 /* src[2] = sampler unit */
4565 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4566 break;
4567
4568 case TGSI_OPCODE_IBFE:
4569 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4570 break;
4571 case TGSI_OPCODE_UBFE:
4572 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4573 break;
4574 case TGSI_OPCODE_BFI:
4575 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4576 break;
4577 case TGSI_OPCODE_BREV:
4578 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4579 break;
4580 case TGSI_OPCODE_POPC:
4581 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4582 break;
4583 case TGSI_OPCODE_LSB:
4584 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4585 break;
4586 case TGSI_OPCODE_IMSB:
4587 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4588 break;
4589 case TGSI_OPCODE_UMSB:
4590 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4591 break;
4592 default:
4593 assert( 0 );
4594 }
4595 }
4596
4597
4598 /**
4599 * Run TGSI interpreter.
4600 * \return bitmask of "alive" quad components
4601 */
4602 uint
4603 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4604 {
4605 uint i;
4606 int pc = 0;
4607 uint default_mask = 0xf;
4608
4609 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4610 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4611
4612 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4613 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4614 mach->Primitives[0] = 0;
4615 /* GS runs on a single primitive for now */
4616 default_mask = 0x1;
4617 }
4618
4619 mach->CondMask = default_mask;
4620 mach->LoopMask = default_mask;
4621 mach->ContMask = default_mask;
4622 mach->FuncMask = default_mask;
4623 mach->ExecMask = default_mask;
4624
4625 mach->Switch.mask = default_mask;
4626
4627 assert(mach->CondStackTop == 0);
4628 assert(mach->LoopStackTop == 0);
4629 assert(mach->ContStackTop == 0);
4630 assert(mach->SwitchStackTop == 0);
4631 assert(mach->BreakStackTop == 0);
4632 assert(mach->CallStackTop == 0);
4633
4634
4635 /* execute declarations (interpolants) */
4636 for (i = 0; i < mach->NumDeclarations; i++) {
4637 exec_declaration( mach, mach->Declarations+i );
4638 }
4639
4640 {
4641 #if DEBUG_EXECUTION
4642 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4643 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4644 uint inst = 1;
4645
4646 memset(mach->Temps, 0, sizeof(temps));
4647 memset(mach->Outputs, 0, sizeof(outputs));
4648 memset(temps, 0, sizeof(temps));
4649 memset(outputs, 0, sizeof(outputs));
4650 #endif
4651
4652 /* execute instructions, until pc is set to -1 */
4653 while (pc != -1) {
4654
4655 #if DEBUG_EXECUTION
4656 uint i;
4657
4658 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4659 #endif
4660
4661 assert(pc < (int) mach->NumInstructions);
4662 exec_instruction(mach, mach->Instructions + pc, &pc);
4663
4664 #if DEBUG_EXECUTION
4665 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4666 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4667 uint j;
4668
4669 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4670 debug_printf("TEMP[%2u] = ", i);
4671 for (j = 0; j < 4; j++) {
4672 if (j > 0) {
4673 debug_printf(" ");
4674 }
4675 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4676 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4677 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4678 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4679 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4680 }
4681 }
4682 }
4683 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4684 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4685 uint j;
4686
4687 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4688 debug_printf("OUT[%2u] = ", i);
4689 for (j = 0; j < 4; j++) {
4690 if (j > 0) {
4691 debug_printf(" ");
4692 }
4693 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4694 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4695 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4696 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4697 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4698 }
4699 }
4700 }
4701 #endif
4702 }
4703 }
4704
4705 #if 0
4706 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4707 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4708 /*
4709 * Scale back depth component.
4710 */
4711 for (i = 0; i < 4; i++)
4712 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4713 }
4714 #endif
4715
4716 /* Strictly speaking, these assertions aren't really needed but they
4717 * can potentially catch some bugs in the control flow code.
4718 */
4719 assert(mach->CondStackTop == 0);
4720 assert(mach->LoopStackTop == 0);
4721 assert(mach->ContStackTop == 0);
4722 assert(mach->SwitchStackTop == 0);
4723 assert(mach->BreakStackTop == 0);
4724 assert(mach->CallStackTop == 0);
4725
4726 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4727 }