1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
65 #define DEBUG_EXECUTION 0
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
75 union tgsi_double_channel
{
76 double d
[TGSI_QUAD_SIZE
];
77 unsigned u
[TGSI_QUAD_SIZE
][2];
80 struct tgsi_double_vector
{
81 union tgsi_double_channel xy
;
82 union tgsi_double_channel zw
;
86 micro_abs(union tgsi_exec_channel
*dst
,
87 const union tgsi_exec_channel
*src
)
89 dst
->f
[0] = fabsf(src
->f
[0]);
90 dst
->f
[1] = fabsf(src
->f
[1]);
91 dst
->f
[2] = fabsf(src
->f
[2]);
92 dst
->f
[3] = fabsf(src
->f
[3]);
96 micro_arl(union tgsi_exec_channel
*dst
,
97 const union tgsi_exec_channel
*src
)
99 dst
->i
[0] = (int)floorf(src
->f
[0]);
100 dst
->i
[1] = (int)floorf(src
->f
[1]);
101 dst
->i
[2] = (int)floorf(src
->f
[2]);
102 dst
->i
[3] = (int)floorf(src
->f
[3]);
106 micro_arr(union tgsi_exec_channel
*dst
,
107 const union tgsi_exec_channel
*src
)
109 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
110 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
111 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
112 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
116 micro_ceil(union tgsi_exec_channel
*dst
,
117 const union tgsi_exec_channel
*src
)
119 dst
->f
[0] = ceilf(src
->f
[0]);
120 dst
->f
[1] = ceilf(src
->f
[1]);
121 dst
->f
[2] = ceilf(src
->f
[2]);
122 dst
->f
[3] = ceilf(src
->f
[3]);
126 micro_clamp(union tgsi_exec_channel
*dst
,
127 const union tgsi_exec_channel
*src0
,
128 const union tgsi_exec_channel
*src1
,
129 const union tgsi_exec_channel
*src2
)
131 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src1
->f
[0] : src0
->f
[0] > src2
->f
[0] ? src2
->f
[0] : src0
->f
[0];
132 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src1
->f
[1] : src0
->f
[1] > src2
->f
[1] ? src2
->f
[1] : src0
->f
[1];
133 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src1
->f
[2] : src0
->f
[2] > src2
->f
[2] ? src2
->f
[2] : src0
->f
[2];
134 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src1
->f
[3] : src0
->f
[3] > src2
->f
[3] ? src2
->f
[3] : src0
->f
[3];
138 micro_cmp(union tgsi_exec_channel
*dst
,
139 const union tgsi_exec_channel
*src0
,
140 const union tgsi_exec_channel
*src1
,
141 const union tgsi_exec_channel
*src2
)
143 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
144 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
145 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
146 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
150 micro_cos(union tgsi_exec_channel
*dst
,
151 const union tgsi_exec_channel
*src
)
153 dst
->f
[0] = cosf(src
->f
[0]);
154 dst
->f
[1] = cosf(src
->f
[1]);
155 dst
->f
[2] = cosf(src
->f
[2]);
156 dst
->f
[3] = cosf(src
->f
[3]);
160 micro_d2f(union tgsi_exec_channel
*dst
,
161 const union tgsi_double_channel
*src
)
163 dst
->f
[0] = (float)src
->d
[0];
164 dst
->f
[1] = (float)src
->d
[1];
165 dst
->f
[2] = (float)src
->d
[2];
166 dst
->f
[3] = (float)src
->d
[3];
170 micro_d2i(union tgsi_exec_channel
*dst
,
171 const union tgsi_double_channel
*src
)
173 dst
->i
[0] = (int)src
->d
[0];
174 dst
->i
[1] = (int)src
->d
[1];
175 dst
->i
[2] = (int)src
->d
[2];
176 dst
->i
[3] = (int)src
->d
[3];
180 micro_d2u(union tgsi_exec_channel
*dst
,
181 const union tgsi_double_channel
*src
)
183 dst
->u
[0] = (unsigned)src
->d
[0];
184 dst
->u
[1] = (unsigned)src
->d
[1];
185 dst
->u
[2] = (unsigned)src
->d
[2];
186 dst
->u
[3] = (unsigned)src
->d
[3];
189 micro_dabs(union tgsi_double_channel
*dst
,
190 const union tgsi_double_channel
*src
)
192 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
193 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
194 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
195 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
199 micro_dadd(union tgsi_double_channel
*dst
,
200 const union tgsi_double_channel
*src
)
202 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
203 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
204 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
205 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
209 micro_ddx(union tgsi_exec_channel
*dst
,
210 const union tgsi_exec_channel
*src
)
215 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
219 micro_ddy(union tgsi_exec_channel
*dst
,
220 const union tgsi_exec_channel
*src
)
225 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
229 micro_dmul(union tgsi_double_channel
*dst
,
230 const union tgsi_double_channel
*src
)
232 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
233 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
234 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
235 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
239 micro_dmax(union tgsi_double_channel
*dst
,
240 const union tgsi_double_channel
*src
)
242 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
243 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
244 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
245 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
249 micro_dmin(union tgsi_double_channel
*dst
,
250 const union tgsi_double_channel
*src
)
252 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
253 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
254 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
255 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
259 micro_dneg(union tgsi_double_channel
*dst
,
260 const union tgsi_double_channel
*src
)
262 dst
->d
[0] = -src
->d
[0];
263 dst
->d
[1] = -src
->d
[1];
264 dst
->d
[2] = -src
->d
[2];
265 dst
->d
[3] = -src
->d
[3];
269 micro_dslt(union tgsi_double_channel
*dst
,
270 const union tgsi_double_channel
*src
)
272 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
273 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
274 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
275 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
279 micro_dsne(union tgsi_double_channel
*dst
,
280 const union tgsi_double_channel
*src
)
282 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
283 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
284 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
285 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
289 micro_dsge(union tgsi_double_channel
*dst
,
290 const union tgsi_double_channel
*src
)
292 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
293 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
294 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
295 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
299 micro_dseq(union tgsi_double_channel
*dst
,
300 const union tgsi_double_channel
*src
)
302 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
303 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
304 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
305 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
309 micro_drcp(union tgsi_double_channel
*dst
,
310 const union tgsi_double_channel
*src
)
312 dst
->d
[0] = 1.0 / src
->d
[0];
313 dst
->d
[1] = 1.0 / src
->d
[1];
314 dst
->d
[2] = 1.0 / src
->d
[2];
315 dst
->d
[3] = 1.0 / src
->d
[3];
319 micro_dsqrt(union tgsi_double_channel
*dst
,
320 const union tgsi_double_channel
*src
)
322 dst
->d
[0] = sqrt(src
->d
[0]);
323 dst
->d
[1] = sqrt(src
->d
[1]);
324 dst
->d
[2] = sqrt(src
->d
[2]);
325 dst
->d
[3] = sqrt(src
->d
[3]);
329 micro_drsq(union tgsi_double_channel
*dst
,
330 const union tgsi_double_channel
*src
)
332 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
333 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
334 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
335 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
339 micro_dmad(union tgsi_double_channel
*dst
,
340 const union tgsi_double_channel
*src
)
342 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
343 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
344 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
345 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
349 micro_dfrac(union tgsi_double_channel
*dst
,
350 const union tgsi_double_channel
*src
)
352 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
353 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
354 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
355 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
359 micro_dldexp(union tgsi_double_channel
*dst
,
360 const union tgsi_double_channel
*src0
,
361 union tgsi_exec_channel
*src1
)
363 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
364 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
365 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
366 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
370 micro_dfracexp(union tgsi_double_channel
*dst
,
371 union tgsi_exec_channel
*dst_exp
,
372 const union tgsi_double_channel
*src
)
374 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
375 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
376 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
377 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
381 micro_exp2(union tgsi_exec_channel
*dst
,
382 const union tgsi_exec_channel
*src
)
385 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
386 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
387 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
388 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
391 /* Inf is okay for this instruction, so clamp it to silence assertions. */
393 union tgsi_exec_channel clamped
;
395 for (i
= 0; i
< 4; i
++) {
396 if (src
->f
[i
] > 127.99999f
) {
397 clamped
.f
[i
] = 127.99999f
;
398 } else if (src
->f
[i
] < -126.99999f
) {
399 clamped
.f
[i
] = -126.99999f
;
401 clamped
.f
[i
] = src
->f
[i
];
407 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
408 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
409 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
410 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
411 #endif /* FAST_MATH */
415 micro_f2d(union tgsi_double_channel
*dst
,
416 const union tgsi_exec_channel
*src
)
418 dst
->d
[0] = (double)src
->f
[0];
419 dst
->d
[1] = (double)src
->f
[1];
420 dst
->d
[2] = (double)src
->f
[2];
421 dst
->d
[3] = (double)src
->f
[3];
425 micro_flr(union tgsi_exec_channel
*dst
,
426 const union tgsi_exec_channel
*src
)
428 dst
->f
[0] = floorf(src
->f
[0]);
429 dst
->f
[1] = floorf(src
->f
[1]);
430 dst
->f
[2] = floorf(src
->f
[2]);
431 dst
->f
[3] = floorf(src
->f
[3]);
435 micro_frc(union tgsi_exec_channel
*dst
,
436 const union tgsi_exec_channel
*src
)
438 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
439 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
440 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
441 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
445 micro_i2d(union tgsi_double_channel
*dst
,
446 const union tgsi_exec_channel
*src
)
448 dst
->d
[0] = (double)src
->i
[0];
449 dst
->d
[1] = (double)src
->i
[1];
450 dst
->d
[2] = (double)src
->i
[2];
451 dst
->d
[3] = (double)src
->i
[3];
455 micro_iabs(union tgsi_exec_channel
*dst
,
456 const union tgsi_exec_channel
*src
)
458 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
459 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
460 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
461 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
465 micro_ineg(union tgsi_exec_channel
*dst
,
466 const union tgsi_exec_channel
*src
)
468 dst
->i
[0] = -src
->i
[0];
469 dst
->i
[1] = -src
->i
[1];
470 dst
->i
[2] = -src
->i
[2];
471 dst
->i
[3] = -src
->i
[3];
475 micro_lg2(union tgsi_exec_channel
*dst
,
476 const union tgsi_exec_channel
*src
)
479 dst
->f
[0] = util_fast_log2(src
->f
[0]);
480 dst
->f
[1] = util_fast_log2(src
->f
[1]);
481 dst
->f
[2] = util_fast_log2(src
->f
[2]);
482 dst
->f
[3] = util_fast_log2(src
->f
[3]);
484 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
485 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
486 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
487 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
492 micro_lrp(union tgsi_exec_channel
*dst
,
493 const union tgsi_exec_channel
*src0
,
494 const union tgsi_exec_channel
*src1
,
495 const union tgsi_exec_channel
*src2
)
497 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
498 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
499 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
500 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
504 micro_mad(union tgsi_exec_channel
*dst
,
505 const union tgsi_exec_channel
*src0
,
506 const union tgsi_exec_channel
*src1
,
507 const union tgsi_exec_channel
*src2
)
509 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
510 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
511 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
512 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
516 micro_mov(union tgsi_exec_channel
*dst
,
517 const union tgsi_exec_channel
*src
)
519 dst
->u
[0] = src
->u
[0];
520 dst
->u
[1] = src
->u
[1];
521 dst
->u
[2] = src
->u
[2];
522 dst
->u
[3] = src
->u
[3];
526 micro_rcp(union tgsi_exec_channel
*dst
,
527 const union tgsi_exec_channel
*src
)
529 #if 0 /* for debugging */
530 assert(src
->f
[0] != 0.0f
);
531 assert(src
->f
[1] != 0.0f
);
532 assert(src
->f
[2] != 0.0f
);
533 assert(src
->f
[3] != 0.0f
);
535 dst
->f
[0] = 1.0f
/ src
->f
[0];
536 dst
->f
[1] = 1.0f
/ src
->f
[1];
537 dst
->f
[2] = 1.0f
/ src
->f
[2];
538 dst
->f
[3] = 1.0f
/ src
->f
[3];
542 micro_rnd(union tgsi_exec_channel
*dst
,
543 const union tgsi_exec_channel
*src
)
545 dst
->f
[0] = floorf(src
->f
[0] + 0.5f
);
546 dst
->f
[1] = floorf(src
->f
[1] + 0.5f
);
547 dst
->f
[2] = floorf(src
->f
[2] + 0.5f
);
548 dst
->f
[3] = floorf(src
->f
[3] + 0.5f
);
552 micro_rsq(union tgsi_exec_channel
*dst
,
553 const union tgsi_exec_channel
*src
)
555 #if 0 /* for debugging */
556 assert(src
->f
[0] != 0.0f
);
557 assert(src
->f
[1] != 0.0f
);
558 assert(src
->f
[2] != 0.0f
);
559 assert(src
->f
[3] != 0.0f
);
561 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
562 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
563 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
564 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
568 micro_sqrt(union tgsi_exec_channel
*dst
,
569 const union tgsi_exec_channel
*src
)
571 dst
->f
[0] = sqrtf(src
->f
[0]);
572 dst
->f
[1] = sqrtf(src
->f
[1]);
573 dst
->f
[2] = sqrtf(src
->f
[2]);
574 dst
->f
[3] = sqrtf(src
->f
[3]);
578 micro_seq(union tgsi_exec_channel
*dst
,
579 const union tgsi_exec_channel
*src0
,
580 const union tgsi_exec_channel
*src1
)
582 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
583 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
584 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
585 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
589 micro_sge(union tgsi_exec_channel
*dst
,
590 const union tgsi_exec_channel
*src0
,
591 const union tgsi_exec_channel
*src1
)
593 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
594 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
595 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
596 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
600 micro_sgn(union tgsi_exec_channel
*dst
,
601 const union tgsi_exec_channel
*src
)
603 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
604 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
605 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
606 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
610 micro_isgn(union tgsi_exec_channel
*dst
,
611 const union tgsi_exec_channel
*src
)
613 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
614 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
615 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
616 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
620 micro_sgt(union tgsi_exec_channel
*dst
,
621 const union tgsi_exec_channel
*src0
,
622 const union tgsi_exec_channel
*src1
)
624 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
625 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
626 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
627 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
631 micro_sin(union tgsi_exec_channel
*dst
,
632 const union tgsi_exec_channel
*src
)
634 dst
->f
[0] = sinf(src
->f
[0]);
635 dst
->f
[1] = sinf(src
->f
[1]);
636 dst
->f
[2] = sinf(src
->f
[2]);
637 dst
->f
[3] = sinf(src
->f
[3]);
641 micro_sle(union tgsi_exec_channel
*dst
,
642 const union tgsi_exec_channel
*src0
,
643 const union tgsi_exec_channel
*src1
)
645 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
646 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
647 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
648 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
652 micro_slt(union tgsi_exec_channel
*dst
,
653 const union tgsi_exec_channel
*src0
,
654 const union tgsi_exec_channel
*src1
)
656 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
657 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
658 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
659 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
663 micro_sne(union tgsi_exec_channel
*dst
,
664 const union tgsi_exec_channel
*src0
,
665 const union tgsi_exec_channel
*src1
)
667 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
668 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
669 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
670 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
674 micro_trunc(union tgsi_exec_channel
*dst
,
675 const union tgsi_exec_channel
*src
)
677 dst
->f
[0] = (float)(int)src
->f
[0];
678 dst
->f
[1] = (float)(int)src
->f
[1];
679 dst
->f
[2] = (float)(int)src
->f
[2];
680 dst
->f
[3] = (float)(int)src
->f
[3];
684 micro_u2d(union tgsi_double_channel
*dst
,
685 const union tgsi_exec_channel
*src
)
687 dst
->d
[0] = (double)src
->u
[0];
688 dst
->d
[1] = (double)src
->u
[1];
689 dst
->d
[2] = (double)src
->u
[2];
690 dst
->d
[3] = (double)src
->u
[3];
693 enum tgsi_exec_datatype
{
694 TGSI_EXEC_DATA_FLOAT
,
697 TGSI_EXEC_DATA_DOUBLE
701 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
703 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
704 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
705 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
706 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
707 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
708 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
711 /** The execution mask depends on the conditional mask and the loop mask */
712 #define UPDATE_EXEC_MASK(MACH) \
713 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
716 static const union tgsi_exec_channel ZeroVec
=
717 { { 0.0, 0.0, 0.0, 0.0 } };
719 static const union tgsi_exec_channel OneVec
= {
720 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
723 static const union tgsi_exec_channel P128Vec
= {
724 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
727 static const union tgsi_exec_channel M128Vec
= {
728 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
733 * Assert that none of the float values in 'chan' are infinite or NaN.
734 * NaN and Inf may occur normally during program execution and should
735 * not lead to crashes, etc. But when debugging, it's helpful to catch
739 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
741 assert(!util_is_inf_or_nan((chan
)->f
[0]));
742 assert(!util_is_inf_or_nan((chan
)->f
[1]));
743 assert(!util_is_inf_or_nan((chan
)->f
[2]));
744 assert(!util_is_inf_or_nan((chan
)->f
[3]));
750 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
752 debug_printf("%s = {%f, %f, %f, %f}\n",
753 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
760 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
762 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
764 debug_printf("Temp[%u] =\n", index
);
765 for (i
= 0; i
< 4; i
++) {
766 debug_printf(" %c: { %f, %f, %f, %f }\n",
778 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
781 const unsigned *buf_sizes
)
785 for (i
= 0; i
< num_bufs
; i
++) {
786 mach
->Consts
[i
] = bufs
[i
];
787 mach
->ConstsSize
[i
] = buf_sizes
[i
];
793 * Check if there's a potential src/dst register data dependency when
794 * using SOA execution.
797 * This would expand into:
802 * The second instruction will have the wrong value for t0 if executed as-is.
805 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
809 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
810 if (writemask
== TGSI_WRITEMASK_X
||
811 writemask
== TGSI_WRITEMASK_Y
||
812 writemask
== TGSI_WRITEMASK_Z
||
813 writemask
== TGSI_WRITEMASK_W
||
814 writemask
== TGSI_WRITEMASK_NONE
) {
815 /* no chance of data dependency */
819 /* loop over src regs */
820 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
821 if ((inst
->Src
[i
].Register
.File
==
822 inst
->Dst
[0].Register
.File
) &&
823 ((inst
->Src
[i
].Register
.Index
==
824 inst
->Dst
[0].Register
.Index
) ||
825 inst
->Src
[i
].Register
.Indirect
||
826 inst
->Dst
[0].Register
.Indirect
)) {
827 /* loop over dest channels */
828 uint channelsWritten
= 0x0;
829 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
830 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
831 /* check if we're reading a channel that's been written */
832 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
833 if (channelsWritten
& (1 << swizzle
)) {
837 channelsWritten
|= (1 << chan
);
847 * Initialize machine state by expanding tokens to full instructions,
848 * allocating temporary storage, setting up constants, etc.
849 * After this, we can call tgsi_exec_machine_run() many times.
852 tgsi_exec_machine_bind_shader(
853 struct tgsi_exec_machine
*mach
,
854 const struct tgsi_token
*tokens
,
855 struct tgsi_sampler
*sampler
)
858 struct tgsi_parse_context parse
;
859 struct tgsi_full_instruction
*instructions
;
860 struct tgsi_full_declaration
*declarations
;
861 uint maxInstructions
= 10, numInstructions
= 0;
862 uint maxDeclarations
= 10, numDeclarations
= 0;
865 tgsi_dump(tokens
, 0);
871 mach
->Tokens
= tokens
;
872 mach
->Sampler
= sampler
;
875 /* unbind and free all */
876 FREE(mach
->Declarations
);
877 mach
->Declarations
= NULL
;
878 mach
->NumDeclarations
= 0;
880 FREE(mach
->Instructions
);
881 mach
->Instructions
= NULL
;
882 mach
->NumInstructions
= 0;
887 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
888 if (k
!= TGSI_PARSE_OK
) {
889 debug_printf( "Problem parsing!\n" );
893 mach
->Processor
= parse
.FullHeader
.Processor
.Processor
;
895 mach
->NumOutputs
= 0;
897 if (mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
&&
898 !mach
->UsedGeometryShader
) {
899 struct tgsi_exec_vector
*inputs
;
900 struct tgsi_exec_vector
*outputs
;
902 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
903 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
909 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
910 TGSI_MAX_TOTAL_VERTICES
, 16);
917 align_free(mach
->Inputs
);
918 align_free(mach
->Outputs
);
920 mach
->Inputs
= inputs
;
921 mach
->Outputs
= outputs
;
922 mach
->UsedGeometryShader
= TRUE
;
925 declarations
= (struct tgsi_full_declaration
*)
926 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
932 instructions
= (struct tgsi_full_instruction
*)
933 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
936 FREE( declarations
);
940 while( !tgsi_parse_end_of_tokens( &parse
) ) {
943 tgsi_parse_token( &parse
);
944 switch( parse
.FullToken
.Token
.Type
) {
945 case TGSI_TOKEN_TYPE_DECLARATION
:
946 /* save expanded declaration */
947 if (numDeclarations
== maxDeclarations
) {
948 declarations
= REALLOC(declarations
,
950 * sizeof(struct tgsi_full_declaration
),
951 (maxDeclarations
+ 10)
952 * sizeof(struct tgsi_full_declaration
));
953 maxDeclarations
+= 10;
955 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
957 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
958 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
963 memcpy(declarations
+ numDeclarations
,
964 &parse
.FullToken
.FullDeclaration
,
965 sizeof(declarations
[0]));
969 case TGSI_TOKEN_TYPE_IMMEDIATE
:
971 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
973 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
975 for( i
= 0; i
< size
; i
++ ) {
976 mach
->Imms
[mach
->ImmLimit
][i
] =
977 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
983 case TGSI_TOKEN_TYPE_INSTRUCTION
:
985 /* save expanded instruction */
986 if (numInstructions
== maxInstructions
) {
987 instructions
= REALLOC(instructions
,
989 * sizeof(struct tgsi_full_instruction
),
990 (maxInstructions
+ 10)
991 * sizeof(struct tgsi_full_instruction
));
992 maxInstructions
+= 10;
995 memcpy(instructions
+ numInstructions
,
996 &parse
.FullToken
.FullInstruction
,
997 sizeof(instructions
[0]));
1002 case TGSI_TOKEN_TYPE_PROPERTY
:
1003 if (mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
) {
1004 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1005 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1014 tgsi_parse_free (&parse
);
1016 FREE(mach
->Declarations
);
1017 mach
->Declarations
= declarations
;
1018 mach
->NumDeclarations
= numDeclarations
;
1020 FREE(mach
->Instructions
);
1021 mach
->Instructions
= instructions
;
1022 mach
->NumInstructions
= numInstructions
;
1026 struct tgsi_exec_machine
*
1027 tgsi_exec_machine_create( void )
1029 struct tgsi_exec_machine
*mach
;
1032 mach
= align_malloc( sizeof *mach
, 16 );
1036 memset(mach
, 0, sizeof(*mach
));
1038 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1039 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1040 mach
->Predicates
= &mach
->Temps
[TGSI_EXEC_TEMP_P0
];
1042 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1043 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1044 if (!mach
->Inputs
|| !mach
->Outputs
)
1047 /* Setup constants needed by the SSE2 executor. */
1048 for( i
= 0; i
< 4; i
++ ) {
1049 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
1050 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
1051 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
1052 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
1053 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
1054 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
1055 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
1056 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
1057 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
1058 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
1062 /* silence warnings */
1071 align_free(mach
->Inputs
);
1072 align_free(mach
->Outputs
);
1080 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1083 FREE(mach
->Instructions
);
1084 FREE(mach
->Declarations
);
1086 align_free(mach
->Inputs
);
1087 align_free(mach
->Outputs
);
1094 micro_add(union tgsi_exec_channel
*dst
,
1095 const union tgsi_exec_channel
*src0
,
1096 const union tgsi_exec_channel
*src1
)
1098 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1099 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1100 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1101 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1106 union tgsi_exec_channel
*dst
,
1107 const union tgsi_exec_channel
*src0
,
1108 const union tgsi_exec_channel
*src1
)
1110 if (src1
->f
[0] != 0) {
1111 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1113 if (src1
->f
[1] != 0) {
1114 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1116 if (src1
->f
[2] != 0) {
1117 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1119 if (src1
->f
[3] != 0) {
1120 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1126 union tgsi_exec_channel
*dst
,
1127 const union tgsi_exec_channel
*src0
,
1128 const union tgsi_exec_channel
*src1
,
1129 const union tgsi_exec_channel
*src2
,
1130 const union tgsi_exec_channel
*src3
)
1132 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1133 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1134 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1135 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1139 micro_max(union tgsi_exec_channel
*dst
,
1140 const union tgsi_exec_channel
*src0
,
1141 const union tgsi_exec_channel
*src1
)
1143 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1144 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1145 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1146 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1150 micro_min(union tgsi_exec_channel
*dst
,
1151 const union tgsi_exec_channel
*src0
,
1152 const union tgsi_exec_channel
*src1
)
1154 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1155 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1156 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1157 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1161 micro_mul(union tgsi_exec_channel
*dst
,
1162 const union tgsi_exec_channel
*src0
,
1163 const union tgsi_exec_channel
*src1
)
1165 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1166 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1167 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1168 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1173 union tgsi_exec_channel
*dst
,
1174 const union tgsi_exec_channel
*src
)
1176 dst
->f
[0] = -src
->f
[0];
1177 dst
->f
[1] = -src
->f
[1];
1178 dst
->f
[2] = -src
->f
[2];
1179 dst
->f
[3] = -src
->f
[3];
1184 union tgsi_exec_channel
*dst
,
1185 const union tgsi_exec_channel
*src0
,
1186 const union tgsi_exec_channel
*src1
)
1189 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1190 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1191 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1192 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1194 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1195 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1196 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1197 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1202 micro_sub(union tgsi_exec_channel
*dst
,
1203 const union tgsi_exec_channel
*src0
,
1204 const union tgsi_exec_channel
*src1
)
1206 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1207 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1208 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1209 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1213 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1214 const uint chan_index
,
1217 const union tgsi_exec_channel
*index
,
1218 const union tgsi_exec_channel
*index2D
,
1219 union tgsi_exec_channel
*chan
)
1223 assert(swizzle
< 4);
1226 case TGSI_FILE_CONSTANT
:
1227 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1228 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1229 assert(mach
->Consts
[index2D
->i
[i
]]);
1231 if (index
->i
[i
] < 0) {
1234 /* NOTE: copying the const value as a uint instead of float */
1235 const uint constbuf
= index2D
->i
[i
];
1236 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1237 const int pos
= index
->i
[i
] * 4 + swizzle
;
1238 /* const buffer bounds check */
1239 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1241 /* Debug: print warning */
1242 static int count
= 0;
1244 debug_printf("TGSI Exec: const buffer index %d"
1245 " out of bounds\n", pos
);
1250 chan
->u
[i
] = buf
[pos
];
1255 case TGSI_FILE_INPUT
:
1256 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1258 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1259 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1260 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1261 index2D->i[i], index->i[i]);
1263 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1265 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1266 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1270 case TGSI_FILE_SYSTEM_VALUE
:
1271 /* XXX no swizzling at this point. Will be needed if we put
1272 * gl_FragCoord, for example, in a sys value register.
1274 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1275 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].u
[i
];
1279 case TGSI_FILE_TEMPORARY
:
1280 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1281 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1282 assert(index2D
->i
[i
] == 0);
1284 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1288 case TGSI_FILE_IMMEDIATE
:
1289 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1290 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1291 assert(index2D
->i
[i
] == 0);
1293 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1297 case TGSI_FILE_ADDRESS
:
1298 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1299 assert(index
->i
[i
] >= 0);
1300 assert(index2D
->i
[i
] == 0);
1302 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1306 case TGSI_FILE_PREDICATE
:
1307 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1308 assert(index
->i
[i
] >= 0 && index
->i
[i
] < TGSI_EXEC_NUM_PREDS
);
1309 assert(index2D
->i
[i
] == 0);
1311 chan
->u
[i
] = mach
->Predicates
[0].xyzw
[swizzle
].u
[i
];
1315 case TGSI_FILE_OUTPUT
:
1316 /* vertex/fragment output vars can be read too */
1317 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1318 assert(index
->i
[i
] >= 0);
1319 assert(index2D
->i
[i
] == 0);
1321 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1327 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1334 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1335 union tgsi_exec_channel
*chan
,
1336 const struct tgsi_full_src_register
*reg
,
1337 const uint chan_index
,
1338 enum tgsi_exec_datatype src_datatype
)
1340 union tgsi_exec_channel index
;
1341 union tgsi_exec_channel index2D
;
1344 /* We start with a direct index into a register file.
1348 * file = Register.File
1349 * [1] = Register.Index
1354 index
.i
[3] = reg
->Register
.Index
;
1356 /* There is an extra source register that indirectly subscripts
1357 * a register file. The direct index now becomes an offset
1358 * that is being added to the indirect register.
1362 * ind = Indirect.File
1363 * [2] = Indirect.Index
1364 * .x = Indirect.SwizzleX
1366 if (reg
->Register
.Indirect
) {
1367 union tgsi_exec_channel index2
;
1368 union tgsi_exec_channel indir_index
;
1369 const uint execmask
= mach
->ExecMask
;
1372 /* which address register (always zero now) */
1376 index2
.i
[3] = reg
->Indirect
.Index
;
1377 /* get current value of address register[swizzle] */
1378 swizzle
= reg
->Indirect
.Swizzle
;
1379 fetch_src_file_channel(mach
,
1387 /* add value of address register to the offset */
1388 index
.i
[0] += indir_index
.i
[0];
1389 index
.i
[1] += indir_index
.i
[1];
1390 index
.i
[2] += indir_index
.i
[2];
1391 index
.i
[3] += indir_index
.i
[3];
1393 /* for disabled execution channels, zero-out the index to
1394 * avoid using a potential garbage value.
1396 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1397 if ((execmask
& (1 << i
)) == 0)
1402 /* There is an extra source register that is a second
1403 * subscript to a register file. Effectively it means that
1404 * the register file is actually a 2D array of registers.
1408 * [3] = Dimension.Index
1410 if (reg
->Register
.Dimension
) {
1414 index2D
.i
[3] = reg
->Dimension
.Index
;
1416 /* Again, the second subscript index can be addressed indirectly
1417 * identically to the first one.
1418 * Nothing stops us from indirectly addressing the indirect register,
1419 * but there is no need for that, so we won't exercise it.
1421 * file[ind[4].y+3][1],
1423 * ind = DimIndirect.File
1424 * [4] = DimIndirect.Index
1425 * .y = DimIndirect.SwizzleX
1427 if (reg
->Dimension
.Indirect
) {
1428 union tgsi_exec_channel index2
;
1429 union tgsi_exec_channel indir_index
;
1430 const uint execmask
= mach
->ExecMask
;
1436 index2
.i
[3] = reg
->DimIndirect
.Index
;
1438 swizzle
= reg
->DimIndirect
.Swizzle
;
1439 fetch_src_file_channel(mach
,
1441 reg
->DimIndirect
.File
,
1447 index2D
.i
[0] += indir_index
.i
[0];
1448 index2D
.i
[1] += indir_index
.i
[1];
1449 index2D
.i
[2] += indir_index
.i
[2];
1450 index2D
.i
[3] += indir_index
.i
[3];
1452 /* for disabled execution channels, zero-out the index to
1453 * avoid using a potential garbage value.
1455 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1456 if ((execmask
& (1 << i
)) == 0) {
1462 /* If by any chance there was a need for a 3D array of register
1463 * files, we would have to check whether Dimension is followed
1464 * by a dimension register and continue the saga.
1473 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1474 fetch_src_file_channel(mach
,
1484 fetch_source(const struct tgsi_exec_machine
*mach
,
1485 union tgsi_exec_channel
*chan
,
1486 const struct tgsi_full_src_register
*reg
,
1487 const uint chan_index
,
1488 enum tgsi_exec_datatype src_datatype
)
1490 fetch_source_d(mach
, chan
, reg
, chan_index
, src_datatype
);
1492 if (reg
->Register
.Absolute
) {
1493 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1494 micro_abs(chan
, chan
);
1496 micro_iabs(chan
, chan
);
1500 if (reg
->Register
.Negate
) {
1501 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1502 micro_neg(chan
, chan
);
1504 micro_ineg(chan
, chan
);
1509 static union tgsi_exec_channel
*
1510 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1511 const union tgsi_exec_channel
*chan
,
1512 const struct tgsi_full_dst_register
*reg
,
1513 const struct tgsi_full_instruction
*inst
,
1515 enum tgsi_exec_datatype dst_datatype
)
1518 static union tgsi_exec_channel null
;
1519 union tgsi_exec_channel
*dst
;
1520 union tgsi_exec_channel index2D
;
1521 uint execmask
= mach
->ExecMask
;
1522 int offset
= 0; /* indirection offset */
1526 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1527 check_inf_or_nan(chan
);
1530 /* There is an extra source register that indirectly subscripts
1531 * a register file. The direct index now becomes an offset
1532 * that is being added to the indirect register.
1536 * ind = Indirect.File
1537 * [2] = Indirect.Index
1538 * .x = Indirect.SwizzleX
1540 if (reg
->Register
.Indirect
) {
1541 union tgsi_exec_channel index
;
1542 union tgsi_exec_channel indir_index
;
1545 /* which address register (always zero for now) */
1549 index
.i
[3] = reg
->Indirect
.Index
;
1551 /* get current value of address register[swizzle] */
1552 swizzle
= reg
->Indirect
.Swizzle
;
1554 /* fetch values from the address/indirection register */
1555 fetch_src_file_channel(mach
,
1563 /* save indirection offset */
1564 offset
= indir_index
.i
[0];
1567 /* There is an extra source register that is a second
1568 * subscript to a register file. Effectively it means that
1569 * the register file is actually a 2D array of registers.
1573 * [3] = Dimension.Index
1575 if (reg
->Register
.Dimension
) {
1579 index2D
.i
[3] = reg
->Dimension
.Index
;
1581 /* Again, the second subscript index can be addressed indirectly
1582 * identically to the first one.
1583 * Nothing stops us from indirectly addressing the indirect register,
1584 * but there is no need for that, so we won't exercise it.
1586 * file[ind[4].y+3][1],
1588 * ind = DimIndirect.File
1589 * [4] = DimIndirect.Index
1590 * .y = DimIndirect.SwizzleX
1592 if (reg
->Dimension
.Indirect
) {
1593 union tgsi_exec_channel index2
;
1594 union tgsi_exec_channel indir_index
;
1595 const uint execmask
= mach
->ExecMask
;
1602 index2
.i
[3] = reg
->DimIndirect
.Index
;
1604 swizzle
= reg
->DimIndirect
.Swizzle
;
1605 fetch_src_file_channel(mach
,
1607 reg
->DimIndirect
.File
,
1613 index2D
.i
[0] += indir_index
.i
[0];
1614 index2D
.i
[1] += indir_index
.i
[1];
1615 index2D
.i
[2] += indir_index
.i
[2];
1616 index2D
.i
[3] += indir_index
.i
[3];
1618 /* for disabled execution channels, zero-out the index to
1619 * avoid using a potential garbage value.
1621 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1622 if ((execmask
& (1 << i
)) == 0) {
1628 /* If by any chance there was a need for a 3D array of register
1629 * files, we would have to check whether Dimension is followed
1630 * by a dimension register and continue the saga.
1639 switch (reg
->Register
.File
) {
1640 case TGSI_FILE_NULL
:
1644 case TGSI_FILE_OUTPUT
:
1645 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1646 + reg
->Register
.Index
;
1647 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1649 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1650 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1651 reg
->Register
.Index
);
1652 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1653 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1654 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1655 if (execmask
& (1 << i
))
1656 debug_printf("%f, ", chan
->f
[i
]);
1657 debug_printf(")\n");
1662 case TGSI_FILE_TEMPORARY
:
1663 index
= reg
->Register
.Index
;
1664 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1665 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1668 case TGSI_FILE_ADDRESS
:
1669 index
= reg
->Register
.Index
;
1670 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1673 case TGSI_FILE_PREDICATE
:
1674 index
= reg
->Register
.Index
;
1675 assert(index
< TGSI_EXEC_NUM_PREDS
);
1676 dst
= &mach
->Predicates
[index
].xyzw
[chan_index
];
1684 if (inst
->Instruction
.Predicate
) {
1686 union tgsi_exec_channel
*pred
;
1688 switch (chan_index
) {
1690 swizzle
= inst
->Predicate
.SwizzleX
;
1693 swizzle
= inst
->Predicate
.SwizzleY
;
1696 swizzle
= inst
->Predicate
.SwizzleZ
;
1699 swizzle
= inst
->Predicate
.SwizzleW
;
1706 assert(inst
->Predicate
.Index
== 0);
1708 pred
= &mach
->Predicates
[inst
->Predicate
.Index
].xyzw
[swizzle
];
1710 if (inst
->Predicate
.Negate
) {
1711 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1713 execmask
&= ~(1 << i
);
1717 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1719 execmask
&= ~(1 << i
);
1729 store_dest_double(struct tgsi_exec_machine
*mach
,
1730 const union tgsi_exec_channel
*chan
,
1731 const struct tgsi_full_dst_register
*reg
,
1732 const struct tgsi_full_instruction
*inst
,
1734 enum tgsi_exec_datatype dst_datatype
)
1736 union tgsi_exec_channel
*dst
;
1737 const uint execmask
= mach
->ExecMask
;
1740 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
1746 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1747 if (execmask
& (1 << i
))
1748 dst
->i
[i
] = chan
->i
[i
];
1752 store_dest(struct tgsi_exec_machine
*mach
,
1753 const union tgsi_exec_channel
*chan
,
1754 const struct tgsi_full_dst_register
*reg
,
1755 const struct tgsi_full_instruction
*inst
,
1757 enum tgsi_exec_datatype dst_datatype
)
1759 union tgsi_exec_channel
*dst
;
1760 const uint execmask
= mach
->ExecMask
;
1763 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
1768 if (!inst
->Instruction
.Saturate
) {
1769 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1770 if (execmask
& (1 << i
))
1771 dst
->i
[i
] = chan
->i
[i
];
1774 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1775 if (execmask
& (1 << i
)) {
1776 if (chan
->f
[i
] < 0.0f
)
1778 else if (chan
->f
[i
] > 1.0f
)
1781 dst
->i
[i
] = chan
->i
[i
];
1786 #define FETCH(VAL,INDEX,CHAN)\
1787 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1789 #define IFETCH(VAL,INDEX,CHAN)\
1790 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1794 * Execute ARB-style KIL which is predicated by a src register.
1795 * Kill fragment if any of the four values is less than zero.
1798 exec_kill_if(struct tgsi_exec_machine
*mach
,
1799 const struct tgsi_full_instruction
*inst
)
1803 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1804 union tgsi_exec_channel r
[1];
1806 /* This mask stores component bits that were already tested. */
1809 for (chan_index
= 0; chan_index
< 4; chan_index
++)
1814 /* unswizzle channel */
1815 swizzle
= tgsi_util_get_full_src_register_swizzle (
1819 /* check if the component has not been already tested */
1820 if (uniquemask
& (1 << swizzle
))
1822 uniquemask
|= 1 << swizzle
;
1824 FETCH(&r
[0], 0, chan_index
);
1825 for (i
= 0; i
< 4; i
++)
1826 if (r
[0].f
[i
] < 0.0f
)
1830 /* restrict to fragments currently executing */
1831 kilmask
&= mach
->ExecMask
;
1833 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1837 * Unconditional fragment kill/discard.
1840 exec_kill(struct tgsi_exec_machine
*mach
,
1841 const struct tgsi_full_instruction
*inst
)
1843 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1845 /* kill fragment for all fragments currently executing */
1846 kilmask
= mach
->ExecMask
;
1847 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1851 emit_vertex(struct tgsi_exec_machine
*mach
)
1853 /* FIXME: check for exec mask correctly
1855 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1856 if ((mach->ExecMask & (1 << i)))
1858 if (mach
->ExecMask
) {
1859 if (mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]] >= mach
->MaxOutputVertices
)
1862 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
1863 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
1868 emit_primitive(struct tgsi_exec_machine
*mach
)
1870 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
1871 /* FIXME: check for exec mask correctly
1873 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1874 if ((mach->ExecMask & (1 << i)))
1876 if (mach
->ExecMask
) {
1878 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
1879 mach
->Primitives
[*prim_count
] = 0;
1884 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
1886 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1888 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
1889 if (emitted_verts
) {
1890 emit_primitive(mach
);
1897 * Fetch four texture samples using STR texture coordinates.
1900 fetch_texel( struct tgsi_sampler
*sampler
,
1901 const unsigned sview_idx
,
1902 const unsigned sampler_idx
,
1903 const union tgsi_exec_channel
*s
,
1904 const union tgsi_exec_channel
*t
,
1905 const union tgsi_exec_channel
*p
,
1906 const union tgsi_exec_channel
*c0
,
1907 const union tgsi_exec_channel
*c1
,
1908 float derivs
[3][2][TGSI_QUAD_SIZE
],
1909 const int8_t offset
[3],
1910 enum tgsi_sampler_control control
,
1911 union tgsi_exec_channel
*r
,
1912 union tgsi_exec_channel
*g
,
1913 union tgsi_exec_channel
*b
,
1914 union tgsi_exec_channel
*a
)
1917 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
1919 /* FIXME: handle explicit derivs, offsets */
1920 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
1921 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
1923 for (j
= 0; j
< 4; j
++) {
1924 r
->f
[j
] = rgba
[0][j
];
1925 g
->f
[j
] = rgba
[1][j
];
1926 b
->f
[j
] = rgba
[2][j
];
1927 a
->f
[j
] = rgba
[3][j
];
1932 #define TEX_MODIFIER_NONE 0
1933 #define TEX_MODIFIER_PROJECTED 1
1934 #define TEX_MODIFIER_LOD_BIAS 2
1935 #define TEX_MODIFIER_EXPLICIT_LOD 3
1936 #define TEX_MODIFIER_LEVEL_ZERO 4
1937 #define TEX_MODIFIER_GATHER 5
1940 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1943 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
1944 const struct tgsi_full_instruction
*inst
,
1947 if (inst
->Texture
.NumOffsets
== 1) {
1948 union tgsi_exec_channel index
;
1949 union tgsi_exec_channel offset
[3];
1950 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
1951 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1952 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
1953 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1954 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
1955 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1956 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
1957 offsets
[0] = offset
[0].i
[0];
1958 offsets
[1] = offset
[1].i
[0];
1959 offsets
[2] = offset
[2].i
[0];
1961 assert(inst
->Texture
.NumOffsets
== 0);
1962 offsets
[0] = offsets
[1] = offsets
[2] = 0;
1968 * Fetch dx and dy values for one channel (s, t or r).
1969 * Put dx values into one float array, dy values into another.
1972 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
1973 const struct tgsi_full_instruction
*inst
,
1976 float derivs
[2][TGSI_QUAD_SIZE
])
1978 union tgsi_exec_channel d
;
1979 FETCH(&d
, regdsrcx
, chan
);
1980 derivs
[0][0] = d
.f
[0];
1981 derivs
[0][1] = d
.f
[1];
1982 derivs
[0][2] = d
.f
[2];
1983 derivs
[0][3] = d
.f
[3];
1984 FETCH(&d
, regdsrcx
+ 1, chan
);
1985 derivs
[1][0] = d
.f
[0];
1986 derivs
[1][1] = d
.f
[1];
1987 derivs
[1][2] = d
.f
[2];
1988 derivs
[1][3] = d
.f
[3];
1992 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
1993 const struct tgsi_full_instruction
*inst
,
1998 if (inst
->Src
[sampler
].Register
.Indirect
) {
1999 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2000 union tgsi_exec_channel indir_index
, index2
;
2005 index2
.i
[3] = reg
->Indirect
.Index
;
2007 fetch_src_file_channel(mach
,
2010 reg
->Indirect
.Swizzle
,
2014 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[0];
2016 unit
= inst
->Src
[sampler
].Register
.Index
;
2022 * execute a texture instruction.
2024 * modifier is used to control the channel routing for the
2025 * instruction variants like proj, lod, and texture with lod bias.
2026 * sampler indicates which src register the sampler is contained in.
2029 exec_tex(struct tgsi_exec_machine
*mach
,
2030 const struct tgsi_full_instruction
*inst
,
2031 uint modifier
, uint sampler
)
2033 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2034 union tgsi_exec_channel r
[5];
2035 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2039 int dim
, shadow_ref
, i
;
2041 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2042 /* always fetch all 3 offsets, overkill but keeps code simple */
2043 fetch_texel_offsets(mach
, inst
, offsets
);
2045 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2046 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2048 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
, &shadow_ref
);
2051 if (shadow_ref
>= 0)
2052 assert(shadow_ref
>= dim
&& shadow_ref
< Elements(args
));
2054 /* fetch modifier to the last argument */
2055 if (modifier
!= TEX_MODIFIER_NONE
) {
2056 const int last
= Elements(args
) - 1;
2058 /* fetch modifier from src0.w or src1.x */
2060 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2061 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2064 assert(shadow_ref
!= 4);
2065 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2068 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2069 args
[last
] = &r
[last
];
2073 args
[last
] = &ZeroVec
;
2076 /* point unused arguments to zero vector */
2077 for (i
= dim
; i
< last
; i
++)
2080 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2081 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2082 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2083 control
= TGSI_SAMPLER_LOD_BIAS
;
2084 else if (modifier
== TEX_MODIFIER_GATHER
)
2085 control
= TGSI_SAMPLER_GATHER
;
2088 for (i
= dim
; i
< Elements(args
); i
++)
2092 /* fetch coordinates */
2093 for (i
= 0; i
< dim
; i
++) {
2094 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2097 micro_div(&r
[i
], &r
[i
], proj
);
2102 /* fetch reference value */
2103 if (shadow_ref
>= 0) {
2104 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2107 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2109 args
[shadow_ref
] = &r
[shadow_ref
];
2112 fetch_texel(mach
->Sampler
, unit
, unit
,
2113 args
[0], args
[1], args
[2], args
[3], args
[4],
2114 NULL
, offsets
, control
,
2115 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2118 debug_printf("fetch r: %g %g %g %g\n",
2119 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2120 debug_printf("fetch g: %g %g %g %g\n",
2121 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2122 debug_printf("fetch b: %g %g %g %g\n",
2123 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2124 debug_printf("fetch a: %g %g %g %g\n",
2125 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2128 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2129 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2130 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2136 exec_lodq(struct tgsi_exec_machine
*mach
,
2137 const struct tgsi_full_instruction
*inst
)
2142 union tgsi_exec_channel coords
[4];
2143 const union tgsi_exec_channel
*args
[Elements(coords
)];
2144 union tgsi_exec_channel r
[2];
2146 unit
= fetch_sampler_unit(mach
, inst
, 1);
2147 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
, NULL
);
2148 assert(dim
<= Elements(coords
));
2149 /* fetch coordinates */
2150 for (i
= 0; i
< dim
; i
++) {
2151 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2152 args
[i
] = &coords
[i
];
2154 for (i
= dim
; i
< Elements(coords
); i
++) {
2157 mach
->Sampler
->query_lod(mach
->Sampler
, unit
, unit
,
2162 TGSI_SAMPLER_LOD_NONE
,
2166 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2167 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2168 TGSI_EXEC_DATA_FLOAT
);
2170 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2171 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2172 TGSI_EXEC_DATA_FLOAT
);
2177 exec_txd(struct tgsi_exec_machine
*mach
,
2178 const struct tgsi_full_instruction
*inst
)
2180 union tgsi_exec_channel r
[4];
2181 float derivs
[3][2][TGSI_QUAD_SIZE
];
2186 unit
= fetch_sampler_unit(mach
, inst
, 3);
2187 /* always fetch all 3 offsets, overkill but keeps code simple */
2188 fetch_texel_offsets(mach
, inst
, offsets
);
2190 switch (inst
->Texture
.Texture
) {
2191 case TGSI_TEXTURE_1D
:
2192 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2194 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2196 fetch_texel(mach
->Sampler
, unit
, unit
,
2197 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2198 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2199 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2202 case TGSI_TEXTURE_SHADOW1D
:
2203 case TGSI_TEXTURE_1D_ARRAY
:
2204 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2205 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2206 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2207 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2208 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2210 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2212 fetch_texel(mach
->Sampler
, unit
, unit
,
2213 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2214 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2215 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2218 case TGSI_TEXTURE_2D
:
2219 case TGSI_TEXTURE_RECT
:
2220 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2221 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2223 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2224 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2226 fetch_texel(mach
->Sampler
, unit
, unit
,
2227 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2228 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2229 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2233 case TGSI_TEXTURE_SHADOW2D
:
2234 case TGSI_TEXTURE_SHADOWRECT
:
2235 case TGSI_TEXTURE_2D_ARRAY
:
2236 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2237 /* only SHADOW2D_ARRAY actually needs W */
2238 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2239 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2240 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2241 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2243 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2244 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2246 fetch_texel(mach
->Sampler
, unit
, unit
,
2247 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2248 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2249 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2252 case TGSI_TEXTURE_3D
:
2253 case TGSI_TEXTURE_CUBE
:
2254 case TGSI_TEXTURE_CUBE_ARRAY
:
2255 case TGSI_TEXTURE_SHADOWCUBE
:
2256 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2257 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2258 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2259 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2260 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2262 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2263 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2264 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2266 fetch_texel(mach
->Sampler
, unit
, unit
,
2267 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2268 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2269 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2276 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2277 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2278 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2285 exec_txf(struct tgsi_exec_machine
*mach
,
2286 const struct tgsi_full_instruction
*inst
)
2288 union tgsi_exec_channel r
[4];
2291 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2296 unit
= fetch_sampler_unit(mach
, inst
, 1);
2297 /* always fetch all 3 offsets, overkill but keeps code simple */
2298 fetch_texel_offsets(mach
, inst
, offsets
);
2300 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2302 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
) {
2303 target
= mach
->SamplerViews
[unit
].Resource
;
2306 target
= inst
->Texture
.Texture
;
2309 case TGSI_TEXTURE_3D
:
2310 case TGSI_TEXTURE_2D_ARRAY
:
2311 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2312 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2313 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2315 case TGSI_TEXTURE_2D
:
2316 case TGSI_TEXTURE_RECT
:
2317 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2318 case TGSI_TEXTURE_SHADOW2D
:
2319 case TGSI_TEXTURE_SHADOWRECT
:
2320 case TGSI_TEXTURE_1D_ARRAY
:
2321 case TGSI_TEXTURE_2D_MSAA
:
2322 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2324 case TGSI_TEXTURE_BUFFER
:
2325 case TGSI_TEXTURE_1D
:
2326 case TGSI_TEXTURE_SHADOW1D
:
2327 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2334 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2337 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2338 r
[0].f
[j
] = rgba
[0][j
];
2339 r
[1].f
[j
] = rgba
[1][j
];
2340 r
[2].f
[j
] = rgba
[2][j
];
2341 r
[3].f
[j
] = rgba
[3][j
];
2344 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
) {
2345 unsigned char swizzles
[4];
2346 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2347 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2348 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2349 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2351 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2352 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2353 store_dest(mach
, &r
[swizzles
[chan
]],
2354 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2359 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2360 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2361 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2368 exec_txq(struct tgsi_exec_machine
*mach
,
2369 const struct tgsi_full_instruction
*inst
)
2372 union tgsi_exec_channel r
[4], src
;
2377 unit
= fetch_sampler_unit(mach
, inst
, 1);
2379 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2381 /* XXX: This interface can't return per-pixel values */
2382 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2384 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2385 for (j
= 0; j
< 4; j
++) {
2386 r
[j
].i
[i
] = result
[j
];
2390 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2391 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2392 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2393 TGSI_EXEC_DATA_INT
);
2399 exec_sample(struct tgsi_exec_machine
*mach
,
2400 const struct tgsi_full_instruction
*inst
,
2401 uint modifier
, boolean compare
)
2403 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2404 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2405 union tgsi_exec_channel r
[5], c1
;
2406 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2407 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2409 unsigned char swizzles
[4];
2412 /* always fetch all 3 offsets, overkill but keeps code simple */
2413 fetch_texel_offsets(mach
, inst
, offsets
);
2415 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2417 if (modifier
!= TEX_MODIFIER_NONE
) {
2418 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2419 FETCH(&c1
, 3, TGSI_CHAN_X
);
2421 control
= TGSI_SAMPLER_LOD_BIAS
;
2423 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2424 FETCH(&c1
, 3, TGSI_CHAN_X
);
2426 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2429 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2430 control
= TGSI_SAMPLER_LOD_ZERO
;
2434 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2436 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2437 case TGSI_TEXTURE_1D
:
2439 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2440 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2441 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2442 NULL
, offsets
, control
,
2443 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2446 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2447 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2448 NULL
, offsets
, control
,
2449 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2453 case TGSI_TEXTURE_1D_ARRAY
:
2454 case TGSI_TEXTURE_2D
:
2455 case TGSI_TEXTURE_RECT
:
2456 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2458 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2459 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2460 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2461 NULL
, offsets
, control
,
2462 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2465 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2466 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2467 NULL
, offsets
, control
,
2468 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2472 case TGSI_TEXTURE_2D_ARRAY
:
2473 case TGSI_TEXTURE_3D
:
2474 case TGSI_TEXTURE_CUBE
:
2475 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2476 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2478 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2479 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2480 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2481 NULL
, offsets
, control
,
2482 &r
[0], &r
[1], &r
[2], &r
[3]);
2485 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2486 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2487 NULL
, offsets
, control
,
2488 &r
[0], &r
[1], &r
[2], &r
[3]);
2492 case TGSI_TEXTURE_CUBE_ARRAY
:
2493 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2494 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2495 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2497 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2498 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2499 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2500 NULL
, offsets
, control
,
2501 &r
[0], &r
[1], &r
[2], &r
[3]);
2504 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2505 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2506 NULL
, offsets
, control
,
2507 &r
[0], &r
[1], &r
[2], &r
[3]);
2516 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2517 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2518 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2519 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2521 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2522 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2523 store_dest(mach
, &r
[swizzles
[chan
]],
2524 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2530 exec_sample_d(struct tgsi_exec_machine
*mach
,
2531 const struct tgsi_full_instruction
*inst
)
2533 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2534 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2535 union tgsi_exec_channel r
[4];
2536 float derivs
[3][2][TGSI_QUAD_SIZE
];
2538 unsigned char swizzles
[4];
2541 /* always fetch all 3 offsets, overkill but keeps code simple */
2542 fetch_texel_offsets(mach
, inst
, offsets
);
2544 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2546 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2547 case TGSI_TEXTURE_1D
:
2548 case TGSI_TEXTURE_1D_ARRAY
:
2549 /* only 1D array actually needs Y */
2550 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2552 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2554 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2555 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2556 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2557 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2560 case TGSI_TEXTURE_2D
:
2561 case TGSI_TEXTURE_RECT
:
2562 case TGSI_TEXTURE_2D_ARRAY
:
2563 /* only 2D array actually needs Z */
2564 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2565 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2567 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2568 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2570 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2571 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2572 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2573 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2576 case TGSI_TEXTURE_3D
:
2577 case TGSI_TEXTURE_CUBE
:
2578 case TGSI_TEXTURE_CUBE_ARRAY
:
2579 /* only cube array actually needs W */
2580 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2581 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2582 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2584 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2585 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2586 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2588 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2589 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2590 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2591 &r
[0], &r
[1], &r
[2], &r
[3]);
2598 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2599 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2600 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2601 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2603 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2604 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2605 store_dest(mach
, &r
[swizzles
[chan
]],
2606 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2613 * Evaluate a constant-valued coefficient at the position of the
2618 struct tgsi_exec_machine
*mach
,
2624 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2625 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2630 * Evaluate a linear-valued coefficient at the position of the
2635 struct tgsi_exec_machine
*mach
,
2639 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2640 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2641 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2642 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2643 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2644 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2645 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2646 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2647 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2651 * Evaluate a perspective-valued coefficient at the position of the
2655 eval_perspective_coef(
2656 struct tgsi_exec_machine
*mach
,
2660 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2661 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2662 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2663 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2664 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2665 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2666 /* divide by W here */
2667 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2668 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2669 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2670 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2674 typedef void (* eval_coef_func
)(
2675 struct tgsi_exec_machine
*mach
,
2680 exec_declaration(struct tgsi_exec_machine
*mach
,
2681 const struct tgsi_full_declaration
*decl
)
2683 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2684 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2688 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
2689 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2690 uint first
, last
, mask
;
2692 first
= decl
->Range
.First
;
2693 last
= decl
->Range
.Last
;
2694 mask
= decl
->Declaration
.UsageMask
;
2696 /* XXX we could remove this special-case code since
2697 * mach->InterpCoefs[first].a0 should already have the
2698 * front/back-face value. But we should first update the
2699 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2700 * Then, we could remove the tgsi_exec_machine::Face field.
2702 /* XXX make FACE a system value */
2703 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2706 assert(decl
->Semantic
.Index
== 0);
2707 assert(first
== last
);
2709 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2710 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2713 eval_coef_func eval
;
2716 switch (decl
->Interp
.Interpolate
) {
2717 case TGSI_INTERPOLATE_CONSTANT
:
2718 eval
= eval_constant_coef
;
2721 case TGSI_INTERPOLATE_LINEAR
:
2722 eval
= eval_linear_coef
;
2725 case TGSI_INTERPOLATE_PERSPECTIVE
:
2726 eval
= eval_perspective_coef
;
2729 case TGSI_INTERPOLATE_COLOR
:
2730 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
2738 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2739 if (mask
& (1 << j
)) {
2740 for (i
= first
; i
<= last
; i
++) {
2747 if (DEBUG_EXECUTION
) {
2749 for (i
= first
; i
<= last
; ++i
) {
2750 debug_printf("IN[%2u] = ", i
);
2751 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2755 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2756 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
2757 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
2758 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
2759 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
2766 if (decl
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
2767 mach
->SysSemanticToIndex
[decl
->Declaration
.Semantic
] = decl
->Range
.First
;
2771 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
2772 const union tgsi_exec_channel
*src
);
2775 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
2776 const struct tgsi_full_instruction
*inst
,
2778 enum tgsi_exec_datatype dst_datatype
,
2779 enum tgsi_exec_datatype src_datatype
)
2782 union tgsi_exec_channel src
;
2783 union tgsi_exec_channel dst
;
2785 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2787 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2788 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2789 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2795 exec_vector_unary(struct tgsi_exec_machine
*mach
,
2796 const struct tgsi_full_instruction
*inst
,
2798 enum tgsi_exec_datatype dst_datatype
,
2799 enum tgsi_exec_datatype src_datatype
)
2802 struct tgsi_exec_vector dst
;
2804 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2805 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2806 union tgsi_exec_channel src
;
2808 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
2809 op(&dst
.xyzw
[chan
], &src
);
2812 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2813 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2814 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2819 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
2820 const union tgsi_exec_channel
*src0
,
2821 const union tgsi_exec_channel
*src1
);
2824 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
2825 const struct tgsi_full_instruction
*inst
,
2827 enum tgsi_exec_datatype dst_datatype
,
2828 enum tgsi_exec_datatype src_datatype
)
2831 union tgsi_exec_channel src
[2];
2832 union tgsi_exec_channel dst
;
2834 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2835 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
2836 op(&dst
, &src
[0], &src
[1]);
2837 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2838 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2839 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2845 exec_vector_binary(struct tgsi_exec_machine
*mach
,
2846 const struct tgsi_full_instruction
*inst
,
2848 enum tgsi_exec_datatype dst_datatype
,
2849 enum tgsi_exec_datatype src_datatype
)
2852 struct tgsi_exec_vector dst
;
2854 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2855 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2856 union tgsi_exec_channel src
[2];
2858 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2859 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2860 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
2863 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2864 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2865 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2870 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
2871 const union tgsi_exec_channel
*src0
,
2872 const union tgsi_exec_channel
*src1
,
2873 const union tgsi_exec_channel
*src2
);
2876 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
2877 const struct tgsi_full_instruction
*inst
,
2878 micro_trinary_op op
,
2879 enum tgsi_exec_datatype dst_datatype
,
2880 enum tgsi_exec_datatype src_datatype
)
2883 struct tgsi_exec_vector dst
;
2885 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2886 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2887 union tgsi_exec_channel src
[3];
2889 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2890 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2891 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2892 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
2895 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2896 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2897 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2902 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
2903 const union tgsi_exec_channel
*src0
,
2904 const union tgsi_exec_channel
*src1
,
2905 const union tgsi_exec_channel
*src2
,
2906 const union tgsi_exec_channel
*src3
);
2909 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
2910 const struct tgsi_full_instruction
*inst
,
2911 micro_quaternary_op op
,
2912 enum tgsi_exec_datatype dst_datatype
,
2913 enum tgsi_exec_datatype src_datatype
)
2916 struct tgsi_exec_vector dst
;
2918 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2919 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2920 union tgsi_exec_channel src
[4];
2922 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2923 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2924 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2925 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
2926 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
2929 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2930 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2931 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2937 exec_dp3(struct tgsi_exec_machine
*mach
,
2938 const struct tgsi_full_instruction
*inst
)
2941 union tgsi_exec_channel arg
[3];
2943 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2944 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2945 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2947 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
2948 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2949 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2950 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2953 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2954 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2955 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2961 exec_dp4(struct tgsi_exec_machine
*mach
,
2962 const struct tgsi_full_instruction
*inst
)
2965 union tgsi_exec_channel arg
[3];
2967 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2968 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2969 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2971 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
2972 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2973 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2974 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2977 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2978 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2979 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2985 exec_dp2a(struct tgsi_exec_machine
*mach
,
2986 const struct tgsi_full_instruction
*inst
)
2989 union tgsi_exec_channel arg
[3];
2991 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2992 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2993 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2995 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2996 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2997 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
2999 fetch_source(mach
, &arg
[1], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3000 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3002 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3003 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3004 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3010 exec_dph(struct tgsi_exec_machine
*mach
,
3011 const struct tgsi_full_instruction
*inst
)
3014 union tgsi_exec_channel arg
[3];
3016 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3017 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3018 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3020 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3021 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3022 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3024 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3025 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3026 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3028 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3029 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3031 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3032 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3033 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3039 exec_dp2(struct tgsi_exec_machine
*mach
,
3040 const struct tgsi_full_instruction
*inst
)
3043 union tgsi_exec_channel arg
[3];
3045 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3046 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3047 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3049 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3050 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3051 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3053 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3054 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3055 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3061 exec_scs(struct tgsi_exec_machine
*mach
,
3062 const struct tgsi_full_instruction
*inst
)
3064 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
3065 union tgsi_exec_channel arg
;
3066 union tgsi_exec_channel result
;
3068 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3070 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3071 micro_cos(&result
, &arg
);
3072 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3074 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3075 micro_sin(&result
, &arg
);
3076 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3079 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3080 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3082 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3083 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3088 exec_xpd(struct tgsi_exec_machine
*mach
,
3089 const struct tgsi_full_instruction
*inst
)
3091 union tgsi_exec_channel r
[6];
3092 union tgsi_exec_channel d
[3];
3094 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3095 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3097 micro_mul(&r
[2], &r
[0], &r
[1]);
3099 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3100 fetch_source(mach
, &r
[4], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3102 micro_mul(&r
[5], &r
[3], &r
[4] );
3103 micro_sub(&d
[TGSI_CHAN_X
], &r
[2], &r
[5]);
3105 fetch_source(mach
, &r
[2], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3107 micro_mul(&r
[3], &r
[3], &r
[2]);
3109 fetch_source(mach
, &r
[5], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3111 micro_mul(&r
[1], &r
[1], &r
[5]);
3112 micro_sub(&d
[TGSI_CHAN_Y
], &r
[3], &r
[1]);
3114 micro_mul(&r
[5], &r
[5], &r
[4]);
3115 micro_mul(&r
[0], &r
[0], &r
[2]);
3116 micro_sub(&d
[TGSI_CHAN_Z
], &r
[5], &r
[0]);
3118 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3119 store_dest(mach
, &d
[TGSI_CHAN_X
], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3121 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3122 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3124 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3125 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3127 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3128 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3133 exec_dst(struct tgsi_exec_machine
*mach
,
3134 const struct tgsi_full_instruction
*inst
)
3136 union tgsi_exec_channel r
[2];
3137 union tgsi_exec_channel d
[4];
3139 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3140 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3141 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3142 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3144 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3145 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3147 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3148 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3151 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3152 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3154 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3155 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3157 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3158 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3160 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3161 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3166 exec_log(struct tgsi_exec_machine
*mach
,
3167 const struct tgsi_full_instruction
*inst
)
3169 union tgsi_exec_channel r
[3];
3171 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3172 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3173 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3174 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3175 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3176 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3178 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3179 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3180 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3181 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3183 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3184 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3186 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3187 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3192 exec_exp(struct tgsi_exec_machine
*mach
,
3193 const struct tgsi_full_instruction
*inst
)
3195 union tgsi_exec_channel r
[3];
3197 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3198 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3199 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3200 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3201 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3203 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3204 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3205 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3207 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3208 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3209 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3211 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3212 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3217 exec_lit(struct tgsi_exec_machine
*mach
,
3218 const struct tgsi_full_instruction
*inst
)
3220 union tgsi_exec_channel r
[3];
3221 union tgsi_exec_channel d
[3];
3223 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3224 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3225 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3226 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3227 micro_max(&r
[1], &r
[1], &ZeroVec
);
3229 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3230 micro_min(&r
[2], &r
[2], &P128Vec
);
3231 micro_max(&r
[2], &r
[2], &M128Vec
);
3232 micro_pow(&r
[1], &r
[1], &r
[2]);
3233 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3234 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3236 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3237 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3238 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3241 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3242 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3245 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3246 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3251 exec_break(struct tgsi_exec_machine
*mach
)
3253 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3254 /* turn off loop channels for each enabled exec channel */
3255 mach
->LoopMask
&= ~mach
->ExecMask
;
3256 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3257 UPDATE_EXEC_MASK(mach
);
3259 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3261 mach
->Switch
.mask
= 0x0;
3263 UPDATE_EXEC_MASK(mach
);
3268 exec_switch(struct tgsi_exec_machine
*mach
,
3269 const struct tgsi_full_instruction
*inst
)
3271 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3272 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3274 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3275 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3276 mach
->Switch
.mask
= 0x0;
3277 mach
->Switch
.defaultMask
= 0x0;
3279 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3280 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3282 UPDATE_EXEC_MASK(mach
);
3286 exec_case(struct tgsi_exec_machine
*mach
,
3287 const struct tgsi_full_instruction
*inst
)
3289 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3290 union tgsi_exec_channel src
;
3293 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3295 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3298 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3301 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3304 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3308 mach
->Switch
.defaultMask
|= mask
;
3310 mach
->Switch
.mask
|= mask
& prevMask
;
3312 UPDATE_EXEC_MASK(mach
);
3315 /* FIXME: this will only work if default is last */
3317 exec_default(struct tgsi_exec_machine
*mach
)
3319 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3321 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3323 UPDATE_EXEC_MASK(mach
);
3327 exec_endswitch(struct tgsi_exec_machine
*mach
)
3329 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3330 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3332 UPDATE_EXEC_MASK(mach
);
3335 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3336 const union tgsi_double_channel
*src
);
3339 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3340 union tgsi_double_channel
*chan
,
3341 const struct tgsi_full_src_register
*reg
,
3345 union tgsi_exec_channel src
[2];
3348 fetch_source_d(mach
, &src
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3349 fetch_source_d(mach
, &src
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3351 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3352 chan
->u
[i
][0] = src
[0].u
[i
];
3353 chan
->u
[i
][1] = src
[1].u
[i
];
3355 if (reg
->Register
.Absolute
) {
3356 micro_dabs(chan
, chan
);
3358 if (reg
->Register
.Negate
) {
3359 micro_dneg(chan
, chan
);
3364 store_double_channel(struct tgsi_exec_machine
*mach
,
3365 const union tgsi_double_channel
*chan
,
3366 const struct tgsi_full_dst_register
*reg
,
3367 const struct tgsi_full_instruction
*inst
,
3371 union tgsi_exec_channel dst
[2];
3373 union tgsi_double_channel temp
;
3374 const uint execmask
= mach
->ExecMask
;
3376 if (!inst
->Instruction
.Saturate
) {
3377 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3378 if (execmask
& (1 << i
)) {
3379 dst
[0].u
[i
] = chan
->u
[i
][0];
3380 dst
[1].u
[i
] = chan
->u
[i
][1];
3384 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3385 if (execmask
& (1 << i
)) {
3386 if (chan
->d
[i
] < 0.0)
3388 else if (chan
->d
[i
] > 1.0)
3391 temp
.d
[i
] = chan
->d
[i
];
3393 dst
[0].u
[i
] = temp
.u
[i
][0];
3394 dst
[1].u
[i
] = temp
.u
[i
][1];
3398 store_dest_double(mach
, &dst
[0], reg
, inst
, chan_0
, TGSI_EXEC_DATA_UINT
);
3400 store_dest_double(mach
, &dst
[1], reg
, inst
, chan_1
, TGSI_EXEC_DATA_UINT
);
3404 exec_double_unary(struct tgsi_exec_machine
*mach
,
3405 const struct tgsi_full_instruction
*inst
,
3408 union tgsi_double_channel src
;
3409 union tgsi_double_channel dst
;
3411 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3412 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3414 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3416 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3417 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3419 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3424 exec_double_binary(struct tgsi_exec_machine
*mach
,
3425 const struct tgsi_full_instruction
*inst
,
3427 enum tgsi_exec_datatype dst_datatype
)
3429 union tgsi_double_channel src
[2];
3430 union tgsi_double_channel dst
;
3431 int first_dest_chan
, second_dest_chan
;
3434 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3435 /* these are & because of the way DSLT etc store their destinations */
3436 if (wmask
& TGSI_WRITEMASK_XY
) {
3437 first_dest_chan
= TGSI_CHAN_X
;
3438 second_dest_chan
= TGSI_CHAN_Y
;
3439 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3440 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3441 second_dest_chan
= -1;
3444 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3445 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3447 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3450 if (wmask
& TGSI_WRITEMASK_ZW
) {
3451 first_dest_chan
= TGSI_CHAN_Z
;
3452 second_dest_chan
= TGSI_CHAN_W
;
3453 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3454 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3455 second_dest_chan
= -1;
3458 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3459 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3461 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3466 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3467 const struct tgsi_full_instruction
*inst
,
3470 union tgsi_double_channel src
[3];
3471 union tgsi_double_channel dst
;
3473 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3474 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3475 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3476 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3478 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3480 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3481 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3482 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3483 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3485 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3490 exec_f2d(struct tgsi_exec_machine
*mach
,
3491 const struct tgsi_full_instruction
*inst
)
3493 union tgsi_exec_channel src
;
3494 union tgsi_double_channel dst
;
3496 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3497 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3498 micro_f2d(&dst
, &src
);
3499 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3501 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3502 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3503 micro_f2d(&dst
, &src
);
3504 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3509 exec_d2f(struct tgsi_exec_machine
*mach
,
3510 const struct tgsi_full_instruction
*inst
)
3512 union tgsi_double_channel src
;
3513 union tgsi_exec_channel dst
;
3514 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3517 for (i
= 0; i
< 2; i
++) {
3520 wm
&= ~(1 << (bit
- 1));
3522 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3524 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3525 micro_d2f(&dst
, &src
);
3526 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_FLOAT
);
3532 exec_i2d(struct tgsi_exec_machine
*mach
,
3533 const struct tgsi_full_instruction
*inst
)
3535 union tgsi_exec_channel src
;
3536 union tgsi_double_channel dst
;
3538 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3539 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3540 micro_i2d(&dst
, &src
);
3541 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3543 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3544 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_INT
);
3545 micro_i2d(&dst
, &src
);
3546 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3551 exec_d2i(struct tgsi_exec_machine
*mach
,
3552 const struct tgsi_full_instruction
*inst
)
3554 union tgsi_double_channel src
;
3555 union tgsi_exec_channel dst
;
3556 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3559 for (i
= 0; i
< 2; i
++) {
3562 wm
&= ~(1 << (bit
- 1));
3564 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3566 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3567 micro_d2i(&dst
, &src
);
3568 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_INT
);
3573 exec_u2d(struct tgsi_exec_machine
*mach
,
3574 const struct tgsi_full_instruction
*inst
)
3576 union tgsi_exec_channel src
;
3577 union tgsi_double_channel dst
;
3579 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3580 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3581 micro_u2d(&dst
, &src
);
3582 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3584 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3585 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_UINT
);
3586 micro_u2d(&dst
, &src
);
3587 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3592 exec_d2u(struct tgsi_exec_machine
*mach
,
3593 const struct tgsi_full_instruction
*inst
)
3595 union tgsi_double_channel src
;
3596 union tgsi_exec_channel dst
;
3597 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3600 for (i
= 0; i
< 2; i
++) {
3603 wm
&= ~(1 << (bit
- 1));
3605 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3607 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3608 micro_d2u(&dst
, &src
);
3609 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_UINT
);
3615 exec_dldexp(struct tgsi_exec_machine
*mach
,
3616 const struct tgsi_full_instruction
*inst
)
3618 union tgsi_double_channel src0
;
3619 union tgsi_exec_channel src1
;
3620 union tgsi_double_channel dst
;
3623 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3624 if (wmask
& TGSI_WRITEMASK_XY
) {
3625 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3626 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3627 micro_dldexp(&dst
, &src0
, &src1
);
3628 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3631 if (wmask
& TGSI_WRITEMASK_ZW
) {
3632 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3633 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3634 micro_dldexp(&dst
, &src0
, &src1
);
3635 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3640 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3641 const struct tgsi_full_instruction
*inst
)
3643 union tgsi_double_channel src
;
3644 union tgsi_double_channel dst
;
3645 union tgsi_exec_channel dst_exp
;
3647 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)) {
3648 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3649 micro_dfracexp(&dst
, &dst_exp
, &src
);
3650 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3651 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3653 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)) {
3654 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3655 micro_dfracexp(&dst
, &dst_exp
, &src
);
3656 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3657 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3663 micro_i2f(union tgsi_exec_channel
*dst
,
3664 const union tgsi_exec_channel
*src
)
3666 dst
->f
[0] = (float)src
->i
[0];
3667 dst
->f
[1] = (float)src
->i
[1];
3668 dst
->f
[2] = (float)src
->i
[2];
3669 dst
->f
[3] = (float)src
->i
[3];
3673 micro_not(union tgsi_exec_channel
*dst
,
3674 const union tgsi_exec_channel
*src
)
3676 dst
->u
[0] = ~src
->u
[0];
3677 dst
->u
[1] = ~src
->u
[1];
3678 dst
->u
[2] = ~src
->u
[2];
3679 dst
->u
[3] = ~src
->u
[3];
3683 micro_shl(union tgsi_exec_channel
*dst
,
3684 const union tgsi_exec_channel
*src0
,
3685 const union tgsi_exec_channel
*src1
)
3687 unsigned masked_count
;
3688 masked_count
= src1
->u
[0] & 0x1f;
3689 dst
->u
[0] = src0
->u
[0] << masked_count
;
3690 masked_count
= src1
->u
[1] & 0x1f;
3691 dst
->u
[1] = src0
->u
[1] << masked_count
;
3692 masked_count
= src1
->u
[2] & 0x1f;
3693 dst
->u
[2] = src0
->u
[2] << masked_count
;
3694 masked_count
= src1
->u
[3] & 0x1f;
3695 dst
->u
[3] = src0
->u
[3] << masked_count
;
3699 micro_and(union tgsi_exec_channel
*dst
,
3700 const union tgsi_exec_channel
*src0
,
3701 const union tgsi_exec_channel
*src1
)
3703 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
3704 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
3705 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
3706 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
3710 micro_or(union tgsi_exec_channel
*dst
,
3711 const union tgsi_exec_channel
*src0
,
3712 const union tgsi_exec_channel
*src1
)
3714 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
3715 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
3716 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
3717 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
3721 micro_xor(union tgsi_exec_channel
*dst
,
3722 const union tgsi_exec_channel
*src0
,
3723 const union tgsi_exec_channel
*src1
)
3725 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
3726 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
3727 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
3728 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
3732 micro_mod(union tgsi_exec_channel
*dst
,
3733 const union tgsi_exec_channel
*src0
,
3734 const union tgsi_exec_channel
*src1
)
3736 dst
->i
[0] = src0
->i
[0] % src1
->i
[0];
3737 dst
->i
[1] = src0
->i
[1] % src1
->i
[1];
3738 dst
->i
[2] = src0
->i
[2] % src1
->i
[2];
3739 dst
->i
[3] = src0
->i
[3] % src1
->i
[3];
3743 micro_f2i(union tgsi_exec_channel
*dst
,
3744 const union tgsi_exec_channel
*src
)
3746 dst
->i
[0] = (int)src
->f
[0];
3747 dst
->i
[1] = (int)src
->f
[1];
3748 dst
->i
[2] = (int)src
->f
[2];
3749 dst
->i
[3] = (int)src
->f
[3];
3753 micro_fseq(union tgsi_exec_channel
*dst
,
3754 const union tgsi_exec_channel
*src0
,
3755 const union tgsi_exec_channel
*src1
)
3757 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
3758 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
3759 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
3760 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
3764 micro_fsge(union tgsi_exec_channel
*dst
,
3765 const union tgsi_exec_channel
*src0
,
3766 const union tgsi_exec_channel
*src1
)
3768 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
3769 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
3770 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
3771 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
3775 micro_fslt(union tgsi_exec_channel
*dst
,
3776 const union tgsi_exec_channel
*src0
,
3777 const union tgsi_exec_channel
*src1
)
3779 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
3780 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
3781 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
3782 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
3786 micro_fsne(union tgsi_exec_channel
*dst
,
3787 const union tgsi_exec_channel
*src0
,
3788 const union tgsi_exec_channel
*src1
)
3790 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
3791 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
3792 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
3793 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
3797 micro_idiv(union tgsi_exec_channel
*dst
,
3798 const union tgsi_exec_channel
*src0
,
3799 const union tgsi_exec_channel
*src1
)
3801 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
3802 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
3803 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
3804 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
3808 micro_imax(union tgsi_exec_channel
*dst
,
3809 const union tgsi_exec_channel
*src0
,
3810 const union tgsi_exec_channel
*src1
)
3812 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
3813 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
3814 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
3815 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
3819 micro_imin(union tgsi_exec_channel
*dst
,
3820 const union tgsi_exec_channel
*src0
,
3821 const union tgsi_exec_channel
*src1
)
3823 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
3824 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
3825 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
3826 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
3830 micro_isge(union tgsi_exec_channel
*dst
,
3831 const union tgsi_exec_channel
*src0
,
3832 const union tgsi_exec_channel
*src1
)
3834 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
3835 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
3836 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
3837 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
3841 micro_ishr(union tgsi_exec_channel
*dst
,
3842 const union tgsi_exec_channel
*src0
,
3843 const union tgsi_exec_channel
*src1
)
3845 unsigned masked_count
;
3846 masked_count
= src1
->i
[0] & 0x1f;
3847 dst
->i
[0] = src0
->i
[0] >> masked_count
;
3848 masked_count
= src1
->i
[1] & 0x1f;
3849 dst
->i
[1] = src0
->i
[1] >> masked_count
;
3850 masked_count
= src1
->i
[2] & 0x1f;
3851 dst
->i
[2] = src0
->i
[2] >> masked_count
;
3852 masked_count
= src1
->i
[3] & 0x1f;
3853 dst
->i
[3] = src0
->i
[3] >> masked_count
;
3857 micro_islt(union tgsi_exec_channel
*dst
,
3858 const union tgsi_exec_channel
*src0
,
3859 const union tgsi_exec_channel
*src1
)
3861 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
3862 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
3863 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
3864 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
3868 micro_f2u(union tgsi_exec_channel
*dst
,
3869 const union tgsi_exec_channel
*src
)
3871 dst
->u
[0] = (uint
)src
->f
[0];
3872 dst
->u
[1] = (uint
)src
->f
[1];
3873 dst
->u
[2] = (uint
)src
->f
[2];
3874 dst
->u
[3] = (uint
)src
->f
[3];
3878 micro_u2f(union tgsi_exec_channel
*dst
,
3879 const union tgsi_exec_channel
*src
)
3881 dst
->f
[0] = (float)src
->u
[0];
3882 dst
->f
[1] = (float)src
->u
[1];
3883 dst
->f
[2] = (float)src
->u
[2];
3884 dst
->f
[3] = (float)src
->u
[3];
3888 micro_uadd(union tgsi_exec_channel
*dst
,
3889 const union tgsi_exec_channel
*src0
,
3890 const union tgsi_exec_channel
*src1
)
3892 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
3893 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
3894 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
3895 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
3899 micro_udiv(union tgsi_exec_channel
*dst
,
3900 const union tgsi_exec_channel
*src0
,
3901 const union tgsi_exec_channel
*src1
)
3903 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
3904 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
3905 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
3906 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
3910 micro_umad(union tgsi_exec_channel
*dst
,
3911 const union tgsi_exec_channel
*src0
,
3912 const union tgsi_exec_channel
*src1
,
3913 const union tgsi_exec_channel
*src2
)
3915 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
3916 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
3917 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
3918 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
3922 micro_umax(union tgsi_exec_channel
*dst
,
3923 const union tgsi_exec_channel
*src0
,
3924 const union tgsi_exec_channel
*src1
)
3926 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
3927 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
3928 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
3929 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
3933 micro_umin(union tgsi_exec_channel
*dst
,
3934 const union tgsi_exec_channel
*src0
,
3935 const union tgsi_exec_channel
*src1
)
3937 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
3938 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
3939 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
3940 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
3944 micro_umod(union tgsi_exec_channel
*dst
,
3945 const union tgsi_exec_channel
*src0
,
3946 const union tgsi_exec_channel
*src1
)
3948 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
3949 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
3950 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
3951 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
3955 micro_umul(union tgsi_exec_channel
*dst
,
3956 const union tgsi_exec_channel
*src0
,
3957 const union tgsi_exec_channel
*src1
)
3959 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
3960 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
3961 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
3962 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
3966 micro_imul_hi(union tgsi_exec_channel
*dst
,
3967 const union tgsi_exec_channel
*src0
,
3968 const union tgsi_exec_channel
*src1
)
3970 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3971 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
3972 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
3973 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
3974 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
3979 micro_umul_hi(union tgsi_exec_channel
*dst
,
3980 const union tgsi_exec_channel
*src0
,
3981 const union tgsi_exec_channel
*src1
)
3983 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3984 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
3985 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
3986 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
3987 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
3992 micro_useq(union tgsi_exec_channel
*dst
,
3993 const union tgsi_exec_channel
*src0
,
3994 const union tgsi_exec_channel
*src1
)
3996 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
3997 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
3998 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
3999 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4003 micro_usge(union tgsi_exec_channel
*dst
,
4004 const union tgsi_exec_channel
*src0
,
4005 const union tgsi_exec_channel
*src1
)
4007 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4008 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4009 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4010 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4014 micro_ushr(union tgsi_exec_channel
*dst
,
4015 const union tgsi_exec_channel
*src0
,
4016 const union tgsi_exec_channel
*src1
)
4018 unsigned masked_count
;
4019 masked_count
= src1
->u
[0] & 0x1f;
4020 dst
->u
[0] = src0
->u
[0] >> masked_count
;
4021 masked_count
= src1
->u
[1] & 0x1f;
4022 dst
->u
[1] = src0
->u
[1] >> masked_count
;
4023 masked_count
= src1
->u
[2] & 0x1f;
4024 dst
->u
[2] = src0
->u
[2] >> masked_count
;
4025 masked_count
= src1
->u
[3] & 0x1f;
4026 dst
->u
[3] = src0
->u
[3] >> masked_count
;
4030 micro_uslt(union tgsi_exec_channel
*dst
,
4031 const union tgsi_exec_channel
*src0
,
4032 const union tgsi_exec_channel
*src1
)
4034 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
4035 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
4036 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
4037 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
4041 micro_usne(union tgsi_exec_channel
*dst
,
4042 const union tgsi_exec_channel
*src0
,
4043 const union tgsi_exec_channel
*src1
)
4045 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
4046 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
4047 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
4048 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
4052 micro_uarl(union tgsi_exec_channel
*dst
,
4053 const union tgsi_exec_channel
*src
)
4055 dst
->i
[0] = src
->u
[0];
4056 dst
->i
[1] = src
->u
[1];
4057 dst
->i
[2] = src
->u
[2];
4058 dst
->i
[3] = src
->u
[3];
4062 micro_ucmp(union tgsi_exec_channel
*dst
,
4063 const union tgsi_exec_channel
*src0
,
4064 const union tgsi_exec_channel
*src1
,
4065 const union tgsi_exec_channel
*src2
)
4067 dst
->u
[0] = src0
->u
[0] ? src1
->u
[0] : src2
->u
[0];
4068 dst
->u
[1] = src0
->u
[1] ? src1
->u
[1] : src2
->u
[1];
4069 dst
->u
[2] = src0
->u
[2] ? src1
->u
[2] : src2
->u
[2];
4070 dst
->u
[3] = src0
->u
[3] ? src1
->u
[3] : src2
->u
[3];
4074 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4077 micro_ibfe(union tgsi_exec_channel
*dst
,
4078 const union tgsi_exec_channel
*src0
,
4079 const union tgsi_exec_channel
*src1
,
4080 const union tgsi_exec_channel
*src2
)
4083 for (i
= 0; i
< 4; i
++) {
4084 int width
= src2
->i
[i
] & 0x1f;
4085 int offset
= src1
->i
[i
] & 0x1f;
4088 else if (width
+ offset
< 32)
4089 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
4091 dst
->i
[i
] = src0
->i
[i
] >> offset
;
4096 * Unsigned bitfield extract
4099 micro_ubfe(union tgsi_exec_channel
*dst
,
4100 const union tgsi_exec_channel
*src0
,
4101 const union tgsi_exec_channel
*src1
,
4102 const union tgsi_exec_channel
*src2
)
4105 for (i
= 0; i
< 4; i
++) {
4106 int width
= src2
->u
[i
] & 0x1f;
4107 int offset
= src1
->u
[i
] & 0x1f;
4110 else if (width
+ offset
< 32)
4111 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
4113 dst
->u
[i
] = src0
->u
[i
] >> offset
;
4118 * Bitfield insert: copy low bits from src1 into a region of src0.
4121 micro_bfi(union tgsi_exec_channel
*dst
,
4122 const union tgsi_exec_channel
*src0
,
4123 const union tgsi_exec_channel
*src1
,
4124 const union tgsi_exec_channel
*src2
,
4125 const union tgsi_exec_channel
*src3
)
4128 for (i
= 0; i
< 4; i
++) {
4129 int width
= src3
->u
[i
] & 0x1f;
4130 int offset
= src2
->u
[i
] & 0x1f;
4131 int bitmask
= ((1 << width
) - 1) << offset
;
4132 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
4137 micro_brev(union tgsi_exec_channel
*dst
,
4138 const union tgsi_exec_channel
*src
)
4140 dst
->u
[0] = util_bitreverse(src
->u
[0]);
4141 dst
->u
[1] = util_bitreverse(src
->u
[1]);
4142 dst
->u
[2] = util_bitreverse(src
->u
[2]);
4143 dst
->u
[3] = util_bitreverse(src
->u
[3]);
4147 micro_popc(union tgsi_exec_channel
*dst
,
4148 const union tgsi_exec_channel
*src
)
4150 dst
->u
[0] = util_bitcount(src
->u
[0]);
4151 dst
->u
[1] = util_bitcount(src
->u
[1]);
4152 dst
->u
[2] = util_bitcount(src
->u
[2]);
4153 dst
->u
[3] = util_bitcount(src
->u
[3]);
4157 micro_lsb(union tgsi_exec_channel
*dst
,
4158 const union tgsi_exec_channel
*src
)
4160 dst
->i
[0] = ffs(src
->u
[0]) - 1;
4161 dst
->i
[1] = ffs(src
->u
[1]) - 1;
4162 dst
->i
[2] = ffs(src
->u
[2]) - 1;
4163 dst
->i
[3] = ffs(src
->u
[3]) - 1;
4167 micro_imsb(union tgsi_exec_channel
*dst
,
4168 const union tgsi_exec_channel
*src
)
4170 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
4171 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
4172 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
4173 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
4177 micro_umsb(union tgsi_exec_channel
*dst
,
4178 const union tgsi_exec_channel
*src
)
4180 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
4181 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
4182 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
4183 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
4188 struct tgsi_exec_machine
*mach
,
4189 const struct tgsi_full_instruction
*inst
,
4192 union tgsi_exec_channel r
[10];
4196 switch (inst
->Instruction
.Opcode
) {
4197 case TGSI_OPCODE_ARL
:
4198 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4201 case TGSI_OPCODE_MOV
:
4202 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4205 case TGSI_OPCODE_LIT
:
4206 exec_lit(mach
, inst
);
4209 case TGSI_OPCODE_RCP
:
4210 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4213 case TGSI_OPCODE_RSQ
:
4214 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4217 case TGSI_OPCODE_EXP
:
4218 exec_exp(mach
, inst
);
4221 case TGSI_OPCODE_LOG
:
4222 exec_log(mach
, inst
);
4225 case TGSI_OPCODE_MUL
:
4226 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4229 case TGSI_OPCODE_ADD
:
4230 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4233 case TGSI_OPCODE_DP3
:
4234 exec_dp3(mach
, inst
);
4237 case TGSI_OPCODE_DP4
:
4238 exec_dp4(mach
, inst
);
4241 case TGSI_OPCODE_DST
:
4242 exec_dst(mach
, inst
);
4245 case TGSI_OPCODE_MIN
:
4246 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4249 case TGSI_OPCODE_MAX
:
4250 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4253 case TGSI_OPCODE_SLT
:
4254 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4257 case TGSI_OPCODE_SGE
:
4258 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4261 case TGSI_OPCODE_MAD
:
4262 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4265 case TGSI_OPCODE_SUB
:
4266 exec_vector_binary(mach
, inst
, micro_sub
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4269 case TGSI_OPCODE_LRP
:
4270 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4273 case TGSI_OPCODE_SQRT
:
4274 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4277 case TGSI_OPCODE_DP2A
:
4278 exec_dp2a(mach
, inst
);
4281 case TGSI_OPCODE_FRC
:
4282 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4285 case TGSI_OPCODE_CLAMP
:
4286 exec_vector_trinary(mach
, inst
, micro_clamp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4289 case TGSI_OPCODE_FLR
:
4290 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4293 case TGSI_OPCODE_ROUND
:
4294 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4297 case TGSI_OPCODE_EX2
:
4298 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4301 case TGSI_OPCODE_LG2
:
4302 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4305 case TGSI_OPCODE_POW
:
4306 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4309 case TGSI_OPCODE_XPD
:
4310 exec_xpd(mach
, inst
);
4313 case TGSI_OPCODE_ABS
:
4314 exec_vector_unary(mach
, inst
, micro_abs
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4317 case TGSI_OPCODE_DPH
:
4318 exec_dph(mach
, inst
);
4321 case TGSI_OPCODE_COS
:
4322 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4325 case TGSI_OPCODE_DDX
:
4326 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4329 case TGSI_OPCODE_DDY
:
4330 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4333 case TGSI_OPCODE_KILL
:
4334 exec_kill (mach
, inst
);
4337 case TGSI_OPCODE_KILL_IF
:
4338 exec_kill_if (mach
, inst
);
4341 case TGSI_OPCODE_PK2H
:
4345 case TGSI_OPCODE_PK2US
:
4349 case TGSI_OPCODE_PK4B
:
4353 case TGSI_OPCODE_PK4UB
:
4357 case TGSI_OPCODE_SEQ
:
4358 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4361 case TGSI_OPCODE_SGT
:
4362 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4365 case TGSI_OPCODE_SIN
:
4366 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4369 case TGSI_OPCODE_SLE
:
4370 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4373 case TGSI_OPCODE_SNE
:
4374 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4377 case TGSI_OPCODE_TEX
:
4378 /* simple texture lookup */
4379 /* src[0] = texcoord */
4380 /* src[1] = sampler unit */
4381 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
4384 case TGSI_OPCODE_TXB
:
4385 /* Texture lookup with lod bias */
4386 /* src[0] = texcoord (src[0].w = LOD bias) */
4387 /* src[1] = sampler unit */
4388 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
4391 case TGSI_OPCODE_TXD
:
4392 /* Texture lookup with explict partial derivatives */
4393 /* src[0] = texcoord */
4394 /* src[1] = d[strq]/dx */
4395 /* src[2] = d[strq]/dy */
4396 /* src[3] = sampler unit */
4397 exec_txd(mach
, inst
);
4400 case TGSI_OPCODE_TXL
:
4401 /* Texture lookup with explit LOD */
4402 /* src[0] = texcoord (src[0].w = LOD) */
4403 /* src[1] = sampler unit */
4404 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
4407 case TGSI_OPCODE_TXP
:
4408 /* Texture lookup with projection */
4409 /* src[0] = texcoord (src[0].w = projection) */
4410 /* src[1] = sampler unit */
4411 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
4414 case TGSI_OPCODE_TG4
:
4415 /* src[0] = texcoord */
4416 /* src[1] = component */
4417 /* src[2] = sampler unit */
4418 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
4421 case TGSI_OPCODE_LODQ
:
4422 /* src[0] = texcoord */
4423 /* src[1] = sampler unit */
4424 exec_lodq(mach
, inst
);
4427 case TGSI_OPCODE_UP2H
:
4431 case TGSI_OPCODE_UP2US
:
4435 case TGSI_OPCODE_UP4B
:
4439 case TGSI_OPCODE_UP4UB
:
4443 case TGSI_OPCODE_ARR
:
4444 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4447 case TGSI_OPCODE_CAL
:
4448 /* skip the call if no execution channels are enabled */
4449 if (mach
->ExecMask
) {
4452 /* First, record the depths of the execution stacks.
4453 * This is important for deeply nested/looped return statements.
4454 * We have to unwind the stacks by the correct amount. For a
4455 * real code generator, we could determine the number of entries
4456 * to pop off each stack with simple static analysis and avoid
4457 * implementing this data structure at run time.
4459 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
4460 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
4461 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
4462 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
4463 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
4464 /* note that PC was already incremented above */
4465 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
4467 mach
->CallStackTop
++;
4469 /* Second, push the Cond, Loop, Cont, Func stacks */
4470 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
4471 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4472 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4473 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
4474 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
4475 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
4477 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
4478 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
4479 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
4480 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
4481 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
4482 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
4484 /* Finally, jump to the subroutine. The label is a pointer
4485 * (an instruction number) to the BGNSUB instruction.
4487 *pc
= inst
->Label
.Label
;
4488 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
4489 == TGSI_OPCODE_BGNSUB
);
4493 case TGSI_OPCODE_RET
:
4494 mach
->FuncMask
&= ~mach
->ExecMask
;
4495 UPDATE_EXEC_MASK(mach
);
4497 if (mach
->FuncMask
== 0x0) {
4498 /* really return now (otherwise, keep executing */
4500 if (mach
->CallStackTop
== 0) {
4501 /* returning from main() */
4502 mach
->CondStackTop
= 0;
4503 mach
->LoopStackTop
= 0;
4508 assert(mach
->CallStackTop
> 0);
4509 mach
->CallStackTop
--;
4511 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
4512 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
4514 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
4515 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
4517 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
4518 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
4520 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
4521 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
4523 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
4524 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
4526 assert(mach
->FuncStackTop
> 0);
4527 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
4529 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
4531 UPDATE_EXEC_MASK(mach
);
4535 case TGSI_OPCODE_SSG
:
4536 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4539 case TGSI_OPCODE_CMP
:
4540 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4543 case TGSI_OPCODE_SCS
:
4544 exec_scs(mach
, inst
);
4547 case TGSI_OPCODE_DIV
:
4548 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4551 case TGSI_OPCODE_DP2
:
4552 exec_dp2(mach
, inst
);
4555 case TGSI_OPCODE_IF
:
4557 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
4558 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
4559 FETCH( &r
[0], 0, TGSI_CHAN_X
);
4560 /* update CondMask */
4562 mach
->CondMask
&= ~0x1;
4565 mach
->CondMask
&= ~0x2;
4568 mach
->CondMask
&= ~0x4;
4571 mach
->CondMask
&= ~0x8;
4573 UPDATE_EXEC_MASK(mach
);
4574 /* Todo: If CondMask==0, jump to ELSE */
4577 case TGSI_OPCODE_UIF
:
4579 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
4580 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
4581 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
4582 /* update CondMask */
4584 mach
->CondMask
&= ~0x1;
4587 mach
->CondMask
&= ~0x2;
4590 mach
->CondMask
&= ~0x4;
4593 mach
->CondMask
&= ~0x8;
4595 UPDATE_EXEC_MASK(mach
);
4596 /* Todo: If CondMask==0, jump to ELSE */
4599 case TGSI_OPCODE_ELSE
:
4600 /* invert CondMask wrt previous mask */
4603 assert(mach
->CondStackTop
> 0);
4604 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
4605 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
4606 UPDATE_EXEC_MASK(mach
);
4607 /* Todo: If CondMask==0, jump to ENDIF */
4611 case TGSI_OPCODE_ENDIF
:
4613 assert(mach
->CondStackTop
> 0);
4614 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
4615 UPDATE_EXEC_MASK(mach
);
4618 case TGSI_OPCODE_END
:
4619 /* make sure we end primitives which haven't
4620 * been explicitly emitted */
4621 conditional_emit_primitive(mach
);
4622 /* halt execution */
4626 case TGSI_OPCODE_PUSHA
:
4630 case TGSI_OPCODE_POPA
:
4634 case TGSI_OPCODE_CEIL
:
4635 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4638 case TGSI_OPCODE_I2F
:
4639 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
4642 case TGSI_OPCODE_NOT
:
4643 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4646 case TGSI_OPCODE_TRUNC
:
4647 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4650 case TGSI_OPCODE_SHL
:
4651 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4654 case TGSI_OPCODE_AND
:
4655 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4658 case TGSI_OPCODE_OR
:
4659 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4662 case TGSI_OPCODE_MOD
:
4663 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4666 case TGSI_OPCODE_XOR
:
4667 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4670 case TGSI_OPCODE_SAD
:
4674 case TGSI_OPCODE_TXF
:
4675 exec_txf(mach
, inst
);
4678 case TGSI_OPCODE_TXQ
:
4679 exec_txq(mach
, inst
);
4682 case TGSI_OPCODE_EMIT
:
4686 case TGSI_OPCODE_ENDPRIM
:
4687 emit_primitive(mach
);
4690 case TGSI_OPCODE_BGNLOOP
:
4691 /* push LoopMask and ContMasks */
4692 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4693 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4694 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4695 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
4697 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
4698 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
4699 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
4700 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
4701 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
4704 case TGSI_OPCODE_ENDLOOP
:
4705 /* Restore ContMask, but don't pop */
4706 assert(mach
->ContStackTop
> 0);
4707 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
4708 UPDATE_EXEC_MASK(mach
);
4709 if (mach
->ExecMask
) {
4710 /* repeat loop: jump to instruction just past BGNLOOP */
4711 assert(mach
->LoopLabelStackTop
> 0);
4712 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
4715 /* exit loop: pop LoopMask */
4716 assert(mach
->LoopStackTop
> 0);
4717 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
4719 assert(mach
->ContStackTop
> 0);
4720 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
4721 assert(mach
->LoopLabelStackTop
> 0);
4722 --mach
->LoopLabelStackTop
;
4724 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
4726 UPDATE_EXEC_MASK(mach
);
4729 case TGSI_OPCODE_BRK
:
4733 case TGSI_OPCODE_CONT
:
4734 /* turn off cont channels for each enabled exec channel */
4735 mach
->ContMask
&= ~mach
->ExecMask
;
4736 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4737 UPDATE_EXEC_MASK(mach
);
4740 case TGSI_OPCODE_BGNSUB
:
4744 case TGSI_OPCODE_ENDSUB
:
4746 * XXX: This really should be a no-op. We should never reach this opcode.
4749 assert(mach
->CallStackTop
> 0);
4750 mach
->CallStackTop
--;
4752 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
4753 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
4755 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
4756 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
4758 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
4759 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
4761 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
4762 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
4764 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
4765 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
4767 assert(mach
->FuncStackTop
> 0);
4768 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
4770 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
4772 UPDATE_EXEC_MASK(mach
);
4775 case TGSI_OPCODE_NOP
:
4778 case TGSI_OPCODE_BREAKC
:
4779 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4780 /* update CondMask */
4781 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
4782 mach
->LoopMask
&= ~0x1;
4784 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
4785 mach
->LoopMask
&= ~0x2;
4787 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
4788 mach
->LoopMask
&= ~0x4;
4790 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
4791 mach
->LoopMask
&= ~0x8;
4793 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4794 UPDATE_EXEC_MASK(mach
);
4797 case TGSI_OPCODE_F2I
:
4798 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4801 case TGSI_OPCODE_FSEQ
:
4802 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4805 case TGSI_OPCODE_FSGE
:
4806 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4809 case TGSI_OPCODE_FSLT
:
4810 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4813 case TGSI_OPCODE_FSNE
:
4814 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4817 case TGSI_OPCODE_IDIV
:
4818 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4821 case TGSI_OPCODE_IMAX
:
4822 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4825 case TGSI_OPCODE_IMIN
:
4826 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4829 case TGSI_OPCODE_INEG
:
4830 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4833 case TGSI_OPCODE_ISGE
:
4834 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4837 case TGSI_OPCODE_ISHR
:
4838 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4841 case TGSI_OPCODE_ISLT
:
4842 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4845 case TGSI_OPCODE_F2U
:
4846 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4849 case TGSI_OPCODE_U2F
:
4850 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
4853 case TGSI_OPCODE_UADD
:
4854 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4857 case TGSI_OPCODE_UDIV
:
4858 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4861 case TGSI_OPCODE_UMAD
:
4862 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4865 case TGSI_OPCODE_UMAX
:
4866 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4869 case TGSI_OPCODE_UMIN
:
4870 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4873 case TGSI_OPCODE_UMOD
:
4874 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4877 case TGSI_OPCODE_UMUL
:
4878 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4881 case TGSI_OPCODE_IMUL_HI
:
4882 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4885 case TGSI_OPCODE_UMUL_HI
:
4886 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4889 case TGSI_OPCODE_USEQ
:
4890 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4893 case TGSI_OPCODE_USGE
:
4894 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4897 case TGSI_OPCODE_USHR
:
4898 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4901 case TGSI_OPCODE_USLT
:
4902 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4905 case TGSI_OPCODE_USNE
:
4906 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4909 case TGSI_OPCODE_SWITCH
:
4910 exec_switch(mach
, inst
);
4913 case TGSI_OPCODE_CASE
:
4914 exec_case(mach
, inst
);
4917 case TGSI_OPCODE_DEFAULT
:
4921 case TGSI_OPCODE_ENDSWITCH
:
4922 exec_endswitch(mach
);
4925 case TGSI_OPCODE_SAMPLE_I
:
4926 exec_txf(mach
, inst
);
4929 case TGSI_OPCODE_SAMPLE_I_MS
:
4933 case TGSI_OPCODE_SAMPLE
:
4934 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
4937 case TGSI_OPCODE_SAMPLE_B
:
4938 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
4941 case TGSI_OPCODE_SAMPLE_C
:
4942 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
4945 case TGSI_OPCODE_SAMPLE_C_LZ
:
4946 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
4949 case TGSI_OPCODE_SAMPLE_D
:
4950 exec_sample_d(mach
, inst
);
4953 case TGSI_OPCODE_SAMPLE_L
:
4954 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
4957 case TGSI_OPCODE_GATHER4
:
4961 case TGSI_OPCODE_SVIEWINFO
:
4962 exec_txq(mach
, inst
);
4965 case TGSI_OPCODE_SAMPLE_POS
:
4969 case TGSI_OPCODE_SAMPLE_INFO
:
4973 case TGSI_OPCODE_UARL
:
4974 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
4977 case TGSI_OPCODE_UCMP
:
4978 exec_vector_trinary(mach
, inst
, micro_ucmp
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4981 case TGSI_OPCODE_IABS
:
4982 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4985 case TGSI_OPCODE_ISSG
:
4986 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4989 case TGSI_OPCODE_TEX2
:
4990 /* simple texture lookup */
4991 /* src[0] = texcoord */
4992 /* src[1] = compare */
4993 /* src[2] = sampler unit */
4994 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
4996 case TGSI_OPCODE_TXB2
:
4997 /* simple texture lookup */
4998 /* src[0] = texcoord */
5000 /* src[2] = sampler unit */
5001 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
5003 case TGSI_OPCODE_TXL2
:
5004 /* simple texture lookup */
5005 /* src[0] = texcoord */
5007 /* src[2] = sampler unit */
5008 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
5011 case TGSI_OPCODE_IBFE
:
5012 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5014 case TGSI_OPCODE_UBFE
:
5015 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5017 case TGSI_OPCODE_BFI
:
5018 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5020 case TGSI_OPCODE_BREV
:
5021 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5023 case TGSI_OPCODE_POPC
:
5024 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5026 case TGSI_OPCODE_LSB
:
5027 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5029 case TGSI_OPCODE_IMSB
:
5030 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5032 case TGSI_OPCODE_UMSB
:
5033 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5036 case TGSI_OPCODE_F2D
:
5037 exec_f2d(mach
, inst
);
5040 case TGSI_OPCODE_D2F
:
5041 exec_d2f(mach
, inst
);
5044 case TGSI_OPCODE_DABS
:
5045 exec_double_unary(mach
, inst
, micro_dabs
);
5048 case TGSI_OPCODE_DNEG
:
5049 exec_double_unary(mach
, inst
, micro_dneg
);
5052 case TGSI_OPCODE_DADD
:
5053 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
5056 case TGSI_OPCODE_DMUL
:
5057 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
5060 case TGSI_OPCODE_DMAX
:
5061 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
5064 case TGSI_OPCODE_DMIN
:
5065 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
5068 case TGSI_OPCODE_DSLT
:
5069 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
5072 case TGSI_OPCODE_DSGE
:
5073 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
5076 case TGSI_OPCODE_DSEQ
:
5077 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
5080 case TGSI_OPCODE_DSNE
:
5081 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
5084 case TGSI_OPCODE_DRCP
:
5085 exec_double_unary(mach
, inst
, micro_drcp
);
5088 case TGSI_OPCODE_DSQRT
:
5089 exec_double_unary(mach
, inst
, micro_dsqrt
);
5092 case TGSI_OPCODE_DRSQ
:
5093 exec_double_unary(mach
, inst
, micro_drsq
);
5096 case TGSI_OPCODE_DMAD
:
5097 exec_double_trinary(mach
, inst
, micro_dmad
);
5100 case TGSI_OPCODE_DFRAC
:
5101 exec_double_unary(mach
, inst
, micro_dfrac
);
5104 case TGSI_OPCODE_DLDEXP
:
5105 exec_dldexp(mach
, inst
);
5108 case TGSI_OPCODE_DFRACEXP
:
5109 exec_dfracexp(mach
, inst
);
5112 case TGSI_OPCODE_I2D
:
5113 exec_i2d(mach
, inst
);
5116 case TGSI_OPCODE_D2I
:
5117 exec_d2i(mach
, inst
);
5120 case TGSI_OPCODE_U2D
:
5121 exec_u2d(mach
, inst
);
5124 case TGSI_OPCODE_D2U
:
5125 exec_d2u(mach
, inst
);
5134 * Run TGSI interpreter.
5135 * \return bitmask of "alive" quad components
5138 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
)
5142 uint default_mask
= 0xf;
5144 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
5145 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
5147 if( mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
) {
5148 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
5149 mach
->Primitives
[0] = 0;
5150 /* GS runs on a single primitive for now */
5154 mach
->CondMask
= default_mask
;
5155 mach
->LoopMask
= default_mask
;
5156 mach
->ContMask
= default_mask
;
5157 mach
->FuncMask
= default_mask
;
5158 mach
->ExecMask
= default_mask
;
5160 mach
->Switch
.mask
= default_mask
;
5162 assert(mach
->CondStackTop
== 0);
5163 assert(mach
->LoopStackTop
== 0);
5164 assert(mach
->ContStackTop
== 0);
5165 assert(mach
->SwitchStackTop
== 0);
5166 assert(mach
->BreakStackTop
== 0);
5167 assert(mach
->CallStackTop
== 0);
5170 /* execute declarations (interpolants) */
5171 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
5172 exec_declaration( mach
, mach
->Declarations
+i
);
5177 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
5178 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
5181 memset(mach
->Temps
, 0, sizeof(temps
));
5182 memset(mach
->Outputs
, 0, sizeof(outputs
));
5183 memset(temps
, 0, sizeof(temps
));
5184 memset(outputs
, 0, sizeof(outputs
));
5187 /* execute instructions, until pc is set to -1 */
5193 tgsi_dump_instruction(&mach
->Instructions
[pc
], inst
++);
5196 assert(pc
< (int) mach
->NumInstructions
);
5197 exec_instruction(mach
, mach
->Instructions
+ pc
, &pc
);
5200 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
5201 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
5204 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
5205 debug_printf("TEMP[%2u] = ", i
);
5206 for (j
= 0; j
< 4; j
++) {
5210 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5211 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
5212 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
5213 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
5214 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
5218 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
5219 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
5222 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
5223 debug_printf("OUT[%2u] = ", i
);
5224 for (j
= 0; j
< 4; j
++) {
5228 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5229 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
5230 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
5231 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
5232 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
5241 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5242 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
5244 * Scale back depth component.
5246 for (i
= 0; i
< 4; i
++)
5247 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
5251 /* Strictly speaking, these assertions aren't really needed but they
5252 * can potentially catch some bugs in the control flow code.
5254 assert(mach
->CondStackTop
== 0);
5255 assert(mach
->LoopStackTop
== 0);
5256 assert(mach
->ContStackTop
== 0);
5257 assert(mach
->SwitchStackTop
== 0);
5258 assert(mach
->BreakStackTop
== 0);
5259 assert(mach
->CallStackTop
== 0);
5261 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];