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Merge branch 'mesa_7_6_branch' into mesa_7_7_branch
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /**
29 * TGSI interpreter/executor.
30 *
31 * Flow control information:
32 *
33 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
34 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
35 * care since a condition may be true for some quad components but false
36 * for other components.
37 *
38 * We basically execute all statements (even if they're in the part of
39 * an IF/ELSE clause that's "not taken") and use a special mask to
40 * control writing to destination registers. This is the ExecMask.
41 * See store_dest().
42 *
43 * The ExecMask is computed from three other masks (CondMask, LoopMask and
44 * ContMask) which are controlled by the flow control instructions (namely:
45 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
46 *
47 *
48 * Authors:
49 * Michal Krol
50 * Brian Paul
51 */
52
53 #include "pipe/p_compiler.h"
54 #include "pipe/p_state.h"
55 #include "pipe/p_shader_tokens.h"
56 #include "tgsi/tgsi_dump.h"
57 #include "tgsi/tgsi_parse.h"
58 #include "tgsi/tgsi_util.h"
59 #include "tgsi_exec.h"
60 #include "util/u_memory.h"
61 #include "util/u_math.h"
62
63 #define FAST_MATH 1
64
65 /** for tgsi_full_instruction::Flags */
66 #define SOA_DEPENDENCY_FLAG 0x1
67
68 #define TILE_TOP_LEFT 0
69 #define TILE_TOP_RIGHT 1
70 #define TILE_BOTTOM_LEFT 2
71 #define TILE_BOTTOM_RIGHT 3
72
73 #define CHAN_X 0
74 #define CHAN_Y 1
75 #define CHAN_Z 2
76 #define CHAN_W 3
77
78 /*
79 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
80 */
81 #define TEMP_0_I TGSI_EXEC_TEMP_00000000_I
82 #define TEMP_0_C TGSI_EXEC_TEMP_00000000_C
83 #define TEMP_7F_I TGSI_EXEC_TEMP_7FFFFFFF_I
84 #define TEMP_7F_C TGSI_EXEC_TEMP_7FFFFFFF_C
85 #define TEMP_80_I TGSI_EXEC_TEMP_80000000_I
86 #define TEMP_80_C TGSI_EXEC_TEMP_80000000_C
87 #define TEMP_FF_I TGSI_EXEC_TEMP_FFFFFFFF_I
88 #define TEMP_FF_C TGSI_EXEC_TEMP_FFFFFFFF_C
89 #define TEMP_1_I TGSI_EXEC_TEMP_ONE_I
90 #define TEMP_1_C TGSI_EXEC_TEMP_ONE_C
91 #define TEMP_2_I TGSI_EXEC_TEMP_TWO_I
92 #define TEMP_2_C TGSI_EXEC_TEMP_TWO_C
93 #define TEMP_128_I TGSI_EXEC_TEMP_128_I
94 #define TEMP_128_C TGSI_EXEC_TEMP_128_C
95 #define TEMP_M128_I TGSI_EXEC_TEMP_MINUS_128_I
96 #define TEMP_M128_C TGSI_EXEC_TEMP_MINUS_128_C
97 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
98 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
99 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
100 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
101 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
102 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
103 #define TEMP_CC_I TGSI_EXEC_TEMP_CC_I
104 #define TEMP_CC_C TGSI_EXEC_TEMP_CC_C
105 #define TEMP_3_I TGSI_EXEC_TEMP_THREE_I
106 #define TEMP_3_C TGSI_EXEC_TEMP_THREE_C
107 #define TEMP_HALF_I TGSI_EXEC_TEMP_HALF_I
108 #define TEMP_HALF_C TGSI_EXEC_TEMP_HALF_C
109 #define TEMP_R0 TGSI_EXEC_TEMP_R0
110 #define TEMP_P0 TGSI_EXEC_TEMP_P0
111
112 #define IS_CHANNEL_ENABLED(INST, CHAN)\
113 ((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
114
115 #define IS_CHANNEL_ENABLED2(INST, CHAN)\
116 ((INST).FullDstRegisters[1].DstRegister.WriteMask & (1 << (CHAN)))
117
118 #define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
119 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
120 if (IS_CHANNEL_ENABLED( INST, CHAN ))
121
122 #define FOR_EACH_ENABLED_CHANNEL2(INST, CHAN)\
123 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
124 if (IS_CHANNEL_ENABLED2( INST, CHAN ))
125
126
127 /** The execution mask depends on the conditional mask and the loop mask */
128 #define UPDATE_EXEC_MASK(MACH) \
129 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->FuncMask
130
131
132 static const union tgsi_exec_channel ZeroVec =
133 { { 0.0, 0.0, 0.0, 0.0 } };
134
135
136 #ifdef DEBUG
137 static void
138 check_inf_or_nan(const union tgsi_exec_channel *chan)
139 {
140 assert(!util_is_inf_or_nan(chan->f[0]));
141 assert(!util_is_inf_or_nan(chan->f[1]));
142 assert(!util_is_inf_or_nan(chan->f[2]));
143 assert(!util_is_inf_or_nan(chan->f[3]));
144 }
145 #endif
146
147
148 #ifdef DEBUG
149 static void
150 print_chan(const char *msg, const union tgsi_exec_channel *chan)
151 {
152 debug_printf("%s = {%f, %f, %f, %f}\n",
153 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
154 }
155 #endif
156
157
158 #ifdef DEBUG
159 static void
160 print_temp(const struct tgsi_exec_machine *mach, uint index)
161 {
162 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
163 int i;
164 debug_printf("Temp[%u] =\n", index);
165 for (i = 0; i < 4; i++) {
166 debug_printf(" %c: { %f, %f, %f, %f }\n",
167 "XYZW"[i],
168 tmp->xyzw[i].f[0],
169 tmp->xyzw[i].f[1],
170 tmp->xyzw[i].f[2],
171 tmp->xyzw[i].f[3]);
172 }
173 }
174 #endif
175
176
177 /**
178 * Check if there's a potential src/dst register data dependency when
179 * using SOA execution.
180 * Example:
181 * MOV T, T.yxwz;
182 * This would expand into:
183 * MOV t0, t1;
184 * MOV t1, t0;
185 * MOV t2, t3;
186 * MOV t3, t2;
187 * The second instruction will have the wrong value for t0 if executed as-is.
188 */
189 boolean
190 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
191 {
192 uint i, chan;
193
194 uint writemask = inst->FullDstRegisters[0].DstRegister.WriteMask;
195 if (writemask == TGSI_WRITEMASK_X ||
196 writemask == TGSI_WRITEMASK_Y ||
197 writemask == TGSI_WRITEMASK_Z ||
198 writemask == TGSI_WRITEMASK_W ||
199 writemask == TGSI_WRITEMASK_NONE) {
200 /* no chance of data dependency */
201 return FALSE;
202 }
203
204 /* loop over src regs */
205 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
206 if ((inst->FullSrcRegisters[i].SrcRegister.File ==
207 inst->FullDstRegisters[0].DstRegister.File) &&
208 (inst->FullSrcRegisters[i].SrcRegister.Index ==
209 inst->FullDstRegisters[0].DstRegister.Index)) {
210 /* loop over dest channels */
211 uint channelsWritten = 0x0;
212 FOR_EACH_ENABLED_CHANNEL(*inst, chan) {
213 /* check if we're reading a channel that's been written */
214 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->FullSrcRegisters[i], chan);
215 if (channelsWritten & (1 << swizzle)) {
216 return TRUE;
217 }
218
219 channelsWritten |= (1 << chan);
220 }
221 }
222 }
223 return FALSE;
224 }
225
226
227 /**
228 * Initialize machine state by expanding tokens to full instructions,
229 * allocating temporary storage, setting up constants, etc.
230 * After this, we can call tgsi_exec_machine_run() many times.
231 */
232 void
233 tgsi_exec_machine_bind_shader(
234 struct tgsi_exec_machine *mach,
235 const struct tgsi_token *tokens,
236 uint numSamplers,
237 struct tgsi_sampler **samplers)
238 {
239 uint k;
240 struct tgsi_parse_context parse;
241 struct tgsi_exec_labels *labels = &mach->Labels;
242 struct tgsi_full_instruction *instructions;
243 struct tgsi_full_declaration *declarations;
244 uint maxInstructions = 10, numInstructions = 0;
245 uint maxDeclarations = 10, numDeclarations = 0;
246 uint instno = 0;
247
248 #if 0
249 tgsi_dump(tokens, 0);
250 #endif
251
252 util_init_math();
253
254 mach->Tokens = tokens;
255 mach->Samplers = samplers;
256
257 k = tgsi_parse_init (&parse, mach->Tokens);
258 if (k != TGSI_PARSE_OK) {
259 debug_printf( "Problem parsing!\n" );
260 return;
261 }
262
263 mach->Processor = parse.FullHeader.Processor.Processor;
264 mach->ImmLimit = 0;
265 labels->count = 0;
266
267 declarations = (struct tgsi_full_declaration *)
268 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
269
270 if (!declarations) {
271 return;
272 }
273
274 instructions = (struct tgsi_full_instruction *)
275 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
276
277 if (!instructions) {
278 FREE( declarations );
279 return;
280 }
281
282 while( !tgsi_parse_end_of_tokens( &parse ) ) {
283 uint pointer = parse.Position;
284 uint i;
285
286 tgsi_parse_token( &parse );
287 switch( parse.FullToken.Token.Type ) {
288 case TGSI_TOKEN_TYPE_DECLARATION:
289 /* save expanded declaration */
290 if (numDeclarations == maxDeclarations) {
291 declarations = REALLOC(declarations,
292 maxDeclarations
293 * sizeof(struct tgsi_full_declaration),
294 (maxDeclarations + 10)
295 * sizeof(struct tgsi_full_declaration));
296 maxDeclarations += 10;
297 }
298 memcpy(declarations + numDeclarations,
299 &parse.FullToken.FullDeclaration,
300 sizeof(declarations[0]));
301 numDeclarations++;
302 break;
303
304 case TGSI_TOKEN_TYPE_IMMEDIATE:
305 {
306 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
307 assert( size <= 4 );
308 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
309
310 for( i = 0; i < size; i++ ) {
311 mach->Imms[mach->ImmLimit][i] =
312 parse.FullToken.FullImmediate.u[i].Float;
313 }
314 mach->ImmLimit += 1;
315 }
316 break;
317
318 case TGSI_TOKEN_TYPE_INSTRUCTION:
319 assert( labels->count < MAX_LABELS );
320
321 labels->labels[labels->count][0] = instno;
322 labels->labels[labels->count][1] = pointer;
323 labels->count++;
324
325 /* save expanded instruction */
326 if (numInstructions == maxInstructions) {
327 instructions = REALLOC(instructions,
328 maxInstructions
329 * sizeof(struct tgsi_full_instruction),
330 (maxInstructions + 10)
331 * sizeof(struct tgsi_full_instruction));
332 maxInstructions += 10;
333 }
334
335 if (tgsi_check_soa_dependencies(&parse.FullToken.FullInstruction)) {
336 uint opcode = parse.FullToken.FullInstruction.Instruction.Opcode;
337 parse.FullToken.FullInstruction.Flags = SOA_DEPENDENCY_FLAG;
338 /* XXX we only handle SOA dependencies properly for MOV/SWZ
339 * at this time!
340 */
341 if (opcode != TGSI_OPCODE_MOV) {
342 debug_printf("Warning: SOA dependency in instruction"
343 " is not handled:\n");
344 tgsi_dump_instruction(&parse.FullToken.FullInstruction,
345 numInstructions);
346 }
347 }
348
349 memcpy(instructions + numInstructions,
350 &parse.FullToken.FullInstruction,
351 sizeof(instructions[0]));
352
353 numInstructions++;
354 break;
355
356 default:
357 assert( 0 );
358 }
359 }
360 tgsi_parse_free (&parse);
361
362 if (mach->Declarations) {
363 FREE( mach->Declarations );
364 }
365 mach->Declarations = declarations;
366 mach->NumDeclarations = numDeclarations;
367
368 if (mach->Instructions) {
369 FREE( mach->Instructions );
370 }
371 mach->Instructions = instructions;
372 mach->NumInstructions = numInstructions;
373 }
374
375
376 struct tgsi_exec_machine *
377 tgsi_exec_machine_create( void )
378 {
379 struct tgsi_exec_machine *mach;
380 uint i;
381
382 mach = align_malloc( sizeof *mach, 16 );
383 if (!mach)
384 goto fail;
385
386 memset(mach, 0, sizeof(*mach));
387
388 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
389
390 /* Setup constants. */
391 for( i = 0; i < 4; i++ ) {
392 mach->Temps[TEMP_0_I].xyzw[TEMP_0_C].u[i] = 0x00000000;
393 mach->Temps[TEMP_7F_I].xyzw[TEMP_7F_C].u[i] = 0x7FFFFFFF;
394 mach->Temps[TEMP_80_I].xyzw[TEMP_80_C].u[i] = 0x80000000;
395 mach->Temps[TEMP_FF_I].xyzw[TEMP_FF_C].u[i] = 0xFFFFFFFF;
396 mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].f[i] = 1.0f;
397 mach->Temps[TEMP_2_I].xyzw[TEMP_2_C].f[i] = 2.0f;
398 mach->Temps[TEMP_128_I].xyzw[TEMP_128_C].f[i] = 128.0f;
399 mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C].f[i] = -128.0f;
400 mach->Temps[TEMP_3_I].xyzw[TEMP_3_C].f[i] = 3.0f;
401 mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C].f[i] = 0.5f;
402 }
403
404 #ifdef DEBUG
405 /* silence warnings */
406 (void) print_chan;
407 (void) print_temp;
408 #endif
409
410 return mach;
411
412 fail:
413 align_free(mach);
414 return NULL;
415 }
416
417
418 void
419 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
420 {
421 if (mach) {
422 FREE(mach->Instructions);
423 FREE(mach->Declarations);
424 }
425
426 align_free(mach);
427 }
428
429
430 static void
431 micro_abs(
432 union tgsi_exec_channel *dst,
433 const union tgsi_exec_channel *src )
434 {
435 dst->f[0] = fabsf( src->f[0] );
436 dst->f[1] = fabsf( src->f[1] );
437 dst->f[2] = fabsf( src->f[2] );
438 dst->f[3] = fabsf( src->f[3] );
439 }
440
441 static void
442 micro_add(
443 union tgsi_exec_channel *dst,
444 const union tgsi_exec_channel *src0,
445 const union tgsi_exec_channel *src1 )
446 {
447 dst->f[0] = src0->f[0] + src1->f[0];
448 dst->f[1] = src0->f[1] + src1->f[1];
449 dst->f[2] = src0->f[2] + src1->f[2];
450 dst->f[3] = src0->f[3] + src1->f[3];
451 }
452
453 #if 0
454 static void
455 micro_iadd(
456 union tgsi_exec_channel *dst,
457 const union tgsi_exec_channel *src0,
458 const union tgsi_exec_channel *src1 )
459 {
460 dst->i[0] = src0->i[0] + src1->i[0];
461 dst->i[1] = src0->i[1] + src1->i[1];
462 dst->i[2] = src0->i[2] + src1->i[2];
463 dst->i[3] = src0->i[3] + src1->i[3];
464 }
465 #endif
466
467 static void
468 micro_and(
469 union tgsi_exec_channel *dst,
470 const union tgsi_exec_channel *src0,
471 const union tgsi_exec_channel *src1 )
472 {
473 dst->u[0] = src0->u[0] & src1->u[0];
474 dst->u[1] = src0->u[1] & src1->u[1];
475 dst->u[2] = src0->u[2] & src1->u[2];
476 dst->u[3] = src0->u[3] & src1->u[3];
477 }
478
479 static void
480 micro_ceil(
481 union tgsi_exec_channel *dst,
482 const union tgsi_exec_channel *src )
483 {
484 dst->f[0] = ceilf( src->f[0] );
485 dst->f[1] = ceilf( src->f[1] );
486 dst->f[2] = ceilf( src->f[2] );
487 dst->f[3] = ceilf( src->f[3] );
488 }
489
490 static void
491 micro_cos(
492 union tgsi_exec_channel *dst,
493 const union tgsi_exec_channel *src )
494 {
495 dst->f[0] = cosf( src->f[0] );
496 dst->f[1] = cosf( src->f[1] );
497 dst->f[2] = cosf( src->f[2] );
498 dst->f[3] = cosf( src->f[3] );
499 }
500
501 static void
502 micro_ddx(
503 union tgsi_exec_channel *dst,
504 const union tgsi_exec_channel *src )
505 {
506 dst->f[0] =
507 dst->f[1] =
508 dst->f[2] =
509 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
510 }
511
512 static void
513 micro_ddy(
514 union tgsi_exec_channel *dst,
515 const union tgsi_exec_channel *src )
516 {
517 dst->f[0] =
518 dst->f[1] =
519 dst->f[2] =
520 dst->f[3] = src->f[TILE_TOP_LEFT] - src->f[TILE_BOTTOM_LEFT];
521 }
522
523 static void
524 micro_div(
525 union tgsi_exec_channel *dst,
526 const union tgsi_exec_channel *src0,
527 const union tgsi_exec_channel *src1 )
528 {
529 if (src1->f[0] != 0) {
530 dst->f[0] = src0->f[0] / src1->f[0];
531 }
532 if (src1->f[1] != 0) {
533 dst->f[1] = src0->f[1] / src1->f[1];
534 }
535 if (src1->f[2] != 0) {
536 dst->f[2] = src0->f[2] / src1->f[2];
537 }
538 if (src1->f[3] != 0) {
539 dst->f[3] = src0->f[3] / src1->f[3];
540 }
541 }
542
543 #if 0
544 static void
545 micro_udiv(
546 union tgsi_exec_channel *dst,
547 const union tgsi_exec_channel *src0,
548 const union tgsi_exec_channel *src1 )
549 {
550 dst->u[0] = src0->u[0] / src1->u[0];
551 dst->u[1] = src0->u[1] / src1->u[1];
552 dst->u[2] = src0->u[2] / src1->u[2];
553 dst->u[3] = src0->u[3] / src1->u[3];
554 }
555 #endif
556
557 static void
558 micro_eq(
559 union tgsi_exec_channel *dst,
560 const union tgsi_exec_channel *src0,
561 const union tgsi_exec_channel *src1,
562 const union tgsi_exec_channel *src2,
563 const union tgsi_exec_channel *src3 )
564 {
565 dst->f[0] = src0->f[0] == src1->f[0] ? src2->f[0] : src3->f[0];
566 dst->f[1] = src0->f[1] == src1->f[1] ? src2->f[1] : src3->f[1];
567 dst->f[2] = src0->f[2] == src1->f[2] ? src2->f[2] : src3->f[2];
568 dst->f[3] = src0->f[3] == src1->f[3] ? src2->f[3] : src3->f[3];
569 }
570
571 #if 0
572 static void
573 micro_ieq(
574 union tgsi_exec_channel *dst,
575 const union tgsi_exec_channel *src0,
576 const union tgsi_exec_channel *src1,
577 const union tgsi_exec_channel *src2,
578 const union tgsi_exec_channel *src3 )
579 {
580 dst->i[0] = src0->i[0] == src1->i[0] ? src2->i[0] : src3->i[0];
581 dst->i[1] = src0->i[1] == src1->i[1] ? src2->i[1] : src3->i[1];
582 dst->i[2] = src0->i[2] == src1->i[2] ? src2->i[2] : src3->i[2];
583 dst->i[3] = src0->i[3] == src1->i[3] ? src2->i[3] : src3->i[3];
584 }
585 #endif
586
587 static void
588 micro_exp2(
589 union tgsi_exec_channel *dst,
590 const union tgsi_exec_channel *src)
591 {
592 #if FAST_MATH
593 dst->f[0] = util_fast_exp2( src->f[0] );
594 dst->f[1] = util_fast_exp2( src->f[1] );
595 dst->f[2] = util_fast_exp2( src->f[2] );
596 dst->f[3] = util_fast_exp2( src->f[3] );
597 #else
598 dst->f[0] = powf( 2.0f, src->f[0] );
599 dst->f[1] = powf( 2.0f, src->f[1] );
600 dst->f[2] = powf( 2.0f, src->f[2] );
601 dst->f[3] = powf( 2.0f, src->f[3] );
602 #endif
603 }
604
605 #if 0
606 static void
607 micro_f2ut(
608 union tgsi_exec_channel *dst,
609 const union tgsi_exec_channel *src )
610 {
611 dst->u[0] = (uint) src->f[0];
612 dst->u[1] = (uint) src->f[1];
613 dst->u[2] = (uint) src->f[2];
614 dst->u[3] = (uint) src->f[3];
615 }
616 #endif
617
618 static void
619 micro_float_clamp(union tgsi_exec_channel *dst,
620 const union tgsi_exec_channel *src)
621 {
622 uint i;
623
624 for (i = 0; i < 4; i++) {
625 if (src->f[i] > 0.0f) {
626 if (src->f[i] > 1.884467e+019f)
627 dst->f[i] = 1.884467e+019f;
628 else if (src->f[i] < 5.42101e-020f)
629 dst->f[i] = 5.42101e-020f;
630 else
631 dst->f[i] = src->f[i];
632 }
633 else {
634 if (src->f[i] < -1.884467e+019f)
635 dst->f[i] = -1.884467e+019f;
636 else if (src->f[i] > -5.42101e-020f)
637 dst->f[i] = -5.42101e-020f;
638 else
639 dst->f[i] = src->f[i];
640 }
641 }
642 }
643
644 static void
645 micro_flr(
646 union tgsi_exec_channel *dst,
647 const union tgsi_exec_channel *src )
648 {
649 dst->f[0] = floorf( src->f[0] );
650 dst->f[1] = floorf( src->f[1] );
651 dst->f[2] = floorf( src->f[2] );
652 dst->f[3] = floorf( src->f[3] );
653 }
654
655 static void
656 micro_frc(
657 union tgsi_exec_channel *dst,
658 const union tgsi_exec_channel *src )
659 {
660 dst->f[0] = src->f[0] - floorf( src->f[0] );
661 dst->f[1] = src->f[1] - floorf( src->f[1] );
662 dst->f[2] = src->f[2] - floorf( src->f[2] );
663 dst->f[3] = src->f[3] - floorf( src->f[3] );
664 }
665
666 static void
667 micro_i2f(
668 union tgsi_exec_channel *dst,
669 const union tgsi_exec_channel *src )
670 {
671 dst->f[0] = (float) src->i[0];
672 dst->f[1] = (float) src->i[1];
673 dst->f[2] = (float) src->i[2];
674 dst->f[3] = (float) src->i[3];
675 }
676
677 static void
678 micro_lg2(
679 union tgsi_exec_channel *dst,
680 const union tgsi_exec_channel *src )
681 {
682 #if FAST_MATH
683 dst->f[0] = util_fast_log2( src->f[0] );
684 dst->f[1] = util_fast_log2( src->f[1] );
685 dst->f[2] = util_fast_log2( src->f[2] );
686 dst->f[3] = util_fast_log2( src->f[3] );
687 #else
688 dst->f[0] = logf( src->f[0] ) * 1.442695f;
689 dst->f[1] = logf( src->f[1] ) * 1.442695f;
690 dst->f[2] = logf( src->f[2] ) * 1.442695f;
691 dst->f[3] = logf( src->f[3] ) * 1.442695f;
692 #endif
693 }
694
695 static void
696 micro_le(
697 union tgsi_exec_channel *dst,
698 const union tgsi_exec_channel *src0,
699 const union tgsi_exec_channel *src1,
700 const union tgsi_exec_channel *src2,
701 const union tgsi_exec_channel *src3 )
702 {
703 dst->f[0] = src0->f[0] <= src1->f[0] ? src2->f[0] : src3->f[0];
704 dst->f[1] = src0->f[1] <= src1->f[1] ? src2->f[1] : src3->f[1];
705 dst->f[2] = src0->f[2] <= src1->f[2] ? src2->f[2] : src3->f[2];
706 dst->f[3] = src0->f[3] <= src1->f[3] ? src2->f[3] : src3->f[3];
707 }
708
709 static void
710 micro_lt(
711 union tgsi_exec_channel *dst,
712 const union tgsi_exec_channel *src0,
713 const union tgsi_exec_channel *src1,
714 const union tgsi_exec_channel *src2,
715 const union tgsi_exec_channel *src3 )
716 {
717 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
718 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
719 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
720 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
721 }
722
723 #if 0
724 static void
725 micro_ilt(
726 union tgsi_exec_channel *dst,
727 const union tgsi_exec_channel *src0,
728 const union tgsi_exec_channel *src1,
729 const union tgsi_exec_channel *src2,
730 const union tgsi_exec_channel *src3 )
731 {
732 dst->i[0] = src0->i[0] < src1->i[0] ? src2->i[0] : src3->i[0];
733 dst->i[1] = src0->i[1] < src1->i[1] ? src2->i[1] : src3->i[1];
734 dst->i[2] = src0->i[2] < src1->i[2] ? src2->i[2] : src3->i[2];
735 dst->i[3] = src0->i[3] < src1->i[3] ? src2->i[3] : src3->i[3];
736 }
737 #endif
738
739 #if 0
740 static void
741 micro_ult(
742 union tgsi_exec_channel *dst,
743 const union tgsi_exec_channel *src0,
744 const union tgsi_exec_channel *src1,
745 const union tgsi_exec_channel *src2,
746 const union tgsi_exec_channel *src3 )
747 {
748 dst->u[0] = src0->u[0] < src1->u[0] ? src2->u[0] : src3->u[0];
749 dst->u[1] = src0->u[1] < src1->u[1] ? src2->u[1] : src3->u[1];
750 dst->u[2] = src0->u[2] < src1->u[2] ? src2->u[2] : src3->u[2];
751 dst->u[3] = src0->u[3] < src1->u[3] ? src2->u[3] : src3->u[3];
752 }
753 #endif
754
755 static void
756 micro_max(
757 union tgsi_exec_channel *dst,
758 const union tgsi_exec_channel *src0,
759 const union tgsi_exec_channel *src1 )
760 {
761 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
762 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
763 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
764 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
765 }
766
767 #if 0
768 static void
769 micro_imax(
770 union tgsi_exec_channel *dst,
771 const union tgsi_exec_channel *src0,
772 const union tgsi_exec_channel *src1 )
773 {
774 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
775 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
776 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
777 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
778 }
779 #endif
780
781 #if 0
782 static void
783 micro_umax(
784 union tgsi_exec_channel *dst,
785 const union tgsi_exec_channel *src0,
786 const union tgsi_exec_channel *src1 )
787 {
788 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
789 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
790 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
791 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
792 }
793 #endif
794
795 static void
796 micro_min(
797 union tgsi_exec_channel *dst,
798 const union tgsi_exec_channel *src0,
799 const union tgsi_exec_channel *src1 )
800 {
801 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
802 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
803 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
804 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
805 }
806
807 #if 0
808 static void
809 micro_imin(
810 union tgsi_exec_channel *dst,
811 const union tgsi_exec_channel *src0,
812 const union tgsi_exec_channel *src1 )
813 {
814 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
815 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
816 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
817 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
818 }
819 #endif
820
821 #if 0
822 static void
823 micro_umin(
824 union tgsi_exec_channel *dst,
825 const union tgsi_exec_channel *src0,
826 const union tgsi_exec_channel *src1 )
827 {
828 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
829 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
830 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
831 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
832 }
833 #endif
834
835 #if 0
836 static void
837 micro_umod(
838 union tgsi_exec_channel *dst,
839 const union tgsi_exec_channel *src0,
840 const union tgsi_exec_channel *src1 )
841 {
842 dst->u[0] = src0->u[0] % src1->u[0];
843 dst->u[1] = src0->u[1] % src1->u[1];
844 dst->u[2] = src0->u[2] % src1->u[2];
845 dst->u[3] = src0->u[3] % src1->u[3];
846 }
847 #endif
848
849 static void
850 micro_mul(
851 union tgsi_exec_channel *dst,
852 const union tgsi_exec_channel *src0,
853 const union tgsi_exec_channel *src1 )
854 {
855 dst->f[0] = src0->f[0] * src1->f[0];
856 dst->f[1] = src0->f[1] * src1->f[1];
857 dst->f[2] = src0->f[2] * src1->f[2];
858 dst->f[3] = src0->f[3] * src1->f[3];
859 }
860
861 #if 0
862 static void
863 micro_imul(
864 union tgsi_exec_channel *dst,
865 const union tgsi_exec_channel *src0,
866 const union tgsi_exec_channel *src1 )
867 {
868 dst->i[0] = src0->i[0] * src1->i[0];
869 dst->i[1] = src0->i[1] * src1->i[1];
870 dst->i[2] = src0->i[2] * src1->i[2];
871 dst->i[3] = src0->i[3] * src1->i[3];
872 }
873 #endif
874
875 #if 0
876 static void
877 micro_imul64(
878 union tgsi_exec_channel *dst0,
879 union tgsi_exec_channel *dst1,
880 const union tgsi_exec_channel *src0,
881 const union tgsi_exec_channel *src1 )
882 {
883 dst1->i[0] = src0->i[0] * src1->i[0];
884 dst1->i[1] = src0->i[1] * src1->i[1];
885 dst1->i[2] = src0->i[2] * src1->i[2];
886 dst1->i[3] = src0->i[3] * src1->i[3];
887 dst0->i[0] = 0;
888 dst0->i[1] = 0;
889 dst0->i[2] = 0;
890 dst0->i[3] = 0;
891 }
892 #endif
893
894 #if 0
895 static void
896 micro_umul64(
897 union tgsi_exec_channel *dst0,
898 union tgsi_exec_channel *dst1,
899 const union tgsi_exec_channel *src0,
900 const union tgsi_exec_channel *src1 )
901 {
902 dst1->u[0] = src0->u[0] * src1->u[0];
903 dst1->u[1] = src0->u[1] * src1->u[1];
904 dst1->u[2] = src0->u[2] * src1->u[2];
905 dst1->u[3] = src0->u[3] * src1->u[3];
906 dst0->u[0] = 0;
907 dst0->u[1] = 0;
908 dst0->u[2] = 0;
909 dst0->u[3] = 0;
910 }
911 #endif
912
913
914 #if 0
915 static void
916 micro_movc(
917 union tgsi_exec_channel *dst,
918 const union tgsi_exec_channel *src0,
919 const union tgsi_exec_channel *src1,
920 const union tgsi_exec_channel *src2 )
921 {
922 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
923 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
924 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
925 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
926 }
927 #endif
928
929 static void
930 micro_neg(
931 union tgsi_exec_channel *dst,
932 const union tgsi_exec_channel *src )
933 {
934 dst->f[0] = -src->f[0];
935 dst->f[1] = -src->f[1];
936 dst->f[2] = -src->f[2];
937 dst->f[3] = -src->f[3];
938 }
939
940 #if 0
941 static void
942 micro_ineg(
943 union tgsi_exec_channel *dst,
944 const union tgsi_exec_channel *src )
945 {
946 dst->i[0] = -src->i[0];
947 dst->i[1] = -src->i[1];
948 dst->i[2] = -src->i[2];
949 dst->i[3] = -src->i[3];
950 }
951 #endif
952
953 static void
954 micro_not(
955 union tgsi_exec_channel *dst,
956 const union tgsi_exec_channel *src )
957 {
958 dst->u[0] = ~src->u[0];
959 dst->u[1] = ~src->u[1];
960 dst->u[2] = ~src->u[2];
961 dst->u[3] = ~src->u[3];
962 }
963
964 static void
965 micro_or(
966 union tgsi_exec_channel *dst,
967 const union tgsi_exec_channel *src0,
968 const union tgsi_exec_channel *src1 )
969 {
970 dst->u[0] = src0->u[0] | src1->u[0];
971 dst->u[1] = src0->u[1] | src1->u[1];
972 dst->u[2] = src0->u[2] | src1->u[2];
973 dst->u[3] = src0->u[3] | src1->u[3];
974 }
975
976 static void
977 micro_pow(
978 union tgsi_exec_channel *dst,
979 const union tgsi_exec_channel *src0,
980 const union tgsi_exec_channel *src1 )
981 {
982 #if FAST_MATH
983 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
984 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
985 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
986 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
987 #else
988 dst->f[0] = powf( src0->f[0], src1->f[0] );
989 dst->f[1] = powf( src0->f[1], src1->f[1] );
990 dst->f[2] = powf( src0->f[2], src1->f[2] );
991 dst->f[3] = powf( src0->f[3], src1->f[3] );
992 #endif
993 }
994
995 static void
996 micro_rnd(
997 union tgsi_exec_channel *dst,
998 const union tgsi_exec_channel *src )
999 {
1000 dst->f[0] = floorf( src->f[0] + 0.5f );
1001 dst->f[1] = floorf( src->f[1] + 0.5f );
1002 dst->f[2] = floorf( src->f[2] + 0.5f );
1003 dst->f[3] = floorf( src->f[3] + 0.5f );
1004 }
1005
1006 static void
1007 micro_sgn(
1008 union tgsi_exec_channel *dst,
1009 const union tgsi_exec_channel *src )
1010 {
1011 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
1012 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
1013 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
1014 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
1015 }
1016
1017 static void
1018 micro_shl(
1019 union tgsi_exec_channel *dst,
1020 const union tgsi_exec_channel *src0,
1021 const union tgsi_exec_channel *src1 )
1022 {
1023 dst->i[0] = src0->i[0] << src1->i[0];
1024 dst->i[1] = src0->i[1] << src1->i[1];
1025 dst->i[2] = src0->i[2] << src1->i[2];
1026 dst->i[3] = src0->i[3] << src1->i[3];
1027 }
1028
1029 static void
1030 micro_ishr(
1031 union tgsi_exec_channel *dst,
1032 const union tgsi_exec_channel *src0,
1033 const union tgsi_exec_channel *src1 )
1034 {
1035 dst->i[0] = src0->i[0] >> src1->i[0];
1036 dst->i[1] = src0->i[1] >> src1->i[1];
1037 dst->i[2] = src0->i[2] >> src1->i[2];
1038 dst->i[3] = src0->i[3] >> src1->i[3];
1039 }
1040
1041 static void
1042 micro_trunc(
1043 union tgsi_exec_channel *dst,
1044 const union tgsi_exec_channel *src0 )
1045 {
1046 dst->f[0] = (float) (int) src0->f[0];
1047 dst->f[1] = (float) (int) src0->f[1];
1048 dst->f[2] = (float) (int) src0->f[2];
1049 dst->f[3] = (float) (int) src0->f[3];
1050 }
1051
1052 #if 0
1053 static void
1054 micro_ushr(
1055 union tgsi_exec_channel *dst,
1056 const union tgsi_exec_channel *src0,
1057 const union tgsi_exec_channel *src1 )
1058 {
1059 dst->u[0] = src0->u[0] >> src1->u[0];
1060 dst->u[1] = src0->u[1] >> src1->u[1];
1061 dst->u[2] = src0->u[2] >> src1->u[2];
1062 dst->u[3] = src0->u[3] >> src1->u[3];
1063 }
1064 #endif
1065
1066 static void
1067 micro_sin(
1068 union tgsi_exec_channel *dst,
1069 const union tgsi_exec_channel *src )
1070 {
1071 dst->f[0] = sinf( src->f[0] );
1072 dst->f[1] = sinf( src->f[1] );
1073 dst->f[2] = sinf( src->f[2] );
1074 dst->f[3] = sinf( src->f[3] );
1075 }
1076
1077 static void
1078 micro_sqrt( union tgsi_exec_channel *dst,
1079 const union tgsi_exec_channel *src )
1080 {
1081 dst->f[0] = sqrtf( src->f[0] );
1082 dst->f[1] = sqrtf( src->f[1] );
1083 dst->f[2] = sqrtf( src->f[2] );
1084 dst->f[3] = sqrtf( src->f[3] );
1085 }
1086
1087 static void
1088 micro_sub(
1089 union tgsi_exec_channel *dst,
1090 const union tgsi_exec_channel *src0,
1091 const union tgsi_exec_channel *src1 )
1092 {
1093 dst->f[0] = src0->f[0] - src1->f[0];
1094 dst->f[1] = src0->f[1] - src1->f[1];
1095 dst->f[2] = src0->f[2] - src1->f[2];
1096 dst->f[3] = src0->f[3] - src1->f[3];
1097 }
1098
1099 #if 0
1100 static void
1101 micro_u2f(
1102 union tgsi_exec_channel *dst,
1103 const union tgsi_exec_channel *src )
1104 {
1105 dst->f[0] = (float) src->u[0];
1106 dst->f[1] = (float) src->u[1];
1107 dst->f[2] = (float) src->u[2];
1108 dst->f[3] = (float) src->u[3];
1109 }
1110 #endif
1111
1112 static void
1113 micro_xor(
1114 union tgsi_exec_channel *dst,
1115 const union tgsi_exec_channel *src0,
1116 const union tgsi_exec_channel *src1 )
1117 {
1118 dst->u[0] = src0->u[0] ^ src1->u[0];
1119 dst->u[1] = src0->u[1] ^ src1->u[1];
1120 dst->u[2] = src0->u[2] ^ src1->u[2];
1121 dst->u[3] = src0->u[3] ^ src1->u[3];
1122 }
1123
1124 static void
1125 fetch_src_file_channel(
1126 const struct tgsi_exec_machine *mach,
1127 const uint file,
1128 const uint swizzle,
1129 const union tgsi_exec_channel *index,
1130 union tgsi_exec_channel *chan )
1131 {
1132 switch( swizzle ) {
1133 case TGSI_SWIZZLE_X:
1134 case TGSI_SWIZZLE_Y:
1135 case TGSI_SWIZZLE_Z:
1136 case TGSI_SWIZZLE_W:
1137 switch( file ) {
1138 case TGSI_FILE_CONSTANT:
1139 assert(mach->Consts);
1140 if (index->i[0] < 0)
1141 chan->f[0] = 0.0f;
1142 else
1143 chan->f[0] = mach->Consts[index->i[0]][swizzle];
1144 if (index->i[1] < 0)
1145 chan->f[1] = 0.0f;
1146 else
1147 chan->f[1] = mach->Consts[index->i[1]][swizzle];
1148 if (index->i[2] < 0)
1149 chan->f[2] = 0.0f;
1150 else
1151 chan->f[2] = mach->Consts[index->i[2]][swizzle];
1152 if (index->i[3] < 0)
1153 chan->f[3] = 0.0f;
1154 else
1155 chan->f[3] = mach->Consts[index->i[3]][swizzle];
1156 break;
1157
1158 case TGSI_FILE_INPUT:
1159 chan->u[0] = mach->Inputs[index->i[0]].xyzw[swizzle].u[0];
1160 chan->u[1] = mach->Inputs[index->i[1]].xyzw[swizzle].u[1];
1161 chan->u[2] = mach->Inputs[index->i[2]].xyzw[swizzle].u[2];
1162 chan->u[3] = mach->Inputs[index->i[3]].xyzw[swizzle].u[3];
1163 break;
1164
1165 case TGSI_FILE_TEMPORARY:
1166 assert(index->i[0] < TGSI_EXEC_NUM_TEMPS);
1167 chan->u[0] = mach->Temps[index->i[0]].xyzw[swizzle].u[0];
1168 chan->u[1] = mach->Temps[index->i[1]].xyzw[swizzle].u[1];
1169 chan->u[2] = mach->Temps[index->i[2]].xyzw[swizzle].u[2];
1170 chan->u[3] = mach->Temps[index->i[3]].xyzw[swizzle].u[3];
1171 break;
1172
1173 case TGSI_FILE_IMMEDIATE:
1174 assert( index->i[0] < (int) mach->ImmLimit );
1175 chan->f[0] = mach->Imms[index->i[0]][swizzle];
1176 assert( index->i[1] < (int) mach->ImmLimit );
1177 chan->f[1] = mach->Imms[index->i[1]][swizzle];
1178 assert( index->i[2] < (int) mach->ImmLimit );
1179 chan->f[2] = mach->Imms[index->i[2]][swizzle];
1180 assert( index->i[3] < (int) mach->ImmLimit );
1181 chan->f[3] = mach->Imms[index->i[3]][swizzle];
1182 break;
1183
1184 case TGSI_FILE_ADDRESS:
1185 chan->u[0] = mach->Addrs[index->i[0]].xyzw[swizzle].u[0];
1186 chan->u[1] = mach->Addrs[index->i[1]].xyzw[swizzle].u[1];
1187 chan->u[2] = mach->Addrs[index->i[2]].xyzw[swizzle].u[2];
1188 chan->u[3] = mach->Addrs[index->i[3]].xyzw[swizzle].u[3];
1189 break;
1190
1191 case TGSI_FILE_PREDICATE:
1192 assert(index->i[0] < TGSI_EXEC_NUM_PREDS);
1193 assert(index->i[1] < TGSI_EXEC_NUM_PREDS);
1194 assert(index->i[2] < TGSI_EXEC_NUM_PREDS);
1195 assert(index->i[3] < TGSI_EXEC_NUM_PREDS);
1196 chan->u[0] = mach->Addrs[0].xyzw[swizzle].u[0];
1197 chan->u[1] = mach->Addrs[0].xyzw[swizzle].u[1];
1198 chan->u[2] = mach->Addrs[0].xyzw[swizzle].u[2];
1199 chan->u[3] = mach->Addrs[0].xyzw[swizzle].u[3];
1200 break;
1201
1202 case TGSI_FILE_OUTPUT:
1203 /* vertex/fragment output vars can be read too */
1204 chan->u[0] = mach->Outputs[index->i[0]].xyzw[swizzle].u[0];
1205 chan->u[1] = mach->Outputs[index->i[1]].xyzw[swizzle].u[1];
1206 chan->u[2] = mach->Outputs[index->i[2]].xyzw[swizzle].u[2];
1207 chan->u[3] = mach->Outputs[index->i[3]].xyzw[swizzle].u[3];
1208 break;
1209
1210 default:
1211 assert( 0 );
1212 }
1213 break;
1214
1215 default:
1216 assert( 0 );
1217 }
1218 }
1219
1220 static void
1221 fetch_source(
1222 const struct tgsi_exec_machine *mach,
1223 union tgsi_exec_channel *chan,
1224 const struct tgsi_full_src_register *reg,
1225 const uint chan_index )
1226 {
1227 union tgsi_exec_channel index;
1228 uint swizzle;
1229
1230 /* We start with a direct index into a register file.
1231 *
1232 * file[1],
1233 * where:
1234 * file = SrcRegister.File
1235 * [1] = SrcRegister.Index
1236 */
1237 index.i[0] =
1238 index.i[1] =
1239 index.i[2] =
1240 index.i[3] = reg->SrcRegister.Index;
1241
1242 /* There is an extra source register that indirectly subscripts
1243 * a register file. The direct index now becomes an offset
1244 * that is being added to the indirect register.
1245 *
1246 * file[ind[2].x+1],
1247 * where:
1248 * ind = SrcRegisterInd.File
1249 * [2] = SrcRegisterInd.Index
1250 * .x = SrcRegisterInd.SwizzleX
1251 */
1252 if (reg->SrcRegister.Indirect) {
1253 union tgsi_exec_channel index2;
1254 union tgsi_exec_channel indir_index;
1255 const uint execmask = mach->ExecMask;
1256 uint i;
1257
1258 /* which address register (always zero now) */
1259 index2.i[0] =
1260 index2.i[1] =
1261 index2.i[2] =
1262 index2.i[3] = reg->SrcRegisterInd.Index;
1263
1264 /* get current value of address register[swizzle] */
1265 swizzle = tgsi_util_get_src_register_swizzle( &reg->SrcRegisterInd, CHAN_X );
1266 fetch_src_file_channel(
1267 mach,
1268 reg->SrcRegisterInd.File,
1269 swizzle,
1270 &index2,
1271 &indir_index );
1272
1273 /* add value of address register to the offset */
1274 index.i[0] += (int) indir_index.f[0];
1275 index.i[1] += (int) indir_index.f[1];
1276 index.i[2] += (int) indir_index.f[2];
1277 index.i[3] += (int) indir_index.f[3];
1278
1279 /* for disabled execution channels, zero-out the index to
1280 * avoid using a potential garbage value.
1281 */
1282 for (i = 0; i < QUAD_SIZE; i++) {
1283 if ((execmask & (1 << i)) == 0)
1284 index.i[i] = 0;
1285 }
1286 }
1287
1288 /* There is an extra source register that is a second
1289 * subscript to a register file. Effectively it means that
1290 * the register file is actually a 2D array of registers.
1291 *
1292 * file[1][3] == file[1*sizeof(file[1])+3],
1293 * where:
1294 * [3] = SrcRegisterDim.Index
1295 */
1296 if (reg->SrcRegister.Dimension) {
1297 /* The size of the first-order array depends on the register file type.
1298 * We need to multiply the index to the first array to get an effective,
1299 * "flat" index that points to the beginning of the second-order array.
1300 */
1301 switch (reg->SrcRegister.File) {
1302 case TGSI_FILE_INPUT:
1303 index.i[0] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1304 index.i[1] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1305 index.i[2] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1306 index.i[3] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1307 break;
1308 case TGSI_FILE_CONSTANT:
1309 index.i[0] *= TGSI_EXEC_MAX_CONST_BUFFER;
1310 index.i[1] *= TGSI_EXEC_MAX_CONST_BUFFER;
1311 index.i[2] *= TGSI_EXEC_MAX_CONST_BUFFER;
1312 index.i[3] *= TGSI_EXEC_MAX_CONST_BUFFER;
1313 break;
1314 default:
1315 assert( 0 );
1316 }
1317
1318 index.i[0] += reg->SrcRegisterDim.Index;
1319 index.i[1] += reg->SrcRegisterDim.Index;
1320 index.i[2] += reg->SrcRegisterDim.Index;
1321 index.i[3] += reg->SrcRegisterDim.Index;
1322
1323 /* Again, the second subscript index can be addressed indirectly
1324 * identically to the first one.
1325 * Nothing stops us from indirectly addressing the indirect register,
1326 * but there is no need for that, so we won't exercise it.
1327 *
1328 * file[1][ind[4].y+3],
1329 * where:
1330 * ind = SrcRegisterDimInd.File
1331 * [4] = SrcRegisterDimInd.Index
1332 * .y = SrcRegisterDimInd.SwizzleX
1333 */
1334 if (reg->SrcRegisterDim.Indirect) {
1335 union tgsi_exec_channel index2;
1336 union tgsi_exec_channel indir_index;
1337 const uint execmask = mach->ExecMask;
1338 uint i;
1339
1340 index2.i[0] =
1341 index2.i[1] =
1342 index2.i[2] =
1343 index2.i[3] = reg->SrcRegisterDimInd.Index;
1344
1345 swizzle = tgsi_util_get_src_register_swizzle( &reg->SrcRegisterDimInd, CHAN_X );
1346 fetch_src_file_channel(
1347 mach,
1348 reg->SrcRegisterDimInd.File,
1349 swizzle,
1350 &index2,
1351 &indir_index );
1352
1353 index.i[0] += (int) indir_index.f[0];
1354 index.i[1] += (int) indir_index.f[1];
1355 index.i[2] += (int) indir_index.f[2];
1356 index.i[3] += (int) indir_index.f[3];
1357
1358 /* for disabled execution channels, zero-out the index to
1359 * avoid using a potential garbage value.
1360 */
1361 for (i = 0; i < QUAD_SIZE; i++) {
1362 if ((execmask & (1 << i)) == 0)
1363 index.i[i] = 0;
1364 }
1365 }
1366
1367 /* If by any chance there was a need for a 3D array of register
1368 * files, we would have to check whether SrcRegisterDim is followed
1369 * by a dimension register and continue the saga.
1370 */
1371 }
1372
1373 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1374 fetch_src_file_channel(
1375 mach,
1376 reg->SrcRegister.File,
1377 swizzle,
1378 &index,
1379 chan );
1380
1381 switch (tgsi_util_get_full_src_register_sign_mode( reg, chan_index )) {
1382 case TGSI_UTIL_SIGN_CLEAR:
1383 micro_abs( chan, chan );
1384 break;
1385
1386 case TGSI_UTIL_SIGN_SET:
1387 micro_abs( chan, chan );
1388 micro_neg( chan, chan );
1389 break;
1390
1391 case TGSI_UTIL_SIGN_TOGGLE:
1392 micro_neg( chan, chan );
1393 break;
1394
1395 case TGSI_UTIL_SIGN_KEEP:
1396 break;
1397 }
1398
1399 if (reg->SrcRegisterExtMod.Complement) {
1400 micro_sub( chan, &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], chan );
1401 }
1402 }
1403
1404 static void
1405 store_dest(
1406 struct tgsi_exec_machine *mach,
1407 const union tgsi_exec_channel *chan,
1408 const struct tgsi_full_dst_register *reg,
1409 const struct tgsi_full_instruction *inst,
1410 uint chan_index )
1411 {
1412 uint i;
1413 union tgsi_exec_channel null;
1414 union tgsi_exec_channel *dst;
1415 uint execmask = mach->ExecMask;
1416 int offset = 0; /* indirection offset */
1417 int index;
1418
1419 #ifdef DEBUG
1420 check_inf_or_nan(chan);
1421 #endif
1422
1423 /* There is an extra source register that indirectly subscripts
1424 * a register file. The direct index now becomes an offset
1425 * that is being added to the indirect register.
1426 *
1427 * file[ind[2].x+1],
1428 * where:
1429 * ind = DstRegisterInd.File
1430 * [2] = DstRegisterInd.Index
1431 * .x = DstRegisterInd.SwizzleX
1432 */
1433 if (reg->DstRegister.Indirect) {
1434 union tgsi_exec_channel index;
1435 union tgsi_exec_channel indir_index;
1436 uint swizzle;
1437
1438 /* which address register (always zero for now) */
1439 index.i[0] =
1440 index.i[1] =
1441 index.i[2] =
1442 index.i[3] = reg->DstRegisterInd.Index;
1443
1444 /* get current value of address register[swizzle] */
1445 swizzle = tgsi_util_get_src_register_swizzle( &reg->DstRegisterInd, CHAN_X );
1446
1447 /* fetch values from the address/indirection register */
1448 fetch_src_file_channel(
1449 mach,
1450 reg->DstRegisterInd.File,
1451 swizzle,
1452 &index,
1453 &indir_index );
1454
1455 /* save indirection offset */
1456 offset = (int) indir_index.f[0];
1457 }
1458
1459 switch (reg->DstRegister.File) {
1460 case TGSI_FILE_NULL:
1461 dst = &null;
1462 break;
1463
1464 case TGSI_FILE_OUTPUT:
1465 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1466 + reg->DstRegister.Index;
1467 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1468 break;
1469
1470 case TGSI_FILE_TEMPORARY:
1471 index = reg->DstRegister.Index;
1472 assert( index < TGSI_EXEC_NUM_TEMPS );
1473 dst = &mach->Temps[offset + index].xyzw[chan_index];
1474 break;
1475
1476 case TGSI_FILE_ADDRESS:
1477 index = reg->DstRegister.Index;
1478 dst = &mach->Addrs[index].xyzw[chan_index];
1479 break;
1480
1481 case TGSI_FILE_PREDICATE:
1482 index = reg->DstRegister.Index;
1483 assert(index < TGSI_EXEC_NUM_PREDS);
1484 dst = &mach->Addrs[index].xyzw[chan_index];
1485 break;
1486
1487 default:
1488 assert( 0 );
1489 return;
1490 }
1491
1492 switch (inst->Instruction.Saturate) {
1493 case TGSI_SAT_NONE:
1494 for (i = 0; i < QUAD_SIZE; i++)
1495 if (execmask & (1 << i))
1496 dst->i[i] = chan->i[i];
1497 break;
1498
1499 case TGSI_SAT_ZERO_ONE:
1500 for (i = 0; i < QUAD_SIZE; i++)
1501 if (execmask & (1 << i)) {
1502 if (chan->f[i] < 0.0f)
1503 dst->f[i] = 0.0f;
1504 else if (chan->f[i] > 1.0f)
1505 dst->f[i] = 1.0f;
1506 else
1507 dst->i[i] = chan->i[i];
1508 }
1509 break;
1510
1511 case TGSI_SAT_MINUS_PLUS_ONE:
1512 for (i = 0; i < QUAD_SIZE; i++)
1513 if (execmask & (1 << i)) {
1514 if (chan->f[i] < -1.0f)
1515 dst->f[i] = -1.0f;
1516 else if (chan->f[i] > 1.0f)
1517 dst->f[i] = 1.0f;
1518 else
1519 dst->i[i] = chan->i[i];
1520 }
1521 break;
1522
1523 default:
1524 assert( 0 );
1525 }
1526 }
1527
1528 #define FETCH(VAL,INDEX,CHAN)\
1529 fetch_source (mach, VAL, &inst->FullSrcRegisters[INDEX], CHAN)
1530
1531 #define STORE(VAL,INDEX,CHAN)\
1532 store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN )
1533
1534
1535 /**
1536 * Execute ARB-style KIL which is predicated by a src register.
1537 * Kill fragment if any of the four values is less than zero.
1538 */
1539 static void
1540 exec_kil(struct tgsi_exec_machine *mach,
1541 const struct tgsi_full_instruction *inst)
1542 {
1543 uint uniquemask;
1544 uint chan_index;
1545 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1546 union tgsi_exec_channel r[1];
1547
1548 /* This mask stores component bits that were already tested. */
1549 uniquemask = 0;
1550
1551 for (chan_index = 0; chan_index < 4; chan_index++)
1552 {
1553 uint swizzle;
1554 uint i;
1555
1556 /* unswizzle channel */
1557 swizzle = tgsi_util_get_full_src_register_swizzle (
1558 &inst->FullSrcRegisters[0],
1559 chan_index);
1560
1561 /* check if the component has not been already tested */
1562 if (uniquemask & (1 << swizzle))
1563 continue;
1564 uniquemask |= 1 << swizzle;
1565
1566 FETCH(&r[0], 0, chan_index);
1567 for (i = 0; i < 4; i++)
1568 if (r[0].f[i] < 0.0f)
1569 kilmask |= 1 << i;
1570 }
1571
1572 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1573 }
1574
1575 /**
1576 * Execute NVIDIA-style KIL which is predicated by a condition code.
1577 * Kill fragment if the condition code is TRUE.
1578 */
1579 static void
1580 exec_kilp(struct tgsi_exec_machine *mach,
1581 const struct tgsi_full_instruction *inst)
1582 {
1583 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1584
1585 /* "unconditional" kil */
1586 kilmask = mach->ExecMask;
1587 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1588 }
1589
1590
1591 /*
1592 * Fetch a four texture samples using STR texture coordinates.
1593 */
1594 static void
1595 fetch_texel( struct tgsi_sampler *sampler,
1596 const union tgsi_exec_channel *s,
1597 const union tgsi_exec_channel *t,
1598 const union tgsi_exec_channel *p,
1599 float lodbias, /* XXX should be float[4] */
1600 union tgsi_exec_channel *r,
1601 union tgsi_exec_channel *g,
1602 union tgsi_exec_channel *b,
1603 union tgsi_exec_channel *a )
1604 {
1605 uint j;
1606 float rgba[NUM_CHANNELS][QUAD_SIZE];
1607
1608 sampler->get_samples(sampler, s->f, t->f, p->f, lodbias, rgba);
1609
1610 for (j = 0; j < 4; j++) {
1611 r->f[j] = rgba[0][j];
1612 g->f[j] = rgba[1][j];
1613 b->f[j] = rgba[2][j];
1614 a->f[j] = rgba[3][j];
1615 }
1616 }
1617
1618
1619 static void
1620 exec_tex(struct tgsi_exec_machine *mach,
1621 const struct tgsi_full_instruction *inst,
1622 boolean biasLod,
1623 boolean projected)
1624 {
1625 const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
1626 union tgsi_exec_channel r[4];
1627 uint chan_index;
1628 float lodBias;
1629
1630 /* debug_printf("Sampler %u unit %u\n", sampler, unit); */
1631
1632 switch (inst->InstructionExtTexture.Texture) {
1633 case TGSI_TEXTURE_1D:
1634 case TGSI_TEXTURE_SHADOW1D:
1635
1636 FETCH(&r[0], 0, CHAN_X);
1637
1638 if (projected) {
1639 FETCH(&r[1], 0, CHAN_W);
1640 micro_div( &r[0], &r[0], &r[1] );
1641 }
1642
1643 if (biasLod) {
1644 FETCH(&r[1], 0, CHAN_W);
1645 lodBias = r[2].f[0];
1646 }
1647 else
1648 lodBias = 0.0;
1649
1650 fetch_texel(mach->Samplers[unit],
1651 &r[0], &ZeroVec, &ZeroVec, lodBias, /* S, T, P, BIAS */
1652 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1653 break;
1654
1655 case TGSI_TEXTURE_2D:
1656 case TGSI_TEXTURE_RECT:
1657 case TGSI_TEXTURE_SHADOW2D:
1658 case TGSI_TEXTURE_SHADOWRECT:
1659
1660 FETCH(&r[0], 0, CHAN_X);
1661 FETCH(&r[1], 0, CHAN_Y);
1662 FETCH(&r[2], 0, CHAN_Z);
1663
1664 if (projected) {
1665 FETCH(&r[3], 0, CHAN_W);
1666 micro_div( &r[0], &r[0], &r[3] );
1667 micro_div( &r[1], &r[1], &r[3] );
1668 micro_div( &r[2], &r[2], &r[3] );
1669 }
1670
1671 if (biasLod) {
1672 FETCH(&r[3], 0, CHAN_W);
1673 lodBias = r[3].f[0];
1674 }
1675 else
1676 lodBias = 0.0;
1677
1678 fetch_texel(mach->Samplers[unit],
1679 &r[0], &r[1], &r[2], lodBias, /* inputs */
1680 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1681 break;
1682
1683 case TGSI_TEXTURE_3D:
1684 case TGSI_TEXTURE_CUBE:
1685
1686 FETCH(&r[0], 0, CHAN_X);
1687 FETCH(&r[1], 0, CHAN_Y);
1688 FETCH(&r[2], 0, CHAN_Z);
1689
1690 if (projected) {
1691 FETCH(&r[3], 0, CHAN_W);
1692 micro_div( &r[0], &r[0], &r[3] );
1693 micro_div( &r[1], &r[1], &r[3] );
1694 micro_div( &r[2], &r[2], &r[3] );
1695 }
1696
1697 if (biasLod) {
1698 FETCH(&r[3], 0, CHAN_W);
1699 lodBias = r[3].f[0];
1700 }
1701 else
1702 lodBias = 0.0;
1703
1704 fetch_texel(mach->Samplers[unit],
1705 &r[0], &r[1], &r[2], lodBias,
1706 &r[0], &r[1], &r[2], &r[3]);
1707 break;
1708
1709 default:
1710 assert (0);
1711 }
1712
1713 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1714 STORE( &r[chan_index], 0, chan_index );
1715 }
1716 }
1717
1718
1719 /**
1720 * Evaluate a constant-valued coefficient at the position of the
1721 * current quad.
1722 */
1723 static void
1724 eval_constant_coef(
1725 struct tgsi_exec_machine *mach,
1726 unsigned attrib,
1727 unsigned chan )
1728 {
1729 unsigned i;
1730
1731 for( i = 0; i < QUAD_SIZE; i++ ) {
1732 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
1733 }
1734 }
1735
1736 /**
1737 * Evaluate a linear-valued coefficient at the position of the
1738 * current quad.
1739 */
1740 static void
1741 eval_linear_coef(
1742 struct tgsi_exec_machine *mach,
1743 unsigned attrib,
1744 unsigned chan )
1745 {
1746 const float x = mach->QuadPos.xyzw[0].f[0];
1747 const float y = mach->QuadPos.xyzw[1].f[0];
1748 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1749 const float dady = mach->InterpCoefs[attrib].dady[chan];
1750 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1751 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
1752 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
1753 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
1754 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
1755 }
1756
1757 /**
1758 * Evaluate a perspective-valued coefficient at the position of the
1759 * current quad.
1760 */
1761 static void
1762 eval_perspective_coef(
1763 struct tgsi_exec_machine *mach,
1764 unsigned attrib,
1765 unsigned chan )
1766 {
1767 const float x = mach->QuadPos.xyzw[0].f[0];
1768 const float y = mach->QuadPos.xyzw[1].f[0];
1769 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1770 const float dady = mach->InterpCoefs[attrib].dady[chan];
1771 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1772 const float *w = mach->QuadPos.xyzw[3].f;
1773 /* divide by W here */
1774 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
1775 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
1776 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
1777 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
1778 }
1779
1780
1781 typedef void (* eval_coef_func)(
1782 struct tgsi_exec_machine *mach,
1783 unsigned attrib,
1784 unsigned chan );
1785
1786 static void
1787 exec_declaration(
1788 struct tgsi_exec_machine *mach,
1789 const struct tgsi_full_declaration *decl )
1790 {
1791 if( mach->Processor == TGSI_PROCESSOR_FRAGMENT ) {
1792 if( decl->Declaration.File == TGSI_FILE_INPUT ) {
1793 unsigned first, last, mask;
1794 eval_coef_func eval;
1795
1796 first = decl->DeclarationRange.First;
1797 last = decl->DeclarationRange.Last;
1798 mask = decl->Declaration.UsageMask;
1799
1800 switch( decl->Declaration.Interpolate ) {
1801 case TGSI_INTERPOLATE_CONSTANT:
1802 eval = eval_constant_coef;
1803 break;
1804
1805 case TGSI_INTERPOLATE_LINEAR:
1806 eval = eval_linear_coef;
1807 break;
1808
1809 case TGSI_INTERPOLATE_PERSPECTIVE:
1810 eval = eval_perspective_coef;
1811 break;
1812
1813 default:
1814 assert( 0 );
1815 return;
1816 }
1817
1818 if( mask == TGSI_WRITEMASK_XYZW ) {
1819 unsigned i, j;
1820
1821 for( i = first; i <= last; i++ ) {
1822 for( j = 0; j < NUM_CHANNELS; j++ ) {
1823 eval( mach, i, j );
1824 }
1825 }
1826 }
1827 else {
1828 unsigned i, j;
1829
1830 for( j = 0; j < NUM_CHANNELS; j++ ) {
1831 if( mask & (1 << j) ) {
1832 for( i = first; i <= last; i++ ) {
1833 eval( mach, i, j );
1834 }
1835 }
1836 }
1837 }
1838 }
1839 }
1840 }
1841
1842 static void
1843 exec_instruction(
1844 struct tgsi_exec_machine *mach,
1845 const struct tgsi_full_instruction *inst,
1846 int *pc )
1847 {
1848 uint chan_index;
1849 union tgsi_exec_channel r[10];
1850
1851 (*pc)++;
1852
1853 switch (inst->Instruction.Opcode) {
1854 case TGSI_OPCODE_ARL:
1855 case TGSI_OPCODE_FLR:
1856 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1857 FETCH( &r[0], 0, chan_index );
1858 micro_flr( &r[0], &r[0] );
1859 STORE( &r[0], 0, chan_index );
1860 }
1861 break;
1862
1863 case TGSI_OPCODE_MOV:
1864 if (inst->Flags & SOA_DEPENDENCY_FLAG) {
1865 /* Do all fetches into temp regs, then do all stores to avoid
1866 * intermediate/accidental clobbering. This could be done all the
1867 * time for MOV but for other instructions we'll need more temps...
1868 */
1869 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1870 FETCH( &r[chan_index], 0, chan_index );
1871 }
1872 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1873 STORE( &r[chan_index], 0, chan_index );
1874 }
1875 }
1876 else {
1877 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1878 FETCH( &r[0], 0, chan_index );
1879 STORE( &r[0], 0, chan_index );
1880 }
1881 }
1882 break;
1883
1884 case TGSI_OPCODE_LIT:
1885 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
1886 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
1887 }
1888
1889 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y ) || IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1890 FETCH( &r[0], 0, CHAN_X );
1891 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
1892 micro_max( &r[0], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
1893 STORE( &r[0], 0, CHAN_Y );
1894 }
1895
1896 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1897 FETCH( &r[1], 0, CHAN_Y );
1898 micro_max( &r[1], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
1899
1900 FETCH( &r[2], 0, CHAN_W );
1901 micro_min( &r[2], &r[2], &mach->Temps[TEMP_128_I].xyzw[TEMP_128_C] );
1902 micro_max( &r[2], &r[2], &mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C] );
1903 micro_pow( &r[1], &r[1], &r[2] );
1904 micro_lt( &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
1905 STORE( &r[0], 0, CHAN_Z );
1906 }
1907 }
1908
1909 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
1910 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
1911 }
1912 break;
1913
1914 case TGSI_OPCODE_RCP:
1915 /* TGSI_OPCODE_RECIP */
1916 FETCH( &r[0], 0, CHAN_X );
1917 micro_div( &r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0] );
1918 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1919 STORE( &r[0], 0, chan_index );
1920 }
1921 break;
1922
1923 case TGSI_OPCODE_RSQ:
1924 /* TGSI_OPCODE_RECIPSQRT */
1925 FETCH( &r[0], 0, CHAN_X );
1926 micro_abs( &r[0], &r[0] );
1927 micro_sqrt( &r[0], &r[0] );
1928 micro_div( &r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0] );
1929 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1930 STORE( &r[0], 0, chan_index );
1931 }
1932 break;
1933
1934 case TGSI_OPCODE_EXP:
1935 FETCH( &r[0], 0, CHAN_X );
1936 micro_flr( &r[1], &r[0] ); /* r1 = floor(r0) */
1937 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
1938 micro_exp2( &r[2], &r[1] ); /* r2 = 2 ^ r1 */
1939 STORE( &r[2], 0, CHAN_X ); /* store r2 */
1940 }
1941 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
1942 micro_sub( &r[2], &r[0], &r[1] ); /* r2 = r0 - r1 */
1943 STORE( &r[2], 0, CHAN_Y ); /* store r2 */
1944 }
1945 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1946 micro_exp2( &r[2], &r[0] ); /* r2 = 2 ^ r0 */
1947 STORE( &r[2], 0, CHAN_Z ); /* store r2 */
1948 }
1949 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
1950 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
1951 }
1952 break;
1953
1954 case TGSI_OPCODE_LOG:
1955 FETCH( &r[0], 0, CHAN_X );
1956 micro_abs( &r[2], &r[0] ); /* r2 = abs(r0) */
1957 micro_lg2( &r[1], &r[2] ); /* r1 = lg2(r2) */
1958 micro_flr( &r[0], &r[1] ); /* r0 = floor(r1) */
1959 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
1960 STORE( &r[0], 0, CHAN_X );
1961 }
1962 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
1963 micro_exp2( &r[0], &r[0] ); /* r0 = 2 ^ r0 */
1964 micro_div( &r[0], &r[2], &r[0] ); /* r0 = r2 / r0 */
1965 STORE( &r[0], 0, CHAN_Y );
1966 }
1967 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1968 STORE( &r[1], 0, CHAN_Z );
1969 }
1970 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
1971 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
1972 }
1973 break;
1974
1975 case TGSI_OPCODE_MUL:
1976 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index )
1977 {
1978 FETCH(&r[0], 0, chan_index);
1979 FETCH(&r[1], 1, chan_index);
1980
1981 micro_mul( &r[0], &r[0], &r[1] );
1982
1983 STORE(&r[0], 0, chan_index);
1984 }
1985 break;
1986
1987 case TGSI_OPCODE_ADD:
1988 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1989 FETCH( &r[0], 0, chan_index );
1990 FETCH( &r[1], 1, chan_index );
1991 micro_add( &r[0], &r[0], &r[1] );
1992 STORE( &r[0], 0, chan_index );
1993 }
1994 break;
1995
1996 case TGSI_OPCODE_DP3:
1997 /* TGSI_OPCODE_DOT3 */
1998 FETCH( &r[0], 0, CHAN_X );
1999 FETCH( &r[1], 1, CHAN_X );
2000 micro_mul( &r[0], &r[0], &r[1] );
2001
2002 FETCH( &r[1], 0, CHAN_Y );
2003 FETCH( &r[2], 1, CHAN_Y );
2004 micro_mul( &r[1], &r[1], &r[2] );
2005 micro_add( &r[0], &r[0], &r[1] );
2006
2007 FETCH( &r[1], 0, CHAN_Z );
2008 FETCH( &r[2], 1, CHAN_Z );
2009 micro_mul( &r[1], &r[1], &r[2] );
2010 micro_add( &r[0], &r[0], &r[1] );
2011
2012 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2013 STORE( &r[0], 0, chan_index );
2014 }
2015 break;
2016
2017 case TGSI_OPCODE_DP4:
2018 /* TGSI_OPCODE_DOT4 */
2019 FETCH(&r[0], 0, CHAN_X);
2020 FETCH(&r[1], 1, CHAN_X);
2021
2022 micro_mul( &r[0], &r[0], &r[1] );
2023
2024 FETCH(&r[1], 0, CHAN_Y);
2025 FETCH(&r[2], 1, CHAN_Y);
2026
2027 micro_mul( &r[1], &r[1], &r[2] );
2028 micro_add( &r[0], &r[0], &r[1] );
2029
2030 FETCH(&r[1], 0, CHAN_Z);
2031 FETCH(&r[2], 1, CHAN_Z);
2032
2033 micro_mul( &r[1], &r[1], &r[2] );
2034 micro_add( &r[0], &r[0], &r[1] );
2035
2036 FETCH(&r[1], 0, CHAN_W);
2037 FETCH(&r[2], 1, CHAN_W);
2038
2039 micro_mul( &r[1], &r[1], &r[2] );
2040 micro_add( &r[0], &r[0], &r[1] );
2041
2042 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2043 STORE( &r[0], 0, chan_index );
2044 }
2045 break;
2046
2047 case TGSI_OPCODE_DST:
2048 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2049 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
2050 }
2051
2052 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2053 FETCH( &r[0], 0, CHAN_Y );
2054 FETCH( &r[1], 1, CHAN_Y);
2055 micro_mul( &r[0], &r[0], &r[1] );
2056 STORE( &r[0], 0, CHAN_Y );
2057 }
2058
2059 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2060 FETCH( &r[0], 0, CHAN_Z );
2061 STORE( &r[0], 0, CHAN_Z );
2062 }
2063
2064 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2065 FETCH( &r[0], 1, CHAN_W );
2066 STORE( &r[0], 0, CHAN_W );
2067 }
2068 break;
2069
2070 case TGSI_OPCODE_MIN:
2071 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2072 FETCH(&r[0], 0, chan_index);
2073 FETCH(&r[1], 1, chan_index);
2074
2075 /* XXX use micro_min()?? */
2076 micro_lt( &r[0], &r[0], &r[1], &r[0], &r[1] );
2077
2078 STORE(&r[0], 0, chan_index);
2079 }
2080 break;
2081
2082 case TGSI_OPCODE_MAX:
2083 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2084 FETCH(&r[0], 0, chan_index);
2085 FETCH(&r[1], 1, chan_index);
2086
2087 /* XXX use micro_max()?? */
2088 micro_lt( &r[0], &r[0], &r[1], &r[1], &r[0] );
2089
2090 STORE(&r[0], 0, chan_index );
2091 }
2092 break;
2093
2094 case TGSI_OPCODE_SLT:
2095 /* TGSI_OPCODE_SETLT */
2096 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2097 FETCH( &r[0], 0, chan_index );
2098 FETCH( &r[1], 1, chan_index );
2099 micro_lt( &r[0], &r[0], &r[1], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2100 STORE( &r[0], 0, chan_index );
2101 }
2102 break;
2103
2104 case TGSI_OPCODE_SGE:
2105 /* TGSI_OPCODE_SETGE */
2106 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2107 FETCH( &r[0], 0, chan_index );
2108 FETCH( &r[1], 1, chan_index );
2109 micro_le( &r[0], &r[1], &r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2110 STORE( &r[0], 0, chan_index );
2111 }
2112 break;
2113
2114 case TGSI_OPCODE_MAD:
2115 /* TGSI_OPCODE_MADD */
2116 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2117 FETCH( &r[0], 0, chan_index );
2118 FETCH( &r[1], 1, chan_index );
2119 micro_mul( &r[0], &r[0], &r[1] );
2120 FETCH( &r[1], 2, chan_index );
2121 micro_add( &r[0], &r[0], &r[1] );
2122 STORE( &r[0], 0, chan_index );
2123 }
2124 break;
2125
2126 case TGSI_OPCODE_SUB:
2127 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2128 FETCH(&r[0], 0, chan_index);
2129 FETCH(&r[1], 1, chan_index);
2130
2131 micro_sub( &r[0], &r[0], &r[1] );
2132
2133 STORE(&r[0], 0, chan_index);
2134 }
2135 break;
2136
2137 case TGSI_OPCODE_LRP:
2138 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2139 FETCH(&r[0], 0, chan_index);
2140 FETCH(&r[1], 1, chan_index);
2141 FETCH(&r[2], 2, chan_index);
2142
2143 micro_sub( &r[1], &r[1], &r[2] );
2144 micro_mul( &r[0], &r[0], &r[1] );
2145 micro_add( &r[0], &r[0], &r[2] );
2146
2147 STORE(&r[0], 0, chan_index);
2148 }
2149 break;
2150
2151 case TGSI_OPCODE_CND:
2152 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2153 FETCH(&r[0], 0, chan_index);
2154 FETCH(&r[1], 1, chan_index);
2155 FETCH(&r[2], 2, chan_index);
2156 micro_lt(&r[0], &mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C], &r[2], &r[0], &r[1]);
2157 STORE(&r[0], 0, chan_index);
2158 }
2159 break;
2160
2161 case TGSI_OPCODE_DP2A:
2162 FETCH( &r[0], 0, CHAN_X );
2163 FETCH( &r[1], 1, CHAN_X );
2164 micro_mul( &r[0], &r[0], &r[1] );
2165
2166 FETCH( &r[1], 0, CHAN_Y );
2167 FETCH( &r[2], 1, CHAN_Y );
2168 micro_mul( &r[1], &r[1], &r[2] );
2169 micro_add( &r[0], &r[0], &r[1] );
2170
2171 FETCH( &r[2], 2, CHAN_X );
2172 micro_add( &r[0], &r[0], &r[2] );
2173
2174 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2175 STORE( &r[0], 0, chan_index );
2176 }
2177 break;
2178
2179 case TGSI_OPCODE_FRC:
2180 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2181 FETCH( &r[0], 0, chan_index );
2182 micro_frc( &r[0], &r[0] );
2183 STORE( &r[0], 0, chan_index );
2184 }
2185 break;
2186
2187 case TGSI_OPCODE_CLAMP:
2188 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2189 FETCH(&r[0], 0, chan_index);
2190 FETCH(&r[1], 1, chan_index);
2191 micro_max(&r[0], &r[0], &r[1]);
2192 FETCH(&r[1], 2, chan_index);
2193 micro_min(&r[0], &r[0], &r[1]);
2194 STORE(&r[0], 0, chan_index);
2195 }
2196 break;
2197
2198 case TGSI_OPCODE_ROUND:
2199 case TGSI_OPCODE_ARR:
2200 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2201 FETCH( &r[0], 0, chan_index );
2202 micro_rnd( &r[0], &r[0] );
2203 STORE( &r[0], 0, chan_index );
2204 }
2205 break;
2206
2207 case TGSI_OPCODE_EX2:
2208 FETCH(&r[0], 0, CHAN_X);
2209
2210 #if FAST_MATH
2211 micro_exp2( &r[0], &r[0] );
2212 #else
2213 micro_pow( &r[0], &mach->Temps[TEMP_2_I].xyzw[TEMP_2_C], &r[0] );
2214 #endif
2215
2216 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2217 STORE( &r[0], 0, chan_index );
2218 }
2219 break;
2220
2221 case TGSI_OPCODE_LG2:
2222 FETCH( &r[0], 0, CHAN_X );
2223 micro_lg2( &r[0], &r[0] );
2224 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2225 STORE( &r[0], 0, chan_index );
2226 }
2227 break;
2228
2229 case TGSI_OPCODE_POW:
2230 FETCH(&r[0], 0, CHAN_X);
2231 FETCH(&r[1], 1, CHAN_X);
2232
2233 micro_pow( &r[0], &r[0], &r[1] );
2234
2235 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2236 STORE( &r[0], 0, chan_index );
2237 }
2238 break;
2239
2240 case TGSI_OPCODE_XPD:
2241 FETCH(&r[0], 0, CHAN_Y);
2242 FETCH(&r[1], 1, CHAN_Z);
2243
2244 micro_mul( &r[2], &r[0], &r[1] );
2245
2246 FETCH(&r[3], 0, CHAN_Z);
2247 FETCH(&r[4], 1, CHAN_Y);
2248
2249 micro_mul( &r[5], &r[3], &r[4] );
2250 micro_sub( &r[2], &r[2], &r[5] );
2251
2252 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2253 STORE( &r[2], 0, CHAN_X );
2254 }
2255
2256 FETCH(&r[2], 1, CHAN_X);
2257
2258 micro_mul( &r[3], &r[3], &r[2] );
2259
2260 FETCH(&r[5], 0, CHAN_X);
2261
2262 micro_mul( &r[1], &r[1], &r[5] );
2263 micro_sub( &r[3], &r[3], &r[1] );
2264
2265 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2266 STORE( &r[3], 0, CHAN_Y );
2267 }
2268
2269 micro_mul( &r[5], &r[5], &r[4] );
2270 micro_mul( &r[0], &r[0], &r[2] );
2271 micro_sub( &r[5], &r[5], &r[0] );
2272
2273 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2274 STORE( &r[5], 0, CHAN_Z );
2275 }
2276
2277 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2278 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2279 }
2280 break;
2281
2282 case TGSI_OPCODE_ABS:
2283 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2284 FETCH(&r[0], 0, chan_index);
2285
2286 micro_abs( &r[0], &r[0] );
2287
2288 STORE(&r[0], 0, chan_index);
2289 }
2290 break;
2291
2292 case TGSI_OPCODE_RCC:
2293 FETCH(&r[0], 0, CHAN_X);
2294 micro_div(&r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0]);
2295 micro_float_clamp(&r[0], &r[0]);
2296 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2297 STORE(&r[0], 0, chan_index);
2298 }
2299 break;
2300
2301 case TGSI_OPCODE_DPH:
2302 FETCH(&r[0], 0, CHAN_X);
2303 FETCH(&r[1], 1, CHAN_X);
2304
2305 micro_mul( &r[0], &r[0], &r[1] );
2306
2307 FETCH(&r[1], 0, CHAN_Y);
2308 FETCH(&r[2], 1, CHAN_Y);
2309
2310 micro_mul( &r[1], &r[1], &r[2] );
2311 micro_add( &r[0], &r[0], &r[1] );
2312
2313 FETCH(&r[1], 0, CHAN_Z);
2314 FETCH(&r[2], 1, CHAN_Z);
2315
2316 micro_mul( &r[1], &r[1], &r[2] );
2317 micro_add( &r[0], &r[0], &r[1] );
2318
2319 FETCH(&r[1], 1, CHAN_W);
2320
2321 micro_add( &r[0], &r[0], &r[1] );
2322
2323 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2324 STORE( &r[0], 0, chan_index );
2325 }
2326 break;
2327
2328 case TGSI_OPCODE_COS:
2329 FETCH(&r[0], 0, CHAN_X);
2330
2331 micro_cos( &r[0], &r[0] );
2332
2333 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2334 STORE( &r[0], 0, chan_index );
2335 }
2336 break;
2337
2338 case TGSI_OPCODE_DDX:
2339 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2340 FETCH( &r[0], 0, chan_index );
2341 micro_ddx( &r[0], &r[0] );
2342 STORE( &r[0], 0, chan_index );
2343 }
2344 break;
2345
2346 case TGSI_OPCODE_DDY:
2347 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2348 FETCH( &r[0], 0, chan_index );
2349 micro_ddy( &r[0], &r[0] );
2350 STORE( &r[0], 0, chan_index );
2351 }
2352 break;
2353
2354 case TGSI_OPCODE_KILP:
2355 exec_kilp (mach, inst);
2356 break;
2357
2358 case TGSI_OPCODE_KIL:
2359 exec_kil (mach, inst);
2360 break;
2361
2362 case TGSI_OPCODE_PK2H:
2363 assert (0);
2364 break;
2365
2366 case TGSI_OPCODE_PK2US:
2367 assert (0);
2368 break;
2369
2370 case TGSI_OPCODE_PK4B:
2371 assert (0);
2372 break;
2373
2374 case TGSI_OPCODE_PK4UB:
2375 assert (0);
2376 break;
2377
2378 case TGSI_OPCODE_RFL:
2379 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2380 IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2381 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2382 /* r0 = dp3(src0, src0) */
2383 FETCH(&r[2], 0, CHAN_X);
2384 micro_mul(&r[0], &r[2], &r[2]);
2385 FETCH(&r[4], 0, CHAN_Y);
2386 micro_mul(&r[8], &r[4], &r[4]);
2387 micro_add(&r[0], &r[0], &r[8]);
2388 FETCH(&r[6], 0, CHAN_Z);
2389 micro_mul(&r[8], &r[6], &r[6]);
2390 micro_add(&r[0], &r[0], &r[8]);
2391
2392 /* r1 = dp3(src0, src1) */
2393 FETCH(&r[3], 1, CHAN_X);
2394 micro_mul(&r[1], &r[2], &r[3]);
2395 FETCH(&r[5], 1, CHAN_Y);
2396 micro_mul(&r[8], &r[4], &r[5]);
2397 micro_add(&r[1], &r[1], &r[8]);
2398 FETCH(&r[7], 1, CHAN_Z);
2399 micro_mul(&r[8], &r[6], &r[7]);
2400 micro_add(&r[1], &r[1], &r[8]);
2401
2402 /* r1 = 2 * r1 / r0 */
2403 micro_add(&r[1], &r[1], &r[1]);
2404 micro_div(&r[1], &r[1], &r[0]);
2405
2406 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2407 micro_mul(&r[2], &r[2], &r[1]);
2408 micro_sub(&r[2], &r[2], &r[3]);
2409 STORE(&r[2], 0, CHAN_X);
2410 }
2411 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2412 micro_mul(&r[4], &r[4], &r[1]);
2413 micro_sub(&r[4], &r[4], &r[5]);
2414 STORE(&r[4], 0, CHAN_Y);
2415 }
2416 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2417 micro_mul(&r[6], &r[6], &r[1]);
2418 micro_sub(&r[6], &r[6], &r[7]);
2419 STORE(&r[6], 0, CHAN_Z);
2420 }
2421 }
2422 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2423 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W);
2424 }
2425 break;
2426
2427 case TGSI_OPCODE_SEQ:
2428 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2429 FETCH( &r[0], 0, chan_index );
2430 FETCH( &r[1], 1, chan_index );
2431 micro_eq( &r[0], &r[0], &r[1],
2432 &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C],
2433 &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2434 STORE( &r[0], 0, chan_index );
2435 }
2436 break;
2437
2438 case TGSI_OPCODE_SFL:
2439 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2440 STORE(&mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, chan_index);
2441 }
2442 break;
2443
2444 case TGSI_OPCODE_SGT:
2445 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2446 FETCH( &r[0], 0, chan_index );
2447 FETCH( &r[1], 1, chan_index );
2448 micro_le( &r[0], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C] );
2449 STORE( &r[0], 0, chan_index );
2450 }
2451 break;
2452
2453 case TGSI_OPCODE_SIN:
2454 FETCH( &r[0], 0, CHAN_X );
2455 micro_sin( &r[0], &r[0] );
2456 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2457 STORE( &r[0], 0, chan_index );
2458 }
2459 break;
2460
2461 case TGSI_OPCODE_SLE:
2462 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2463 FETCH( &r[0], 0, chan_index );
2464 FETCH( &r[1], 1, chan_index );
2465 micro_le( &r[0], &r[0], &r[1], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2466 STORE( &r[0], 0, chan_index );
2467 }
2468 break;
2469
2470 case TGSI_OPCODE_SNE:
2471 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2472 FETCH( &r[0], 0, chan_index );
2473 FETCH( &r[1], 1, chan_index );
2474 micro_eq( &r[0], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C] );
2475 STORE( &r[0], 0, chan_index );
2476 }
2477 break;
2478
2479 case TGSI_OPCODE_STR:
2480 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2481 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, chan_index);
2482 }
2483 break;
2484
2485 case TGSI_OPCODE_TEX:
2486 /* simple texture lookup */
2487 /* src[0] = texcoord */
2488 /* src[1] = sampler unit */
2489 exec_tex(mach, inst, FALSE, FALSE);
2490 break;
2491
2492 case TGSI_OPCODE_TXB:
2493 /* Texture lookup with lod bias */
2494 /* src[0] = texcoord (src[0].w = LOD bias) */
2495 /* src[1] = sampler unit */
2496 exec_tex(mach, inst, TRUE, FALSE);
2497 break;
2498
2499 case TGSI_OPCODE_TXD:
2500 /* Texture lookup with explict partial derivatives */
2501 /* src[0] = texcoord */
2502 /* src[1] = d[strq]/dx */
2503 /* src[2] = d[strq]/dy */
2504 /* src[3] = sampler unit */
2505 assert (0);
2506 break;
2507
2508 case TGSI_OPCODE_TXL:
2509 /* Texture lookup with explit LOD */
2510 /* src[0] = texcoord (src[0].w = LOD) */
2511 /* src[1] = sampler unit */
2512 exec_tex(mach, inst, TRUE, FALSE);
2513 break;
2514
2515 case TGSI_OPCODE_TXP:
2516 /* Texture lookup with projection */
2517 /* src[0] = texcoord (src[0].w = projection) */
2518 /* src[1] = sampler unit */
2519 exec_tex(mach, inst, FALSE, TRUE);
2520 break;
2521
2522 case TGSI_OPCODE_UP2H:
2523 assert (0);
2524 break;
2525
2526 case TGSI_OPCODE_UP2US:
2527 assert (0);
2528 break;
2529
2530 case TGSI_OPCODE_UP4B:
2531 assert (0);
2532 break;
2533
2534 case TGSI_OPCODE_UP4UB:
2535 assert (0);
2536 break;
2537
2538 case TGSI_OPCODE_X2D:
2539 FETCH(&r[0], 1, CHAN_X);
2540 FETCH(&r[1], 1, CHAN_Y);
2541 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2542 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2543 FETCH(&r[2], 2, CHAN_X);
2544 micro_mul(&r[2], &r[2], &r[0]);
2545 FETCH(&r[3], 2, CHAN_Y);
2546 micro_mul(&r[3], &r[3], &r[1]);
2547 micro_add(&r[2], &r[2], &r[3]);
2548 FETCH(&r[3], 0, CHAN_X);
2549 micro_add(&r[2], &r[2], &r[3]);
2550 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2551 STORE(&r[2], 0, CHAN_X);
2552 }
2553 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2554 STORE(&r[2], 0, CHAN_Z);
2555 }
2556 }
2557 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2558 IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2559 FETCH(&r[2], 2, CHAN_Z);
2560 micro_mul(&r[2], &r[2], &r[0]);
2561 FETCH(&r[3], 2, CHAN_W);
2562 micro_mul(&r[3], &r[3], &r[1]);
2563 micro_add(&r[2], &r[2], &r[3]);
2564 FETCH(&r[3], 0, CHAN_Y);
2565 micro_add(&r[2], &r[2], &r[3]);
2566 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2567 STORE(&r[2], 0, CHAN_Y);
2568 }
2569 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2570 STORE(&r[2], 0, CHAN_W);
2571 }
2572 }
2573 break;
2574
2575 case TGSI_OPCODE_ARA:
2576 assert (0);
2577 break;
2578
2579 case TGSI_OPCODE_BRA:
2580 assert (0);
2581 break;
2582
2583 case TGSI_OPCODE_CAL:
2584 /* skip the call if no execution channels are enabled */
2585 if (mach->ExecMask) {
2586 /* do the call */
2587
2588 /* First, record the depths of the execution stacks.
2589 * This is important for deeply nested/looped return statements.
2590 * We have to unwind the stacks by the correct amount. For a
2591 * real code generator, we could determine the number of entries
2592 * to pop off each stack with simple static analysis and avoid
2593 * implementing this data structure at run time.
2594 */
2595 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
2596 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
2597 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
2598 /* note that PC was already incremented above */
2599 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
2600
2601 mach->CallStackTop++;
2602
2603 /* Second, push the Cond, Loop, Cont, Func stacks */
2604 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
2605 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
2606 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2607 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
2608 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2609 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
2610 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
2611 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
2612
2613 /* Finally, jump to the subroutine */
2614 *pc = inst->InstructionExtLabel.Label;
2615 }
2616 break;
2617
2618 case TGSI_OPCODE_RET:
2619 mach->FuncMask &= ~mach->ExecMask;
2620 UPDATE_EXEC_MASK(mach);
2621
2622 if (mach->FuncMask == 0x0) {
2623 /* really return now (otherwise, keep executing */
2624
2625 if (mach->CallStackTop == 0) {
2626 /* returning from main() */
2627 *pc = -1;
2628 return;
2629 }
2630
2631 assert(mach->CallStackTop > 0);
2632 mach->CallStackTop--;
2633
2634 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
2635 mach->CondMask = mach->CondStack[mach->CondStackTop];
2636
2637 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
2638 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
2639
2640 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
2641 mach->ContMask = mach->ContStack[mach->ContStackTop];
2642
2643 assert(mach->FuncStackTop > 0);
2644 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
2645
2646 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
2647
2648 UPDATE_EXEC_MASK(mach);
2649 }
2650 break;
2651
2652 case TGSI_OPCODE_SSG:
2653 /* TGSI_OPCODE_SGN */
2654 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2655 FETCH( &r[0], 0, chan_index );
2656 micro_sgn( &r[0], &r[0] );
2657 STORE( &r[0], 0, chan_index );
2658 }
2659 break;
2660
2661 case TGSI_OPCODE_CMP:
2662 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2663 FETCH(&r[0], 0, chan_index);
2664 FETCH(&r[1], 1, chan_index);
2665 FETCH(&r[2], 2, chan_index);
2666
2667 micro_lt( &r[0], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[1], &r[2] );
2668
2669 STORE(&r[0], 0, chan_index);
2670 }
2671 break;
2672
2673 case TGSI_OPCODE_SCS:
2674 if( IS_CHANNEL_ENABLED( *inst, CHAN_X ) || IS_CHANNEL_ENABLED( *inst, CHAN_Y ) ) {
2675 FETCH( &r[0], 0, CHAN_X );
2676 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2677 micro_cos(&r[1], &r[0]);
2678 STORE(&r[1], 0, CHAN_X);
2679 }
2680 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2681 micro_sin(&r[1], &r[0]);
2682 STORE(&r[1], 0, CHAN_Y);
2683 }
2684 }
2685 if( IS_CHANNEL_ENABLED( *inst, CHAN_Z ) ) {
2686 STORE( &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, CHAN_Z );
2687 }
2688 if( IS_CHANNEL_ENABLED( *inst, CHAN_W ) ) {
2689 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2690 }
2691 break;
2692
2693 case TGSI_OPCODE_NRM:
2694 /* 3-component vector normalize */
2695 if(IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2696 IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2697 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2698 /* r3 = sqrt(dp3(src0, src0)) */
2699 FETCH(&r[0], 0, CHAN_X);
2700 micro_mul(&r[3], &r[0], &r[0]);
2701 FETCH(&r[1], 0, CHAN_Y);
2702 micro_mul(&r[4], &r[1], &r[1]);
2703 micro_add(&r[3], &r[3], &r[4]);
2704 FETCH(&r[2], 0, CHAN_Z);
2705 micro_mul(&r[4], &r[2], &r[2]);
2706 micro_add(&r[3], &r[3], &r[4]);
2707 micro_sqrt(&r[3], &r[3]);
2708
2709 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2710 micro_div(&r[0], &r[0], &r[3]);
2711 STORE(&r[0], 0, CHAN_X);
2712 }
2713 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2714 micro_div(&r[1], &r[1], &r[3]);
2715 STORE(&r[1], 0, CHAN_Y);
2716 }
2717 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2718 micro_div(&r[2], &r[2], &r[3]);
2719 STORE(&r[2], 0, CHAN_Z);
2720 }
2721 }
2722 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2723 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W);
2724 }
2725 break;
2726
2727 case TGSI_OPCODE_NRM4:
2728 /* 4-component vector normalize */
2729 {
2730 union tgsi_exec_channel tmp, dot;
2731
2732 /* tmp = dp4(src0, src0): */
2733 FETCH( &r[0], 0, CHAN_X );
2734 micro_mul( &tmp, &r[0], &r[0] );
2735
2736 FETCH( &r[1], 0, CHAN_Y );
2737 micro_mul( &dot, &r[1], &r[1] );
2738 micro_add( &tmp, &tmp, &dot );
2739
2740 FETCH( &r[2], 0, CHAN_Z );
2741 micro_mul( &dot, &r[2], &r[2] );
2742 micro_add( &tmp, &tmp, &dot );
2743
2744 FETCH( &r[3], 0, CHAN_W );
2745 micro_mul( &dot, &r[3], &r[3] );
2746 micro_add( &tmp, &tmp, &dot );
2747
2748 /* tmp = 1 / sqrt(tmp) */
2749 micro_sqrt( &tmp, &tmp );
2750 micro_div( &tmp, &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &tmp );
2751
2752 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2753 /* chan = chan * tmp */
2754 micro_mul( &r[chan_index], &tmp, &r[chan_index] );
2755 STORE( &r[chan_index], 0, chan_index );
2756 }
2757 }
2758 break;
2759
2760 case TGSI_OPCODE_DIV:
2761 assert( 0 );
2762 break;
2763
2764 case TGSI_OPCODE_DP2:
2765 FETCH( &r[0], 0, CHAN_X );
2766 FETCH( &r[1], 1, CHAN_X );
2767 micro_mul( &r[0], &r[0], &r[1] );
2768
2769 FETCH( &r[1], 0, CHAN_Y );
2770 FETCH( &r[2], 1, CHAN_Y );
2771 micro_mul( &r[1], &r[1], &r[2] );
2772 micro_add( &r[0], &r[0], &r[1] );
2773
2774 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2775 STORE( &r[0], 0, chan_index );
2776 }
2777 break;
2778
2779 case TGSI_OPCODE_IF:
2780 /* push CondMask */
2781 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
2782 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
2783 FETCH( &r[0], 0, CHAN_X );
2784 /* update CondMask */
2785 if( ! r[0].u[0] ) {
2786 mach->CondMask &= ~0x1;
2787 }
2788 if( ! r[0].u[1] ) {
2789 mach->CondMask &= ~0x2;
2790 }
2791 if( ! r[0].u[2] ) {
2792 mach->CondMask &= ~0x4;
2793 }
2794 if( ! r[0].u[3] ) {
2795 mach->CondMask &= ~0x8;
2796 }
2797 UPDATE_EXEC_MASK(mach);
2798 /* Todo: If CondMask==0, jump to ELSE */
2799 break;
2800
2801 case TGSI_OPCODE_ELSE:
2802 /* invert CondMask wrt previous mask */
2803 {
2804 uint prevMask;
2805 assert(mach->CondStackTop > 0);
2806 prevMask = mach->CondStack[mach->CondStackTop - 1];
2807 mach->CondMask = ~mach->CondMask & prevMask;
2808 UPDATE_EXEC_MASK(mach);
2809 /* Todo: If CondMask==0, jump to ENDIF */
2810 }
2811 break;
2812
2813 case TGSI_OPCODE_ENDIF:
2814 /* pop CondMask */
2815 assert(mach->CondStackTop > 0);
2816 mach->CondMask = mach->CondStack[--mach->CondStackTop];
2817 UPDATE_EXEC_MASK(mach);
2818 break;
2819
2820 case TGSI_OPCODE_END:
2821 /* halt execution */
2822 *pc = -1;
2823 break;
2824
2825 case TGSI_OPCODE_REP:
2826 assert (0);
2827 break;
2828
2829 case TGSI_OPCODE_ENDREP:
2830 assert (0);
2831 break;
2832
2833 case TGSI_OPCODE_PUSHA:
2834 assert (0);
2835 break;
2836
2837 case TGSI_OPCODE_POPA:
2838 assert (0);
2839 break;
2840
2841 case TGSI_OPCODE_CEIL:
2842 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2843 FETCH( &r[0], 0, chan_index );
2844 micro_ceil( &r[0], &r[0] );
2845 STORE( &r[0], 0, chan_index );
2846 }
2847 break;
2848
2849 case TGSI_OPCODE_I2F:
2850 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2851 FETCH( &r[0], 0, chan_index );
2852 micro_i2f( &r[0], &r[0] );
2853 STORE( &r[0], 0, chan_index );
2854 }
2855 break;
2856
2857 case TGSI_OPCODE_NOT:
2858 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2859 FETCH( &r[0], 0, chan_index );
2860 micro_not( &r[0], &r[0] );
2861 STORE( &r[0], 0, chan_index );
2862 }
2863 break;
2864
2865 case TGSI_OPCODE_TRUNC:
2866 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2867 FETCH( &r[0], 0, chan_index );
2868 micro_trunc( &r[0], &r[0] );
2869 STORE( &r[0], 0, chan_index );
2870 }
2871 break;
2872
2873 case TGSI_OPCODE_SHL:
2874 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2875 FETCH( &r[0], 0, chan_index );
2876 FETCH( &r[1], 1, chan_index );
2877 micro_shl( &r[0], &r[0], &r[1] );
2878 STORE( &r[0], 0, chan_index );
2879 }
2880 break;
2881
2882 case TGSI_OPCODE_SHR:
2883 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2884 FETCH( &r[0], 0, chan_index );
2885 FETCH( &r[1], 1, chan_index );
2886 micro_ishr( &r[0], &r[0], &r[1] );
2887 STORE( &r[0], 0, chan_index );
2888 }
2889 break;
2890
2891 case TGSI_OPCODE_AND:
2892 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2893 FETCH( &r[0], 0, chan_index );
2894 FETCH( &r[1], 1, chan_index );
2895 micro_and( &r[0], &r[0], &r[1] );
2896 STORE( &r[0], 0, chan_index );
2897 }
2898 break;
2899
2900 case TGSI_OPCODE_OR:
2901 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2902 FETCH( &r[0], 0, chan_index );
2903 FETCH( &r[1], 1, chan_index );
2904 micro_or( &r[0], &r[0], &r[1] );
2905 STORE( &r[0], 0, chan_index );
2906 }
2907 break;
2908
2909 case TGSI_OPCODE_MOD:
2910 assert (0);
2911 break;
2912
2913 case TGSI_OPCODE_XOR:
2914 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2915 FETCH( &r[0], 0, chan_index );
2916 FETCH( &r[1], 1, chan_index );
2917 micro_xor( &r[0], &r[0], &r[1] );
2918 STORE( &r[0], 0, chan_index );
2919 }
2920 break;
2921
2922 case TGSI_OPCODE_SAD:
2923 assert (0);
2924 break;
2925
2926 case TGSI_OPCODE_TXF:
2927 assert (0);
2928 break;
2929
2930 case TGSI_OPCODE_TXQ:
2931 assert (0);
2932 break;
2933
2934 case TGSI_OPCODE_EMIT:
2935 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += 16;
2936 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
2937 break;
2938
2939 case TGSI_OPCODE_ENDPRIM:
2940 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]++;
2941 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] = 0;
2942 break;
2943
2944 case TGSI_OPCODE_BGNFOR:
2945 assert(mach->LoopCounterStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2946 for (chan_index = 0; chan_index < 3; chan_index++) {
2947 FETCH( &mach->LoopCounterStack[mach->LoopCounterStackTop].xyzw[chan_index], 0, chan_index );
2948 }
2949 STORE( &mach->LoopCounterStack[mach->LoopCounterStackTop].xyzw[CHAN_Y], 0, CHAN_X );
2950 ++mach->LoopCounterStackTop;
2951 /* fall-through (for now) */
2952 case TGSI_OPCODE_BGNLOOP:
2953 /* push LoopMask and ContMasks */
2954 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2955 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
2956 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2957 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
2958 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2959 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
2960 break;
2961
2962 case TGSI_OPCODE_ENDFOR:
2963 assert(mach->LoopCounterStackTop > 0);
2964 micro_sub( &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X],
2965 &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X],
2966 &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C] );
2967 /* update LoopMask */
2968 if( mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X].f[0] <= 0) {
2969 mach->LoopMask &= ~0x1;
2970 }
2971 if( mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X].f[1] <= 0 ) {
2972 mach->LoopMask &= ~0x2;
2973 }
2974 if( mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X].f[2] <= 0 ) {
2975 mach->LoopMask &= ~0x4;
2976 }
2977 if( mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X].f[3] <= 0 ) {
2978 mach->LoopMask &= ~0x8;
2979 }
2980 micro_add( &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y],
2981 &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y],
2982 &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Z]);
2983 assert(mach->LoopLabelStackTop > 0);
2984 inst = mach->Instructions + mach->LoopLabelStack[mach->LoopLabelStackTop - 1];
2985 STORE( &mach->LoopCounterStack[mach->LoopCounterStackTop].xyzw[CHAN_Y], 0, CHAN_X );
2986 /* Restore ContMask, but don't pop */
2987 assert(mach->ContStackTop > 0);
2988 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
2989 UPDATE_EXEC_MASK(mach);
2990 if (mach->ExecMask) {
2991 /* repeat loop: jump to instruction just past BGNLOOP */
2992 assert(mach->LoopLabelStackTop > 0);
2993 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
2994 }
2995 else {
2996 /* exit loop: pop LoopMask */
2997 assert(mach->LoopStackTop > 0);
2998 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
2999 /* pop ContMask */
3000 assert(mach->ContStackTop > 0);
3001 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3002 assert(mach->LoopLabelStackTop > 0);
3003 --mach->LoopLabelStackTop;
3004 assert(mach->LoopCounterStackTop > 0);
3005 --mach->LoopCounterStackTop;
3006 }
3007 UPDATE_EXEC_MASK(mach);
3008 break;
3009
3010 case TGSI_OPCODE_ENDLOOP:
3011 /* Restore ContMask, but don't pop */
3012 assert(mach->ContStackTop > 0);
3013 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3014 UPDATE_EXEC_MASK(mach);
3015 if (mach->ExecMask) {
3016 /* repeat loop: jump to instruction just past BGNLOOP */
3017 assert(mach->LoopLabelStackTop > 0);
3018 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3019 }
3020 else {
3021 /* exit loop: pop LoopMask */
3022 assert(mach->LoopStackTop > 0);
3023 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3024 /* pop ContMask */
3025 assert(mach->ContStackTop > 0);
3026 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3027 assert(mach->LoopLabelStackTop > 0);
3028 --mach->LoopLabelStackTop;
3029 }
3030 UPDATE_EXEC_MASK(mach);
3031 break;
3032
3033 case TGSI_OPCODE_BRK:
3034 /* turn off loop channels for each enabled exec channel */
3035 mach->LoopMask &= ~mach->ExecMask;
3036 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3037 UPDATE_EXEC_MASK(mach);
3038 break;
3039
3040 case TGSI_OPCODE_CONT:
3041 /* turn off cont channels for each enabled exec channel */
3042 mach->ContMask &= ~mach->ExecMask;
3043 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3044 UPDATE_EXEC_MASK(mach);
3045 break;
3046
3047 case TGSI_OPCODE_BGNSUB:
3048 /* no-op */
3049 break;
3050
3051 case TGSI_OPCODE_ENDSUB:
3052 /* no-op */
3053 break;
3054
3055 case TGSI_OPCODE_NOP:
3056 break;
3057
3058 default:
3059 assert( 0 );
3060 }
3061 }
3062
3063
3064 /**
3065 * Run TGSI interpreter.
3066 * \return bitmask of "alive" quad components
3067 */
3068 uint
3069 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
3070 {
3071 uint i;
3072 int pc = 0;
3073
3074 mach->CondMask = 0xf;
3075 mach->LoopMask = 0xf;
3076 mach->ContMask = 0xf;
3077 mach->FuncMask = 0xf;
3078 mach->ExecMask = 0xf;
3079
3080 assert(mach->CondStackTop == 0);
3081 assert(mach->LoopStackTop == 0);
3082 assert(mach->ContStackTop == 0);
3083 assert(mach->CallStackTop == 0);
3084
3085 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
3086 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
3087
3088 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
3089 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
3090 mach->Primitives[0] = 0;
3091 }
3092
3093 for (i = 0; i < QUAD_SIZE; i++) {
3094 mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C].u[i] =
3095 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_X_SHIFT) |
3096 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Y_SHIFT) |
3097 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Z_SHIFT) |
3098 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_W_SHIFT);
3099 }
3100
3101 /* execute declarations (interpolants) */
3102 for (i = 0; i < mach->NumDeclarations; i++) {
3103 exec_declaration( mach, mach->Declarations+i );
3104 }
3105
3106 /* execute instructions, until pc is set to -1 */
3107 while (pc != -1) {
3108 assert(pc < (int) mach->NumInstructions);
3109 exec_instruction( mach, mach->Instructions + pc, &pc );
3110 }
3111
3112 #if 0
3113 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
3114 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
3115 /*
3116 * Scale back depth component.
3117 */
3118 for (i = 0; i < 4; i++)
3119 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
3120 }
3121 #endif
3122
3123 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3124 }