1 /**************************************************************************
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
65 #define DEBUG_EXECUTION 0
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
76 micro_abs(union tgsi_exec_channel
*dst
,
77 const union tgsi_exec_channel
*src
)
79 dst
->f
[0] = fabsf(src
->f
[0]);
80 dst
->f
[1] = fabsf(src
->f
[1]);
81 dst
->f
[2] = fabsf(src
->f
[2]);
82 dst
->f
[3] = fabsf(src
->f
[3]);
86 micro_arl(union tgsi_exec_channel
*dst
,
87 const union tgsi_exec_channel
*src
)
89 dst
->i
[0] = (int)floorf(src
->f
[0]);
90 dst
->i
[1] = (int)floorf(src
->f
[1]);
91 dst
->i
[2] = (int)floorf(src
->f
[2]);
92 dst
->i
[3] = (int)floorf(src
->f
[3]);
96 micro_arr(union tgsi_exec_channel
*dst
,
97 const union tgsi_exec_channel
*src
)
99 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
100 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
101 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
102 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
106 micro_ceil(union tgsi_exec_channel
*dst
,
107 const union tgsi_exec_channel
*src
)
109 dst
->f
[0] = ceilf(src
->f
[0]);
110 dst
->f
[1] = ceilf(src
->f
[1]);
111 dst
->f
[2] = ceilf(src
->f
[2]);
112 dst
->f
[3] = ceilf(src
->f
[3]);
116 micro_clamp(union tgsi_exec_channel
*dst
,
117 const union tgsi_exec_channel
*src0
,
118 const union tgsi_exec_channel
*src1
,
119 const union tgsi_exec_channel
*src2
)
121 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src1
->f
[0] : src0
->f
[0] > src2
->f
[0] ? src2
->f
[0] : src0
->f
[0];
122 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src1
->f
[1] : src0
->f
[1] > src2
->f
[1] ? src2
->f
[1] : src0
->f
[1];
123 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src1
->f
[2] : src0
->f
[2] > src2
->f
[2] ? src2
->f
[2] : src0
->f
[2];
124 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src1
->f
[3] : src0
->f
[3] > src2
->f
[3] ? src2
->f
[3] : src0
->f
[3];
128 micro_cmp(union tgsi_exec_channel
*dst
,
129 const union tgsi_exec_channel
*src0
,
130 const union tgsi_exec_channel
*src1
,
131 const union tgsi_exec_channel
*src2
)
133 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
134 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
135 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
136 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
140 micro_cnd(union tgsi_exec_channel
*dst
,
141 const union tgsi_exec_channel
*src0
,
142 const union tgsi_exec_channel
*src1
,
143 const union tgsi_exec_channel
*src2
)
145 dst
->f
[0] = src2
->f
[0] > 0.5f
? src0
->f
[0] : src1
->f
[0];
146 dst
->f
[1] = src2
->f
[1] > 0.5f
? src0
->f
[1] : src1
->f
[1];
147 dst
->f
[2] = src2
->f
[2] > 0.5f
? src0
->f
[2] : src1
->f
[2];
148 dst
->f
[3] = src2
->f
[3] > 0.5f
? src0
->f
[3] : src1
->f
[3];
152 micro_cos(union tgsi_exec_channel
*dst
,
153 const union tgsi_exec_channel
*src
)
155 dst
->f
[0] = cosf(src
->f
[0]);
156 dst
->f
[1] = cosf(src
->f
[1]);
157 dst
->f
[2] = cosf(src
->f
[2]);
158 dst
->f
[3] = cosf(src
->f
[3]);
162 micro_ddx(union tgsi_exec_channel
*dst
,
163 const union tgsi_exec_channel
*src
)
168 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
172 micro_ddy(union tgsi_exec_channel
*dst
,
173 const union tgsi_exec_channel
*src
)
178 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
182 micro_exp2(union tgsi_exec_channel
*dst
,
183 const union tgsi_exec_channel
*src
)
186 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
187 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
188 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
189 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
192 /* Inf is okay for this instruction, so clamp it to silence assertions. */
194 union tgsi_exec_channel clamped
;
196 for (i
= 0; i
< 4; i
++) {
197 if (src
->f
[i
] > 127.99999f
) {
198 clamped
.f
[i
] = 127.99999f
;
199 } else if (src
->f
[i
] < -126.99999f
) {
200 clamped
.f
[i
] = -126.99999f
;
202 clamped
.f
[i
] = src
->f
[i
];
208 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
209 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
210 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
211 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
212 #endif /* FAST_MATH */
216 micro_flr(union tgsi_exec_channel
*dst
,
217 const union tgsi_exec_channel
*src
)
219 dst
->f
[0] = floorf(src
->f
[0]);
220 dst
->f
[1] = floorf(src
->f
[1]);
221 dst
->f
[2] = floorf(src
->f
[2]);
222 dst
->f
[3] = floorf(src
->f
[3]);
226 micro_frc(union tgsi_exec_channel
*dst
,
227 const union tgsi_exec_channel
*src
)
229 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
230 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
231 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
232 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
236 micro_iabs(union tgsi_exec_channel
*dst
,
237 const union tgsi_exec_channel
*src
)
239 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
240 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
241 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
242 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
246 micro_ineg(union tgsi_exec_channel
*dst
,
247 const union tgsi_exec_channel
*src
)
249 dst
->i
[0] = -src
->i
[0];
250 dst
->i
[1] = -src
->i
[1];
251 dst
->i
[2] = -src
->i
[2];
252 dst
->i
[3] = -src
->i
[3];
256 micro_lg2(union tgsi_exec_channel
*dst
,
257 const union tgsi_exec_channel
*src
)
260 dst
->f
[0] = util_fast_log2(src
->f
[0]);
261 dst
->f
[1] = util_fast_log2(src
->f
[1]);
262 dst
->f
[2] = util_fast_log2(src
->f
[2]);
263 dst
->f
[3] = util_fast_log2(src
->f
[3]);
265 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
266 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
267 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
268 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
273 micro_lrp(union tgsi_exec_channel
*dst
,
274 const union tgsi_exec_channel
*src0
,
275 const union tgsi_exec_channel
*src1
,
276 const union tgsi_exec_channel
*src2
)
278 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
279 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
280 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
281 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
285 micro_mad(union tgsi_exec_channel
*dst
,
286 const union tgsi_exec_channel
*src0
,
287 const union tgsi_exec_channel
*src1
,
288 const union tgsi_exec_channel
*src2
)
290 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
291 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
292 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
293 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
297 micro_mov(union tgsi_exec_channel
*dst
,
298 const union tgsi_exec_channel
*src
)
300 dst
->u
[0] = src
->u
[0];
301 dst
->u
[1] = src
->u
[1];
302 dst
->u
[2] = src
->u
[2];
303 dst
->u
[3] = src
->u
[3];
307 micro_rcp(union tgsi_exec_channel
*dst
,
308 const union tgsi_exec_channel
*src
)
310 #if 0 /* for debugging */
311 assert(src
->f
[0] != 0.0f
);
312 assert(src
->f
[1] != 0.0f
);
313 assert(src
->f
[2] != 0.0f
);
314 assert(src
->f
[3] != 0.0f
);
316 dst
->f
[0] = 1.0f
/ src
->f
[0];
317 dst
->f
[1] = 1.0f
/ src
->f
[1];
318 dst
->f
[2] = 1.0f
/ src
->f
[2];
319 dst
->f
[3] = 1.0f
/ src
->f
[3];
323 micro_rnd(union tgsi_exec_channel
*dst
,
324 const union tgsi_exec_channel
*src
)
326 dst
->f
[0] = floorf(src
->f
[0] + 0.5f
);
327 dst
->f
[1] = floorf(src
->f
[1] + 0.5f
);
328 dst
->f
[2] = floorf(src
->f
[2] + 0.5f
);
329 dst
->f
[3] = floorf(src
->f
[3] + 0.5f
);
333 micro_rsq(union tgsi_exec_channel
*dst
,
334 const union tgsi_exec_channel
*src
)
336 #if 0 /* for debugging */
337 assert(src
->f
[0] != 0.0f
);
338 assert(src
->f
[1] != 0.0f
);
339 assert(src
->f
[2] != 0.0f
);
340 assert(src
->f
[3] != 0.0f
);
342 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
343 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
344 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
345 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
349 micro_sqrt(union tgsi_exec_channel
*dst
,
350 const union tgsi_exec_channel
*src
)
352 dst
->f
[0] = sqrtf(src
->f
[0]);
353 dst
->f
[1] = sqrtf(src
->f
[1]);
354 dst
->f
[2] = sqrtf(src
->f
[2]);
355 dst
->f
[3] = sqrtf(src
->f
[3]);
359 micro_seq(union tgsi_exec_channel
*dst
,
360 const union tgsi_exec_channel
*src0
,
361 const union tgsi_exec_channel
*src1
)
363 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
364 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
365 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
366 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
370 micro_sge(union tgsi_exec_channel
*dst
,
371 const union tgsi_exec_channel
*src0
,
372 const union tgsi_exec_channel
*src1
)
374 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
375 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
376 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
377 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
381 micro_sgn(union tgsi_exec_channel
*dst
,
382 const union tgsi_exec_channel
*src
)
384 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
385 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
386 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
387 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
391 micro_isgn(union tgsi_exec_channel
*dst
,
392 const union tgsi_exec_channel
*src
)
394 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
395 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
396 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
397 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
401 micro_sgt(union tgsi_exec_channel
*dst
,
402 const union tgsi_exec_channel
*src0
,
403 const union tgsi_exec_channel
*src1
)
405 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
406 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
407 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
408 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
412 micro_sin(union tgsi_exec_channel
*dst
,
413 const union tgsi_exec_channel
*src
)
415 dst
->f
[0] = sinf(src
->f
[0]);
416 dst
->f
[1] = sinf(src
->f
[1]);
417 dst
->f
[2] = sinf(src
->f
[2]);
418 dst
->f
[3] = sinf(src
->f
[3]);
422 micro_sle(union tgsi_exec_channel
*dst
,
423 const union tgsi_exec_channel
*src0
,
424 const union tgsi_exec_channel
*src1
)
426 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
427 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
428 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
429 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
433 micro_slt(union tgsi_exec_channel
*dst
,
434 const union tgsi_exec_channel
*src0
,
435 const union tgsi_exec_channel
*src1
)
437 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
438 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
439 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
440 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
444 micro_sne(union tgsi_exec_channel
*dst
,
445 const union tgsi_exec_channel
*src0
,
446 const union tgsi_exec_channel
*src1
)
448 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
449 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
450 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
451 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
455 micro_sfl(union tgsi_exec_channel
*dst
)
464 micro_str(union tgsi_exec_channel
*dst
)
473 micro_trunc(union tgsi_exec_channel
*dst
,
474 const union tgsi_exec_channel
*src
)
476 dst
->f
[0] = (float)(int)src
->f
[0];
477 dst
->f
[1] = (float)(int)src
->f
[1];
478 dst
->f
[2] = (float)(int)src
->f
[2];
479 dst
->f
[3] = (float)(int)src
->f
[3];
483 enum tgsi_exec_datatype
{
484 TGSI_EXEC_DATA_FLOAT
,
490 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
492 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
493 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
494 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
495 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
496 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
497 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
500 /** The execution mask depends on the conditional mask and the loop mask */
501 #define UPDATE_EXEC_MASK(MACH) \
502 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
505 static const union tgsi_exec_channel ZeroVec
=
506 { { 0.0, 0.0, 0.0, 0.0 } };
508 static const union tgsi_exec_channel OneVec
= {
509 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
512 static const union tgsi_exec_channel P128Vec
= {
513 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
516 static const union tgsi_exec_channel M128Vec
= {
517 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
522 * Assert that none of the float values in 'chan' are infinite or NaN.
523 * NaN and Inf may occur normally during program execution and should
524 * not lead to crashes, etc. But when debugging, it's helpful to catch
528 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
530 assert(!util_is_inf_or_nan((chan
)->f
[0]));
531 assert(!util_is_inf_or_nan((chan
)->f
[1]));
532 assert(!util_is_inf_or_nan((chan
)->f
[2]));
533 assert(!util_is_inf_or_nan((chan
)->f
[3]));
539 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
541 debug_printf("%s = {%f, %f, %f, %f}\n",
542 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
549 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
551 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
553 debug_printf("Temp[%u] =\n", index
);
554 for (i
= 0; i
< 4; i
++) {
555 debug_printf(" %c: { %f, %f, %f, %f }\n",
567 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
570 const unsigned *buf_sizes
)
574 for (i
= 0; i
< num_bufs
; i
++) {
575 mach
->Consts
[i
] = bufs
[i
];
576 mach
->ConstsSize
[i
] = buf_sizes
[i
];
582 * Check if there's a potential src/dst register data dependency when
583 * using SOA execution.
586 * This would expand into:
591 * The second instruction will have the wrong value for t0 if executed as-is.
594 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
598 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
599 if (writemask
== TGSI_WRITEMASK_X
||
600 writemask
== TGSI_WRITEMASK_Y
||
601 writemask
== TGSI_WRITEMASK_Z
||
602 writemask
== TGSI_WRITEMASK_W
||
603 writemask
== TGSI_WRITEMASK_NONE
) {
604 /* no chance of data dependency */
608 /* loop over src regs */
609 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
610 if ((inst
->Src
[i
].Register
.File
==
611 inst
->Dst
[0].Register
.File
) &&
612 ((inst
->Src
[i
].Register
.Index
==
613 inst
->Dst
[0].Register
.Index
) ||
614 inst
->Src
[i
].Register
.Indirect
||
615 inst
->Dst
[0].Register
.Indirect
)) {
616 /* loop over dest channels */
617 uint channelsWritten
= 0x0;
618 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
619 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
620 /* check if we're reading a channel that's been written */
621 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
622 if (channelsWritten
& (1 << swizzle
)) {
626 channelsWritten
|= (1 << chan
);
636 * Initialize machine state by expanding tokens to full instructions,
637 * allocating temporary storage, setting up constants, etc.
638 * After this, we can call tgsi_exec_machine_run() many times.
641 tgsi_exec_machine_bind_shader(
642 struct tgsi_exec_machine
*mach
,
643 const struct tgsi_token
*tokens
,
644 struct tgsi_sampler
*sampler
)
647 struct tgsi_parse_context parse
;
648 struct tgsi_full_instruction
*instructions
;
649 struct tgsi_full_declaration
*declarations
;
650 uint maxInstructions
= 10, numInstructions
= 0;
651 uint maxDeclarations
= 10, numDeclarations
= 0;
654 tgsi_dump(tokens
, 0);
660 mach
->Tokens
= tokens
;
661 mach
->Sampler
= sampler
;
664 /* unbind and free all */
665 FREE(mach
->Declarations
);
666 mach
->Declarations
= NULL
;
667 mach
->NumDeclarations
= 0;
669 FREE(mach
->Instructions
);
670 mach
->Instructions
= NULL
;
671 mach
->NumInstructions
= 0;
676 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
677 if (k
!= TGSI_PARSE_OK
) {
678 debug_printf( "Problem parsing!\n" );
682 mach
->Processor
= parse
.FullHeader
.Processor
.Processor
;
684 mach
->NumOutputs
= 0;
686 if (mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
&&
687 !mach
->UsedGeometryShader
) {
688 struct tgsi_exec_vector
*inputs
;
689 struct tgsi_exec_vector
*outputs
;
691 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
692 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
,
698 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
699 TGSI_MAX_TOTAL_VERTICES
, 16);
706 align_free(mach
->Inputs
);
707 align_free(mach
->Outputs
);
709 mach
->Inputs
= inputs
;
710 mach
->Outputs
= outputs
;
711 mach
->UsedGeometryShader
= TRUE
;
714 declarations
= (struct tgsi_full_declaration
*)
715 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
721 instructions
= (struct tgsi_full_instruction
*)
722 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
725 FREE( declarations
);
729 while( !tgsi_parse_end_of_tokens( &parse
) ) {
732 tgsi_parse_token( &parse
);
733 switch( parse
.FullToken
.Token
.Type
) {
734 case TGSI_TOKEN_TYPE_DECLARATION
:
735 /* save expanded declaration */
736 if (numDeclarations
== maxDeclarations
) {
737 declarations
= REALLOC(declarations
,
739 * sizeof(struct tgsi_full_declaration
),
740 (maxDeclarations
+ 10)
741 * sizeof(struct tgsi_full_declaration
));
742 maxDeclarations
+= 10;
744 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
746 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
747 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
752 memcpy(declarations
+ numDeclarations
,
753 &parse
.FullToken
.FullDeclaration
,
754 sizeof(declarations
[0]));
758 case TGSI_TOKEN_TYPE_IMMEDIATE
:
760 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
762 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
764 for( i
= 0; i
< size
; i
++ ) {
765 mach
->Imms
[mach
->ImmLimit
][i
] =
766 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
772 case TGSI_TOKEN_TYPE_INSTRUCTION
:
774 /* save expanded instruction */
775 if (numInstructions
== maxInstructions
) {
776 instructions
= REALLOC(instructions
,
778 * sizeof(struct tgsi_full_instruction
),
779 (maxInstructions
+ 10)
780 * sizeof(struct tgsi_full_instruction
));
781 maxInstructions
+= 10;
784 memcpy(instructions
+ numInstructions
,
785 &parse
.FullToken
.FullInstruction
,
786 sizeof(instructions
[0]));
791 case TGSI_TOKEN_TYPE_PROPERTY
:
798 tgsi_parse_free (&parse
);
800 FREE(mach
->Declarations
);
801 mach
->Declarations
= declarations
;
802 mach
->NumDeclarations
= numDeclarations
;
804 FREE(mach
->Instructions
);
805 mach
->Instructions
= instructions
;
806 mach
->NumInstructions
= numInstructions
;
810 struct tgsi_exec_machine
*
811 tgsi_exec_machine_create( void )
813 struct tgsi_exec_machine
*mach
;
816 mach
= align_malloc( sizeof *mach
, 16 );
820 memset(mach
, 0, sizeof(*mach
));
822 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
823 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
824 mach
->Predicates
= &mach
->Temps
[TGSI_EXEC_TEMP_P0
];
826 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_ATTRIBS
, 16);
827 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_ATTRIBS
, 16);
828 if (!mach
->Inputs
|| !mach
->Outputs
)
831 /* Setup constants needed by the SSE2 executor. */
832 for( i
= 0; i
< 4; i
++ ) {
833 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
834 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
835 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
836 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
837 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
838 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
839 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
840 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
841 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
842 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
846 /* silence warnings */
855 align_free(mach
->Inputs
);
856 align_free(mach
->Outputs
);
864 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
867 FREE(mach
->Instructions
);
868 FREE(mach
->Declarations
);
870 align_free(mach
->Inputs
);
871 align_free(mach
->Outputs
);
878 micro_add(union tgsi_exec_channel
*dst
,
879 const union tgsi_exec_channel
*src0
,
880 const union tgsi_exec_channel
*src1
)
882 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
883 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
884 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
885 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
890 union tgsi_exec_channel
*dst
,
891 const union tgsi_exec_channel
*src0
,
892 const union tgsi_exec_channel
*src1
)
894 if (src1
->f
[0] != 0) {
895 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
897 if (src1
->f
[1] != 0) {
898 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
900 if (src1
->f
[2] != 0) {
901 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
903 if (src1
->f
[3] != 0) {
904 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
909 micro_rcc(union tgsi_exec_channel
*dst
,
910 const union tgsi_exec_channel
*src
)
914 for (i
= 0; i
< 4; i
++) {
915 float recip
= 1.0f
/ src
->f
[i
];
918 if (recip
> 1.884467e+019f
) {
919 dst
->f
[i
] = 1.884467e+019f
;
921 else if (recip
< 5.42101e-020f
) {
922 dst
->f
[i
] = 5.42101e-020f
;
929 if (recip
< -1.884467e+019f
) {
930 dst
->f
[i
] = -1.884467e+019f
;
932 else if (recip
> -5.42101e-020f
) {
933 dst
->f
[i
] = -5.42101e-020f
;
944 union tgsi_exec_channel
*dst
,
945 const union tgsi_exec_channel
*src0
,
946 const union tgsi_exec_channel
*src1
,
947 const union tgsi_exec_channel
*src2
,
948 const union tgsi_exec_channel
*src3
)
950 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
951 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
952 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
953 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
957 micro_max(union tgsi_exec_channel
*dst
,
958 const union tgsi_exec_channel
*src0
,
959 const union tgsi_exec_channel
*src1
)
961 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
962 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
963 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
964 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
968 micro_min(union tgsi_exec_channel
*dst
,
969 const union tgsi_exec_channel
*src0
,
970 const union tgsi_exec_channel
*src1
)
972 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
973 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
974 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
975 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
979 micro_mul(union tgsi_exec_channel
*dst
,
980 const union tgsi_exec_channel
*src0
,
981 const union tgsi_exec_channel
*src1
)
983 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
984 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
985 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
986 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
991 union tgsi_exec_channel
*dst
,
992 const union tgsi_exec_channel
*src
)
994 dst
->f
[0] = -src
->f
[0];
995 dst
->f
[1] = -src
->f
[1];
996 dst
->f
[2] = -src
->f
[2];
997 dst
->f
[3] = -src
->f
[3];
1002 union tgsi_exec_channel
*dst
,
1003 const union tgsi_exec_channel
*src0
,
1004 const union tgsi_exec_channel
*src1
)
1007 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1008 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1009 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1010 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1012 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1013 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1014 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1015 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1020 micro_sub(union tgsi_exec_channel
*dst
,
1021 const union tgsi_exec_channel
*src0
,
1022 const union tgsi_exec_channel
*src1
)
1024 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1025 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1026 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1027 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1031 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1032 const uint chan_index
,
1035 const union tgsi_exec_channel
*index
,
1036 const union tgsi_exec_channel
*index2D
,
1037 union tgsi_exec_channel
*chan
)
1041 assert(swizzle
< 4);
1044 case TGSI_FILE_CONSTANT
:
1045 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1046 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1047 assert(mach
->Consts
[index2D
->i
[i
]]);
1049 if (index
->i
[i
] < 0) {
1052 /* NOTE: copying the const value as a uint instead of float */
1053 const uint constbuf
= index2D
->i
[i
];
1054 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1055 const int pos
= index
->i
[i
] * 4 + swizzle
;
1056 /* const buffer bounds check */
1057 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1059 /* Debug: print warning */
1060 static int count
= 0;
1062 debug_printf("TGSI Exec: const buffer index %d"
1063 " out of bounds\n", pos
);
1068 chan
->u
[i
] = buf
[pos
];
1073 case TGSI_FILE_INPUT
:
1074 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1076 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1077 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1078 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1079 index2D->i[i], index->i[i]);
1081 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1083 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1084 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1088 case TGSI_FILE_SYSTEM_VALUE
:
1089 /* XXX no swizzling at this point. Will be needed if we put
1090 * gl_FragCoord, for example, in a sys value register.
1092 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1093 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].u
[i
];
1097 case TGSI_FILE_TEMPORARY
:
1098 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1099 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1100 assert(index2D
->i
[i
] == 0);
1102 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1106 case TGSI_FILE_IMMEDIATE
:
1107 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1108 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1109 assert(index2D
->i
[i
] == 0);
1111 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1115 case TGSI_FILE_ADDRESS
:
1116 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1117 assert(index
->i
[i
] >= 0);
1118 assert(index2D
->i
[i
] == 0);
1120 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1124 case TGSI_FILE_PREDICATE
:
1125 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1126 assert(index
->i
[i
] >= 0 && index
->i
[i
] < TGSI_EXEC_NUM_PREDS
);
1127 assert(index2D
->i
[i
] == 0);
1129 chan
->u
[i
] = mach
->Predicates
[0].xyzw
[swizzle
].u
[i
];
1133 case TGSI_FILE_OUTPUT
:
1134 /* vertex/fragment output vars can be read too */
1135 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1136 assert(index
->i
[i
] >= 0);
1137 assert(index2D
->i
[i
] == 0);
1139 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1145 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1152 fetch_source(const struct tgsi_exec_machine
*mach
,
1153 union tgsi_exec_channel
*chan
,
1154 const struct tgsi_full_src_register
*reg
,
1155 const uint chan_index
,
1156 enum tgsi_exec_datatype src_datatype
)
1158 union tgsi_exec_channel index
;
1159 union tgsi_exec_channel index2D
;
1162 /* We start with a direct index into a register file.
1166 * file = Register.File
1167 * [1] = Register.Index
1172 index
.i
[3] = reg
->Register
.Index
;
1174 /* There is an extra source register that indirectly subscripts
1175 * a register file. The direct index now becomes an offset
1176 * that is being added to the indirect register.
1180 * ind = Indirect.File
1181 * [2] = Indirect.Index
1182 * .x = Indirect.SwizzleX
1184 if (reg
->Register
.Indirect
) {
1185 union tgsi_exec_channel index2
;
1186 union tgsi_exec_channel indir_index
;
1187 const uint execmask
= mach
->ExecMask
;
1190 /* which address register (always zero now) */
1194 index2
.i
[3] = reg
->Indirect
.Index
;
1195 /* get current value of address register[swizzle] */
1196 swizzle
= reg
->Indirect
.Swizzle
;
1197 fetch_src_file_channel(mach
,
1205 /* add value of address register to the offset */
1206 index
.i
[0] += indir_index
.i
[0];
1207 index
.i
[1] += indir_index
.i
[1];
1208 index
.i
[2] += indir_index
.i
[2];
1209 index
.i
[3] += indir_index
.i
[3];
1211 /* for disabled execution channels, zero-out the index to
1212 * avoid using a potential garbage value.
1214 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1215 if ((execmask
& (1 << i
)) == 0)
1220 /* There is an extra source register that is a second
1221 * subscript to a register file. Effectively it means that
1222 * the register file is actually a 2D array of registers.
1226 * [3] = Dimension.Index
1228 if (reg
->Register
.Dimension
) {
1232 index2D
.i
[3] = reg
->Dimension
.Index
;
1234 /* Again, the second subscript index can be addressed indirectly
1235 * identically to the first one.
1236 * Nothing stops us from indirectly addressing the indirect register,
1237 * but there is no need for that, so we won't exercise it.
1239 * file[ind[4].y+3][1],
1241 * ind = DimIndirect.File
1242 * [4] = DimIndirect.Index
1243 * .y = DimIndirect.SwizzleX
1245 if (reg
->Dimension
.Indirect
) {
1246 union tgsi_exec_channel index2
;
1247 union tgsi_exec_channel indir_index
;
1248 const uint execmask
= mach
->ExecMask
;
1254 index2
.i
[3] = reg
->DimIndirect
.Index
;
1256 swizzle
= reg
->DimIndirect
.Swizzle
;
1257 fetch_src_file_channel(mach
,
1259 reg
->DimIndirect
.File
,
1265 index2D
.i
[0] += indir_index
.i
[0];
1266 index2D
.i
[1] += indir_index
.i
[1];
1267 index2D
.i
[2] += indir_index
.i
[2];
1268 index2D
.i
[3] += indir_index
.i
[3];
1270 /* for disabled execution channels, zero-out the index to
1271 * avoid using a potential garbage value.
1273 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1274 if ((execmask
& (1 << i
)) == 0) {
1280 /* If by any chance there was a need for a 3D array of register
1281 * files, we would have to check whether Dimension is followed
1282 * by a dimension register and continue the saga.
1291 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1292 fetch_src_file_channel(mach
,
1300 if (reg
->Register
.Absolute
) {
1301 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1302 micro_abs(chan
, chan
);
1304 micro_iabs(chan
, chan
);
1308 if (reg
->Register
.Negate
) {
1309 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1310 micro_neg(chan
, chan
);
1312 micro_ineg(chan
, chan
);
1318 store_dest(struct tgsi_exec_machine
*mach
,
1319 const union tgsi_exec_channel
*chan
,
1320 const struct tgsi_full_dst_register
*reg
,
1321 const struct tgsi_full_instruction
*inst
,
1323 enum tgsi_exec_datatype dst_datatype
)
1326 union tgsi_exec_channel null
;
1327 union tgsi_exec_channel
*dst
;
1328 union tgsi_exec_channel index2D
;
1329 uint execmask
= mach
->ExecMask
;
1330 int offset
= 0; /* indirection offset */
1334 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1335 check_inf_or_nan(chan
);
1338 /* There is an extra source register that indirectly subscripts
1339 * a register file. The direct index now becomes an offset
1340 * that is being added to the indirect register.
1344 * ind = Indirect.File
1345 * [2] = Indirect.Index
1346 * .x = Indirect.SwizzleX
1348 if (reg
->Register
.Indirect
) {
1349 union tgsi_exec_channel index
;
1350 union tgsi_exec_channel indir_index
;
1353 /* which address register (always zero for now) */
1357 index
.i
[3] = reg
->Indirect
.Index
;
1359 /* get current value of address register[swizzle] */
1360 swizzle
= reg
->Indirect
.Swizzle
;
1362 /* fetch values from the address/indirection register */
1363 fetch_src_file_channel(mach
,
1371 /* save indirection offset */
1372 offset
= indir_index
.i
[0];
1375 /* There is an extra source register that is a second
1376 * subscript to a register file. Effectively it means that
1377 * the register file is actually a 2D array of registers.
1381 * [3] = Dimension.Index
1383 if (reg
->Register
.Dimension
) {
1387 index2D
.i
[3] = reg
->Dimension
.Index
;
1389 /* Again, the second subscript index can be addressed indirectly
1390 * identically to the first one.
1391 * Nothing stops us from indirectly addressing the indirect register,
1392 * but there is no need for that, so we won't exercise it.
1394 * file[ind[4].y+3][1],
1396 * ind = DimIndirect.File
1397 * [4] = DimIndirect.Index
1398 * .y = DimIndirect.SwizzleX
1400 if (reg
->Dimension
.Indirect
) {
1401 union tgsi_exec_channel index2
;
1402 union tgsi_exec_channel indir_index
;
1403 const uint execmask
= mach
->ExecMask
;
1410 index2
.i
[3] = reg
->DimIndirect
.Index
;
1412 swizzle
= reg
->DimIndirect
.Swizzle
;
1413 fetch_src_file_channel(mach
,
1415 reg
->DimIndirect
.File
,
1421 index2D
.i
[0] += indir_index
.i
[0];
1422 index2D
.i
[1] += indir_index
.i
[1];
1423 index2D
.i
[2] += indir_index
.i
[2];
1424 index2D
.i
[3] += indir_index
.i
[3];
1426 /* for disabled execution channels, zero-out the index to
1427 * avoid using a potential garbage value.
1429 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1430 if ((execmask
& (1 << i
)) == 0) {
1436 /* If by any chance there was a need for a 3D array of register
1437 * files, we would have to check whether Dimension is followed
1438 * by a dimension register and continue the saga.
1447 switch (reg
->Register
.File
) {
1448 case TGSI_FILE_NULL
:
1452 case TGSI_FILE_OUTPUT
:
1453 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1454 + reg
->Register
.Index
;
1455 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1457 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1458 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1459 reg
->Register
.Index
);
1460 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1461 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1462 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1463 if (execmask
& (1 << i
))
1464 debug_printf("%f, ", chan
->f
[i
]);
1465 debug_printf(")\n");
1470 case TGSI_FILE_TEMPORARY
:
1471 index
= reg
->Register
.Index
;
1472 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1473 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1476 case TGSI_FILE_ADDRESS
:
1477 index
= reg
->Register
.Index
;
1478 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1481 case TGSI_FILE_PREDICATE
:
1482 index
= reg
->Register
.Index
;
1483 assert(index
< TGSI_EXEC_NUM_PREDS
);
1484 dst
= &mach
->Predicates
[index
].xyzw
[chan_index
];
1492 if (inst
->Instruction
.Predicate
) {
1494 union tgsi_exec_channel
*pred
;
1496 switch (chan_index
) {
1498 swizzle
= inst
->Predicate
.SwizzleX
;
1501 swizzle
= inst
->Predicate
.SwizzleY
;
1504 swizzle
= inst
->Predicate
.SwizzleZ
;
1507 swizzle
= inst
->Predicate
.SwizzleW
;
1514 assert(inst
->Predicate
.Index
== 0);
1516 pred
= &mach
->Predicates
[inst
->Predicate
.Index
].xyzw
[swizzle
];
1518 if (inst
->Predicate
.Negate
) {
1519 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1521 execmask
&= ~(1 << i
);
1525 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1527 execmask
&= ~(1 << i
);
1533 switch (inst
->Instruction
.Saturate
) {
1535 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1536 if (execmask
& (1 << i
))
1537 dst
->i
[i
] = chan
->i
[i
];
1540 case TGSI_SAT_ZERO_ONE
:
1541 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1542 if (execmask
& (1 << i
)) {
1543 if (chan
->f
[i
] < 0.0f
)
1545 else if (chan
->f
[i
] > 1.0f
)
1548 dst
->i
[i
] = chan
->i
[i
];
1552 case TGSI_SAT_MINUS_PLUS_ONE
:
1553 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1554 if (execmask
& (1 << i
)) {
1555 if (chan
->f
[i
] < -1.0f
)
1557 else if (chan
->f
[i
] > 1.0f
)
1560 dst
->i
[i
] = chan
->i
[i
];
1569 #define FETCH(VAL,INDEX,CHAN)\
1570 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1572 #define IFETCH(VAL,INDEX,CHAN)\
1573 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1577 * Execute ARB-style KIL which is predicated by a src register.
1578 * Kill fragment if any of the four values is less than zero.
1581 exec_kill_if(struct tgsi_exec_machine
*mach
,
1582 const struct tgsi_full_instruction
*inst
)
1586 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1587 union tgsi_exec_channel r
[1];
1589 /* This mask stores component bits that were already tested. */
1592 for (chan_index
= 0; chan_index
< 4; chan_index
++)
1597 /* unswizzle channel */
1598 swizzle
= tgsi_util_get_full_src_register_swizzle (
1602 /* check if the component has not been already tested */
1603 if (uniquemask
& (1 << swizzle
))
1605 uniquemask
|= 1 << swizzle
;
1607 FETCH(&r
[0], 0, chan_index
);
1608 for (i
= 0; i
< 4; i
++)
1609 if (r
[0].f
[i
] < 0.0f
)
1613 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1617 * Unconditional fragment kill/discard.
1620 exec_kill(struct tgsi_exec_machine
*mach
,
1621 const struct tgsi_full_instruction
*inst
)
1623 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1625 /* kill fragment for all fragments currently executing */
1626 kilmask
= mach
->ExecMask
;
1627 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1631 emit_vertex(struct tgsi_exec_machine
*mach
)
1633 /* FIXME: check for exec mask correctly
1635 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1636 if ((mach->ExecMask & (1 << i)))
1638 if (mach
->ExecMask
) {
1639 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
1640 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
1645 emit_primitive(struct tgsi_exec_machine
*mach
)
1647 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
1648 /* FIXME: check for exec mask correctly
1650 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1651 if ((mach->ExecMask & (1 << i)))
1653 if (mach
->ExecMask
) {
1655 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
1656 mach
->Primitives
[*prim_count
] = 0;
1661 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
1663 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1665 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
1666 if (emitted_verts
) {
1667 emit_primitive(mach
);
1674 * Fetch four texture samples using STR texture coordinates.
1677 fetch_texel( struct tgsi_sampler
*sampler
,
1678 const unsigned sview_idx
,
1679 const unsigned sampler_idx
,
1680 const union tgsi_exec_channel
*s
,
1681 const union tgsi_exec_channel
*t
,
1682 const union tgsi_exec_channel
*p
,
1683 const union tgsi_exec_channel
*c0
,
1684 const union tgsi_exec_channel
*c1
,
1685 float derivs
[3][2][TGSI_QUAD_SIZE
],
1686 const int8_t offset
[3],
1687 enum tgsi_sampler_control control
,
1688 union tgsi_exec_channel
*r
,
1689 union tgsi_exec_channel
*g
,
1690 union tgsi_exec_channel
*b
,
1691 union tgsi_exec_channel
*a
)
1694 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
1696 /* FIXME: handle explicit derivs, offsets */
1697 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
1698 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
1700 for (j
= 0; j
< 4; j
++) {
1701 r
->f
[j
] = rgba
[0][j
];
1702 g
->f
[j
] = rgba
[1][j
];
1703 b
->f
[j
] = rgba
[2][j
];
1704 a
->f
[j
] = rgba
[3][j
];
1709 #define TEX_MODIFIER_NONE 0
1710 #define TEX_MODIFIER_PROJECTED 1
1711 #define TEX_MODIFIER_LOD_BIAS 2
1712 #define TEX_MODIFIER_EXPLICIT_LOD 3
1713 #define TEX_MODIFIER_LEVEL_ZERO 4
1717 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1720 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
1721 const struct tgsi_full_instruction
*inst
,
1724 if (inst
->Texture
.NumOffsets
== 1) {
1725 union tgsi_exec_channel index
;
1726 union tgsi_exec_channel offset
[3];
1727 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
1728 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1729 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
1730 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1731 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
1732 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1733 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
1734 offsets
[0] = offset
[0].i
[0];
1735 offsets
[1] = offset
[1].i
[0];
1736 offsets
[2] = offset
[2].i
[0];
1738 assert(inst
->Texture
.NumOffsets
== 0);
1739 offsets
[0] = offsets
[1] = offsets
[2] = 0;
1745 * Fetch dx and dy values for one channel (s, t or r).
1746 * Put dx values into one float array, dy values into another.
1749 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
1750 const struct tgsi_full_instruction
*inst
,
1753 float derivs
[2][TGSI_QUAD_SIZE
])
1755 union tgsi_exec_channel d
;
1756 FETCH(&d
, regdsrcx
, chan
);
1757 derivs
[0][0] = d
.f
[0];
1758 derivs
[0][1] = d
.f
[1];
1759 derivs
[0][2] = d
.f
[2];
1760 derivs
[0][3] = d
.f
[3];
1761 FETCH(&d
, regdsrcx
+ 1, chan
);
1762 derivs
[1][0] = d
.f
[0];
1763 derivs
[1][1] = d
.f
[1];
1764 derivs
[1][2] = d
.f
[2];
1765 derivs
[1][3] = d
.f
[3];
1770 * execute a texture instruction.
1772 * modifier is used to control the channel routing for the\
1773 * instruction variants like proj, lod, and texture with lod bias.
1774 * sampler indicates which src register the sampler is contained in.
1777 exec_tex(struct tgsi_exec_machine
*mach
,
1778 const struct tgsi_full_instruction
*inst
,
1779 uint modifier
, uint sampler
)
1781 const uint unit
= inst
->Src
[sampler
].Register
.Index
;
1782 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
1783 union tgsi_exec_channel r
[5];
1784 enum tgsi_sampler_control control
= tgsi_sampler_lod_none
;
1787 int dim
, shadow_ref
, i
;
1789 /* always fetch all 3 offsets, overkill but keeps code simple */
1790 fetch_texel_offsets(mach
, inst
, offsets
);
1792 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
1793 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
1795 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
, &shadow_ref
);
1798 if (shadow_ref
>= 0)
1799 assert(shadow_ref
>= dim
&& shadow_ref
< Elements(args
));
1801 /* fetch modifier to the last argument */
1802 if (modifier
!= TEX_MODIFIER_NONE
) {
1803 const int last
= Elements(args
) - 1;
1805 /* fetch modifier from src0.w or src1.x */
1807 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
1808 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
1811 assert(shadow_ref
!= 4);
1812 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
1815 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
1816 args
[last
] = &r
[last
];
1820 args
[last
] = &ZeroVec
;
1823 /* point unused arguments to zero vector */
1824 for (i
= dim
; i
< last
; i
++)
1827 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
1828 control
= tgsi_sampler_lod_explicit
;
1829 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
1830 control
= tgsi_sampler_lod_bias
;
1833 for (i
= dim
; i
< Elements(args
); i
++)
1837 /* fetch coordinates */
1838 for (i
= 0; i
< dim
; i
++) {
1839 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
1842 micro_div(&r
[i
], &r
[i
], proj
);
1847 /* fetch reference value */
1848 if (shadow_ref
>= 0) {
1849 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
1852 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
1854 args
[shadow_ref
] = &r
[shadow_ref
];
1857 fetch_texel(mach
->Sampler
, unit
, unit
,
1858 args
[0], args
[1], args
[2], args
[3], args
[4],
1859 NULL
, offsets
, control
,
1860 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1863 debug_printf("fetch r: %g %g %g %g\n",
1864 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
1865 debug_printf("fetch g: %g %g %g %g\n",
1866 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
1867 debug_printf("fetch b: %g %g %g %g\n",
1868 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
1869 debug_printf("fetch a: %g %g %g %g\n",
1870 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
1873 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1874 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1875 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
1882 exec_txd(struct tgsi_exec_machine
*mach
,
1883 const struct tgsi_full_instruction
*inst
)
1885 const uint unit
= inst
->Src
[3].Register
.Index
;
1886 union tgsi_exec_channel r
[4];
1887 float derivs
[3][2][TGSI_QUAD_SIZE
];
1891 /* always fetch all 3 offsets, overkill but keeps code simple */
1892 fetch_texel_offsets(mach
, inst
, offsets
);
1894 switch (inst
->Texture
.Texture
) {
1895 case TGSI_TEXTURE_1D
:
1896 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1898 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1900 fetch_texel(mach
->Sampler
, unit
, unit
,
1901 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
1902 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1903 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1906 case TGSI_TEXTURE_SHADOW1D
:
1907 case TGSI_TEXTURE_1D_ARRAY
:
1908 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1909 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
1910 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1911 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1912 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1914 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1916 fetch_texel(mach
->Sampler
, unit
, unit
,
1917 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
1918 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1919 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1922 case TGSI_TEXTURE_2D
:
1923 case TGSI_TEXTURE_RECT
:
1924 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1925 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1927 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1928 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
1930 fetch_texel(mach
->Sampler
, unit
, unit
,
1931 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
1932 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1933 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1937 case TGSI_TEXTURE_SHADOW2D
:
1938 case TGSI_TEXTURE_SHADOWRECT
:
1939 case TGSI_TEXTURE_2D_ARRAY
:
1940 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1941 /* only SHADOW2D_ARRAY actually needs W */
1942 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1943 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1944 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1945 FETCH(&r
[3], 0, TGSI_CHAN_W
);
1947 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1948 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
1950 fetch_texel(mach
->Sampler
, unit
, unit
,
1951 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
1952 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1953 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1956 case TGSI_TEXTURE_3D
:
1957 case TGSI_TEXTURE_CUBE
:
1958 case TGSI_TEXTURE_CUBE_ARRAY
:
1959 /* only TEXTURE_CUBE_ARRAY actually needs W */
1960 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1961 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1962 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1963 FETCH(&r
[3], 0, TGSI_CHAN_W
);
1965 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1966 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
1967 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
1969 fetch_texel(mach
->Sampler
, unit
, unit
,
1970 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
1971 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1972 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1979 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1980 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1981 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
1988 exec_txf(struct tgsi_exec_machine
*mach
,
1989 const struct tgsi_full_instruction
*inst
)
1991 const uint unit
= inst
->Src
[1].Register
.Index
;
1992 union tgsi_exec_channel r
[4];
1994 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
1999 /* always fetch all 3 offsets, overkill but keeps code simple */
2000 fetch_texel_offsets(mach
, inst
, offsets
);
2002 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2004 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
) {
2005 target
= mach
->SamplerViews
[unit
].Resource
;
2008 target
= inst
->Texture
.Texture
;
2011 case TGSI_TEXTURE_3D
:
2012 case TGSI_TEXTURE_2D_ARRAY
:
2013 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2014 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2016 case TGSI_TEXTURE_2D
:
2017 case TGSI_TEXTURE_RECT
:
2018 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2019 case TGSI_TEXTURE_SHADOW2D
:
2020 case TGSI_TEXTURE_SHADOWRECT
:
2021 case TGSI_TEXTURE_1D_ARRAY
:
2022 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2024 case TGSI_TEXTURE_BUFFER
:
2025 case TGSI_TEXTURE_1D
:
2026 case TGSI_TEXTURE_SHADOW1D
:
2027 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2034 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2037 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2038 r
[0].f
[j
] = rgba
[0][j
];
2039 r
[1].f
[j
] = rgba
[1][j
];
2040 r
[2].f
[j
] = rgba
[2][j
];
2041 r
[3].f
[j
] = rgba
[3][j
];
2044 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
) {
2045 unsigned char swizzles
[4];
2046 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2047 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2048 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2049 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2051 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2052 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2053 store_dest(mach
, &r
[swizzles
[chan
]],
2054 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2059 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2060 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2061 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2068 exec_txq(struct tgsi_exec_machine
*mach
,
2069 const struct tgsi_full_instruction
*inst
)
2071 const uint unit
= inst
->Src
[1].Register
.Index
;
2073 union tgsi_exec_channel r
[4], src
;
2077 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2079 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2081 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2082 for (j
= 0; j
< 4; j
++) {
2083 r
[j
].i
[i
] = result
[j
];
2087 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2088 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2089 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2090 TGSI_EXEC_DATA_INT
);
2096 exec_sample(struct tgsi_exec_machine
*mach
,
2097 const struct tgsi_full_instruction
*inst
,
2098 uint modifier
, boolean compare
)
2100 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2101 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2102 union tgsi_exec_channel r
[4], c1
;
2103 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2104 enum tgsi_sampler_control control
= tgsi_sampler_lod_none
;
2106 unsigned char swizzles
[4];
2109 /* always fetch all 3 offsets, overkill but keeps code simple */
2110 fetch_texel_offsets(mach
, inst
, offsets
);
2112 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2114 if (modifier
!= TEX_MODIFIER_NONE
) {
2115 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2116 FETCH(&c1
, 3, TGSI_CHAN_X
);
2118 control
= tgsi_sampler_lod_bias
;
2120 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2121 FETCH(&c1
, 3, TGSI_CHAN_X
);
2123 control
= tgsi_sampler_lod_explicit
;
2126 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2127 control
= tgsi_sampler_lod_zero
;
2131 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2133 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2134 case TGSI_TEXTURE_1D
:
2136 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2137 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2138 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2139 NULL
, offsets
, control
,
2140 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2143 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2144 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2145 NULL
, offsets
, control
,
2146 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2150 case TGSI_TEXTURE_1D_ARRAY
:
2151 case TGSI_TEXTURE_2D
:
2152 case TGSI_TEXTURE_RECT
:
2153 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2155 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2156 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2157 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2158 NULL
, offsets
, control
,
2159 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2162 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2163 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2164 NULL
, offsets
, control
,
2165 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2169 case TGSI_TEXTURE_2D_ARRAY
:
2170 case TGSI_TEXTURE_3D
:
2171 case TGSI_TEXTURE_CUBE
:
2172 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2173 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2175 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2176 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2177 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2178 NULL
, offsets
, control
,
2179 &r
[0], &r
[1], &r
[2], &r
[3]);
2182 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2183 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2184 NULL
, offsets
, control
,
2185 &r
[0], &r
[1], &r
[2], &r
[3]);
2189 case TGSI_TEXTURE_CUBE_ARRAY
:
2190 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2191 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2192 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2194 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2195 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2196 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2197 NULL
, offsets
, control
,
2198 &r
[0], &r
[1], &r
[2], &r
[3]);
2201 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2202 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2203 NULL
, offsets
, control
,
2204 &r
[0], &r
[1], &r
[2], &r
[3]);
2213 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2214 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2215 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2216 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2218 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2219 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2220 store_dest(mach
, &r
[swizzles
[chan
]],
2221 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2227 exec_sample_d(struct tgsi_exec_machine
*mach
,
2228 const struct tgsi_full_instruction
*inst
)
2230 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2231 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2232 union tgsi_exec_channel r
[4];
2233 float derivs
[3][2][TGSI_QUAD_SIZE
];
2235 unsigned char swizzles
[4];
2238 /* always fetch all 3 offsets, overkill but keeps code simple */
2239 fetch_texel_offsets(mach
, inst
, offsets
);
2241 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2243 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2244 case TGSI_TEXTURE_1D
:
2245 case TGSI_TEXTURE_1D_ARRAY
:
2246 /* only 1D array actually needs Y */
2247 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2249 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2251 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2252 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2253 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
2254 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2257 case TGSI_TEXTURE_2D
:
2258 case TGSI_TEXTURE_RECT
:
2259 case TGSI_TEXTURE_2D_ARRAY
:
2260 /* only 2D array actually needs Z */
2261 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2262 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2264 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2265 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2267 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2268 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2269 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
2270 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2273 case TGSI_TEXTURE_3D
:
2274 case TGSI_TEXTURE_CUBE
:
2275 case TGSI_TEXTURE_CUBE_ARRAY
:
2276 /* only cube array actually needs W */
2277 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2278 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2279 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2281 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2282 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2283 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2285 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2286 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2287 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
2288 &r
[0], &r
[1], &r
[2], &r
[3]);
2295 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2296 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2297 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2298 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2300 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2301 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2302 store_dest(mach
, &r
[swizzles
[chan
]],
2303 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2310 * Evaluate a constant-valued coefficient at the position of the
2315 struct tgsi_exec_machine
*mach
,
2321 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2322 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2327 * Evaluate a linear-valued coefficient at the position of the
2332 struct tgsi_exec_machine
*mach
,
2336 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2337 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2338 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2339 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2340 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2341 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2342 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2343 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2344 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2348 * Evaluate a perspective-valued coefficient at the position of the
2352 eval_perspective_coef(
2353 struct tgsi_exec_machine
*mach
,
2357 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2358 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2359 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2360 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2361 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2362 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2363 /* divide by W here */
2364 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2365 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2366 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2367 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2371 typedef void (* eval_coef_func
)(
2372 struct tgsi_exec_machine
*mach
,
2377 exec_declaration(struct tgsi_exec_machine
*mach
,
2378 const struct tgsi_full_declaration
*decl
)
2380 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2381 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2385 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
2386 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2387 uint first
, last
, mask
;
2389 first
= decl
->Range
.First
;
2390 last
= decl
->Range
.Last
;
2391 mask
= decl
->Declaration
.UsageMask
;
2393 /* XXX we could remove this special-case code since
2394 * mach->InterpCoefs[first].a0 should already have the
2395 * front/back-face value. But we should first update the
2396 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2397 * Then, we could remove the tgsi_exec_machine::Face field.
2399 /* XXX make FACE a system value */
2400 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2403 assert(decl
->Semantic
.Index
== 0);
2404 assert(first
== last
);
2406 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2407 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2410 eval_coef_func eval
;
2413 switch (decl
->Interp
.Interpolate
) {
2414 case TGSI_INTERPOLATE_CONSTANT
:
2415 eval
= eval_constant_coef
;
2418 case TGSI_INTERPOLATE_LINEAR
:
2419 eval
= eval_linear_coef
;
2422 case TGSI_INTERPOLATE_PERSPECTIVE
:
2423 eval
= eval_perspective_coef
;
2426 case TGSI_INTERPOLATE_COLOR
:
2427 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
2435 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2436 if (mask
& (1 << j
)) {
2437 for (i
= first
; i
<= last
; i
++) {
2444 if (DEBUG_EXECUTION
) {
2446 for (i
= first
; i
<= last
; ++i
) {
2447 debug_printf("IN[%2u] = ", i
);
2448 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2452 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2453 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
2454 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
2455 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
2456 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
2463 if (decl
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
2464 mach
->SysSemanticToIndex
[decl
->Declaration
.Semantic
] = decl
->Range
.First
;
2469 typedef void (* micro_op
)(union tgsi_exec_channel
*dst
);
2472 exec_vector(struct tgsi_exec_machine
*mach
,
2473 const struct tgsi_full_instruction
*inst
,
2475 enum tgsi_exec_datatype dst_datatype
)
2479 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2480 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2481 union tgsi_exec_channel dst
;
2484 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2489 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
2490 const union tgsi_exec_channel
*src
);
2493 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
2494 const struct tgsi_full_instruction
*inst
,
2496 enum tgsi_exec_datatype dst_datatype
,
2497 enum tgsi_exec_datatype src_datatype
)
2500 union tgsi_exec_channel src
;
2501 union tgsi_exec_channel dst
;
2503 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2505 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2506 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2507 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2513 exec_vector_unary(struct tgsi_exec_machine
*mach
,
2514 const struct tgsi_full_instruction
*inst
,
2516 enum tgsi_exec_datatype dst_datatype
,
2517 enum tgsi_exec_datatype src_datatype
)
2520 struct tgsi_exec_vector dst
;
2522 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2523 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2524 union tgsi_exec_channel src
;
2526 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
2527 op(&dst
.xyzw
[chan
], &src
);
2530 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2531 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2532 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2537 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
2538 const union tgsi_exec_channel
*src0
,
2539 const union tgsi_exec_channel
*src1
);
2542 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
2543 const struct tgsi_full_instruction
*inst
,
2545 enum tgsi_exec_datatype dst_datatype
,
2546 enum tgsi_exec_datatype src_datatype
)
2549 union tgsi_exec_channel src
[2];
2550 union tgsi_exec_channel dst
;
2552 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2553 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
2554 op(&dst
, &src
[0], &src
[1]);
2555 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2556 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2557 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2563 exec_vector_binary(struct tgsi_exec_machine
*mach
,
2564 const struct tgsi_full_instruction
*inst
,
2566 enum tgsi_exec_datatype dst_datatype
,
2567 enum tgsi_exec_datatype src_datatype
)
2570 struct tgsi_exec_vector dst
;
2572 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2573 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2574 union tgsi_exec_channel src
[2];
2576 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2577 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2578 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
2581 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2582 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2583 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2588 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
2589 const union tgsi_exec_channel
*src0
,
2590 const union tgsi_exec_channel
*src1
,
2591 const union tgsi_exec_channel
*src2
);
2594 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
2595 const struct tgsi_full_instruction
*inst
,
2596 micro_trinary_op op
,
2597 enum tgsi_exec_datatype dst_datatype
,
2598 enum tgsi_exec_datatype src_datatype
)
2601 struct tgsi_exec_vector dst
;
2603 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2604 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2605 union tgsi_exec_channel src
[3];
2607 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2608 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2609 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2610 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
2613 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2614 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2615 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2621 exec_dp3(struct tgsi_exec_machine
*mach
,
2622 const struct tgsi_full_instruction
*inst
)
2625 union tgsi_exec_channel arg
[3];
2627 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2628 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2629 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2631 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
2632 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2633 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2634 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2637 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2638 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2639 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2645 exec_dp4(struct tgsi_exec_machine
*mach
,
2646 const struct tgsi_full_instruction
*inst
)
2649 union tgsi_exec_channel arg
[3];
2651 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2652 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2653 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2655 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
2656 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2657 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2658 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2661 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2662 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2663 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2669 exec_dp2a(struct tgsi_exec_machine
*mach
,
2670 const struct tgsi_full_instruction
*inst
)
2673 union tgsi_exec_channel arg
[3];
2675 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2676 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2677 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2679 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2680 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2681 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
2683 fetch_source(mach
, &arg
[1], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2684 micro_add(&arg
[0], &arg
[0], &arg
[1]);
2686 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2687 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2688 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2694 exec_dph(struct tgsi_exec_machine
*mach
,
2695 const struct tgsi_full_instruction
*inst
)
2698 union tgsi_exec_channel arg
[3];
2700 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2701 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2702 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2704 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2705 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2706 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2708 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2709 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2710 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
2712 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2713 micro_add(&arg
[0], &arg
[0], &arg
[1]);
2715 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2716 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2717 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2723 exec_dp2(struct tgsi_exec_machine
*mach
,
2724 const struct tgsi_full_instruction
*inst
)
2727 union tgsi_exec_channel arg
[3];
2729 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2730 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2731 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2733 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2734 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2735 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2737 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2738 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2739 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2745 exec_nrm4(struct tgsi_exec_machine
*mach
,
2746 const struct tgsi_full_instruction
*inst
)
2749 union tgsi_exec_channel arg
[4];
2750 union tgsi_exec_channel scale
;
2752 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2753 micro_mul(&scale
, &arg
[0], &arg
[0]);
2755 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
2756 union tgsi_exec_channel product
;
2758 fetch_source(mach
, &arg
[chan
], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2759 micro_mul(&product
, &arg
[chan
], &arg
[chan
]);
2760 micro_add(&scale
, &scale
, &product
);
2763 micro_rsq(&scale
, &scale
);
2765 for (chan
= TGSI_CHAN_X
; chan
<= TGSI_CHAN_W
; chan
++) {
2766 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2767 micro_mul(&arg
[chan
], &arg
[chan
], &scale
);
2768 store_dest(mach
, &arg
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2774 exec_nrm3(struct tgsi_exec_machine
*mach
,
2775 const struct tgsi_full_instruction
*inst
)
2777 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
2779 union tgsi_exec_channel arg
[3];
2780 union tgsi_exec_channel scale
;
2782 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2783 micro_mul(&scale
, &arg
[0], &arg
[0]);
2785 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
2786 union tgsi_exec_channel product
;
2788 fetch_source(mach
, &arg
[chan
], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2789 micro_mul(&product
, &arg
[chan
], &arg
[chan
]);
2790 micro_add(&scale
, &scale
, &product
);
2793 micro_rsq(&scale
, &scale
);
2795 for (chan
= TGSI_CHAN_X
; chan
<= TGSI_CHAN_Z
; chan
++) {
2796 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2797 micro_mul(&arg
[chan
], &arg
[chan
], &scale
);
2798 store_dest(mach
, &arg
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2803 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2804 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2809 exec_scs(struct tgsi_exec_machine
*mach
,
2810 const struct tgsi_full_instruction
*inst
)
2812 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
2813 union tgsi_exec_channel arg
;
2814 union tgsi_exec_channel result
;
2816 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2818 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2819 micro_cos(&result
, &arg
);
2820 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2822 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2823 micro_sin(&result
, &arg
);
2824 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2827 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2828 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2830 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2831 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2836 exec_x2d(struct tgsi_exec_machine
*mach
,
2837 const struct tgsi_full_instruction
*inst
)
2839 union tgsi_exec_channel r
[4];
2840 union tgsi_exec_channel d
[2];
2842 fetch_source(mach
, &r
[0], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2843 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2844 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XZ
) {
2845 fetch_source(mach
, &r
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2846 micro_mul(&r
[2], &r
[2], &r
[0]);
2847 fetch_source(mach
, &r
[3], &inst
->Src
[2], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2848 micro_mul(&r
[3], &r
[3], &r
[1]);
2849 micro_add(&r
[2], &r
[2], &r
[3]);
2850 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2851 micro_add(&d
[0], &r
[2], &r
[3]);
2853 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YW
) {
2854 fetch_source(mach
, &r
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2855 micro_mul(&r
[2], &r
[2], &r
[0]);
2856 fetch_source(mach
, &r
[3], &inst
->Src
[2], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2857 micro_mul(&r
[3], &r
[3], &r
[1]);
2858 micro_add(&r
[2], &r
[2], &r
[3]);
2859 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2860 micro_add(&d
[1], &r
[2], &r
[3]);
2862 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2863 store_dest(mach
, &d
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2865 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2866 store_dest(mach
, &d
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2868 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2869 store_dest(mach
, &d
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2871 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2872 store_dest(mach
, &d
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2877 exec_rfl(struct tgsi_exec_machine
*mach
,
2878 const struct tgsi_full_instruction
*inst
)
2880 union tgsi_exec_channel r
[9];
2882 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
2883 /* r0 = dp3(src0, src0) */
2884 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2885 micro_mul(&r
[0], &r
[2], &r
[2]);
2886 fetch_source(mach
, &r
[4], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2887 micro_mul(&r
[8], &r
[4], &r
[4]);
2888 micro_add(&r
[0], &r
[0], &r
[8]);
2889 fetch_source(mach
, &r
[6], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2890 micro_mul(&r
[8], &r
[6], &r
[6]);
2891 micro_add(&r
[0], &r
[0], &r
[8]);
2893 /* r1 = dp3(src0, src1) */
2894 fetch_source(mach
, &r
[3], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2895 micro_mul(&r
[1], &r
[2], &r
[3]);
2896 fetch_source(mach
, &r
[5], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2897 micro_mul(&r
[8], &r
[4], &r
[5]);
2898 micro_add(&r
[1], &r
[1], &r
[8]);
2899 fetch_source(mach
, &r
[7], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2900 micro_mul(&r
[8], &r
[6], &r
[7]);
2901 micro_add(&r
[1], &r
[1], &r
[8]);
2903 /* r1 = 2 * r1 / r0 */
2904 micro_add(&r
[1], &r
[1], &r
[1]);
2905 micro_div(&r
[1], &r
[1], &r
[0]);
2907 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2908 micro_mul(&r
[2], &r
[2], &r
[1]);
2909 micro_sub(&r
[2], &r
[2], &r
[3]);
2910 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2912 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2913 micro_mul(&r
[4], &r
[4], &r
[1]);
2914 micro_sub(&r
[4], &r
[4], &r
[5]);
2915 store_dest(mach
, &r
[4], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2917 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2918 micro_mul(&r
[6], &r
[6], &r
[1]);
2919 micro_sub(&r
[6], &r
[6], &r
[7]);
2920 store_dest(mach
, &r
[6], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2923 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2924 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2929 exec_xpd(struct tgsi_exec_machine
*mach
,
2930 const struct tgsi_full_instruction
*inst
)
2932 union tgsi_exec_channel r
[6];
2933 union tgsi_exec_channel d
[3];
2935 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2936 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2938 micro_mul(&r
[2], &r
[0], &r
[1]);
2940 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2941 fetch_source(mach
, &r
[4], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2943 micro_mul(&r
[5], &r
[3], &r
[4] );
2944 micro_sub(&d
[TGSI_CHAN_X
], &r
[2], &r
[5]);
2946 fetch_source(mach
, &r
[2], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2948 micro_mul(&r
[3], &r
[3], &r
[2]);
2950 fetch_source(mach
, &r
[5], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2952 micro_mul(&r
[1], &r
[1], &r
[5]);
2953 micro_sub(&d
[TGSI_CHAN_Y
], &r
[3], &r
[1]);
2955 micro_mul(&r
[5], &r
[5], &r
[4]);
2956 micro_mul(&r
[0], &r
[0], &r
[2]);
2957 micro_sub(&d
[TGSI_CHAN_Z
], &r
[5], &r
[0]);
2959 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2960 store_dest(mach
, &d
[TGSI_CHAN_X
], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2962 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2963 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2965 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2966 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2968 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2969 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2974 exec_dst(struct tgsi_exec_machine
*mach
,
2975 const struct tgsi_full_instruction
*inst
)
2977 union tgsi_exec_channel r
[2];
2978 union tgsi_exec_channel d
[4];
2980 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2981 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2982 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2983 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
2985 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2986 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2988 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2989 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2992 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2993 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2995 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2996 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2998 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2999 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3001 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3002 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3007 exec_log(struct tgsi_exec_machine
*mach
,
3008 const struct tgsi_full_instruction
*inst
)
3010 union tgsi_exec_channel r
[3];
3012 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3013 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3014 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3015 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3016 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3017 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3019 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3020 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3021 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3022 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3024 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3025 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3027 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3028 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3033 exec_exp(struct tgsi_exec_machine
*mach
,
3034 const struct tgsi_full_instruction
*inst
)
3036 union tgsi_exec_channel r
[3];
3038 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3039 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3040 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3041 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3042 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3044 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3045 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3046 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3048 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3049 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3050 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3052 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3053 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3058 exec_lit(struct tgsi_exec_machine
*mach
,
3059 const struct tgsi_full_instruction
*inst
)
3061 union tgsi_exec_channel r
[3];
3062 union tgsi_exec_channel d
[3];
3064 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3065 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3066 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3067 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3068 micro_max(&r
[1], &r
[1], &ZeroVec
);
3070 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3071 micro_min(&r
[2], &r
[2], &P128Vec
);
3072 micro_max(&r
[2], &r
[2], &M128Vec
);
3073 micro_pow(&r
[1], &r
[1], &r
[2]);
3074 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3075 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3077 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3078 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3079 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3082 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3083 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3086 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3087 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3092 exec_break(struct tgsi_exec_machine
*mach
)
3094 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3095 /* turn off loop channels for each enabled exec channel */
3096 mach
->LoopMask
&= ~mach
->ExecMask
;
3097 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3098 UPDATE_EXEC_MASK(mach
);
3100 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3102 mach
->Switch
.mask
= 0x0;
3104 UPDATE_EXEC_MASK(mach
);
3109 exec_switch(struct tgsi_exec_machine
*mach
,
3110 const struct tgsi_full_instruction
*inst
)
3112 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3113 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3115 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3116 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3117 mach
->Switch
.mask
= 0x0;
3118 mach
->Switch
.defaultMask
= 0x0;
3120 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3121 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3123 UPDATE_EXEC_MASK(mach
);
3127 exec_case(struct tgsi_exec_machine
*mach
,
3128 const struct tgsi_full_instruction
*inst
)
3130 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3131 union tgsi_exec_channel src
;
3134 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3136 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3139 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3142 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3145 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3149 mach
->Switch
.defaultMask
|= mask
;
3151 mach
->Switch
.mask
|= mask
& prevMask
;
3153 UPDATE_EXEC_MASK(mach
);
3156 /* FIXME: this will only work if default is last */
3158 exec_default(struct tgsi_exec_machine
*mach
)
3160 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3162 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3164 UPDATE_EXEC_MASK(mach
);
3168 exec_endswitch(struct tgsi_exec_machine
*mach
)
3170 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3171 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3173 UPDATE_EXEC_MASK(mach
);
3177 micro_i2f(union tgsi_exec_channel
*dst
,
3178 const union tgsi_exec_channel
*src
)
3180 dst
->f
[0] = (float)src
->i
[0];
3181 dst
->f
[1] = (float)src
->i
[1];
3182 dst
->f
[2] = (float)src
->i
[2];
3183 dst
->f
[3] = (float)src
->i
[3];
3187 micro_not(union tgsi_exec_channel
*dst
,
3188 const union tgsi_exec_channel
*src
)
3190 dst
->u
[0] = ~src
->u
[0];
3191 dst
->u
[1] = ~src
->u
[1];
3192 dst
->u
[2] = ~src
->u
[2];
3193 dst
->u
[3] = ~src
->u
[3];
3197 micro_shl(union tgsi_exec_channel
*dst
,
3198 const union tgsi_exec_channel
*src0
,
3199 const union tgsi_exec_channel
*src1
)
3201 unsigned masked_count
;
3202 masked_count
= src1
->u
[0] & 0x1f;
3203 dst
->u
[0] = src0
->u
[0] << masked_count
;
3204 masked_count
= src1
->u
[1] & 0x1f;
3205 dst
->u
[1] = src0
->u
[1] << masked_count
;
3206 masked_count
= src1
->u
[2] & 0x1f;
3207 dst
->u
[2] = src0
->u
[2] << masked_count
;
3208 masked_count
= src1
->u
[3] & 0x1f;
3209 dst
->u
[3] = src0
->u
[3] << masked_count
;
3213 micro_and(union tgsi_exec_channel
*dst
,
3214 const union tgsi_exec_channel
*src0
,
3215 const union tgsi_exec_channel
*src1
)
3217 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
3218 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
3219 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
3220 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
3224 micro_or(union tgsi_exec_channel
*dst
,
3225 const union tgsi_exec_channel
*src0
,
3226 const union tgsi_exec_channel
*src1
)
3228 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
3229 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
3230 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
3231 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
3235 micro_xor(union tgsi_exec_channel
*dst
,
3236 const union tgsi_exec_channel
*src0
,
3237 const union tgsi_exec_channel
*src1
)
3239 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
3240 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
3241 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
3242 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
3246 micro_mod(union tgsi_exec_channel
*dst
,
3247 const union tgsi_exec_channel
*src0
,
3248 const union tgsi_exec_channel
*src1
)
3250 dst
->i
[0] = src0
->i
[0] % src1
->i
[0];
3251 dst
->i
[1] = src0
->i
[1] % src1
->i
[1];
3252 dst
->i
[2] = src0
->i
[2] % src1
->i
[2];
3253 dst
->i
[3] = src0
->i
[3] % src1
->i
[3];
3257 micro_f2i(union tgsi_exec_channel
*dst
,
3258 const union tgsi_exec_channel
*src
)
3260 dst
->i
[0] = (int)src
->f
[0];
3261 dst
->i
[1] = (int)src
->f
[1];
3262 dst
->i
[2] = (int)src
->f
[2];
3263 dst
->i
[3] = (int)src
->f
[3];
3267 micro_idiv(union tgsi_exec_channel
*dst
,
3268 const union tgsi_exec_channel
*src0
,
3269 const union tgsi_exec_channel
*src1
)
3271 dst
->i
[0] = src0
->i
[0] / src1
->i
[0];
3272 dst
->i
[1] = src0
->i
[1] / src1
->i
[1];
3273 dst
->i
[2] = src0
->i
[2] / src1
->i
[2];
3274 dst
->i
[3] = src0
->i
[3] / src1
->i
[3];
3278 micro_imax(union tgsi_exec_channel
*dst
,
3279 const union tgsi_exec_channel
*src0
,
3280 const union tgsi_exec_channel
*src1
)
3282 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
3283 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
3284 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
3285 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
3289 micro_imin(union tgsi_exec_channel
*dst
,
3290 const union tgsi_exec_channel
*src0
,
3291 const union tgsi_exec_channel
*src1
)
3293 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
3294 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
3295 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
3296 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
3300 micro_isge(union tgsi_exec_channel
*dst
,
3301 const union tgsi_exec_channel
*src0
,
3302 const union tgsi_exec_channel
*src1
)
3304 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
3305 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
3306 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
3307 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
3311 micro_ishr(union tgsi_exec_channel
*dst
,
3312 const union tgsi_exec_channel
*src0
,
3313 const union tgsi_exec_channel
*src1
)
3315 unsigned masked_count
;
3316 masked_count
= src1
->i
[0] & 0x1f;
3317 dst
->i
[0] = src0
->i
[0] >> masked_count
;
3318 masked_count
= src1
->i
[1] & 0x1f;
3319 dst
->i
[1] = src0
->i
[1] >> masked_count
;
3320 masked_count
= src1
->i
[2] & 0x1f;
3321 dst
->i
[2] = src0
->i
[2] >> masked_count
;
3322 masked_count
= src1
->i
[3] & 0x1f;
3323 dst
->i
[3] = src0
->i
[3] >> masked_count
;
3327 micro_islt(union tgsi_exec_channel
*dst
,
3328 const union tgsi_exec_channel
*src0
,
3329 const union tgsi_exec_channel
*src1
)
3331 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
3332 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
3333 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
3334 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
3338 micro_f2u(union tgsi_exec_channel
*dst
,
3339 const union tgsi_exec_channel
*src
)
3341 dst
->u
[0] = (uint
)src
->f
[0];
3342 dst
->u
[1] = (uint
)src
->f
[1];
3343 dst
->u
[2] = (uint
)src
->f
[2];
3344 dst
->u
[3] = (uint
)src
->f
[3];
3348 micro_u2f(union tgsi_exec_channel
*dst
,
3349 const union tgsi_exec_channel
*src
)
3351 dst
->f
[0] = (float)src
->u
[0];
3352 dst
->f
[1] = (float)src
->u
[1];
3353 dst
->f
[2] = (float)src
->u
[2];
3354 dst
->f
[3] = (float)src
->u
[3];
3358 micro_uadd(union tgsi_exec_channel
*dst
,
3359 const union tgsi_exec_channel
*src0
,
3360 const union tgsi_exec_channel
*src1
)
3362 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
3363 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
3364 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
3365 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
3369 micro_udiv(union tgsi_exec_channel
*dst
,
3370 const union tgsi_exec_channel
*src0
,
3371 const union tgsi_exec_channel
*src1
)
3373 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
3374 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
3375 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
3376 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
3380 micro_umad(union tgsi_exec_channel
*dst
,
3381 const union tgsi_exec_channel
*src0
,
3382 const union tgsi_exec_channel
*src1
,
3383 const union tgsi_exec_channel
*src2
)
3385 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
3386 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
3387 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
3388 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
3392 micro_umax(union tgsi_exec_channel
*dst
,
3393 const union tgsi_exec_channel
*src0
,
3394 const union tgsi_exec_channel
*src1
)
3396 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
3397 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
3398 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
3399 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
3403 micro_umin(union tgsi_exec_channel
*dst
,
3404 const union tgsi_exec_channel
*src0
,
3405 const union tgsi_exec_channel
*src1
)
3407 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
3408 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
3409 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
3410 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
3414 micro_umod(union tgsi_exec_channel
*dst
,
3415 const union tgsi_exec_channel
*src0
,
3416 const union tgsi_exec_channel
*src1
)
3418 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
3419 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
3420 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
3421 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
3425 micro_umul(union tgsi_exec_channel
*dst
,
3426 const union tgsi_exec_channel
*src0
,
3427 const union tgsi_exec_channel
*src1
)
3429 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
3430 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
3431 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
3432 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
3436 micro_useq(union tgsi_exec_channel
*dst
,
3437 const union tgsi_exec_channel
*src0
,
3438 const union tgsi_exec_channel
*src1
)
3440 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
3441 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
3442 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
3443 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
3447 micro_usge(union tgsi_exec_channel
*dst
,
3448 const union tgsi_exec_channel
*src0
,
3449 const union tgsi_exec_channel
*src1
)
3451 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
3452 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
3453 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
3454 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
3458 micro_ushr(union tgsi_exec_channel
*dst
,
3459 const union tgsi_exec_channel
*src0
,
3460 const union tgsi_exec_channel
*src1
)
3462 unsigned masked_count
;
3463 masked_count
= src1
->u
[0] & 0x1f;
3464 dst
->u
[0] = src0
->u
[0] >> masked_count
;
3465 masked_count
= src1
->u
[1] & 0x1f;
3466 dst
->u
[1] = src0
->u
[1] >> masked_count
;
3467 masked_count
= src1
->u
[2] & 0x1f;
3468 dst
->u
[2] = src0
->u
[2] >> masked_count
;
3469 masked_count
= src1
->u
[3] & 0x1f;
3470 dst
->u
[3] = src0
->u
[3] >> masked_count
;
3474 micro_uslt(union tgsi_exec_channel
*dst
,
3475 const union tgsi_exec_channel
*src0
,
3476 const union tgsi_exec_channel
*src1
)
3478 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
3479 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
3480 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
3481 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
3485 micro_usne(union tgsi_exec_channel
*dst
,
3486 const union tgsi_exec_channel
*src0
,
3487 const union tgsi_exec_channel
*src1
)
3489 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
3490 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
3491 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
3492 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
3496 micro_uarl(union tgsi_exec_channel
*dst
,
3497 const union tgsi_exec_channel
*src
)
3499 dst
->i
[0] = src
->u
[0];
3500 dst
->i
[1] = src
->u
[1];
3501 dst
->i
[2] = src
->u
[2];
3502 dst
->i
[3] = src
->u
[3];
3506 micro_ucmp(union tgsi_exec_channel
*dst
,
3507 const union tgsi_exec_channel
*src0
,
3508 const union tgsi_exec_channel
*src1
,
3509 const union tgsi_exec_channel
*src2
)
3511 dst
->u
[0] = src0
->u
[0] ? src1
->u
[0] : src2
->u
[0];
3512 dst
->u
[1] = src0
->u
[1] ? src1
->u
[1] : src2
->u
[1];
3513 dst
->u
[2] = src0
->u
[2] ? src1
->u
[2] : src2
->u
[2];
3514 dst
->u
[3] = src0
->u
[3] ? src1
->u
[3] : src2
->u
[3];
3519 struct tgsi_exec_machine
*mach
,
3520 const struct tgsi_full_instruction
*inst
,
3523 union tgsi_exec_channel r
[10];
3527 switch (inst
->Instruction
.Opcode
) {
3528 case TGSI_OPCODE_ARL
:
3529 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
3532 case TGSI_OPCODE_MOV
:
3533 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
3536 case TGSI_OPCODE_LIT
:
3537 exec_lit(mach
, inst
);
3540 case TGSI_OPCODE_RCP
:
3541 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3544 case TGSI_OPCODE_RSQ
:
3545 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3548 case TGSI_OPCODE_EXP
:
3549 exec_exp(mach
, inst
);
3552 case TGSI_OPCODE_LOG
:
3553 exec_log(mach
, inst
);
3556 case TGSI_OPCODE_MUL
:
3557 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3560 case TGSI_OPCODE_ADD
:
3561 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3564 case TGSI_OPCODE_DP3
:
3565 exec_dp3(mach
, inst
);
3568 case TGSI_OPCODE_DP4
:
3569 exec_dp4(mach
, inst
);
3572 case TGSI_OPCODE_DST
:
3573 exec_dst(mach
, inst
);
3576 case TGSI_OPCODE_MIN
:
3577 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3580 case TGSI_OPCODE_MAX
:
3581 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3584 case TGSI_OPCODE_SLT
:
3585 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3588 case TGSI_OPCODE_SGE
:
3589 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3592 case TGSI_OPCODE_MAD
:
3593 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3596 case TGSI_OPCODE_SUB
:
3597 exec_vector_binary(mach
, inst
, micro_sub
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3600 case TGSI_OPCODE_LRP
:
3601 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3604 case TGSI_OPCODE_CND
:
3605 exec_vector_trinary(mach
, inst
, micro_cnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3608 case TGSI_OPCODE_SQRT
:
3609 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3612 case TGSI_OPCODE_DP2A
:
3613 exec_dp2a(mach
, inst
);
3616 case TGSI_OPCODE_FRC
:
3617 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3620 case TGSI_OPCODE_CLAMP
:
3621 exec_vector_trinary(mach
, inst
, micro_clamp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3624 case TGSI_OPCODE_FLR
:
3625 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3628 case TGSI_OPCODE_ROUND
:
3629 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3632 case TGSI_OPCODE_EX2
:
3633 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3636 case TGSI_OPCODE_LG2
:
3637 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3640 case TGSI_OPCODE_POW
:
3641 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3644 case TGSI_OPCODE_XPD
:
3645 exec_xpd(mach
, inst
);
3648 case TGSI_OPCODE_ABS
:
3649 exec_vector_unary(mach
, inst
, micro_abs
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3652 case TGSI_OPCODE_RCC
:
3653 exec_scalar_unary(mach
, inst
, micro_rcc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3656 case TGSI_OPCODE_DPH
:
3657 exec_dph(mach
, inst
);
3660 case TGSI_OPCODE_COS
:
3661 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3664 case TGSI_OPCODE_DDX
:
3665 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3668 case TGSI_OPCODE_DDY
:
3669 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3672 case TGSI_OPCODE_KILL
:
3673 exec_kill (mach
, inst
);
3676 case TGSI_OPCODE_KILL_IF
:
3677 exec_kill_if (mach
, inst
);
3680 case TGSI_OPCODE_PK2H
:
3684 case TGSI_OPCODE_PK2US
:
3688 case TGSI_OPCODE_PK4B
:
3692 case TGSI_OPCODE_PK4UB
:
3696 case TGSI_OPCODE_RFL
:
3697 exec_rfl(mach
, inst
);
3700 case TGSI_OPCODE_SEQ
:
3701 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3704 case TGSI_OPCODE_SFL
:
3705 exec_vector(mach
, inst
, micro_sfl
, TGSI_EXEC_DATA_FLOAT
);
3708 case TGSI_OPCODE_SGT
:
3709 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3712 case TGSI_OPCODE_SIN
:
3713 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3716 case TGSI_OPCODE_SLE
:
3717 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3720 case TGSI_OPCODE_SNE
:
3721 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3724 case TGSI_OPCODE_STR
:
3725 exec_vector(mach
, inst
, micro_str
, TGSI_EXEC_DATA_FLOAT
);
3728 case TGSI_OPCODE_TEX
:
3729 /* simple texture lookup */
3730 /* src[0] = texcoord */
3731 /* src[1] = sampler unit */
3732 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
3735 case TGSI_OPCODE_TXB
:
3736 /* Texture lookup with lod bias */
3737 /* src[0] = texcoord (src[0].w = LOD bias) */
3738 /* src[1] = sampler unit */
3739 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
3742 case TGSI_OPCODE_TXD
:
3743 /* Texture lookup with explict partial derivatives */
3744 /* src[0] = texcoord */
3745 /* src[1] = d[strq]/dx */
3746 /* src[2] = d[strq]/dy */
3747 /* src[3] = sampler unit */
3748 exec_txd(mach
, inst
);
3751 case TGSI_OPCODE_TXL
:
3752 /* Texture lookup with explit LOD */
3753 /* src[0] = texcoord (src[0].w = LOD) */
3754 /* src[1] = sampler unit */
3755 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
3758 case TGSI_OPCODE_TXP
:
3759 /* Texture lookup with projection */
3760 /* src[0] = texcoord (src[0].w = projection) */
3761 /* src[1] = sampler unit */
3762 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
3765 case TGSI_OPCODE_UP2H
:
3769 case TGSI_OPCODE_UP2US
:
3773 case TGSI_OPCODE_UP4B
:
3777 case TGSI_OPCODE_UP4UB
:
3781 case TGSI_OPCODE_X2D
:
3782 exec_x2d(mach
, inst
);
3785 case TGSI_OPCODE_ARA
:
3789 case TGSI_OPCODE_ARR
:
3790 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
3793 case TGSI_OPCODE_BRA
:
3797 case TGSI_OPCODE_CAL
:
3798 /* skip the call if no execution channels are enabled */
3799 if (mach
->ExecMask
) {
3802 /* First, record the depths of the execution stacks.
3803 * This is important for deeply nested/looped return statements.
3804 * We have to unwind the stacks by the correct amount. For a
3805 * real code generator, we could determine the number of entries
3806 * to pop off each stack with simple static analysis and avoid
3807 * implementing this data structure at run time.
3809 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
3810 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
3811 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
3812 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
3813 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
3814 /* note that PC was already incremented above */
3815 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
3817 mach
->CallStackTop
++;
3819 /* Second, push the Cond, Loop, Cont, Func stacks */
3820 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
3821 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3822 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3823 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3824 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3825 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
3827 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
3828 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
3829 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
3830 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3831 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3832 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
3834 /* Finally, jump to the subroutine */
3835 *pc
= inst
->Label
.Label
;
3839 case TGSI_OPCODE_RET
:
3840 mach
->FuncMask
&= ~mach
->ExecMask
;
3841 UPDATE_EXEC_MASK(mach
);
3843 if (mach
->FuncMask
== 0x0) {
3844 /* really return now (otherwise, keep executing */
3846 if (mach
->CallStackTop
== 0) {
3847 /* returning from main() */
3848 mach
->CondStackTop
= 0;
3849 mach
->LoopStackTop
= 0;
3854 assert(mach
->CallStackTop
> 0);
3855 mach
->CallStackTop
--;
3857 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
3858 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
3860 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
3861 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
3863 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
3864 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
3866 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
3867 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
3869 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
3870 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
3872 assert(mach
->FuncStackTop
> 0);
3873 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
3875 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
3877 UPDATE_EXEC_MASK(mach
);
3881 case TGSI_OPCODE_SSG
:
3882 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3885 case TGSI_OPCODE_CMP
:
3886 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3889 case TGSI_OPCODE_SCS
:
3890 exec_scs(mach
, inst
);
3893 case TGSI_OPCODE_NRM
:
3894 exec_nrm3(mach
, inst
);
3897 case TGSI_OPCODE_NRM4
:
3898 exec_nrm4(mach
, inst
);
3901 case TGSI_OPCODE_DIV
:
3902 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3905 case TGSI_OPCODE_DP2
:
3906 exec_dp2(mach
, inst
);
3909 case TGSI_OPCODE_IF
:
3911 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
3912 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
3913 FETCH( &r
[0], 0, TGSI_CHAN_X
);
3914 /* update CondMask */
3916 mach
->CondMask
&= ~0x1;
3919 mach
->CondMask
&= ~0x2;
3922 mach
->CondMask
&= ~0x4;
3925 mach
->CondMask
&= ~0x8;
3927 UPDATE_EXEC_MASK(mach
);
3928 /* Todo: If CondMask==0, jump to ELSE */
3931 case TGSI_OPCODE_UIF
:
3933 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
3934 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
3935 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
3936 /* update CondMask */
3938 mach
->CondMask
&= ~0x1;
3941 mach
->CondMask
&= ~0x2;
3944 mach
->CondMask
&= ~0x4;
3947 mach
->CondMask
&= ~0x8;
3949 UPDATE_EXEC_MASK(mach
);
3950 /* Todo: If CondMask==0, jump to ELSE */
3953 case TGSI_OPCODE_ELSE
:
3954 /* invert CondMask wrt previous mask */
3957 assert(mach
->CondStackTop
> 0);
3958 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
3959 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
3960 UPDATE_EXEC_MASK(mach
);
3961 /* Todo: If CondMask==0, jump to ENDIF */
3965 case TGSI_OPCODE_ENDIF
:
3967 assert(mach
->CondStackTop
> 0);
3968 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
3969 UPDATE_EXEC_MASK(mach
);
3972 case TGSI_OPCODE_END
:
3973 /* make sure we end primitives which haven't
3974 * been explicitly emitted */
3975 conditional_emit_primitive(mach
);
3976 /* halt execution */
3980 case TGSI_OPCODE_PUSHA
:
3984 case TGSI_OPCODE_POPA
:
3988 case TGSI_OPCODE_CEIL
:
3989 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3992 case TGSI_OPCODE_I2F
:
3993 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
3996 case TGSI_OPCODE_NOT
:
3997 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4000 case TGSI_OPCODE_TRUNC
:
4001 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4004 case TGSI_OPCODE_SHL
:
4005 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4008 case TGSI_OPCODE_AND
:
4009 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4012 case TGSI_OPCODE_OR
:
4013 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4016 case TGSI_OPCODE_MOD
:
4017 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4020 case TGSI_OPCODE_XOR
:
4021 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4024 case TGSI_OPCODE_SAD
:
4028 case TGSI_OPCODE_TXF
:
4029 exec_txf(mach
, inst
);
4032 case TGSI_OPCODE_TXQ
:
4033 exec_txq(mach
, inst
);
4036 case TGSI_OPCODE_EMIT
:
4040 case TGSI_OPCODE_ENDPRIM
:
4041 emit_primitive(mach
);
4044 case TGSI_OPCODE_BGNLOOP
:
4045 /* push LoopMask and ContMasks */
4046 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4047 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4048 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4049 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
4051 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
4052 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
4053 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
4054 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
4055 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
4058 case TGSI_OPCODE_ENDLOOP
:
4059 /* Restore ContMask, but don't pop */
4060 assert(mach
->ContStackTop
> 0);
4061 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
4062 UPDATE_EXEC_MASK(mach
);
4063 if (mach
->ExecMask
) {
4064 /* repeat loop: jump to instruction just past BGNLOOP */
4065 assert(mach
->LoopLabelStackTop
> 0);
4066 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
4069 /* exit loop: pop LoopMask */
4070 assert(mach
->LoopStackTop
> 0);
4071 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
4073 assert(mach
->ContStackTop
> 0);
4074 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
4075 assert(mach
->LoopLabelStackTop
> 0);
4076 --mach
->LoopLabelStackTop
;
4078 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
4080 UPDATE_EXEC_MASK(mach
);
4083 case TGSI_OPCODE_BRK
:
4087 case TGSI_OPCODE_CONT
:
4088 /* turn off cont channels for each enabled exec channel */
4089 mach
->ContMask
&= ~mach
->ExecMask
;
4090 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4091 UPDATE_EXEC_MASK(mach
);
4094 case TGSI_OPCODE_BGNSUB
:
4098 case TGSI_OPCODE_ENDSUB
:
4100 * XXX: This really should be a no-op. We should never reach this opcode.
4103 assert(mach
->CallStackTop
> 0);
4104 mach
->CallStackTop
--;
4106 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
4107 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
4109 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
4110 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
4112 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
4113 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
4115 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
4116 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
4118 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
4119 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
4121 assert(mach
->FuncStackTop
> 0);
4122 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
4124 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
4126 UPDATE_EXEC_MASK(mach
);
4129 case TGSI_OPCODE_NOP
:
4132 case TGSI_OPCODE_BREAKC
:
4133 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4134 /* update CondMask */
4135 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
4136 mach
->LoopMask
&= ~0x1;
4138 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
4139 mach
->LoopMask
&= ~0x2;
4141 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
4142 mach
->LoopMask
&= ~0x4;
4144 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
4145 mach
->LoopMask
&= ~0x8;
4147 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4148 UPDATE_EXEC_MASK(mach
);
4151 case TGSI_OPCODE_F2I
:
4152 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4155 case TGSI_OPCODE_IDIV
:
4156 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4159 case TGSI_OPCODE_IMAX
:
4160 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4163 case TGSI_OPCODE_IMIN
:
4164 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4167 case TGSI_OPCODE_INEG
:
4168 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4171 case TGSI_OPCODE_ISGE
:
4172 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4175 case TGSI_OPCODE_ISHR
:
4176 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4179 case TGSI_OPCODE_ISLT
:
4180 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4183 case TGSI_OPCODE_F2U
:
4184 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4187 case TGSI_OPCODE_U2F
:
4188 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
4191 case TGSI_OPCODE_UADD
:
4192 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4195 case TGSI_OPCODE_UDIV
:
4196 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4199 case TGSI_OPCODE_UMAD
:
4200 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4203 case TGSI_OPCODE_UMAX
:
4204 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4207 case TGSI_OPCODE_UMIN
:
4208 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4211 case TGSI_OPCODE_UMOD
:
4212 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4215 case TGSI_OPCODE_UMUL
:
4216 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4219 case TGSI_OPCODE_USEQ
:
4220 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4223 case TGSI_OPCODE_USGE
:
4224 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4227 case TGSI_OPCODE_USHR
:
4228 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4231 case TGSI_OPCODE_USLT
:
4232 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4235 case TGSI_OPCODE_USNE
:
4236 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4239 case TGSI_OPCODE_SWITCH
:
4240 exec_switch(mach
, inst
);
4243 case TGSI_OPCODE_CASE
:
4244 exec_case(mach
, inst
);
4247 case TGSI_OPCODE_DEFAULT
:
4251 case TGSI_OPCODE_ENDSWITCH
:
4252 exec_endswitch(mach
);
4255 case TGSI_OPCODE_SAMPLE_I
:
4256 exec_txf(mach
, inst
);
4259 case TGSI_OPCODE_SAMPLE_I_MS
:
4263 case TGSI_OPCODE_SAMPLE
:
4264 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
4267 case TGSI_OPCODE_SAMPLE_B
:
4268 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
4271 case TGSI_OPCODE_SAMPLE_C
:
4272 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
4275 case TGSI_OPCODE_SAMPLE_C_LZ
:
4276 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
4279 case TGSI_OPCODE_SAMPLE_D
:
4280 exec_sample_d(mach
, inst
);
4283 case TGSI_OPCODE_SAMPLE_L
:
4284 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
4287 case TGSI_OPCODE_GATHER4
:
4291 case TGSI_OPCODE_SVIEWINFO
:
4292 exec_txq(mach
, inst
);
4295 case TGSI_OPCODE_SAMPLE_POS
:
4299 case TGSI_OPCODE_SAMPLE_INFO
:
4303 case TGSI_OPCODE_UARL
:
4304 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
4307 case TGSI_OPCODE_UCMP
:
4308 exec_vector_trinary(mach
, inst
, micro_ucmp
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4311 case TGSI_OPCODE_IABS
:
4312 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4315 case TGSI_OPCODE_ISSG
:
4316 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4319 case TGSI_OPCODE_TEX2
:
4320 /* simple texture lookup */
4321 /* src[0] = texcoord */
4322 /* src[1] = compare */
4323 /* src[2] = sampler unit */
4324 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
4326 case TGSI_OPCODE_TXB2
:
4327 /* simple texture lookup */
4328 /* src[0] = texcoord */
4330 /* src[2] = sampler unit */
4331 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
4333 case TGSI_OPCODE_TXL2
:
4334 /* simple texture lookup */
4335 /* src[0] = texcoord */
4337 /* src[2] = sampler unit */
4338 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
4347 * Run TGSI interpreter.
4348 * \return bitmask of "alive" quad components
4351 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
)
4355 uint default_mask
= 0xf;
4357 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
4358 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
4360 if( mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
) {
4361 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
4362 mach
->Primitives
[0] = 0;
4363 /* GS runs on a single primitive for now */
4367 mach
->CondMask
= default_mask
;
4368 mach
->LoopMask
= default_mask
;
4369 mach
->ContMask
= default_mask
;
4370 mach
->FuncMask
= default_mask
;
4371 mach
->ExecMask
= default_mask
;
4373 mach
->Switch
.mask
= default_mask
;
4375 assert(mach
->CondStackTop
== 0);
4376 assert(mach
->LoopStackTop
== 0);
4377 assert(mach
->ContStackTop
== 0);
4378 assert(mach
->SwitchStackTop
== 0);
4379 assert(mach
->BreakStackTop
== 0);
4380 assert(mach
->CallStackTop
== 0);
4383 /* execute declarations (interpolants) */
4384 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
4385 exec_declaration( mach
, mach
->Declarations
+i
);
4390 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
4391 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
4394 memset(mach
->Temps
, 0, sizeof(temps
));
4395 memset(mach
->Outputs
, 0, sizeof(outputs
));
4396 memset(temps
, 0, sizeof(temps
));
4397 memset(outputs
, 0, sizeof(outputs
));
4400 /* execute instructions, until pc is set to -1 */
4406 tgsi_dump_instruction(&mach
->Instructions
[pc
], inst
++);
4409 assert(pc
< (int) mach
->NumInstructions
);
4410 exec_instruction(mach
, mach
->Instructions
+ pc
, &pc
);
4413 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
4414 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
4417 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
4418 debug_printf("TEMP[%2u] = ", i
);
4419 for (j
= 0; j
< 4; j
++) {
4423 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4424 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
4425 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
4426 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
4427 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
4431 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
4432 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
4435 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
4436 debug_printf("OUT[%2u] = ", i
);
4437 for (j
= 0; j
< 4; j
++) {
4441 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4442 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
4443 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
4444 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
4445 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
4454 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4455 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
4457 * Scale back depth component.
4459 for (i
= 0; i
< 4; i
++)
4460 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
4464 /* Strictly speaking, these assertions aren't really needed but they
4465 * can potentially catch some bugs in the control flow code.
4467 assert(mach
->CondStackTop
== 0);
4468 assert(mach
->LoopStackTop
== 0);
4469 assert(mach
->ContStackTop
== 0);
4470 assert(mach
->SwitchStackTop
== 0);
4471 assert(mach
->BreakStackTop
== 0);
4472 assert(mach
->CallStackTop
== 0);
4474 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];