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tgsi: handle TG4 opcode in tgsi exec
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define DEBUG_EXECUTION 0
66
67
68 #define FAST_MATH 0
69
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
74
75 union tgsi_double_channel {
76 double d[TGSI_QUAD_SIZE];
77 unsigned u[TGSI_QUAD_SIZE][2];
78 };
79
80 struct tgsi_double_vector {
81 union tgsi_double_channel xy;
82 union tgsi_double_channel zw;
83 };
84
85 static void
86 micro_abs(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
88 {
89 dst->f[0] = fabsf(src->f[0]);
90 dst->f[1] = fabsf(src->f[1]);
91 dst->f[2] = fabsf(src->f[2]);
92 dst->f[3] = fabsf(src->f[3]);
93 }
94
95 static void
96 micro_arl(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
98 {
99 dst->i[0] = (int)floorf(src->f[0]);
100 dst->i[1] = (int)floorf(src->f[1]);
101 dst->i[2] = (int)floorf(src->f[2]);
102 dst->i[3] = (int)floorf(src->f[3]);
103 }
104
105 static void
106 micro_arr(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
108 {
109 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
110 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
111 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
112 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
113 }
114
115 static void
116 micro_ceil(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src)
118 {
119 dst->f[0] = ceilf(src->f[0]);
120 dst->f[1] = ceilf(src->f[1]);
121 dst->f[2] = ceilf(src->f[2]);
122 dst->f[3] = ceilf(src->f[3]);
123 }
124
125 static void
126 micro_clamp(union tgsi_exec_channel *dst,
127 const union tgsi_exec_channel *src0,
128 const union tgsi_exec_channel *src1,
129 const union tgsi_exec_channel *src2)
130 {
131 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
132 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
133 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
134 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
135 }
136
137 static void
138 micro_cmp(union tgsi_exec_channel *dst,
139 const union tgsi_exec_channel *src0,
140 const union tgsi_exec_channel *src1,
141 const union tgsi_exec_channel *src2)
142 {
143 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
144 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
145 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
146 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
147 }
148
149 static void
150 micro_cos(union tgsi_exec_channel *dst,
151 const union tgsi_exec_channel *src)
152 {
153 dst->f[0] = cosf(src->f[0]);
154 dst->f[1] = cosf(src->f[1]);
155 dst->f[2] = cosf(src->f[2]);
156 dst->f[3] = cosf(src->f[3]);
157 }
158
159 static void
160 micro_d2f(union tgsi_exec_channel *dst,
161 const union tgsi_double_channel *src)
162 {
163 dst->f[0] = (float)src->d[0];
164 dst->f[1] = (float)src->d[1];
165 dst->f[2] = (float)src->d[2];
166 dst->f[3] = (float)src->d[3];
167 }
168
169 static void
170 micro_d2i(union tgsi_exec_channel *dst,
171 const union tgsi_double_channel *src)
172 {
173 dst->i[0] = (int)src->d[0];
174 dst->i[1] = (int)src->d[1];
175 dst->i[2] = (int)src->d[2];
176 dst->i[3] = (int)src->d[3];
177 }
178
179 static void
180 micro_d2u(union tgsi_exec_channel *dst,
181 const union tgsi_double_channel *src)
182 {
183 dst->u[0] = (unsigned)src->d[0];
184 dst->u[1] = (unsigned)src->d[1];
185 dst->u[2] = (unsigned)src->d[2];
186 dst->u[3] = (unsigned)src->d[3];
187 }
188 static void
189 micro_dabs(union tgsi_double_channel *dst,
190 const union tgsi_double_channel *src)
191 {
192 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
193 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
194 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
195 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
196 }
197
198 static void
199 micro_dadd(union tgsi_double_channel *dst,
200 const union tgsi_double_channel *src)
201 {
202 dst->d[0] = src[0].d[0] + src[1].d[0];
203 dst->d[1] = src[0].d[1] + src[1].d[1];
204 dst->d[2] = src[0].d[2] + src[1].d[2];
205 dst->d[3] = src[0].d[3] + src[1].d[3];
206 }
207
208 static void
209 micro_ddx(union tgsi_exec_channel *dst,
210 const union tgsi_exec_channel *src)
211 {
212 dst->f[0] =
213 dst->f[1] =
214 dst->f[2] =
215 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
216 }
217
218 static void
219 micro_ddy(union tgsi_exec_channel *dst,
220 const union tgsi_exec_channel *src)
221 {
222 dst->f[0] =
223 dst->f[1] =
224 dst->f[2] =
225 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
226 }
227
228 static void
229 micro_dmul(union tgsi_double_channel *dst,
230 const union tgsi_double_channel *src)
231 {
232 dst->d[0] = src[0].d[0] * src[1].d[0];
233 dst->d[1] = src[0].d[1] * src[1].d[1];
234 dst->d[2] = src[0].d[2] * src[1].d[2];
235 dst->d[3] = src[0].d[3] * src[1].d[3];
236 }
237
238 static void
239 micro_dmax(union tgsi_double_channel *dst,
240 const union tgsi_double_channel *src)
241 {
242 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
243 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
244 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
245 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
246 }
247
248 static void
249 micro_dmin(union tgsi_double_channel *dst,
250 const union tgsi_double_channel *src)
251 {
252 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
253 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
254 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
255 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
256 }
257
258 static void
259 micro_dneg(union tgsi_double_channel *dst,
260 const union tgsi_double_channel *src)
261 {
262 dst->d[0] = -src->d[0];
263 dst->d[1] = -src->d[1];
264 dst->d[2] = -src->d[2];
265 dst->d[3] = -src->d[3];
266 }
267
268 static void
269 micro_dslt(union tgsi_double_channel *dst,
270 const union tgsi_double_channel *src)
271 {
272 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
273 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
274 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
275 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
276 }
277
278 static void
279 micro_dsne(union tgsi_double_channel *dst,
280 const union tgsi_double_channel *src)
281 {
282 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
283 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
284 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
285 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
286 }
287
288 static void
289 micro_dsge(union tgsi_double_channel *dst,
290 const union tgsi_double_channel *src)
291 {
292 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
293 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
294 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
295 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
296 }
297
298 static void
299 micro_dseq(union tgsi_double_channel *dst,
300 const union tgsi_double_channel *src)
301 {
302 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
303 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
304 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
305 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
306 }
307
308 static void
309 micro_drcp(union tgsi_double_channel *dst,
310 const union tgsi_double_channel *src)
311 {
312 dst->d[0] = 1.0 / src->d[0];
313 dst->d[1] = 1.0 / src->d[1];
314 dst->d[2] = 1.0 / src->d[2];
315 dst->d[3] = 1.0 / src->d[3];
316 }
317
318 static void
319 micro_dsqrt(union tgsi_double_channel *dst,
320 const union tgsi_double_channel *src)
321 {
322 dst->d[0] = sqrt(src->d[0]);
323 dst->d[1] = sqrt(src->d[1]);
324 dst->d[2] = sqrt(src->d[2]);
325 dst->d[3] = sqrt(src->d[3]);
326 }
327
328 static void
329 micro_drsq(union tgsi_double_channel *dst,
330 const union tgsi_double_channel *src)
331 {
332 dst->d[0] = 1.0 / sqrt(src->d[0]);
333 dst->d[1] = 1.0 / sqrt(src->d[1]);
334 dst->d[2] = 1.0 / sqrt(src->d[2]);
335 dst->d[3] = 1.0 / sqrt(src->d[3]);
336 }
337
338 static void
339 micro_dmad(union tgsi_double_channel *dst,
340 const union tgsi_double_channel *src)
341 {
342 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
343 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
344 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
345 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
346 }
347
348 static void
349 micro_dfrac(union tgsi_double_channel *dst,
350 const union tgsi_double_channel *src)
351 {
352 dst->d[0] = src->d[0] - floor(src->d[0]);
353 dst->d[1] = src->d[1] - floor(src->d[1]);
354 dst->d[2] = src->d[2] - floor(src->d[2]);
355 dst->d[3] = src->d[3] - floor(src->d[3]);
356 }
357
358 static void
359 micro_dldexp(union tgsi_double_channel *dst,
360 const union tgsi_double_channel *src0,
361 union tgsi_exec_channel *src1)
362 {
363 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
364 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
365 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
366 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
367 }
368
369 static void
370 micro_dfracexp(union tgsi_double_channel *dst,
371 union tgsi_exec_channel *dst_exp,
372 const union tgsi_double_channel *src)
373 {
374 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
375 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
376 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
377 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
378 }
379
380 static void
381 micro_exp2(union tgsi_exec_channel *dst,
382 const union tgsi_exec_channel *src)
383 {
384 #if FAST_MATH
385 dst->f[0] = util_fast_exp2(src->f[0]);
386 dst->f[1] = util_fast_exp2(src->f[1]);
387 dst->f[2] = util_fast_exp2(src->f[2]);
388 dst->f[3] = util_fast_exp2(src->f[3]);
389 #else
390 #if DEBUG
391 /* Inf is okay for this instruction, so clamp it to silence assertions. */
392 uint i;
393 union tgsi_exec_channel clamped;
394
395 for (i = 0; i < 4; i++) {
396 if (src->f[i] > 127.99999f) {
397 clamped.f[i] = 127.99999f;
398 } else if (src->f[i] < -126.99999f) {
399 clamped.f[i] = -126.99999f;
400 } else {
401 clamped.f[i] = src->f[i];
402 }
403 }
404 src = &clamped;
405 #endif /* DEBUG */
406
407 dst->f[0] = powf(2.0f, src->f[0]);
408 dst->f[1] = powf(2.0f, src->f[1]);
409 dst->f[2] = powf(2.0f, src->f[2]);
410 dst->f[3] = powf(2.0f, src->f[3]);
411 #endif /* FAST_MATH */
412 }
413
414 static void
415 micro_f2d(union tgsi_double_channel *dst,
416 const union tgsi_exec_channel *src)
417 {
418 dst->d[0] = (double)src->f[0];
419 dst->d[1] = (double)src->f[1];
420 dst->d[2] = (double)src->f[2];
421 dst->d[3] = (double)src->f[3];
422 }
423
424 static void
425 micro_flr(union tgsi_exec_channel *dst,
426 const union tgsi_exec_channel *src)
427 {
428 dst->f[0] = floorf(src->f[0]);
429 dst->f[1] = floorf(src->f[1]);
430 dst->f[2] = floorf(src->f[2]);
431 dst->f[3] = floorf(src->f[3]);
432 }
433
434 static void
435 micro_frc(union tgsi_exec_channel *dst,
436 const union tgsi_exec_channel *src)
437 {
438 dst->f[0] = src->f[0] - floorf(src->f[0]);
439 dst->f[1] = src->f[1] - floorf(src->f[1]);
440 dst->f[2] = src->f[2] - floorf(src->f[2]);
441 dst->f[3] = src->f[3] - floorf(src->f[3]);
442 }
443
444 static void
445 micro_i2d(union tgsi_double_channel *dst,
446 const union tgsi_exec_channel *src)
447 {
448 dst->d[0] = (double)src->i[0];
449 dst->d[1] = (double)src->i[1];
450 dst->d[2] = (double)src->i[2];
451 dst->d[3] = (double)src->i[3];
452 }
453
454 static void
455 micro_iabs(union tgsi_exec_channel *dst,
456 const union tgsi_exec_channel *src)
457 {
458 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
459 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
460 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
461 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
462 }
463
464 static void
465 micro_ineg(union tgsi_exec_channel *dst,
466 const union tgsi_exec_channel *src)
467 {
468 dst->i[0] = -src->i[0];
469 dst->i[1] = -src->i[1];
470 dst->i[2] = -src->i[2];
471 dst->i[3] = -src->i[3];
472 }
473
474 static void
475 micro_lg2(union tgsi_exec_channel *dst,
476 const union tgsi_exec_channel *src)
477 {
478 #if FAST_MATH
479 dst->f[0] = util_fast_log2(src->f[0]);
480 dst->f[1] = util_fast_log2(src->f[1]);
481 dst->f[2] = util_fast_log2(src->f[2]);
482 dst->f[3] = util_fast_log2(src->f[3]);
483 #else
484 dst->f[0] = logf(src->f[0]) * 1.442695f;
485 dst->f[1] = logf(src->f[1]) * 1.442695f;
486 dst->f[2] = logf(src->f[2]) * 1.442695f;
487 dst->f[3] = logf(src->f[3]) * 1.442695f;
488 #endif
489 }
490
491 static void
492 micro_lrp(union tgsi_exec_channel *dst,
493 const union tgsi_exec_channel *src0,
494 const union tgsi_exec_channel *src1,
495 const union tgsi_exec_channel *src2)
496 {
497 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
498 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
499 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
500 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
501 }
502
503 static void
504 micro_mad(union tgsi_exec_channel *dst,
505 const union tgsi_exec_channel *src0,
506 const union tgsi_exec_channel *src1,
507 const union tgsi_exec_channel *src2)
508 {
509 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
510 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
511 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
512 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
513 }
514
515 static void
516 micro_mov(union tgsi_exec_channel *dst,
517 const union tgsi_exec_channel *src)
518 {
519 dst->u[0] = src->u[0];
520 dst->u[1] = src->u[1];
521 dst->u[2] = src->u[2];
522 dst->u[3] = src->u[3];
523 }
524
525 static void
526 micro_rcp(union tgsi_exec_channel *dst,
527 const union tgsi_exec_channel *src)
528 {
529 #if 0 /* for debugging */
530 assert(src->f[0] != 0.0f);
531 assert(src->f[1] != 0.0f);
532 assert(src->f[2] != 0.0f);
533 assert(src->f[3] != 0.0f);
534 #endif
535 dst->f[0] = 1.0f / src->f[0];
536 dst->f[1] = 1.0f / src->f[1];
537 dst->f[2] = 1.0f / src->f[2];
538 dst->f[3] = 1.0f / src->f[3];
539 }
540
541 static void
542 micro_rnd(union tgsi_exec_channel *dst,
543 const union tgsi_exec_channel *src)
544 {
545 dst->f[0] = floorf(src->f[0] + 0.5f);
546 dst->f[1] = floorf(src->f[1] + 0.5f);
547 dst->f[2] = floorf(src->f[2] + 0.5f);
548 dst->f[3] = floorf(src->f[3] + 0.5f);
549 }
550
551 static void
552 micro_rsq(union tgsi_exec_channel *dst,
553 const union tgsi_exec_channel *src)
554 {
555 #if 0 /* for debugging */
556 assert(src->f[0] != 0.0f);
557 assert(src->f[1] != 0.0f);
558 assert(src->f[2] != 0.0f);
559 assert(src->f[3] != 0.0f);
560 #endif
561 dst->f[0] = 1.0f / sqrtf(src->f[0]);
562 dst->f[1] = 1.0f / sqrtf(src->f[1]);
563 dst->f[2] = 1.0f / sqrtf(src->f[2]);
564 dst->f[3] = 1.0f / sqrtf(src->f[3]);
565 }
566
567 static void
568 micro_sqrt(union tgsi_exec_channel *dst,
569 const union tgsi_exec_channel *src)
570 {
571 dst->f[0] = sqrtf(src->f[0]);
572 dst->f[1] = sqrtf(src->f[1]);
573 dst->f[2] = sqrtf(src->f[2]);
574 dst->f[3] = sqrtf(src->f[3]);
575 }
576
577 static void
578 micro_seq(union tgsi_exec_channel *dst,
579 const union tgsi_exec_channel *src0,
580 const union tgsi_exec_channel *src1)
581 {
582 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
583 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
584 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
585 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
586 }
587
588 static void
589 micro_sge(union tgsi_exec_channel *dst,
590 const union tgsi_exec_channel *src0,
591 const union tgsi_exec_channel *src1)
592 {
593 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
594 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
595 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
596 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
597 }
598
599 static void
600 micro_sgn(union tgsi_exec_channel *dst,
601 const union tgsi_exec_channel *src)
602 {
603 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
604 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
605 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
606 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
607 }
608
609 static void
610 micro_isgn(union tgsi_exec_channel *dst,
611 const union tgsi_exec_channel *src)
612 {
613 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
614 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
615 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
616 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
617 }
618
619 static void
620 micro_sgt(union tgsi_exec_channel *dst,
621 const union tgsi_exec_channel *src0,
622 const union tgsi_exec_channel *src1)
623 {
624 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
625 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
626 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
627 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
628 }
629
630 static void
631 micro_sin(union tgsi_exec_channel *dst,
632 const union tgsi_exec_channel *src)
633 {
634 dst->f[0] = sinf(src->f[0]);
635 dst->f[1] = sinf(src->f[1]);
636 dst->f[2] = sinf(src->f[2]);
637 dst->f[3] = sinf(src->f[3]);
638 }
639
640 static void
641 micro_sle(union tgsi_exec_channel *dst,
642 const union tgsi_exec_channel *src0,
643 const union tgsi_exec_channel *src1)
644 {
645 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
646 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
647 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
648 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
649 }
650
651 static void
652 micro_slt(union tgsi_exec_channel *dst,
653 const union tgsi_exec_channel *src0,
654 const union tgsi_exec_channel *src1)
655 {
656 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
657 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
658 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
659 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
660 }
661
662 static void
663 micro_sne(union tgsi_exec_channel *dst,
664 const union tgsi_exec_channel *src0,
665 const union tgsi_exec_channel *src1)
666 {
667 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
668 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
669 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
670 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
671 }
672
673 static void
674 micro_trunc(union tgsi_exec_channel *dst,
675 const union tgsi_exec_channel *src)
676 {
677 dst->f[0] = (float)(int)src->f[0];
678 dst->f[1] = (float)(int)src->f[1];
679 dst->f[2] = (float)(int)src->f[2];
680 dst->f[3] = (float)(int)src->f[3];
681 }
682
683 static void
684 micro_u2d(union tgsi_double_channel *dst,
685 const union tgsi_exec_channel *src)
686 {
687 dst->d[0] = (double)src->u[0];
688 dst->d[1] = (double)src->u[1];
689 dst->d[2] = (double)src->u[2];
690 dst->d[3] = (double)src->u[3];
691 }
692
693 enum tgsi_exec_datatype {
694 TGSI_EXEC_DATA_FLOAT,
695 TGSI_EXEC_DATA_INT,
696 TGSI_EXEC_DATA_UINT,
697 TGSI_EXEC_DATA_DOUBLE
698 };
699
700 /*
701 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
702 */
703 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
704 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
705 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
706 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
707 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
708 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
709
710
711 /** The execution mask depends on the conditional mask and the loop mask */
712 #define UPDATE_EXEC_MASK(MACH) \
713 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
714
715
716 static const union tgsi_exec_channel ZeroVec =
717 { { 0.0, 0.0, 0.0, 0.0 } };
718
719 static const union tgsi_exec_channel OneVec = {
720 {1.0f, 1.0f, 1.0f, 1.0f}
721 };
722
723 static const union tgsi_exec_channel P128Vec = {
724 {128.0f, 128.0f, 128.0f, 128.0f}
725 };
726
727 static const union tgsi_exec_channel M128Vec = {
728 {-128.0f, -128.0f, -128.0f, -128.0f}
729 };
730
731
732 /**
733 * Assert that none of the float values in 'chan' are infinite or NaN.
734 * NaN and Inf may occur normally during program execution and should
735 * not lead to crashes, etc. But when debugging, it's helpful to catch
736 * them.
737 */
738 static INLINE void
739 check_inf_or_nan(const union tgsi_exec_channel *chan)
740 {
741 assert(!util_is_inf_or_nan((chan)->f[0]));
742 assert(!util_is_inf_or_nan((chan)->f[1]));
743 assert(!util_is_inf_or_nan((chan)->f[2]));
744 assert(!util_is_inf_or_nan((chan)->f[3]));
745 }
746
747
748 #ifdef DEBUG
749 static void
750 print_chan(const char *msg, const union tgsi_exec_channel *chan)
751 {
752 debug_printf("%s = {%f, %f, %f, %f}\n",
753 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
754 }
755 #endif
756
757
758 #ifdef DEBUG
759 static void
760 print_temp(const struct tgsi_exec_machine *mach, uint index)
761 {
762 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
763 int i;
764 debug_printf("Temp[%u] =\n", index);
765 for (i = 0; i < 4; i++) {
766 debug_printf(" %c: { %f, %f, %f, %f }\n",
767 "XYZW"[i],
768 tmp->xyzw[i].f[0],
769 tmp->xyzw[i].f[1],
770 tmp->xyzw[i].f[2],
771 tmp->xyzw[i].f[3]);
772 }
773 }
774 #endif
775
776
777 void
778 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
779 unsigned num_bufs,
780 const void **bufs,
781 const unsigned *buf_sizes)
782 {
783 unsigned i;
784
785 for (i = 0; i < num_bufs; i++) {
786 mach->Consts[i] = bufs[i];
787 mach->ConstsSize[i] = buf_sizes[i];
788 }
789 }
790
791
792 /**
793 * Check if there's a potential src/dst register data dependency when
794 * using SOA execution.
795 * Example:
796 * MOV T, T.yxwz;
797 * This would expand into:
798 * MOV t0, t1;
799 * MOV t1, t0;
800 * MOV t2, t3;
801 * MOV t3, t2;
802 * The second instruction will have the wrong value for t0 if executed as-is.
803 */
804 boolean
805 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
806 {
807 uint i, chan;
808
809 uint writemask = inst->Dst[0].Register.WriteMask;
810 if (writemask == TGSI_WRITEMASK_X ||
811 writemask == TGSI_WRITEMASK_Y ||
812 writemask == TGSI_WRITEMASK_Z ||
813 writemask == TGSI_WRITEMASK_W ||
814 writemask == TGSI_WRITEMASK_NONE) {
815 /* no chance of data dependency */
816 return FALSE;
817 }
818
819 /* loop over src regs */
820 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
821 if ((inst->Src[i].Register.File ==
822 inst->Dst[0].Register.File) &&
823 ((inst->Src[i].Register.Index ==
824 inst->Dst[0].Register.Index) ||
825 inst->Src[i].Register.Indirect ||
826 inst->Dst[0].Register.Indirect)) {
827 /* loop over dest channels */
828 uint channelsWritten = 0x0;
829 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
830 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
831 /* check if we're reading a channel that's been written */
832 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
833 if (channelsWritten & (1 << swizzle)) {
834 return TRUE;
835 }
836
837 channelsWritten |= (1 << chan);
838 }
839 }
840 }
841 }
842 return FALSE;
843 }
844
845
846 /**
847 * Initialize machine state by expanding tokens to full instructions,
848 * allocating temporary storage, setting up constants, etc.
849 * After this, we can call tgsi_exec_machine_run() many times.
850 */
851 void
852 tgsi_exec_machine_bind_shader(
853 struct tgsi_exec_machine *mach,
854 const struct tgsi_token *tokens,
855 struct tgsi_sampler *sampler)
856 {
857 uint k;
858 struct tgsi_parse_context parse;
859 struct tgsi_full_instruction *instructions;
860 struct tgsi_full_declaration *declarations;
861 uint maxInstructions = 10, numInstructions = 0;
862 uint maxDeclarations = 10, numDeclarations = 0;
863
864 #if 0
865 tgsi_dump(tokens, 0);
866 #endif
867
868 util_init_math();
869
870
871 mach->Tokens = tokens;
872 mach->Sampler = sampler;
873
874 if (!tokens) {
875 /* unbind and free all */
876 FREE(mach->Declarations);
877 mach->Declarations = NULL;
878 mach->NumDeclarations = 0;
879
880 FREE(mach->Instructions);
881 mach->Instructions = NULL;
882 mach->NumInstructions = 0;
883
884 return;
885 }
886
887 k = tgsi_parse_init (&parse, mach->Tokens);
888 if (k != TGSI_PARSE_OK) {
889 debug_printf( "Problem parsing!\n" );
890 return;
891 }
892
893 mach->Processor = parse.FullHeader.Processor.Processor;
894 mach->ImmLimit = 0;
895 mach->NumOutputs = 0;
896
897 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
898 !mach->UsedGeometryShader) {
899 struct tgsi_exec_vector *inputs;
900 struct tgsi_exec_vector *outputs;
901
902 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
903 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
904 16);
905
906 if (!inputs)
907 return;
908
909 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
910 TGSI_MAX_TOTAL_VERTICES, 16);
911
912 if (!outputs) {
913 align_free(inputs);
914 return;
915 }
916
917 align_free(mach->Inputs);
918 align_free(mach->Outputs);
919
920 mach->Inputs = inputs;
921 mach->Outputs = outputs;
922 mach->UsedGeometryShader = TRUE;
923 }
924
925 declarations = (struct tgsi_full_declaration *)
926 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
927
928 if (!declarations) {
929 return;
930 }
931
932 instructions = (struct tgsi_full_instruction *)
933 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
934
935 if (!instructions) {
936 FREE( declarations );
937 return;
938 }
939
940 while( !tgsi_parse_end_of_tokens( &parse ) ) {
941 uint i;
942
943 tgsi_parse_token( &parse );
944 switch( parse.FullToken.Token.Type ) {
945 case TGSI_TOKEN_TYPE_DECLARATION:
946 /* save expanded declaration */
947 if (numDeclarations == maxDeclarations) {
948 declarations = REALLOC(declarations,
949 maxDeclarations
950 * sizeof(struct tgsi_full_declaration),
951 (maxDeclarations + 10)
952 * sizeof(struct tgsi_full_declaration));
953 maxDeclarations += 10;
954 }
955 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
956 unsigned reg;
957 for (reg = parse.FullToken.FullDeclaration.Range.First;
958 reg <= parse.FullToken.FullDeclaration.Range.Last;
959 ++reg) {
960 ++mach->NumOutputs;
961 }
962 }
963 memcpy(declarations + numDeclarations,
964 &parse.FullToken.FullDeclaration,
965 sizeof(declarations[0]));
966 numDeclarations++;
967 break;
968
969 case TGSI_TOKEN_TYPE_IMMEDIATE:
970 {
971 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
972 assert( size <= 4 );
973 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
974
975 for( i = 0; i < size; i++ ) {
976 mach->Imms[mach->ImmLimit][i] =
977 parse.FullToken.FullImmediate.u[i].Float;
978 }
979 mach->ImmLimit += 1;
980 }
981 break;
982
983 case TGSI_TOKEN_TYPE_INSTRUCTION:
984
985 /* save expanded instruction */
986 if (numInstructions == maxInstructions) {
987 instructions = REALLOC(instructions,
988 maxInstructions
989 * sizeof(struct tgsi_full_instruction),
990 (maxInstructions + 10)
991 * sizeof(struct tgsi_full_instruction));
992 maxInstructions += 10;
993 }
994
995 memcpy(instructions + numInstructions,
996 &parse.FullToken.FullInstruction,
997 sizeof(instructions[0]));
998
999 numInstructions++;
1000 break;
1001
1002 case TGSI_TOKEN_TYPE_PROPERTY:
1003 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY) {
1004 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1005 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1006 }
1007 }
1008 break;
1009
1010 default:
1011 assert( 0 );
1012 }
1013 }
1014 tgsi_parse_free (&parse);
1015
1016 FREE(mach->Declarations);
1017 mach->Declarations = declarations;
1018 mach->NumDeclarations = numDeclarations;
1019
1020 FREE(mach->Instructions);
1021 mach->Instructions = instructions;
1022 mach->NumInstructions = numInstructions;
1023 }
1024
1025
1026 struct tgsi_exec_machine *
1027 tgsi_exec_machine_create( void )
1028 {
1029 struct tgsi_exec_machine *mach;
1030 uint i;
1031
1032 mach = align_malloc( sizeof *mach, 16 );
1033 if (!mach)
1034 goto fail;
1035
1036 memset(mach, 0, sizeof(*mach));
1037
1038 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1039 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1040 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
1041
1042 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1043 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1044 if (!mach->Inputs || !mach->Outputs)
1045 goto fail;
1046
1047 /* Setup constants needed by the SSE2 executor. */
1048 for( i = 0; i < 4; i++ ) {
1049 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1050 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1051 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1052 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1053 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1054 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1055 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1056 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1057 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1058 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1059 }
1060
1061 #ifdef DEBUG
1062 /* silence warnings */
1063 (void) print_chan;
1064 (void) print_temp;
1065 #endif
1066
1067 return mach;
1068
1069 fail:
1070 if (mach) {
1071 align_free(mach->Inputs);
1072 align_free(mach->Outputs);
1073 align_free(mach);
1074 }
1075 return NULL;
1076 }
1077
1078
1079 void
1080 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1081 {
1082 if (mach) {
1083 FREE(mach->Instructions);
1084 FREE(mach->Declarations);
1085
1086 align_free(mach->Inputs);
1087 align_free(mach->Outputs);
1088
1089 align_free(mach);
1090 }
1091 }
1092
1093 static void
1094 micro_add(union tgsi_exec_channel *dst,
1095 const union tgsi_exec_channel *src0,
1096 const union tgsi_exec_channel *src1)
1097 {
1098 dst->f[0] = src0->f[0] + src1->f[0];
1099 dst->f[1] = src0->f[1] + src1->f[1];
1100 dst->f[2] = src0->f[2] + src1->f[2];
1101 dst->f[3] = src0->f[3] + src1->f[3];
1102 }
1103
1104 static void
1105 micro_div(
1106 union tgsi_exec_channel *dst,
1107 const union tgsi_exec_channel *src0,
1108 const union tgsi_exec_channel *src1 )
1109 {
1110 if (src1->f[0] != 0) {
1111 dst->f[0] = src0->f[0] / src1->f[0];
1112 }
1113 if (src1->f[1] != 0) {
1114 dst->f[1] = src0->f[1] / src1->f[1];
1115 }
1116 if (src1->f[2] != 0) {
1117 dst->f[2] = src0->f[2] / src1->f[2];
1118 }
1119 if (src1->f[3] != 0) {
1120 dst->f[3] = src0->f[3] / src1->f[3];
1121 }
1122 }
1123
1124 static void
1125 micro_lt(
1126 union tgsi_exec_channel *dst,
1127 const union tgsi_exec_channel *src0,
1128 const union tgsi_exec_channel *src1,
1129 const union tgsi_exec_channel *src2,
1130 const union tgsi_exec_channel *src3 )
1131 {
1132 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1133 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1134 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1135 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1136 }
1137
1138 static void
1139 micro_max(union tgsi_exec_channel *dst,
1140 const union tgsi_exec_channel *src0,
1141 const union tgsi_exec_channel *src1)
1142 {
1143 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1144 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1145 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1146 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1147 }
1148
1149 static void
1150 micro_min(union tgsi_exec_channel *dst,
1151 const union tgsi_exec_channel *src0,
1152 const union tgsi_exec_channel *src1)
1153 {
1154 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1155 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1156 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1157 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1158 }
1159
1160 static void
1161 micro_mul(union tgsi_exec_channel *dst,
1162 const union tgsi_exec_channel *src0,
1163 const union tgsi_exec_channel *src1)
1164 {
1165 dst->f[0] = src0->f[0] * src1->f[0];
1166 dst->f[1] = src0->f[1] * src1->f[1];
1167 dst->f[2] = src0->f[2] * src1->f[2];
1168 dst->f[3] = src0->f[3] * src1->f[3];
1169 }
1170
1171 static void
1172 micro_neg(
1173 union tgsi_exec_channel *dst,
1174 const union tgsi_exec_channel *src )
1175 {
1176 dst->f[0] = -src->f[0];
1177 dst->f[1] = -src->f[1];
1178 dst->f[2] = -src->f[2];
1179 dst->f[3] = -src->f[3];
1180 }
1181
1182 static void
1183 micro_pow(
1184 union tgsi_exec_channel *dst,
1185 const union tgsi_exec_channel *src0,
1186 const union tgsi_exec_channel *src1 )
1187 {
1188 #if FAST_MATH
1189 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1190 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1191 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1192 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1193 #else
1194 dst->f[0] = powf( src0->f[0], src1->f[0] );
1195 dst->f[1] = powf( src0->f[1], src1->f[1] );
1196 dst->f[2] = powf( src0->f[2], src1->f[2] );
1197 dst->f[3] = powf( src0->f[3], src1->f[3] );
1198 #endif
1199 }
1200
1201 static void
1202 micro_sub(union tgsi_exec_channel *dst,
1203 const union tgsi_exec_channel *src0,
1204 const union tgsi_exec_channel *src1)
1205 {
1206 dst->f[0] = src0->f[0] - src1->f[0];
1207 dst->f[1] = src0->f[1] - src1->f[1];
1208 dst->f[2] = src0->f[2] - src1->f[2];
1209 dst->f[3] = src0->f[3] - src1->f[3];
1210 }
1211
1212 static void
1213 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1214 const uint chan_index,
1215 const uint file,
1216 const uint swizzle,
1217 const union tgsi_exec_channel *index,
1218 const union tgsi_exec_channel *index2D,
1219 union tgsi_exec_channel *chan)
1220 {
1221 uint i;
1222
1223 assert(swizzle < 4);
1224
1225 switch (file) {
1226 case TGSI_FILE_CONSTANT:
1227 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1228 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1229 assert(mach->Consts[index2D->i[i]]);
1230
1231 if (index->i[i] < 0) {
1232 chan->u[i] = 0;
1233 } else {
1234 /* NOTE: copying the const value as a uint instead of float */
1235 const uint constbuf = index2D->i[i];
1236 const uint *buf = (const uint *)mach->Consts[constbuf];
1237 const int pos = index->i[i] * 4 + swizzle;
1238 /* const buffer bounds check */
1239 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1240 if (0) {
1241 /* Debug: print warning */
1242 static int count = 0;
1243 if (count++ < 100)
1244 debug_printf("TGSI Exec: const buffer index %d"
1245 " out of bounds\n", pos);
1246 }
1247 chan->u[i] = 0;
1248 }
1249 else
1250 chan->u[i] = buf[pos];
1251 }
1252 }
1253 break;
1254
1255 case TGSI_FILE_INPUT:
1256 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1257 /*
1258 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1259 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1260 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1261 index2D->i[i], index->i[i]);
1262 }*/
1263 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1264 assert(pos >= 0);
1265 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1266 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1267 }
1268 break;
1269
1270 case TGSI_FILE_SYSTEM_VALUE:
1271 /* XXX no swizzling at this point. Will be needed if we put
1272 * gl_FragCoord, for example, in a sys value register.
1273 */
1274 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1275 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1276 }
1277 break;
1278
1279 case TGSI_FILE_TEMPORARY:
1280 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1281 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1282 assert(index2D->i[i] == 0);
1283
1284 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1285 }
1286 break;
1287
1288 case TGSI_FILE_IMMEDIATE:
1289 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1290 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1291 assert(index2D->i[i] == 0);
1292
1293 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1294 }
1295 break;
1296
1297 case TGSI_FILE_ADDRESS:
1298 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1299 assert(index->i[i] >= 0);
1300 assert(index2D->i[i] == 0);
1301
1302 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1303 }
1304 break;
1305
1306 case TGSI_FILE_PREDICATE:
1307 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1308 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1309 assert(index2D->i[i] == 0);
1310
1311 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1312 }
1313 break;
1314
1315 case TGSI_FILE_OUTPUT:
1316 /* vertex/fragment output vars can be read too */
1317 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1318 assert(index->i[i] >= 0);
1319 assert(index2D->i[i] == 0);
1320
1321 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1322 }
1323 break;
1324
1325 default:
1326 assert(0);
1327 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1328 chan->u[i] = 0;
1329 }
1330 }
1331 }
1332
1333 static void
1334 fetch_source_d(const struct tgsi_exec_machine *mach,
1335 union tgsi_exec_channel *chan,
1336 const struct tgsi_full_src_register *reg,
1337 const uint chan_index,
1338 enum tgsi_exec_datatype src_datatype)
1339 {
1340 union tgsi_exec_channel index;
1341 union tgsi_exec_channel index2D;
1342 uint swizzle;
1343
1344 /* We start with a direct index into a register file.
1345 *
1346 * file[1],
1347 * where:
1348 * file = Register.File
1349 * [1] = Register.Index
1350 */
1351 index.i[0] =
1352 index.i[1] =
1353 index.i[2] =
1354 index.i[3] = reg->Register.Index;
1355
1356 /* There is an extra source register that indirectly subscripts
1357 * a register file. The direct index now becomes an offset
1358 * that is being added to the indirect register.
1359 *
1360 * file[ind[2].x+1],
1361 * where:
1362 * ind = Indirect.File
1363 * [2] = Indirect.Index
1364 * .x = Indirect.SwizzleX
1365 */
1366 if (reg->Register.Indirect) {
1367 union tgsi_exec_channel index2;
1368 union tgsi_exec_channel indir_index;
1369 const uint execmask = mach->ExecMask;
1370 uint i;
1371
1372 /* which address register (always zero now) */
1373 index2.i[0] =
1374 index2.i[1] =
1375 index2.i[2] =
1376 index2.i[3] = reg->Indirect.Index;
1377 /* get current value of address register[swizzle] */
1378 swizzle = reg->Indirect.Swizzle;
1379 fetch_src_file_channel(mach,
1380 chan_index,
1381 reg->Indirect.File,
1382 swizzle,
1383 &index2,
1384 &ZeroVec,
1385 &indir_index);
1386
1387 /* add value of address register to the offset */
1388 index.i[0] += indir_index.i[0];
1389 index.i[1] += indir_index.i[1];
1390 index.i[2] += indir_index.i[2];
1391 index.i[3] += indir_index.i[3];
1392
1393 /* for disabled execution channels, zero-out the index to
1394 * avoid using a potential garbage value.
1395 */
1396 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1397 if ((execmask & (1 << i)) == 0)
1398 index.i[i] = 0;
1399 }
1400 }
1401
1402 /* There is an extra source register that is a second
1403 * subscript to a register file. Effectively it means that
1404 * the register file is actually a 2D array of registers.
1405 *
1406 * file[3][1],
1407 * where:
1408 * [3] = Dimension.Index
1409 */
1410 if (reg->Register.Dimension) {
1411 index2D.i[0] =
1412 index2D.i[1] =
1413 index2D.i[2] =
1414 index2D.i[3] = reg->Dimension.Index;
1415
1416 /* Again, the second subscript index can be addressed indirectly
1417 * identically to the first one.
1418 * Nothing stops us from indirectly addressing the indirect register,
1419 * but there is no need for that, so we won't exercise it.
1420 *
1421 * file[ind[4].y+3][1],
1422 * where:
1423 * ind = DimIndirect.File
1424 * [4] = DimIndirect.Index
1425 * .y = DimIndirect.SwizzleX
1426 */
1427 if (reg->Dimension.Indirect) {
1428 union tgsi_exec_channel index2;
1429 union tgsi_exec_channel indir_index;
1430 const uint execmask = mach->ExecMask;
1431 uint i;
1432
1433 index2.i[0] =
1434 index2.i[1] =
1435 index2.i[2] =
1436 index2.i[3] = reg->DimIndirect.Index;
1437
1438 swizzle = reg->DimIndirect.Swizzle;
1439 fetch_src_file_channel(mach,
1440 chan_index,
1441 reg->DimIndirect.File,
1442 swizzle,
1443 &index2,
1444 &ZeroVec,
1445 &indir_index);
1446
1447 index2D.i[0] += indir_index.i[0];
1448 index2D.i[1] += indir_index.i[1];
1449 index2D.i[2] += indir_index.i[2];
1450 index2D.i[3] += indir_index.i[3];
1451
1452 /* for disabled execution channels, zero-out the index to
1453 * avoid using a potential garbage value.
1454 */
1455 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1456 if ((execmask & (1 << i)) == 0) {
1457 index2D.i[i] = 0;
1458 }
1459 }
1460 }
1461
1462 /* If by any chance there was a need for a 3D array of register
1463 * files, we would have to check whether Dimension is followed
1464 * by a dimension register and continue the saga.
1465 */
1466 } else {
1467 index2D.i[0] =
1468 index2D.i[1] =
1469 index2D.i[2] =
1470 index2D.i[3] = 0;
1471 }
1472
1473 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1474 fetch_src_file_channel(mach,
1475 chan_index,
1476 reg->Register.File,
1477 swizzle,
1478 &index,
1479 &index2D,
1480 chan);
1481 }
1482
1483 static void
1484 fetch_source(const struct tgsi_exec_machine *mach,
1485 union tgsi_exec_channel *chan,
1486 const struct tgsi_full_src_register *reg,
1487 const uint chan_index,
1488 enum tgsi_exec_datatype src_datatype)
1489 {
1490 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1491
1492 if (reg->Register.Absolute) {
1493 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1494 micro_abs(chan, chan);
1495 } else {
1496 micro_iabs(chan, chan);
1497 }
1498 }
1499
1500 if (reg->Register.Negate) {
1501 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1502 micro_neg(chan, chan);
1503 } else {
1504 micro_ineg(chan, chan);
1505 }
1506 }
1507 }
1508
1509 static union tgsi_exec_channel *
1510 store_dest_dstret(struct tgsi_exec_machine *mach,
1511 const union tgsi_exec_channel *chan,
1512 const struct tgsi_full_dst_register *reg,
1513 const struct tgsi_full_instruction *inst,
1514 uint chan_index,
1515 enum tgsi_exec_datatype dst_datatype)
1516 {
1517 uint i;
1518 static union tgsi_exec_channel null;
1519 union tgsi_exec_channel *dst;
1520 union tgsi_exec_channel index2D;
1521 uint execmask = mach->ExecMask;
1522 int offset = 0; /* indirection offset */
1523 int index;
1524
1525 /* for debugging */
1526 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1527 check_inf_or_nan(chan);
1528 }
1529
1530 /* There is an extra source register that indirectly subscripts
1531 * a register file. The direct index now becomes an offset
1532 * that is being added to the indirect register.
1533 *
1534 * file[ind[2].x+1],
1535 * where:
1536 * ind = Indirect.File
1537 * [2] = Indirect.Index
1538 * .x = Indirect.SwizzleX
1539 */
1540 if (reg->Register.Indirect) {
1541 union tgsi_exec_channel index;
1542 union tgsi_exec_channel indir_index;
1543 uint swizzle;
1544
1545 /* which address register (always zero for now) */
1546 index.i[0] =
1547 index.i[1] =
1548 index.i[2] =
1549 index.i[3] = reg->Indirect.Index;
1550
1551 /* get current value of address register[swizzle] */
1552 swizzle = reg->Indirect.Swizzle;
1553
1554 /* fetch values from the address/indirection register */
1555 fetch_src_file_channel(mach,
1556 chan_index,
1557 reg->Indirect.File,
1558 swizzle,
1559 &index,
1560 &ZeroVec,
1561 &indir_index);
1562
1563 /* save indirection offset */
1564 offset = indir_index.i[0];
1565 }
1566
1567 /* There is an extra source register that is a second
1568 * subscript to a register file. Effectively it means that
1569 * the register file is actually a 2D array of registers.
1570 *
1571 * file[3][1],
1572 * where:
1573 * [3] = Dimension.Index
1574 */
1575 if (reg->Register.Dimension) {
1576 index2D.i[0] =
1577 index2D.i[1] =
1578 index2D.i[2] =
1579 index2D.i[3] = reg->Dimension.Index;
1580
1581 /* Again, the second subscript index can be addressed indirectly
1582 * identically to the first one.
1583 * Nothing stops us from indirectly addressing the indirect register,
1584 * but there is no need for that, so we won't exercise it.
1585 *
1586 * file[ind[4].y+3][1],
1587 * where:
1588 * ind = DimIndirect.File
1589 * [4] = DimIndirect.Index
1590 * .y = DimIndirect.SwizzleX
1591 */
1592 if (reg->Dimension.Indirect) {
1593 union tgsi_exec_channel index2;
1594 union tgsi_exec_channel indir_index;
1595 const uint execmask = mach->ExecMask;
1596 unsigned swizzle;
1597 uint i;
1598
1599 index2.i[0] =
1600 index2.i[1] =
1601 index2.i[2] =
1602 index2.i[3] = reg->DimIndirect.Index;
1603
1604 swizzle = reg->DimIndirect.Swizzle;
1605 fetch_src_file_channel(mach,
1606 chan_index,
1607 reg->DimIndirect.File,
1608 swizzle,
1609 &index2,
1610 &ZeroVec,
1611 &indir_index);
1612
1613 index2D.i[0] += indir_index.i[0];
1614 index2D.i[1] += indir_index.i[1];
1615 index2D.i[2] += indir_index.i[2];
1616 index2D.i[3] += indir_index.i[3];
1617
1618 /* for disabled execution channels, zero-out the index to
1619 * avoid using a potential garbage value.
1620 */
1621 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1622 if ((execmask & (1 << i)) == 0) {
1623 index2D.i[i] = 0;
1624 }
1625 }
1626 }
1627
1628 /* If by any chance there was a need for a 3D array of register
1629 * files, we would have to check whether Dimension is followed
1630 * by a dimension register and continue the saga.
1631 */
1632 } else {
1633 index2D.i[0] =
1634 index2D.i[1] =
1635 index2D.i[2] =
1636 index2D.i[3] = 0;
1637 }
1638
1639 switch (reg->Register.File) {
1640 case TGSI_FILE_NULL:
1641 dst = &null;
1642 break;
1643
1644 case TGSI_FILE_OUTPUT:
1645 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1646 + reg->Register.Index;
1647 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1648 #if 0
1649 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1650 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1651 reg->Register.Index);
1652 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1653 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1654 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1655 if (execmask & (1 << i))
1656 debug_printf("%f, ", chan->f[i]);
1657 debug_printf(")\n");
1658 }
1659 #endif
1660 break;
1661
1662 case TGSI_FILE_TEMPORARY:
1663 index = reg->Register.Index;
1664 assert( index < TGSI_EXEC_NUM_TEMPS );
1665 dst = &mach->Temps[offset + index].xyzw[chan_index];
1666 break;
1667
1668 case TGSI_FILE_ADDRESS:
1669 index = reg->Register.Index;
1670 dst = &mach->Addrs[index].xyzw[chan_index];
1671 break;
1672
1673 case TGSI_FILE_PREDICATE:
1674 index = reg->Register.Index;
1675 assert(index < TGSI_EXEC_NUM_PREDS);
1676 dst = &mach->Predicates[index].xyzw[chan_index];
1677 break;
1678
1679 default:
1680 assert( 0 );
1681 return NULL;
1682 }
1683
1684 if (inst->Instruction.Predicate) {
1685 uint swizzle;
1686 union tgsi_exec_channel *pred;
1687
1688 switch (chan_index) {
1689 case TGSI_CHAN_X:
1690 swizzle = inst->Predicate.SwizzleX;
1691 break;
1692 case TGSI_CHAN_Y:
1693 swizzle = inst->Predicate.SwizzleY;
1694 break;
1695 case TGSI_CHAN_Z:
1696 swizzle = inst->Predicate.SwizzleZ;
1697 break;
1698 case TGSI_CHAN_W:
1699 swizzle = inst->Predicate.SwizzleW;
1700 break;
1701 default:
1702 assert(0);
1703 return NULL;
1704 }
1705
1706 assert(inst->Predicate.Index == 0);
1707
1708 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1709
1710 if (inst->Predicate.Negate) {
1711 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1712 if (pred->u[i]) {
1713 execmask &= ~(1 << i);
1714 }
1715 }
1716 } else {
1717 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1718 if (!pred->u[i]) {
1719 execmask &= ~(1 << i);
1720 }
1721 }
1722 }
1723 }
1724
1725 return dst;
1726 }
1727
1728 static void
1729 store_dest_double(struct tgsi_exec_machine *mach,
1730 const union tgsi_exec_channel *chan,
1731 const struct tgsi_full_dst_register *reg,
1732 const struct tgsi_full_instruction *inst,
1733 uint chan_index,
1734 enum tgsi_exec_datatype dst_datatype)
1735 {
1736 union tgsi_exec_channel *dst;
1737 const uint execmask = mach->ExecMask;
1738 int i;
1739
1740 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1741 dst_datatype);
1742 if (!dst)
1743 return;
1744
1745 /* doubles path */
1746 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1747 if (execmask & (1 << i))
1748 dst->i[i] = chan->i[i];
1749 }
1750
1751 static void
1752 store_dest(struct tgsi_exec_machine *mach,
1753 const union tgsi_exec_channel *chan,
1754 const struct tgsi_full_dst_register *reg,
1755 const struct tgsi_full_instruction *inst,
1756 uint chan_index,
1757 enum tgsi_exec_datatype dst_datatype)
1758 {
1759 union tgsi_exec_channel *dst;
1760 const uint execmask = mach->ExecMask;
1761 int i;
1762
1763 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1764 dst_datatype);
1765 if (!dst)
1766 return;
1767
1768 switch (inst->Instruction.Saturate) {
1769 case TGSI_SAT_NONE:
1770 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1771 if (execmask & (1 << i))
1772 dst->i[i] = chan->i[i];
1773 break;
1774
1775 case TGSI_SAT_ZERO_ONE:
1776 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1777 if (execmask & (1 << i)) {
1778 if (chan->f[i] < 0.0f)
1779 dst->f[i] = 0.0f;
1780 else if (chan->f[i] > 1.0f)
1781 dst->f[i] = 1.0f;
1782 else
1783 dst->i[i] = chan->i[i];
1784 }
1785 break;
1786
1787 case TGSI_SAT_MINUS_PLUS_ONE:
1788 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1789 if (execmask & (1 << i)) {
1790 if (chan->f[i] < -1.0f)
1791 dst->f[i] = -1.0f;
1792 else if (chan->f[i] > 1.0f)
1793 dst->f[i] = 1.0f;
1794 else
1795 dst->i[i] = chan->i[i];
1796 }
1797 break;
1798
1799 default:
1800 assert( 0 );
1801 }
1802 }
1803
1804 #define FETCH(VAL,INDEX,CHAN)\
1805 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1806
1807 #define IFETCH(VAL,INDEX,CHAN)\
1808 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1809
1810
1811 /**
1812 * Execute ARB-style KIL which is predicated by a src register.
1813 * Kill fragment if any of the four values is less than zero.
1814 */
1815 static void
1816 exec_kill_if(struct tgsi_exec_machine *mach,
1817 const struct tgsi_full_instruction *inst)
1818 {
1819 uint uniquemask;
1820 uint chan_index;
1821 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1822 union tgsi_exec_channel r[1];
1823
1824 /* This mask stores component bits that were already tested. */
1825 uniquemask = 0;
1826
1827 for (chan_index = 0; chan_index < 4; chan_index++)
1828 {
1829 uint swizzle;
1830 uint i;
1831
1832 /* unswizzle channel */
1833 swizzle = tgsi_util_get_full_src_register_swizzle (
1834 &inst->Src[0],
1835 chan_index);
1836
1837 /* check if the component has not been already tested */
1838 if (uniquemask & (1 << swizzle))
1839 continue;
1840 uniquemask |= 1 << swizzle;
1841
1842 FETCH(&r[0], 0, chan_index);
1843 for (i = 0; i < 4; i++)
1844 if (r[0].f[i] < 0.0f)
1845 kilmask |= 1 << i;
1846 }
1847
1848 /* restrict to fragments currently executing */
1849 kilmask &= mach->ExecMask;
1850
1851 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1852 }
1853
1854 /**
1855 * Unconditional fragment kill/discard.
1856 */
1857 static void
1858 exec_kill(struct tgsi_exec_machine *mach,
1859 const struct tgsi_full_instruction *inst)
1860 {
1861 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1862
1863 /* kill fragment for all fragments currently executing */
1864 kilmask = mach->ExecMask;
1865 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1866 }
1867
1868 static void
1869 emit_vertex(struct tgsi_exec_machine *mach)
1870 {
1871 /* FIXME: check for exec mask correctly
1872 unsigned i;
1873 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1874 if ((mach->ExecMask & (1 << i)))
1875 */
1876 if (mach->ExecMask) {
1877 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1878 return;
1879
1880 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1881 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1882 }
1883 }
1884
1885 static void
1886 emit_primitive(struct tgsi_exec_machine *mach)
1887 {
1888 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1889 /* FIXME: check for exec mask correctly
1890 unsigned i;
1891 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1892 if ((mach->ExecMask & (1 << i)))
1893 */
1894 if (mach->ExecMask) {
1895 ++(*prim_count);
1896 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1897 mach->Primitives[*prim_count] = 0;
1898 }
1899 }
1900
1901 static void
1902 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1903 {
1904 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1905 int emitted_verts =
1906 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1907 if (emitted_verts) {
1908 emit_primitive(mach);
1909 }
1910 }
1911 }
1912
1913
1914 /*
1915 * Fetch four texture samples using STR texture coordinates.
1916 */
1917 static void
1918 fetch_texel( struct tgsi_sampler *sampler,
1919 const unsigned sview_idx,
1920 const unsigned sampler_idx,
1921 const union tgsi_exec_channel *s,
1922 const union tgsi_exec_channel *t,
1923 const union tgsi_exec_channel *p,
1924 const union tgsi_exec_channel *c0,
1925 const union tgsi_exec_channel *c1,
1926 float derivs[3][2][TGSI_QUAD_SIZE],
1927 const int8_t offset[3],
1928 enum tgsi_sampler_control control,
1929 union tgsi_exec_channel *r,
1930 union tgsi_exec_channel *g,
1931 union tgsi_exec_channel *b,
1932 union tgsi_exec_channel *a )
1933 {
1934 uint j;
1935 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1936
1937 /* FIXME: handle explicit derivs, offsets */
1938 sampler->get_samples(sampler, sview_idx, sampler_idx,
1939 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1940
1941 for (j = 0; j < 4; j++) {
1942 r->f[j] = rgba[0][j];
1943 g->f[j] = rgba[1][j];
1944 b->f[j] = rgba[2][j];
1945 a->f[j] = rgba[3][j];
1946 }
1947 }
1948
1949
1950 #define TEX_MODIFIER_NONE 0
1951 #define TEX_MODIFIER_PROJECTED 1
1952 #define TEX_MODIFIER_LOD_BIAS 2
1953 #define TEX_MODIFIER_EXPLICIT_LOD 3
1954 #define TEX_MODIFIER_LEVEL_ZERO 4
1955 #define TEX_MODIFIER_GATHER 5
1956
1957 /*
1958 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1959 */
1960 static void
1961 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1962 const struct tgsi_full_instruction *inst,
1963 int8_t offsets[3])
1964 {
1965 if (inst->Texture.NumOffsets == 1) {
1966 union tgsi_exec_channel index;
1967 union tgsi_exec_channel offset[3];
1968 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1969 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1970 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1971 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1972 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1973 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1974 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1975 offsets[0] = offset[0].i[0];
1976 offsets[1] = offset[1].i[0];
1977 offsets[2] = offset[2].i[0];
1978 } else {
1979 assert(inst->Texture.NumOffsets == 0);
1980 offsets[0] = offsets[1] = offsets[2] = 0;
1981 }
1982 }
1983
1984
1985 /*
1986 * Fetch dx and dy values for one channel (s, t or r).
1987 * Put dx values into one float array, dy values into another.
1988 */
1989 static void
1990 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1991 const struct tgsi_full_instruction *inst,
1992 unsigned regdsrcx,
1993 unsigned chan,
1994 float derivs[2][TGSI_QUAD_SIZE])
1995 {
1996 union tgsi_exec_channel d;
1997 FETCH(&d, regdsrcx, chan);
1998 derivs[0][0] = d.f[0];
1999 derivs[0][1] = d.f[1];
2000 derivs[0][2] = d.f[2];
2001 derivs[0][3] = d.f[3];
2002 FETCH(&d, regdsrcx + 1, chan);
2003 derivs[1][0] = d.f[0];
2004 derivs[1][1] = d.f[1];
2005 derivs[1][2] = d.f[2];
2006 derivs[1][3] = d.f[3];
2007 }
2008
2009
2010 /*
2011 * execute a texture instruction.
2012 *
2013 * modifier is used to control the channel routing for the\
2014 * instruction variants like proj, lod, and texture with lod bias.
2015 * sampler indicates which src register the sampler is contained in.
2016 */
2017 static void
2018 exec_tex(struct tgsi_exec_machine *mach,
2019 const struct tgsi_full_instruction *inst,
2020 uint modifier, uint sampler)
2021 {
2022 const uint unit = inst->Src[sampler].Register.Index;
2023 const union tgsi_exec_channel *args[5], *proj = NULL;
2024 union tgsi_exec_channel r[5];
2025 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2026 uint chan;
2027 int8_t offsets[3];
2028 int dim, shadow_ref, i;
2029
2030 /* always fetch all 3 offsets, overkill but keeps code simple */
2031 fetch_texel_offsets(mach, inst, offsets);
2032
2033 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2034 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2035
2036 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
2037
2038 assert(dim <= 4);
2039 if (shadow_ref >= 0)
2040 assert(shadow_ref >= dim && shadow_ref < Elements(args));
2041
2042 /* fetch modifier to the last argument */
2043 if (modifier != TEX_MODIFIER_NONE) {
2044 const int last = Elements(args) - 1;
2045
2046 /* fetch modifier from src0.w or src1.x */
2047 if (sampler == 1) {
2048 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2049 FETCH(&r[last], 0, TGSI_CHAN_W);
2050 }
2051 else {
2052 assert(shadow_ref != 4);
2053 FETCH(&r[last], 1, TGSI_CHAN_X);
2054 }
2055
2056 if (modifier != TEX_MODIFIER_PROJECTED) {
2057 args[last] = &r[last];
2058 }
2059 else {
2060 proj = &r[last];
2061 args[last] = &ZeroVec;
2062 }
2063
2064 /* point unused arguments to zero vector */
2065 for (i = dim; i < last; i++)
2066 args[i] = &ZeroVec;
2067
2068 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2069 control = tgsi_sampler_lod_explicit;
2070 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2071 control = tgsi_sampler_lod_bias;
2072 else if (modifier == TEX_MODIFIER_GATHER)
2073 control = tgsi_sampler_gather;
2074 }
2075 else {
2076 for (i = dim; i < Elements(args); i++)
2077 args[i] = &ZeroVec;
2078 }
2079
2080 /* fetch coordinates */
2081 for (i = 0; i < dim; i++) {
2082 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2083
2084 if (proj)
2085 micro_div(&r[i], &r[i], proj);
2086
2087 args[i] = &r[i];
2088 }
2089
2090 /* fetch reference value */
2091 if (shadow_ref >= 0) {
2092 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2093
2094 if (proj)
2095 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2096
2097 args[shadow_ref] = &r[shadow_ref];
2098 }
2099
2100 fetch_texel(mach->Sampler, unit, unit,
2101 args[0], args[1], args[2], args[3], args[4],
2102 NULL, offsets, control,
2103 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2104
2105 #if 0
2106 debug_printf("fetch r: %g %g %g %g\n",
2107 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2108 debug_printf("fetch g: %g %g %g %g\n",
2109 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2110 debug_printf("fetch b: %g %g %g %g\n",
2111 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2112 debug_printf("fetch a: %g %g %g %g\n",
2113 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2114 #endif
2115
2116 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2117 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2118 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2119 }
2120 }
2121 }
2122
2123
2124 static void
2125 exec_txd(struct tgsi_exec_machine *mach,
2126 const struct tgsi_full_instruction *inst)
2127 {
2128 const uint unit = inst->Src[3].Register.Index;
2129 union tgsi_exec_channel r[4];
2130 float derivs[3][2][TGSI_QUAD_SIZE];
2131 uint chan;
2132 int8_t offsets[3];
2133
2134 /* always fetch all 3 offsets, overkill but keeps code simple */
2135 fetch_texel_offsets(mach, inst, offsets);
2136
2137 switch (inst->Texture.Texture) {
2138 case TGSI_TEXTURE_1D:
2139 FETCH(&r[0], 0, TGSI_CHAN_X);
2140
2141 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2142
2143 fetch_texel(mach->Sampler, unit, unit,
2144 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2145 derivs, offsets, tgsi_sampler_derivs_explicit,
2146 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2147 break;
2148
2149 case TGSI_TEXTURE_SHADOW1D:
2150 case TGSI_TEXTURE_1D_ARRAY:
2151 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2152 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2153 FETCH(&r[0], 0, TGSI_CHAN_X);
2154 FETCH(&r[1], 0, TGSI_CHAN_Y);
2155 FETCH(&r[2], 0, TGSI_CHAN_Z);
2156
2157 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2158
2159 fetch_texel(mach->Sampler, unit, unit,
2160 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2161 derivs, offsets, tgsi_sampler_derivs_explicit,
2162 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2163 break;
2164
2165 case TGSI_TEXTURE_2D:
2166 case TGSI_TEXTURE_RECT:
2167 FETCH(&r[0], 0, TGSI_CHAN_X);
2168 FETCH(&r[1], 0, TGSI_CHAN_Y);
2169
2170 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2171 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2172
2173 fetch_texel(mach->Sampler, unit, unit,
2174 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2175 derivs, offsets, tgsi_sampler_derivs_explicit,
2176 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2177 break;
2178
2179
2180 case TGSI_TEXTURE_SHADOW2D:
2181 case TGSI_TEXTURE_SHADOWRECT:
2182 case TGSI_TEXTURE_2D_ARRAY:
2183 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2184 /* only SHADOW2D_ARRAY actually needs W */
2185 FETCH(&r[0], 0, TGSI_CHAN_X);
2186 FETCH(&r[1], 0, TGSI_CHAN_Y);
2187 FETCH(&r[2], 0, TGSI_CHAN_Z);
2188 FETCH(&r[3], 0, TGSI_CHAN_W);
2189
2190 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2191 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2192
2193 fetch_texel(mach->Sampler, unit, unit,
2194 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2195 derivs, offsets, tgsi_sampler_derivs_explicit,
2196 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2197 break;
2198
2199 case TGSI_TEXTURE_3D:
2200 case TGSI_TEXTURE_CUBE:
2201 case TGSI_TEXTURE_CUBE_ARRAY:
2202 case TGSI_TEXTURE_SHADOWCUBE:
2203 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2204 FETCH(&r[0], 0, TGSI_CHAN_X);
2205 FETCH(&r[1], 0, TGSI_CHAN_Y);
2206 FETCH(&r[2], 0, TGSI_CHAN_Z);
2207 FETCH(&r[3], 0, TGSI_CHAN_W);
2208
2209 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2210 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2211 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2212
2213 fetch_texel(mach->Sampler, unit, unit,
2214 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2215 derivs, offsets, tgsi_sampler_derivs_explicit,
2216 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2217 break;
2218
2219 default:
2220 assert(0);
2221 }
2222
2223 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2224 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2225 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2226 }
2227 }
2228 }
2229
2230
2231 static void
2232 exec_txf(struct tgsi_exec_machine *mach,
2233 const struct tgsi_full_instruction *inst)
2234 {
2235 const uint unit = inst->Src[1].Register.Index;
2236 union tgsi_exec_channel r[4];
2237 uint chan;
2238 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2239 int j;
2240 int8_t offsets[3];
2241 unsigned target;
2242
2243 /* always fetch all 3 offsets, overkill but keeps code simple */
2244 fetch_texel_offsets(mach, inst, offsets);
2245
2246 IFETCH(&r[3], 0, TGSI_CHAN_W);
2247
2248 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2249 target = mach->SamplerViews[unit].Resource;
2250 }
2251 else {
2252 target = inst->Texture.Texture;
2253 }
2254 switch(target) {
2255 case TGSI_TEXTURE_3D:
2256 case TGSI_TEXTURE_2D_ARRAY:
2257 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2258 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2259 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2260 /* fallthrough */
2261 case TGSI_TEXTURE_2D:
2262 case TGSI_TEXTURE_RECT:
2263 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2264 case TGSI_TEXTURE_SHADOW2D:
2265 case TGSI_TEXTURE_SHADOWRECT:
2266 case TGSI_TEXTURE_1D_ARRAY:
2267 case TGSI_TEXTURE_2D_MSAA:
2268 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2269 /* fallthrough */
2270 case TGSI_TEXTURE_BUFFER:
2271 case TGSI_TEXTURE_1D:
2272 case TGSI_TEXTURE_SHADOW1D:
2273 IFETCH(&r[0], 0, TGSI_CHAN_X);
2274 break;
2275 default:
2276 assert(0);
2277 break;
2278 }
2279
2280 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2281 offsets, rgba);
2282
2283 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2284 r[0].f[j] = rgba[0][j];
2285 r[1].f[j] = rgba[1][j];
2286 r[2].f[j] = rgba[2][j];
2287 r[3].f[j] = rgba[3][j];
2288 }
2289
2290 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2291 unsigned char swizzles[4];
2292 swizzles[0] = inst->Src[1].Register.SwizzleX;
2293 swizzles[1] = inst->Src[1].Register.SwizzleY;
2294 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2295 swizzles[3] = inst->Src[1].Register.SwizzleW;
2296
2297 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2298 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2299 store_dest(mach, &r[swizzles[chan]],
2300 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2301 }
2302 }
2303 }
2304 else {
2305 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2306 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2307 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2308 }
2309 }
2310 }
2311 }
2312
2313 static void
2314 exec_txq(struct tgsi_exec_machine *mach,
2315 const struct tgsi_full_instruction *inst)
2316 {
2317 const uint unit = inst->Src[1].Register.Index;
2318 int result[4];
2319 union tgsi_exec_channel r[4], src;
2320 uint chan;
2321 int i,j;
2322
2323 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2324
2325 /* XXX: This interface can't return per-pixel values */
2326 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2327
2328 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2329 for (j = 0; j < 4; j++) {
2330 r[j].i[i] = result[j];
2331 }
2332 }
2333
2334 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2335 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2336 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2337 TGSI_EXEC_DATA_INT);
2338 }
2339 }
2340 }
2341
2342 static void
2343 exec_sample(struct tgsi_exec_machine *mach,
2344 const struct tgsi_full_instruction *inst,
2345 uint modifier, boolean compare)
2346 {
2347 const uint resource_unit = inst->Src[1].Register.Index;
2348 const uint sampler_unit = inst->Src[2].Register.Index;
2349 union tgsi_exec_channel r[5], c1;
2350 const union tgsi_exec_channel *lod = &ZeroVec;
2351 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2352 uint chan;
2353 unsigned char swizzles[4];
2354 int8_t offsets[3];
2355
2356 /* always fetch all 3 offsets, overkill but keeps code simple */
2357 fetch_texel_offsets(mach, inst, offsets);
2358
2359 assert(modifier != TEX_MODIFIER_PROJECTED);
2360
2361 if (modifier != TEX_MODIFIER_NONE) {
2362 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2363 FETCH(&c1, 3, TGSI_CHAN_X);
2364 lod = &c1;
2365 control = tgsi_sampler_lod_bias;
2366 }
2367 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2368 FETCH(&c1, 3, TGSI_CHAN_X);
2369 lod = &c1;
2370 control = tgsi_sampler_lod_explicit;
2371 }
2372 else {
2373 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2374 control = tgsi_sampler_lod_zero;
2375 }
2376 }
2377
2378 FETCH(&r[0], 0, TGSI_CHAN_X);
2379
2380 switch (mach->SamplerViews[resource_unit].Resource) {
2381 case TGSI_TEXTURE_1D:
2382 if (compare) {
2383 FETCH(&r[2], 3, TGSI_CHAN_X);
2384 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2385 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2386 NULL, offsets, control,
2387 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2388 }
2389 else {
2390 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2391 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2392 NULL, offsets, control,
2393 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2394 }
2395 break;
2396
2397 case TGSI_TEXTURE_1D_ARRAY:
2398 case TGSI_TEXTURE_2D:
2399 case TGSI_TEXTURE_RECT:
2400 FETCH(&r[1], 0, TGSI_CHAN_Y);
2401 if (compare) {
2402 FETCH(&r[2], 3, TGSI_CHAN_X);
2403 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2404 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2405 NULL, offsets, control,
2406 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2407 }
2408 else {
2409 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2410 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2411 NULL, offsets, control,
2412 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2413 }
2414 break;
2415
2416 case TGSI_TEXTURE_2D_ARRAY:
2417 case TGSI_TEXTURE_3D:
2418 case TGSI_TEXTURE_CUBE:
2419 FETCH(&r[1], 0, TGSI_CHAN_Y);
2420 FETCH(&r[2], 0, TGSI_CHAN_Z);
2421 if(compare) {
2422 FETCH(&r[3], 3, TGSI_CHAN_X);
2423 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2424 &r[0], &r[1], &r[2], &r[3], lod,
2425 NULL, offsets, control,
2426 &r[0], &r[1], &r[2], &r[3]);
2427 }
2428 else {
2429 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2430 &r[0], &r[1], &r[2], &ZeroVec, lod,
2431 NULL, offsets, control,
2432 &r[0], &r[1], &r[2], &r[3]);
2433 }
2434 break;
2435
2436 case TGSI_TEXTURE_CUBE_ARRAY:
2437 FETCH(&r[1], 0, TGSI_CHAN_Y);
2438 FETCH(&r[2], 0, TGSI_CHAN_Z);
2439 FETCH(&r[3], 0, TGSI_CHAN_W);
2440 if(compare) {
2441 FETCH(&r[4], 3, TGSI_CHAN_X);
2442 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2443 &r[0], &r[1], &r[2], &r[3], &r[4],
2444 NULL, offsets, control,
2445 &r[0], &r[1], &r[2], &r[3]);
2446 }
2447 else {
2448 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2449 &r[0], &r[1], &r[2], &r[3], lod,
2450 NULL, offsets, control,
2451 &r[0], &r[1], &r[2], &r[3]);
2452 }
2453 break;
2454
2455
2456 default:
2457 assert(0);
2458 }
2459
2460 swizzles[0] = inst->Src[1].Register.SwizzleX;
2461 swizzles[1] = inst->Src[1].Register.SwizzleY;
2462 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2463 swizzles[3] = inst->Src[1].Register.SwizzleW;
2464
2465 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2466 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2467 store_dest(mach, &r[swizzles[chan]],
2468 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2469 }
2470 }
2471 }
2472
2473 static void
2474 exec_sample_d(struct tgsi_exec_machine *mach,
2475 const struct tgsi_full_instruction *inst)
2476 {
2477 const uint resource_unit = inst->Src[1].Register.Index;
2478 const uint sampler_unit = inst->Src[2].Register.Index;
2479 union tgsi_exec_channel r[4];
2480 float derivs[3][2][TGSI_QUAD_SIZE];
2481 uint chan;
2482 unsigned char swizzles[4];
2483 int8_t offsets[3];
2484
2485 /* always fetch all 3 offsets, overkill but keeps code simple */
2486 fetch_texel_offsets(mach, inst, offsets);
2487
2488 FETCH(&r[0], 0, TGSI_CHAN_X);
2489
2490 switch (mach->SamplerViews[resource_unit].Resource) {
2491 case TGSI_TEXTURE_1D:
2492 case TGSI_TEXTURE_1D_ARRAY:
2493 /* only 1D array actually needs Y */
2494 FETCH(&r[1], 0, TGSI_CHAN_Y);
2495
2496 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2497
2498 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2499 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2500 derivs, offsets, tgsi_sampler_derivs_explicit,
2501 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2502 break;
2503
2504 case TGSI_TEXTURE_2D:
2505 case TGSI_TEXTURE_RECT:
2506 case TGSI_TEXTURE_2D_ARRAY:
2507 /* only 2D array actually needs Z */
2508 FETCH(&r[1], 0, TGSI_CHAN_Y);
2509 FETCH(&r[2], 0, TGSI_CHAN_Z);
2510
2511 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2512 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2513
2514 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2515 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2516 derivs, offsets, tgsi_sampler_derivs_explicit,
2517 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2518 break;
2519
2520 case TGSI_TEXTURE_3D:
2521 case TGSI_TEXTURE_CUBE:
2522 case TGSI_TEXTURE_CUBE_ARRAY:
2523 /* only cube array actually needs W */
2524 FETCH(&r[1], 0, TGSI_CHAN_Y);
2525 FETCH(&r[2], 0, TGSI_CHAN_Z);
2526 FETCH(&r[3], 0, TGSI_CHAN_W);
2527
2528 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2529 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2530 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2531
2532 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2533 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2534 derivs, offsets, tgsi_sampler_derivs_explicit,
2535 &r[0], &r[1], &r[2], &r[3]);
2536 break;
2537
2538 default:
2539 assert(0);
2540 }
2541
2542 swizzles[0] = inst->Src[1].Register.SwizzleX;
2543 swizzles[1] = inst->Src[1].Register.SwizzleY;
2544 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2545 swizzles[3] = inst->Src[1].Register.SwizzleW;
2546
2547 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2548 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2549 store_dest(mach, &r[swizzles[chan]],
2550 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2551 }
2552 }
2553 }
2554
2555
2556 /**
2557 * Evaluate a constant-valued coefficient at the position of the
2558 * current quad.
2559 */
2560 static void
2561 eval_constant_coef(
2562 struct tgsi_exec_machine *mach,
2563 unsigned attrib,
2564 unsigned chan )
2565 {
2566 unsigned i;
2567
2568 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2569 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2570 }
2571 }
2572
2573 /**
2574 * Evaluate a linear-valued coefficient at the position of the
2575 * current quad.
2576 */
2577 static void
2578 eval_linear_coef(
2579 struct tgsi_exec_machine *mach,
2580 unsigned attrib,
2581 unsigned chan )
2582 {
2583 const float x = mach->QuadPos.xyzw[0].f[0];
2584 const float y = mach->QuadPos.xyzw[1].f[0];
2585 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2586 const float dady = mach->InterpCoefs[attrib].dady[chan];
2587 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2588 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2589 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2590 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2591 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2592 }
2593
2594 /**
2595 * Evaluate a perspective-valued coefficient at the position of the
2596 * current quad.
2597 */
2598 static void
2599 eval_perspective_coef(
2600 struct tgsi_exec_machine *mach,
2601 unsigned attrib,
2602 unsigned chan )
2603 {
2604 const float x = mach->QuadPos.xyzw[0].f[0];
2605 const float y = mach->QuadPos.xyzw[1].f[0];
2606 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2607 const float dady = mach->InterpCoefs[attrib].dady[chan];
2608 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2609 const float *w = mach->QuadPos.xyzw[3].f;
2610 /* divide by W here */
2611 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2612 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2613 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2614 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2615 }
2616
2617
2618 typedef void (* eval_coef_func)(
2619 struct tgsi_exec_machine *mach,
2620 unsigned attrib,
2621 unsigned chan );
2622
2623 static void
2624 exec_declaration(struct tgsi_exec_machine *mach,
2625 const struct tgsi_full_declaration *decl)
2626 {
2627 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2628 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2629 return;
2630 }
2631
2632 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2633 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2634 uint first, last, mask;
2635
2636 first = decl->Range.First;
2637 last = decl->Range.Last;
2638 mask = decl->Declaration.UsageMask;
2639
2640 /* XXX we could remove this special-case code since
2641 * mach->InterpCoefs[first].a0 should already have the
2642 * front/back-face value. But we should first update the
2643 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2644 * Then, we could remove the tgsi_exec_machine::Face field.
2645 */
2646 /* XXX make FACE a system value */
2647 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2648 uint i;
2649
2650 assert(decl->Semantic.Index == 0);
2651 assert(first == last);
2652
2653 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2654 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2655 }
2656 } else {
2657 eval_coef_func eval;
2658 uint i, j;
2659
2660 switch (decl->Interp.Interpolate) {
2661 case TGSI_INTERPOLATE_CONSTANT:
2662 eval = eval_constant_coef;
2663 break;
2664
2665 case TGSI_INTERPOLATE_LINEAR:
2666 eval = eval_linear_coef;
2667 break;
2668
2669 case TGSI_INTERPOLATE_PERSPECTIVE:
2670 eval = eval_perspective_coef;
2671 break;
2672
2673 case TGSI_INTERPOLATE_COLOR:
2674 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2675 break;
2676
2677 default:
2678 assert(0);
2679 return;
2680 }
2681
2682 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2683 if (mask & (1 << j)) {
2684 for (i = first; i <= last; i++) {
2685 eval(mach, i, j);
2686 }
2687 }
2688 }
2689 }
2690
2691 if (DEBUG_EXECUTION) {
2692 uint i, j;
2693 for (i = first; i <= last; ++i) {
2694 debug_printf("IN[%2u] = ", i);
2695 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2696 if (j > 0) {
2697 debug_printf(" ");
2698 }
2699 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2700 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2701 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2702 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2703 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2704 }
2705 }
2706 }
2707 }
2708 }
2709
2710 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2711 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2712 }
2713 }
2714
2715 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2716 const union tgsi_exec_channel *src);
2717
2718 static void
2719 exec_scalar_unary(struct tgsi_exec_machine *mach,
2720 const struct tgsi_full_instruction *inst,
2721 micro_unary_op op,
2722 enum tgsi_exec_datatype dst_datatype,
2723 enum tgsi_exec_datatype src_datatype)
2724 {
2725 unsigned int chan;
2726 union tgsi_exec_channel src;
2727 union tgsi_exec_channel dst;
2728
2729 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2730 op(&dst, &src);
2731 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2732 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2733 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2734 }
2735 }
2736 }
2737
2738 static void
2739 exec_vector_unary(struct tgsi_exec_machine *mach,
2740 const struct tgsi_full_instruction *inst,
2741 micro_unary_op op,
2742 enum tgsi_exec_datatype dst_datatype,
2743 enum tgsi_exec_datatype src_datatype)
2744 {
2745 unsigned int chan;
2746 struct tgsi_exec_vector dst;
2747
2748 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2749 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2750 union tgsi_exec_channel src;
2751
2752 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2753 op(&dst.xyzw[chan], &src);
2754 }
2755 }
2756 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2757 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2758 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2759 }
2760 }
2761 }
2762
2763 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2764 const union tgsi_exec_channel *src0,
2765 const union tgsi_exec_channel *src1);
2766
2767 static void
2768 exec_scalar_binary(struct tgsi_exec_machine *mach,
2769 const struct tgsi_full_instruction *inst,
2770 micro_binary_op op,
2771 enum tgsi_exec_datatype dst_datatype,
2772 enum tgsi_exec_datatype src_datatype)
2773 {
2774 unsigned int chan;
2775 union tgsi_exec_channel src[2];
2776 union tgsi_exec_channel dst;
2777
2778 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2779 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2780 op(&dst, &src[0], &src[1]);
2781 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2782 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2783 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2784 }
2785 }
2786 }
2787
2788 static void
2789 exec_vector_binary(struct tgsi_exec_machine *mach,
2790 const struct tgsi_full_instruction *inst,
2791 micro_binary_op op,
2792 enum tgsi_exec_datatype dst_datatype,
2793 enum tgsi_exec_datatype src_datatype)
2794 {
2795 unsigned int chan;
2796 struct tgsi_exec_vector dst;
2797
2798 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2799 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2800 union tgsi_exec_channel src[2];
2801
2802 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2803 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2804 op(&dst.xyzw[chan], &src[0], &src[1]);
2805 }
2806 }
2807 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2808 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2809 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2810 }
2811 }
2812 }
2813
2814 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2815 const union tgsi_exec_channel *src0,
2816 const union tgsi_exec_channel *src1,
2817 const union tgsi_exec_channel *src2);
2818
2819 static void
2820 exec_vector_trinary(struct tgsi_exec_machine *mach,
2821 const struct tgsi_full_instruction *inst,
2822 micro_trinary_op op,
2823 enum tgsi_exec_datatype dst_datatype,
2824 enum tgsi_exec_datatype src_datatype)
2825 {
2826 unsigned int chan;
2827 struct tgsi_exec_vector dst;
2828
2829 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2830 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2831 union tgsi_exec_channel src[3];
2832
2833 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2834 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2835 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2836 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2837 }
2838 }
2839 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2840 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2841 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2842 }
2843 }
2844 }
2845
2846 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2847 const union tgsi_exec_channel *src0,
2848 const union tgsi_exec_channel *src1,
2849 const union tgsi_exec_channel *src2,
2850 const union tgsi_exec_channel *src3);
2851
2852 static void
2853 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2854 const struct tgsi_full_instruction *inst,
2855 micro_quaternary_op op,
2856 enum tgsi_exec_datatype dst_datatype,
2857 enum tgsi_exec_datatype src_datatype)
2858 {
2859 unsigned int chan;
2860 struct tgsi_exec_vector dst;
2861
2862 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2863 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2864 union tgsi_exec_channel src[4];
2865
2866 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2867 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2868 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2869 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2870 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2871 }
2872 }
2873 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2874 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2875 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2876 }
2877 }
2878 }
2879
2880 static void
2881 exec_dp3(struct tgsi_exec_machine *mach,
2882 const struct tgsi_full_instruction *inst)
2883 {
2884 unsigned int chan;
2885 union tgsi_exec_channel arg[3];
2886
2887 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2888 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2889 micro_mul(&arg[2], &arg[0], &arg[1]);
2890
2891 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2892 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2893 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2894 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2895 }
2896
2897 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2898 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2899 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2900 }
2901 }
2902 }
2903
2904 static void
2905 exec_dp4(struct tgsi_exec_machine *mach,
2906 const struct tgsi_full_instruction *inst)
2907 {
2908 unsigned int chan;
2909 union tgsi_exec_channel arg[3];
2910
2911 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2912 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2913 micro_mul(&arg[2], &arg[0], &arg[1]);
2914
2915 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2916 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2917 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2918 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2919 }
2920
2921 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2922 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2923 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2924 }
2925 }
2926 }
2927
2928 static void
2929 exec_dp2a(struct tgsi_exec_machine *mach,
2930 const struct tgsi_full_instruction *inst)
2931 {
2932 unsigned int chan;
2933 union tgsi_exec_channel arg[3];
2934
2935 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2936 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2937 micro_mul(&arg[2], &arg[0], &arg[1]);
2938
2939 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2940 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2941 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2942
2943 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2944 micro_add(&arg[0], &arg[0], &arg[1]);
2945
2946 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2947 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2948 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2949 }
2950 }
2951 }
2952
2953 static void
2954 exec_dph(struct tgsi_exec_machine *mach,
2955 const struct tgsi_full_instruction *inst)
2956 {
2957 unsigned int chan;
2958 union tgsi_exec_channel arg[3];
2959
2960 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2961 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2962 micro_mul(&arg[2], &arg[0], &arg[1]);
2963
2964 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2965 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2966 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2967
2968 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2969 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2970 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2971
2972 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2973 micro_add(&arg[0], &arg[0], &arg[1]);
2974
2975 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2976 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2977 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2978 }
2979 }
2980 }
2981
2982 static void
2983 exec_dp2(struct tgsi_exec_machine *mach,
2984 const struct tgsi_full_instruction *inst)
2985 {
2986 unsigned int chan;
2987 union tgsi_exec_channel arg[3];
2988
2989 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2990 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2991 micro_mul(&arg[2], &arg[0], &arg[1]);
2992
2993 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2994 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2995 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2996
2997 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2998 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2999 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3000 }
3001 }
3002 }
3003
3004 static void
3005 exec_scs(struct tgsi_exec_machine *mach,
3006 const struct tgsi_full_instruction *inst)
3007 {
3008 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
3009 union tgsi_exec_channel arg;
3010 union tgsi_exec_channel result;
3011
3012 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3013
3014 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3015 micro_cos(&result, &arg);
3016 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3017 }
3018 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3019 micro_sin(&result, &arg);
3020 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3021 }
3022 }
3023 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3024 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3025 }
3026 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3027 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3028 }
3029 }
3030
3031 static void
3032 exec_xpd(struct tgsi_exec_machine *mach,
3033 const struct tgsi_full_instruction *inst)
3034 {
3035 union tgsi_exec_channel r[6];
3036 union tgsi_exec_channel d[3];
3037
3038 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3039 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3040
3041 micro_mul(&r[2], &r[0], &r[1]);
3042
3043 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3044 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3045
3046 micro_mul(&r[5], &r[3], &r[4] );
3047 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
3048
3049 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3050
3051 micro_mul(&r[3], &r[3], &r[2]);
3052
3053 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3054
3055 micro_mul(&r[1], &r[1], &r[5]);
3056 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
3057
3058 micro_mul(&r[5], &r[5], &r[4]);
3059 micro_mul(&r[0], &r[0], &r[2]);
3060 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
3061
3062 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3063 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3064 }
3065 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3066 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3067 }
3068 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3069 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3070 }
3071 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3072 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3073 }
3074 }
3075
3076 static void
3077 exec_dst(struct tgsi_exec_machine *mach,
3078 const struct tgsi_full_instruction *inst)
3079 {
3080 union tgsi_exec_channel r[2];
3081 union tgsi_exec_channel d[4];
3082
3083 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3084 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3085 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3086 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3087 }
3088 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3089 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3090 }
3091 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3092 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3093 }
3094
3095 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3096 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3097 }
3098 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3099 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3100 }
3101 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3102 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3103 }
3104 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3105 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3106 }
3107 }
3108
3109 static void
3110 exec_log(struct tgsi_exec_machine *mach,
3111 const struct tgsi_full_instruction *inst)
3112 {
3113 union tgsi_exec_channel r[3];
3114
3115 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3116 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3117 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3118 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3119 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3120 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3121 }
3122 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3123 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3124 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3125 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3126 }
3127 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3128 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3129 }
3130 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3131 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3132 }
3133 }
3134
3135 static void
3136 exec_exp(struct tgsi_exec_machine *mach,
3137 const struct tgsi_full_instruction *inst)
3138 {
3139 union tgsi_exec_channel r[3];
3140
3141 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3142 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3143 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3144 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3145 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3146 }
3147 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3148 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3149 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3150 }
3151 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3152 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3153 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3154 }
3155 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3156 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3157 }
3158 }
3159
3160 static void
3161 exec_lit(struct tgsi_exec_machine *mach,
3162 const struct tgsi_full_instruction *inst)
3163 {
3164 union tgsi_exec_channel r[3];
3165 union tgsi_exec_channel d[3];
3166
3167 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3168 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3169 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3170 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3171 micro_max(&r[1], &r[1], &ZeroVec);
3172
3173 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3174 micro_min(&r[2], &r[2], &P128Vec);
3175 micro_max(&r[2], &r[2], &M128Vec);
3176 micro_pow(&r[1], &r[1], &r[2]);
3177 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3178 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3179 }
3180 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3181 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3182 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3183 }
3184 }
3185 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3186 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3187 }
3188
3189 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3190 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3191 }
3192 }
3193
3194 static void
3195 exec_break(struct tgsi_exec_machine *mach)
3196 {
3197 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3198 /* turn off loop channels for each enabled exec channel */
3199 mach->LoopMask &= ~mach->ExecMask;
3200 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3201 UPDATE_EXEC_MASK(mach);
3202 } else {
3203 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3204
3205 mach->Switch.mask = 0x0;
3206
3207 UPDATE_EXEC_MASK(mach);
3208 }
3209 }
3210
3211 static void
3212 exec_switch(struct tgsi_exec_machine *mach,
3213 const struct tgsi_full_instruction *inst)
3214 {
3215 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3216 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3217
3218 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3219 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3220 mach->Switch.mask = 0x0;
3221 mach->Switch.defaultMask = 0x0;
3222
3223 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3224 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3225
3226 UPDATE_EXEC_MASK(mach);
3227 }
3228
3229 static void
3230 exec_case(struct tgsi_exec_machine *mach,
3231 const struct tgsi_full_instruction *inst)
3232 {
3233 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3234 union tgsi_exec_channel src;
3235 uint mask = 0;
3236
3237 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3238
3239 if (mach->Switch.selector.u[0] == src.u[0]) {
3240 mask |= 0x1;
3241 }
3242 if (mach->Switch.selector.u[1] == src.u[1]) {
3243 mask |= 0x2;
3244 }
3245 if (mach->Switch.selector.u[2] == src.u[2]) {
3246 mask |= 0x4;
3247 }
3248 if (mach->Switch.selector.u[3] == src.u[3]) {
3249 mask |= 0x8;
3250 }
3251
3252 mach->Switch.defaultMask |= mask;
3253
3254 mach->Switch.mask |= mask & prevMask;
3255
3256 UPDATE_EXEC_MASK(mach);
3257 }
3258
3259 /* FIXME: this will only work if default is last */
3260 static void
3261 exec_default(struct tgsi_exec_machine *mach)
3262 {
3263 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3264
3265 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3266
3267 UPDATE_EXEC_MASK(mach);
3268 }
3269
3270 static void
3271 exec_endswitch(struct tgsi_exec_machine *mach)
3272 {
3273 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3274 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3275
3276 UPDATE_EXEC_MASK(mach);
3277 }
3278
3279 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3280 const union tgsi_double_channel *src);
3281
3282 static void
3283 fetch_double_channel(struct tgsi_exec_machine *mach,
3284 union tgsi_double_channel *chan,
3285 const struct tgsi_full_src_register *reg,
3286 uint chan_0,
3287 uint chan_1)
3288 {
3289 union tgsi_exec_channel src[2];
3290 uint i;
3291
3292 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3293 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3294
3295 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3296 chan->u[i][0] = src[0].u[i];
3297 chan->u[i][1] = src[1].u[i];
3298 }
3299 if (reg->Register.Absolute) {
3300 micro_dabs(chan, chan);
3301 }
3302 if (reg->Register.Negate) {
3303 micro_dneg(chan, chan);
3304 }
3305 }
3306
3307 static void
3308 store_double_channel(struct tgsi_exec_machine *mach,
3309 const union tgsi_double_channel *chan,
3310 const struct tgsi_full_dst_register *reg,
3311 const struct tgsi_full_instruction *inst,
3312 uint chan_0,
3313 uint chan_1)
3314 {
3315 union tgsi_exec_channel dst[2];
3316 uint i;
3317 union tgsi_double_channel temp;
3318 const uint execmask = mach->ExecMask;
3319
3320 switch (inst->Instruction.Saturate) {
3321 case TGSI_SAT_NONE:
3322 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3323 if (execmask & (1 << i)) {
3324 dst[0].u[i] = chan->u[i][0];
3325 dst[1].u[i] = chan->u[i][1];
3326 }
3327 break;
3328
3329 case TGSI_SAT_ZERO_ONE:
3330 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3331 if (execmask & (1 << i)) {
3332 if (chan->d[i] < 0.0)
3333 temp.d[i] = 0.0;
3334 else if (chan->d[i] > 1.0)
3335 temp.d[i] = 1.0;
3336 else
3337 temp.d[i] = chan->d[i];
3338
3339 dst[0].u[i] = temp.u[i][0];
3340 dst[1].u[i] = temp.u[i][1];
3341 }
3342 break;
3343
3344 case TGSI_SAT_MINUS_PLUS_ONE:
3345 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3346 if (execmask & (1 << i)) {
3347 if (chan->d[i] < -1.0)
3348 temp.d[i] = -1.0;
3349 else if (chan->d[i] > 1.0)
3350 temp.d[i] = 1.0;
3351 else
3352 temp.d[i] = chan->d[i];
3353
3354 dst[0].u[i] = temp.u[i][0];
3355 dst[1].u[i] = temp.u[i][1];
3356 }
3357 break;
3358
3359 default:
3360 assert( 0 );
3361 }
3362
3363 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3364 if (chan_1 != -1)
3365 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3366 }
3367
3368 static void
3369 exec_double_unary(struct tgsi_exec_machine *mach,
3370 const struct tgsi_full_instruction *inst,
3371 micro_dop op)
3372 {
3373 union tgsi_double_channel src;
3374 union tgsi_double_channel dst;
3375
3376 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3377 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3378 op(&dst, &src);
3379 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3380 }
3381 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3382 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3383 op(&dst, &src);
3384 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3385 }
3386 }
3387
3388 static void
3389 exec_double_binary(struct tgsi_exec_machine *mach,
3390 const struct tgsi_full_instruction *inst,
3391 micro_dop op,
3392 enum tgsi_exec_datatype dst_datatype)
3393 {
3394 union tgsi_double_channel src[2];
3395 union tgsi_double_channel dst;
3396 int first_dest_chan, second_dest_chan;
3397 int wmask;
3398
3399 wmask = inst->Dst[0].Register.WriteMask;
3400 /* these are & because of the way DSLT etc store their destinations */
3401 if (wmask & TGSI_WRITEMASK_XY) {
3402 first_dest_chan = TGSI_CHAN_X;
3403 second_dest_chan = TGSI_CHAN_Y;
3404 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3405 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3406 second_dest_chan = -1;
3407 }
3408
3409 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3410 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3411 op(&dst, src);
3412 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3413 }
3414
3415 if (wmask & TGSI_WRITEMASK_ZW) {
3416 first_dest_chan = TGSI_CHAN_Z;
3417 second_dest_chan = TGSI_CHAN_W;
3418 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3419 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3420 second_dest_chan = -1;
3421 }
3422
3423 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3424 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3425 op(&dst, src);
3426 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3427 }
3428 }
3429
3430 static void
3431 exec_double_trinary(struct tgsi_exec_machine *mach,
3432 const struct tgsi_full_instruction *inst,
3433 micro_dop op)
3434 {
3435 union tgsi_double_channel src[3];
3436 union tgsi_double_channel dst;
3437
3438 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3439 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3440 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3441 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3442 op(&dst, src);
3443 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3444 }
3445 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3446 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3447 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3448 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3449 op(&dst, src);
3450 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3451 }
3452 }
3453
3454 static void
3455 exec_f2d(struct tgsi_exec_machine *mach,
3456 const struct tgsi_full_instruction *inst)
3457 {
3458 union tgsi_exec_channel src;
3459 union tgsi_double_channel dst;
3460
3461 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3462 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3463 micro_f2d(&dst, &src);
3464 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3465 }
3466 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3467 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3468 micro_f2d(&dst, &src);
3469 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3470 }
3471 }
3472
3473 static void
3474 exec_d2f(struct tgsi_exec_machine *mach,
3475 const struct tgsi_full_instruction *inst)
3476 {
3477 union tgsi_double_channel src;
3478 union tgsi_exec_channel dst;
3479 int wm = inst->Dst[0].Register.WriteMask;
3480 int i;
3481 int bit;
3482 for (i = 0; i < 2; i++) {
3483 bit = ffs(wm);
3484 if (bit) {
3485 wm &= ~(1 << (bit - 1));
3486 if (i == 0)
3487 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3488 else
3489 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3490 micro_d2f(&dst, &src);
3491 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_FLOAT);
3492 }
3493 }
3494 }
3495
3496 static void
3497 exec_i2d(struct tgsi_exec_machine *mach,
3498 const struct tgsi_full_instruction *inst)
3499 {
3500 union tgsi_exec_channel src;
3501 union tgsi_double_channel dst;
3502
3503 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3504 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3505 micro_i2d(&dst, &src);
3506 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3507 }
3508 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3509 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_INT);
3510 micro_i2d(&dst, &src);
3511 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3512 }
3513 }
3514
3515 static void
3516 exec_d2i(struct tgsi_exec_machine *mach,
3517 const struct tgsi_full_instruction *inst)
3518 {
3519 union tgsi_double_channel src;
3520 union tgsi_exec_channel dst;
3521 int wm = inst->Dst[0].Register.WriteMask;
3522 int i;
3523 int bit;
3524 for (i = 0; i < 2; i++) {
3525 bit = ffs(wm);
3526 if (bit) {
3527 wm &= ~(1 << (bit - 1));
3528 if (i == 0)
3529 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3530 else
3531 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3532 micro_d2i(&dst, &src);
3533 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_INT);
3534 }
3535 }
3536 }
3537 static void
3538 exec_u2d(struct tgsi_exec_machine *mach,
3539 const struct tgsi_full_instruction *inst)
3540 {
3541 union tgsi_exec_channel src;
3542 union tgsi_double_channel dst;
3543
3544 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3545 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3546 micro_u2d(&dst, &src);
3547 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3548 }
3549 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3550 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_UINT);
3551 micro_u2d(&dst, &src);
3552 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3553 }
3554 }
3555
3556 static void
3557 exec_d2u(struct tgsi_exec_machine *mach,
3558 const struct tgsi_full_instruction *inst)
3559 {
3560 union tgsi_double_channel src;
3561 union tgsi_exec_channel dst;
3562 int wm = inst->Dst[0].Register.WriteMask;
3563 int i;
3564 int bit;
3565 for (i = 0; i < 2; i++) {
3566 bit = ffs(wm);
3567 if (bit) {
3568 wm &= ~(1 << (bit - 1));
3569 if (i == 0)
3570 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3571 else
3572 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3573 micro_d2u(&dst, &src);
3574 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_UINT);
3575 }
3576 }
3577 }
3578
3579 static void
3580 exec_dldexp(struct tgsi_exec_machine *mach,
3581 const struct tgsi_full_instruction *inst)
3582 {
3583 union tgsi_double_channel src0;
3584 union tgsi_exec_channel src1;
3585 union tgsi_double_channel dst;
3586 int wmask;
3587
3588 wmask = inst->Dst[0].Register.WriteMask;
3589 if (wmask & TGSI_WRITEMASK_XY) {
3590 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3591 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3592 micro_dldexp(&dst, &src0, &src1);
3593 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3594 }
3595
3596 if (wmask & TGSI_WRITEMASK_ZW) {
3597 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3598 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3599 micro_dldexp(&dst, &src0, &src1);
3600 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3601 }
3602 }
3603
3604 static void
3605 exec_dfracexp(struct tgsi_exec_machine *mach,
3606 const struct tgsi_full_instruction *inst)
3607 {
3608 union tgsi_double_channel src;
3609 union tgsi_double_channel dst;
3610 union tgsi_exec_channel dst_exp;
3611
3612 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)) {
3613 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3614 micro_dfracexp(&dst, &dst_exp, &src);
3615 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3616 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3617 }
3618 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)) {
3619 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3620 micro_dfracexp(&dst, &dst_exp, &src);
3621 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3622 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3623 }
3624 }
3625
3626
3627 static void
3628 micro_i2f(union tgsi_exec_channel *dst,
3629 const union tgsi_exec_channel *src)
3630 {
3631 dst->f[0] = (float)src->i[0];
3632 dst->f[1] = (float)src->i[1];
3633 dst->f[2] = (float)src->i[2];
3634 dst->f[3] = (float)src->i[3];
3635 }
3636
3637 static void
3638 micro_not(union tgsi_exec_channel *dst,
3639 const union tgsi_exec_channel *src)
3640 {
3641 dst->u[0] = ~src->u[0];
3642 dst->u[1] = ~src->u[1];
3643 dst->u[2] = ~src->u[2];
3644 dst->u[3] = ~src->u[3];
3645 }
3646
3647 static void
3648 micro_shl(union tgsi_exec_channel *dst,
3649 const union tgsi_exec_channel *src0,
3650 const union tgsi_exec_channel *src1)
3651 {
3652 unsigned masked_count;
3653 masked_count = src1->u[0] & 0x1f;
3654 dst->u[0] = src0->u[0] << masked_count;
3655 masked_count = src1->u[1] & 0x1f;
3656 dst->u[1] = src0->u[1] << masked_count;
3657 masked_count = src1->u[2] & 0x1f;
3658 dst->u[2] = src0->u[2] << masked_count;
3659 masked_count = src1->u[3] & 0x1f;
3660 dst->u[3] = src0->u[3] << masked_count;
3661 }
3662
3663 static void
3664 micro_and(union tgsi_exec_channel *dst,
3665 const union tgsi_exec_channel *src0,
3666 const union tgsi_exec_channel *src1)
3667 {
3668 dst->u[0] = src0->u[0] & src1->u[0];
3669 dst->u[1] = src0->u[1] & src1->u[1];
3670 dst->u[2] = src0->u[2] & src1->u[2];
3671 dst->u[3] = src0->u[3] & src1->u[3];
3672 }
3673
3674 static void
3675 micro_or(union tgsi_exec_channel *dst,
3676 const union tgsi_exec_channel *src0,
3677 const union tgsi_exec_channel *src1)
3678 {
3679 dst->u[0] = src0->u[0] | src1->u[0];
3680 dst->u[1] = src0->u[1] | src1->u[1];
3681 dst->u[2] = src0->u[2] | src1->u[2];
3682 dst->u[3] = src0->u[3] | src1->u[3];
3683 }
3684
3685 static void
3686 micro_xor(union tgsi_exec_channel *dst,
3687 const union tgsi_exec_channel *src0,
3688 const union tgsi_exec_channel *src1)
3689 {
3690 dst->u[0] = src0->u[0] ^ src1->u[0];
3691 dst->u[1] = src0->u[1] ^ src1->u[1];
3692 dst->u[2] = src0->u[2] ^ src1->u[2];
3693 dst->u[3] = src0->u[3] ^ src1->u[3];
3694 }
3695
3696 static void
3697 micro_mod(union tgsi_exec_channel *dst,
3698 const union tgsi_exec_channel *src0,
3699 const union tgsi_exec_channel *src1)
3700 {
3701 dst->i[0] = src0->i[0] % src1->i[0];
3702 dst->i[1] = src0->i[1] % src1->i[1];
3703 dst->i[2] = src0->i[2] % src1->i[2];
3704 dst->i[3] = src0->i[3] % src1->i[3];
3705 }
3706
3707 static void
3708 micro_f2i(union tgsi_exec_channel *dst,
3709 const union tgsi_exec_channel *src)
3710 {
3711 dst->i[0] = (int)src->f[0];
3712 dst->i[1] = (int)src->f[1];
3713 dst->i[2] = (int)src->f[2];
3714 dst->i[3] = (int)src->f[3];
3715 }
3716
3717 static void
3718 micro_fseq(union tgsi_exec_channel *dst,
3719 const union tgsi_exec_channel *src0,
3720 const union tgsi_exec_channel *src1)
3721 {
3722 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
3723 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
3724 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
3725 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
3726 }
3727
3728 static void
3729 micro_fsge(union tgsi_exec_channel *dst,
3730 const union tgsi_exec_channel *src0,
3731 const union tgsi_exec_channel *src1)
3732 {
3733 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
3734 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
3735 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
3736 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
3737 }
3738
3739 static void
3740 micro_fslt(union tgsi_exec_channel *dst,
3741 const union tgsi_exec_channel *src0,
3742 const union tgsi_exec_channel *src1)
3743 {
3744 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
3745 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
3746 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
3747 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
3748 }
3749
3750 static void
3751 micro_fsne(union tgsi_exec_channel *dst,
3752 const union tgsi_exec_channel *src0,
3753 const union tgsi_exec_channel *src1)
3754 {
3755 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
3756 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
3757 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
3758 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
3759 }
3760
3761 static void
3762 micro_idiv(union tgsi_exec_channel *dst,
3763 const union tgsi_exec_channel *src0,
3764 const union tgsi_exec_channel *src1)
3765 {
3766 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
3767 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
3768 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
3769 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
3770 }
3771
3772 static void
3773 micro_imax(union tgsi_exec_channel *dst,
3774 const union tgsi_exec_channel *src0,
3775 const union tgsi_exec_channel *src1)
3776 {
3777 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3778 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3779 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3780 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3781 }
3782
3783 static void
3784 micro_imin(union tgsi_exec_channel *dst,
3785 const union tgsi_exec_channel *src0,
3786 const union tgsi_exec_channel *src1)
3787 {
3788 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3789 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3790 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3791 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3792 }
3793
3794 static void
3795 micro_isge(union tgsi_exec_channel *dst,
3796 const union tgsi_exec_channel *src0,
3797 const union tgsi_exec_channel *src1)
3798 {
3799 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3800 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3801 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3802 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3803 }
3804
3805 static void
3806 micro_ishr(union tgsi_exec_channel *dst,
3807 const union tgsi_exec_channel *src0,
3808 const union tgsi_exec_channel *src1)
3809 {
3810 unsigned masked_count;
3811 masked_count = src1->i[0] & 0x1f;
3812 dst->i[0] = src0->i[0] >> masked_count;
3813 masked_count = src1->i[1] & 0x1f;
3814 dst->i[1] = src0->i[1] >> masked_count;
3815 masked_count = src1->i[2] & 0x1f;
3816 dst->i[2] = src0->i[2] >> masked_count;
3817 masked_count = src1->i[3] & 0x1f;
3818 dst->i[3] = src0->i[3] >> masked_count;
3819 }
3820
3821 static void
3822 micro_islt(union tgsi_exec_channel *dst,
3823 const union tgsi_exec_channel *src0,
3824 const union tgsi_exec_channel *src1)
3825 {
3826 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3827 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3828 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3829 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3830 }
3831
3832 static void
3833 micro_f2u(union tgsi_exec_channel *dst,
3834 const union tgsi_exec_channel *src)
3835 {
3836 dst->u[0] = (uint)src->f[0];
3837 dst->u[1] = (uint)src->f[1];
3838 dst->u[2] = (uint)src->f[2];
3839 dst->u[3] = (uint)src->f[3];
3840 }
3841
3842 static void
3843 micro_u2f(union tgsi_exec_channel *dst,
3844 const union tgsi_exec_channel *src)
3845 {
3846 dst->f[0] = (float)src->u[0];
3847 dst->f[1] = (float)src->u[1];
3848 dst->f[2] = (float)src->u[2];
3849 dst->f[3] = (float)src->u[3];
3850 }
3851
3852 static void
3853 micro_uadd(union tgsi_exec_channel *dst,
3854 const union tgsi_exec_channel *src0,
3855 const union tgsi_exec_channel *src1)
3856 {
3857 dst->u[0] = src0->u[0] + src1->u[0];
3858 dst->u[1] = src0->u[1] + src1->u[1];
3859 dst->u[2] = src0->u[2] + src1->u[2];
3860 dst->u[3] = src0->u[3] + src1->u[3];
3861 }
3862
3863 static void
3864 micro_udiv(union tgsi_exec_channel *dst,
3865 const union tgsi_exec_channel *src0,
3866 const union tgsi_exec_channel *src1)
3867 {
3868 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
3869 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
3870 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
3871 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
3872 }
3873
3874 static void
3875 micro_umad(union tgsi_exec_channel *dst,
3876 const union tgsi_exec_channel *src0,
3877 const union tgsi_exec_channel *src1,
3878 const union tgsi_exec_channel *src2)
3879 {
3880 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3881 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3882 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3883 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3884 }
3885
3886 static void
3887 micro_umax(union tgsi_exec_channel *dst,
3888 const union tgsi_exec_channel *src0,
3889 const union tgsi_exec_channel *src1)
3890 {
3891 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3892 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3893 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3894 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3895 }
3896
3897 static void
3898 micro_umin(union tgsi_exec_channel *dst,
3899 const union tgsi_exec_channel *src0,
3900 const union tgsi_exec_channel *src1)
3901 {
3902 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3903 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3904 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3905 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3906 }
3907
3908 static void
3909 micro_umod(union tgsi_exec_channel *dst,
3910 const union tgsi_exec_channel *src0,
3911 const union tgsi_exec_channel *src1)
3912 {
3913 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
3914 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
3915 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
3916 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
3917 }
3918
3919 static void
3920 micro_umul(union tgsi_exec_channel *dst,
3921 const union tgsi_exec_channel *src0,
3922 const union tgsi_exec_channel *src1)
3923 {
3924 dst->u[0] = src0->u[0] * src1->u[0];
3925 dst->u[1] = src0->u[1] * src1->u[1];
3926 dst->u[2] = src0->u[2] * src1->u[2];
3927 dst->u[3] = src0->u[3] * src1->u[3];
3928 }
3929
3930 static void
3931 micro_imul_hi(union tgsi_exec_channel *dst,
3932 const union tgsi_exec_channel *src0,
3933 const union tgsi_exec_channel *src1)
3934 {
3935 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3936 dst->i[0] = I64M(src0->i[0], src1->i[0]);
3937 dst->i[1] = I64M(src0->i[1], src1->i[1]);
3938 dst->i[2] = I64M(src0->i[2], src1->i[2]);
3939 dst->i[3] = I64M(src0->i[3], src1->i[3]);
3940 #undef I64M
3941 }
3942
3943 static void
3944 micro_umul_hi(union tgsi_exec_channel *dst,
3945 const union tgsi_exec_channel *src0,
3946 const union tgsi_exec_channel *src1)
3947 {
3948 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3949 dst->u[0] = U64M(src0->u[0], src1->u[0]);
3950 dst->u[1] = U64M(src0->u[1], src1->u[1]);
3951 dst->u[2] = U64M(src0->u[2], src1->u[2]);
3952 dst->u[3] = U64M(src0->u[3], src1->u[3]);
3953 #undef U64M
3954 }
3955
3956 static void
3957 micro_useq(union tgsi_exec_channel *dst,
3958 const union tgsi_exec_channel *src0,
3959 const union tgsi_exec_channel *src1)
3960 {
3961 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3962 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3963 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3964 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3965 }
3966
3967 static void
3968 micro_usge(union tgsi_exec_channel *dst,
3969 const union tgsi_exec_channel *src0,
3970 const union tgsi_exec_channel *src1)
3971 {
3972 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3973 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3974 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3975 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3976 }
3977
3978 static void
3979 micro_ushr(union tgsi_exec_channel *dst,
3980 const union tgsi_exec_channel *src0,
3981 const union tgsi_exec_channel *src1)
3982 {
3983 unsigned masked_count;
3984 masked_count = src1->u[0] & 0x1f;
3985 dst->u[0] = src0->u[0] >> masked_count;
3986 masked_count = src1->u[1] & 0x1f;
3987 dst->u[1] = src0->u[1] >> masked_count;
3988 masked_count = src1->u[2] & 0x1f;
3989 dst->u[2] = src0->u[2] >> masked_count;
3990 masked_count = src1->u[3] & 0x1f;
3991 dst->u[3] = src0->u[3] >> masked_count;
3992 }
3993
3994 static void
3995 micro_uslt(union tgsi_exec_channel *dst,
3996 const union tgsi_exec_channel *src0,
3997 const union tgsi_exec_channel *src1)
3998 {
3999 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
4000 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
4001 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
4002 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
4003 }
4004
4005 static void
4006 micro_usne(union tgsi_exec_channel *dst,
4007 const union tgsi_exec_channel *src0,
4008 const union tgsi_exec_channel *src1)
4009 {
4010 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
4011 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
4012 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
4013 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
4014 }
4015
4016 static void
4017 micro_uarl(union tgsi_exec_channel *dst,
4018 const union tgsi_exec_channel *src)
4019 {
4020 dst->i[0] = src->u[0];
4021 dst->i[1] = src->u[1];
4022 dst->i[2] = src->u[2];
4023 dst->i[3] = src->u[3];
4024 }
4025
4026 static void
4027 micro_ucmp(union tgsi_exec_channel *dst,
4028 const union tgsi_exec_channel *src0,
4029 const union tgsi_exec_channel *src1,
4030 const union tgsi_exec_channel *src2)
4031 {
4032 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
4033 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
4034 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
4035 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
4036 }
4037
4038 /**
4039 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4040 */
4041 static void
4042 micro_ibfe(union tgsi_exec_channel *dst,
4043 const union tgsi_exec_channel *src0,
4044 const union tgsi_exec_channel *src1,
4045 const union tgsi_exec_channel *src2)
4046 {
4047 int i;
4048 for (i = 0; i < 4; i++) {
4049 int width = src2->i[i] & 0x1f;
4050 int offset = src1->i[i] & 0x1f;
4051 if (width == 0)
4052 dst->i[i] = 0;
4053 else if (width + offset < 32)
4054 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
4055 else
4056 dst->i[i] = src0->i[i] >> offset;
4057 }
4058 }
4059
4060 /**
4061 * Unsigned bitfield extract
4062 */
4063 static void
4064 micro_ubfe(union tgsi_exec_channel *dst,
4065 const union tgsi_exec_channel *src0,
4066 const union tgsi_exec_channel *src1,
4067 const union tgsi_exec_channel *src2)
4068 {
4069 int i;
4070 for (i = 0; i < 4; i++) {
4071 int width = src2->u[i] & 0x1f;
4072 int offset = src1->u[i] & 0x1f;
4073 if (width == 0)
4074 dst->u[i] = 0;
4075 else if (width + offset < 32)
4076 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
4077 else
4078 dst->u[i] = src0->u[i] >> offset;
4079 }
4080 }
4081
4082 /**
4083 * Bitfield insert: copy low bits from src1 into a region of src0.
4084 */
4085 static void
4086 micro_bfi(union tgsi_exec_channel *dst,
4087 const union tgsi_exec_channel *src0,
4088 const union tgsi_exec_channel *src1,
4089 const union tgsi_exec_channel *src2,
4090 const union tgsi_exec_channel *src3)
4091 {
4092 int i;
4093 for (i = 0; i < 4; i++) {
4094 int width = src3->u[i] & 0x1f;
4095 int offset = src2->u[i] & 0x1f;
4096 int bitmask = ((1 << width) - 1) << offset;
4097 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
4098 }
4099 }
4100
4101 static void
4102 micro_brev(union tgsi_exec_channel *dst,
4103 const union tgsi_exec_channel *src)
4104 {
4105 dst->u[0] = util_bitreverse(src->u[0]);
4106 dst->u[1] = util_bitreverse(src->u[1]);
4107 dst->u[2] = util_bitreverse(src->u[2]);
4108 dst->u[3] = util_bitreverse(src->u[3]);
4109 }
4110
4111 static void
4112 micro_popc(union tgsi_exec_channel *dst,
4113 const union tgsi_exec_channel *src)
4114 {
4115 dst->u[0] = util_bitcount(src->u[0]);
4116 dst->u[1] = util_bitcount(src->u[1]);
4117 dst->u[2] = util_bitcount(src->u[2]);
4118 dst->u[3] = util_bitcount(src->u[3]);
4119 }
4120
4121 static void
4122 micro_lsb(union tgsi_exec_channel *dst,
4123 const union tgsi_exec_channel *src)
4124 {
4125 dst->i[0] = ffs(src->u[0]) - 1;
4126 dst->i[1] = ffs(src->u[1]) - 1;
4127 dst->i[2] = ffs(src->u[2]) - 1;
4128 dst->i[3] = ffs(src->u[3]) - 1;
4129 }
4130
4131 static void
4132 micro_imsb(union tgsi_exec_channel *dst,
4133 const union tgsi_exec_channel *src)
4134 {
4135 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
4136 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
4137 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
4138 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
4139 }
4140
4141 static void
4142 micro_umsb(union tgsi_exec_channel *dst,
4143 const union tgsi_exec_channel *src)
4144 {
4145 dst->i[0] = util_last_bit(src->u[0]) - 1;
4146 dst->i[1] = util_last_bit(src->u[1]) - 1;
4147 dst->i[2] = util_last_bit(src->u[2]) - 1;
4148 dst->i[3] = util_last_bit(src->u[3]) - 1;
4149 }
4150
4151 static void
4152 exec_instruction(
4153 struct tgsi_exec_machine *mach,
4154 const struct tgsi_full_instruction *inst,
4155 int *pc )
4156 {
4157 union tgsi_exec_channel r[10];
4158
4159 (*pc)++;
4160
4161 switch (inst->Instruction.Opcode) {
4162 case TGSI_OPCODE_ARL:
4163 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4164 break;
4165
4166 case TGSI_OPCODE_MOV:
4167 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4168 break;
4169
4170 case TGSI_OPCODE_LIT:
4171 exec_lit(mach, inst);
4172 break;
4173
4174 case TGSI_OPCODE_RCP:
4175 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4176 break;
4177
4178 case TGSI_OPCODE_RSQ:
4179 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4180 break;
4181
4182 case TGSI_OPCODE_EXP:
4183 exec_exp(mach, inst);
4184 break;
4185
4186 case TGSI_OPCODE_LOG:
4187 exec_log(mach, inst);
4188 break;
4189
4190 case TGSI_OPCODE_MUL:
4191 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4192 break;
4193
4194 case TGSI_OPCODE_ADD:
4195 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4196 break;
4197
4198 case TGSI_OPCODE_DP3:
4199 exec_dp3(mach, inst);
4200 break;
4201
4202 case TGSI_OPCODE_DP4:
4203 exec_dp4(mach, inst);
4204 break;
4205
4206 case TGSI_OPCODE_DST:
4207 exec_dst(mach, inst);
4208 break;
4209
4210 case TGSI_OPCODE_MIN:
4211 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4212 break;
4213
4214 case TGSI_OPCODE_MAX:
4215 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4216 break;
4217
4218 case TGSI_OPCODE_SLT:
4219 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4220 break;
4221
4222 case TGSI_OPCODE_SGE:
4223 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4224 break;
4225
4226 case TGSI_OPCODE_MAD:
4227 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4228 break;
4229
4230 case TGSI_OPCODE_SUB:
4231 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4232 break;
4233
4234 case TGSI_OPCODE_LRP:
4235 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4236 break;
4237
4238 case TGSI_OPCODE_SQRT:
4239 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4240 break;
4241
4242 case TGSI_OPCODE_DP2A:
4243 exec_dp2a(mach, inst);
4244 break;
4245
4246 case TGSI_OPCODE_FRC:
4247 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4248 break;
4249
4250 case TGSI_OPCODE_CLAMP:
4251 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4252 break;
4253
4254 case TGSI_OPCODE_FLR:
4255 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4256 break;
4257
4258 case TGSI_OPCODE_ROUND:
4259 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4260 break;
4261
4262 case TGSI_OPCODE_EX2:
4263 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4264 break;
4265
4266 case TGSI_OPCODE_LG2:
4267 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4268 break;
4269
4270 case TGSI_OPCODE_POW:
4271 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4272 break;
4273
4274 case TGSI_OPCODE_XPD:
4275 exec_xpd(mach, inst);
4276 break;
4277
4278 case TGSI_OPCODE_ABS:
4279 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4280 break;
4281
4282 case TGSI_OPCODE_DPH:
4283 exec_dph(mach, inst);
4284 break;
4285
4286 case TGSI_OPCODE_COS:
4287 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4288 break;
4289
4290 case TGSI_OPCODE_DDX:
4291 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4292 break;
4293
4294 case TGSI_OPCODE_DDY:
4295 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4296 break;
4297
4298 case TGSI_OPCODE_KILL:
4299 exec_kill (mach, inst);
4300 break;
4301
4302 case TGSI_OPCODE_KILL_IF:
4303 exec_kill_if (mach, inst);
4304 break;
4305
4306 case TGSI_OPCODE_PK2H:
4307 assert (0);
4308 break;
4309
4310 case TGSI_OPCODE_PK2US:
4311 assert (0);
4312 break;
4313
4314 case TGSI_OPCODE_PK4B:
4315 assert (0);
4316 break;
4317
4318 case TGSI_OPCODE_PK4UB:
4319 assert (0);
4320 break;
4321
4322 case TGSI_OPCODE_SEQ:
4323 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4324 break;
4325
4326 case TGSI_OPCODE_SGT:
4327 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4328 break;
4329
4330 case TGSI_OPCODE_SIN:
4331 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4332 break;
4333
4334 case TGSI_OPCODE_SLE:
4335 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4336 break;
4337
4338 case TGSI_OPCODE_SNE:
4339 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4340 break;
4341
4342 case TGSI_OPCODE_TEX:
4343 /* simple texture lookup */
4344 /* src[0] = texcoord */
4345 /* src[1] = sampler unit */
4346 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
4347 break;
4348
4349 case TGSI_OPCODE_TXB:
4350 /* Texture lookup with lod bias */
4351 /* src[0] = texcoord (src[0].w = LOD bias) */
4352 /* src[1] = sampler unit */
4353 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
4354 break;
4355
4356 case TGSI_OPCODE_TXD:
4357 /* Texture lookup with explict partial derivatives */
4358 /* src[0] = texcoord */
4359 /* src[1] = d[strq]/dx */
4360 /* src[2] = d[strq]/dy */
4361 /* src[3] = sampler unit */
4362 exec_txd(mach, inst);
4363 break;
4364
4365 case TGSI_OPCODE_TXL:
4366 /* Texture lookup with explit LOD */
4367 /* src[0] = texcoord (src[0].w = LOD) */
4368 /* src[1] = sampler unit */
4369 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
4370 break;
4371
4372 case TGSI_OPCODE_TXP:
4373 /* Texture lookup with projection */
4374 /* src[0] = texcoord (src[0].w = projection) */
4375 /* src[1] = sampler unit */
4376 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
4377 break;
4378
4379 case TGSI_OPCODE_TG4:
4380 /* src[0] = texcoord */
4381 /* src[1] = component */
4382 /* src[2] = sampler unit */
4383 exec_tex(mach, inst, TEX_MODIFIER_GATHER, 2);
4384 break;
4385
4386 case TGSI_OPCODE_UP2H:
4387 assert (0);
4388 break;
4389
4390 case TGSI_OPCODE_UP2US:
4391 assert (0);
4392 break;
4393
4394 case TGSI_OPCODE_UP4B:
4395 assert (0);
4396 break;
4397
4398 case TGSI_OPCODE_UP4UB:
4399 assert (0);
4400 break;
4401
4402 case TGSI_OPCODE_ARR:
4403 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4404 break;
4405
4406 case TGSI_OPCODE_CAL:
4407 /* skip the call if no execution channels are enabled */
4408 if (mach->ExecMask) {
4409 /* do the call */
4410
4411 /* First, record the depths of the execution stacks.
4412 * This is important for deeply nested/looped return statements.
4413 * We have to unwind the stacks by the correct amount. For a
4414 * real code generator, we could determine the number of entries
4415 * to pop off each stack with simple static analysis and avoid
4416 * implementing this data structure at run time.
4417 */
4418 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
4419 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
4420 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
4421 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
4422 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
4423 /* note that PC was already incremented above */
4424 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
4425
4426 mach->CallStackTop++;
4427
4428 /* Second, push the Cond, Loop, Cont, Func stacks */
4429 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4430 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4431 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4432 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
4433 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4434 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
4435
4436 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4437 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4438 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4439 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
4440 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4441 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
4442
4443 /* Finally, jump to the subroutine */
4444 *pc = inst->Label.Label;
4445 }
4446 break;
4447
4448 case TGSI_OPCODE_RET:
4449 mach->FuncMask &= ~mach->ExecMask;
4450 UPDATE_EXEC_MASK(mach);
4451
4452 if (mach->FuncMask == 0x0) {
4453 /* really return now (otherwise, keep executing */
4454
4455 if (mach->CallStackTop == 0) {
4456 /* returning from main() */
4457 mach->CondStackTop = 0;
4458 mach->LoopStackTop = 0;
4459 *pc = -1;
4460 return;
4461 }
4462
4463 assert(mach->CallStackTop > 0);
4464 mach->CallStackTop--;
4465
4466 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4467 mach->CondMask = mach->CondStack[mach->CondStackTop];
4468
4469 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4470 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4471
4472 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4473 mach->ContMask = mach->ContStack[mach->ContStackTop];
4474
4475 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4476 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4477
4478 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4479 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4480
4481 assert(mach->FuncStackTop > 0);
4482 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4483
4484 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4485
4486 UPDATE_EXEC_MASK(mach);
4487 }
4488 break;
4489
4490 case TGSI_OPCODE_SSG:
4491 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4492 break;
4493
4494 case TGSI_OPCODE_CMP:
4495 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4496 break;
4497
4498 case TGSI_OPCODE_SCS:
4499 exec_scs(mach, inst);
4500 break;
4501
4502 case TGSI_OPCODE_DIV:
4503 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4504 break;
4505
4506 case TGSI_OPCODE_DP2:
4507 exec_dp2(mach, inst);
4508 break;
4509
4510 case TGSI_OPCODE_IF:
4511 /* push CondMask */
4512 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4513 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4514 FETCH( &r[0], 0, TGSI_CHAN_X );
4515 /* update CondMask */
4516 if( ! r[0].f[0] ) {
4517 mach->CondMask &= ~0x1;
4518 }
4519 if( ! r[0].f[1] ) {
4520 mach->CondMask &= ~0x2;
4521 }
4522 if( ! r[0].f[2] ) {
4523 mach->CondMask &= ~0x4;
4524 }
4525 if( ! r[0].f[3] ) {
4526 mach->CondMask &= ~0x8;
4527 }
4528 UPDATE_EXEC_MASK(mach);
4529 /* Todo: If CondMask==0, jump to ELSE */
4530 break;
4531
4532 case TGSI_OPCODE_UIF:
4533 /* push CondMask */
4534 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4535 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4536 IFETCH( &r[0], 0, TGSI_CHAN_X );
4537 /* update CondMask */
4538 if( ! r[0].u[0] ) {
4539 mach->CondMask &= ~0x1;
4540 }
4541 if( ! r[0].u[1] ) {
4542 mach->CondMask &= ~0x2;
4543 }
4544 if( ! r[0].u[2] ) {
4545 mach->CondMask &= ~0x4;
4546 }
4547 if( ! r[0].u[3] ) {
4548 mach->CondMask &= ~0x8;
4549 }
4550 UPDATE_EXEC_MASK(mach);
4551 /* Todo: If CondMask==0, jump to ELSE */
4552 break;
4553
4554 case TGSI_OPCODE_ELSE:
4555 /* invert CondMask wrt previous mask */
4556 {
4557 uint prevMask;
4558 assert(mach->CondStackTop > 0);
4559 prevMask = mach->CondStack[mach->CondStackTop - 1];
4560 mach->CondMask = ~mach->CondMask & prevMask;
4561 UPDATE_EXEC_MASK(mach);
4562 /* Todo: If CondMask==0, jump to ENDIF */
4563 }
4564 break;
4565
4566 case TGSI_OPCODE_ENDIF:
4567 /* pop CondMask */
4568 assert(mach->CondStackTop > 0);
4569 mach->CondMask = mach->CondStack[--mach->CondStackTop];
4570 UPDATE_EXEC_MASK(mach);
4571 break;
4572
4573 case TGSI_OPCODE_END:
4574 /* make sure we end primitives which haven't
4575 * been explicitly emitted */
4576 conditional_emit_primitive(mach);
4577 /* halt execution */
4578 *pc = -1;
4579 break;
4580
4581 case TGSI_OPCODE_PUSHA:
4582 assert (0);
4583 break;
4584
4585 case TGSI_OPCODE_POPA:
4586 assert (0);
4587 break;
4588
4589 case TGSI_OPCODE_CEIL:
4590 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4591 break;
4592
4593 case TGSI_OPCODE_I2F:
4594 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
4595 break;
4596
4597 case TGSI_OPCODE_NOT:
4598 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4599 break;
4600
4601 case TGSI_OPCODE_TRUNC:
4602 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4603 break;
4604
4605 case TGSI_OPCODE_SHL:
4606 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4607 break;
4608
4609 case TGSI_OPCODE_AND:
4610 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4611 break;
4612
4613 case TGSI_OPCODE_OR:
4614 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4615 break;
4616
4617 case TGSI_OPCODE_MOD:
4618 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4619 break;
4620
4621 case TGSI_OPCODE_XOR:
4622 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4623 break;
4624
4625 case TGSI_OPCODE_SAD:
4626 assert (0);
4627 break;
4628
4629 case TGSI_OPCODE_TXF:
4630 exec_txf(mach, inst);
4631 break;
4632
4633 case TGSI_OPCODE_TXQ:
4634 exec_txq(mach, inst);
4635 break;
4636
4637 case TGSI_OPCODE_EMIT:
4638 emit_vertex(mach);
4639 break;
4640
4641 case TGSI_OPCODE_ENDPRIM:
4642 emit_primitive(mach);
4643 break;
4644
4645 case TGSI_OPCODE_BGNLOOP:
4646 /* push LoopMask and ContMasks */
4647 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4648 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4649 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4650 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4651
4652 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4653 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4654 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4655 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4656 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4657 break;
4658
4659 case TGSI_OPCODE_ENDLOOP:
4660 /* Restore ContMask, but don't pop */
4661 assert(mach->ContStackTop > 0);
4662 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4663 UPDATE_EXEC_MASK(mach);
4664 if (mach->ExecMask) {
4665 /* repeat loop: jump to instruction just past BGNLOOP */
4666 assert(mach->LoopLabelStackTop > 0);
4667 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4668 }
4669 else {
4670 /* exit loop: pop LoopMask */
4671 assert(mach->LoopStackTop > 0);
4672 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4673 /* pop ContMask */
4674 assert(mach->ContStackTop > 0);
4675 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4676 assert(mach->LoopLabelStackTop > 0);
4677 --mach->LoopLabelStackTop;
4678
4679 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4680 }
4681 UPDATE_EXEC_MASK(mach);
4682 break;
4683
4684 case TGSI_OPCODE_BRK:
4685 exec_break(mach);
4686 break;
4687
4688 case TGSI_OPCODE_CONT:
4689 /* turn off cont channels for each enabled exec channel */
4690 mach->ContMask &= ~mach->ExecMask;
4691 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4692 UPDATE_EXEC_MASK(mach);
4693 break;
4694
4695 case TGSI_OPCODE_BGNSUB:
4696 /* no-op */
4697 break;
4698
4699 case TGSI_OPCODE_ENDSUB:
4700 /*
4701 * XXX: This really should be a no-op. We should never reach this opcode.
4702 */
4703
4704 assert(mach->CallStackTop > 0);
4705 mach->CallStackTop--;
4706
4707 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4708 mach->CondMask = mach->CondStack[mach->CondStackTop];
4709
4710 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4711 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4712
4713 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4714 mach->ContMask = mach->ContStack[mach->ContStackTop];
4715
4716 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4717 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4718
4719 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4720 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4721
4722 assert(mach->FuncStackTop > 0);
4723 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4724
4725 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4726
4727 UPDATE_EXEC_MASK(mach);
4728 break;
4729
4730 case TGSI_OPCODE_NOP:
4731 break;
4732
4733 case TGSI_OPCODE_BREAKC:
4734 IFETCH(&r[0], 0, TGSI_CHAN_X);
4735 /* update CondMask */
4736 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4737 mach->LoopMask &= ~0x1;
4738 }
4739 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4740 mach->LoopMask &= ~0x2;
4741 }
4742 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4743 mach->LoopMask &= ~0x4;
4744 }
4745 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4746 mach->LoopMask &= ~0x8;
4747 }
4748 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4749 UPDATE_EXEC_MASK(mach);
4750 break;
4751
4752 case TGSI_OPCODE_F2I:
4753 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4754 break;
4755
4756 case TGSI_OPCODE_FSEQ:
4757 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4758 break;
4759
4760 case TGSI_OPCODE_FSGE:
4761 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4762 break;
4763
4764 case TGSI_OPCODE_FSLT:
4765 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4766 break;
4767
4768 case TGSI_OPCODE_FSNE:
4769 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4770 break;
4771
4772 case TGSI_OPCODE_IDIV:
4773 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4774 break;
4775
4776 case TGSI_OPCODE_IMAX:
4777 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4778 break;
4779
4780 case TGSI_OPCODE_IMIN:
4781 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4782 break;
4783
4784 case TGSI_OPCODE_INEG:
4785 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4786 break;
4787
4788 case TGSI_OPCODE_ISGE:
4789 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4790 break;
4791
4792 case TGSI_OPCODE_ISHR:
4793 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4794 break;
4795
4796 case TGSI_OPCODE_ISLT:
4797 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4798 break;
4799
4800 case TGSI_OPCODE_F2U:
4801 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4802 break;
4803
4804 case TGSI_OPCODE_U2F:
4805 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4806 break;
4807
4808 case TGSI_OPCODE_UADD:
4809 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4810 break;
4811
4812 case TGSI_OPCODE_UDIV:
4813 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4814 break;
4815
4816 case TGSI_OPCODE_UMAD:
4817 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4818 break;
4819
4820 case TGSI_OPCODE_UMAX:
4821 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4822 break;
4823
4824 case TGSI_OPCODE_UMIN:
4825 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4826 break;
4827
4828 case TGSI_OPCODE_UMOD:
4829 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4830 break;
4831
4832 case TGSI_OPCODE_UMUL:
4833 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4834 break;
4835
4836 case TGSI_OPCODE_IMUL_HI:
4837 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4838 break;
4839
4840 case TGSI_OPCODE_UMUL_HI:
4841 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4842 break;
4843
4844 case TGSI_OPCODE_USEQ:
4845 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4846 break;
4847
4848 case TGSI_OPCODE_USGE:
4849 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4850 break;
4851
4852 case TGSI_OPCODE_USHR:
4853 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4854 break;
4855
4856 case TGSI_OPCODE_USLT:
4857 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4858 break;
4859
4860 case TGSI_OPCODE_USNE:
4861 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4862 break;
4863
4864 case TGSI_OPCODE_SWITCH:
4865 exec_switch(mach, inst);
4866 break;
4867
4868 case TGSI_OPCODE_CASE:
4869 exec_case(mach, inst);
4870 break;
4871
4872 case TGSI_OPCODE_DEFAULT:
4873 exec_default(mach);
4874 break;
4875
4876 case TGSI_OPCODE_ENDSWITCH:
4877 exec_endswitch(mach);
4878 break;
4879
4880 case TGSI_OPCODE_SAMPLE_I:
4881 exec_txf(mach, inst);
4882 break;
4883
4884 case TGSI_OPCODE_SAMPLE_I_MS:
4885 assert(0);
4886 break;
4887
4888 case TGSI_OPCODE_SAMPLE:
4889 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4890 break;
4891
4892 case TGSI_OPCODE_SAMPLE_B:
4893 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4894 break;
4895
4896 case TGSI_OPCODE_SAMPLE_C:
4897 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4898 break;
4899
4900 case TGSI_OPCODE_SAMPLE_C_LZ:
4901 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4902 break;
4903
4904 case TGSI_OPCODE_SAMPLE_D:
4905 exec_sample_d(mach, inst);
4906 break;
4907
4908 case TGSI_OPCODE_SAMPLE_L:
4909 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4910 break;
4911
4912 case TGSI_OPCODE_GATHER4:
4913 assert(0);
4914 break;
4915
4916 case TGSI_OPCODE_SVIEWINFO:
4917 exec_txq(mach, inst);
4918 break;
4919
4920 case TGSI_OPCODE_SAMPLE_POS:
4921 assert(0);
4922 break;
4923
4924 case TGSI_OPCODE_SAMPLE_INFO:
4925 assert(0);
4926 break;
4927
4928 case TGSI_OPCODE_UARL:
4929 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4930 break;
4931
4932 case TGSI_OPCODE_UCMP:
4933 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4934 break;
4935
4936 case TGSI_OPCODE_IABS:
4937 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4938 break;
4939
4940 case TGSI_OPCODE_ISSG:
4941 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4942 break;
4943
4944 case TGSI_OPCODE_TEX2:
4945 /* simple texture lookup */
4946 /* src[0] = texcoord */
4947 /* src[1] = compare */
4948 /* src[2] = sampler unit */
4949 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4950 break;
4951 case TGSI_OPCODE_TXB2:
4952 /* simple texture lookup */
4953 /* src[0] = texcoord */
4954 /* src[1] = bias */
4955 /* src[2] = sampler unit */
4956 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4957 break;
4958 case TGSI_OPCODE_TXL2:
4959 /* simple texture lookup */
4960 /* src[0] = texcoord */
4961 /* src[1] = lod */
4962 /* src[2] = sampler unit */
4963 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4964 break;
4965
4966 case TGSI_OPCODE_IBFE:
4967 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4968 break;
4969 case TGSI_OPCODE_UBFE:
4970 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4971 break;
4972 case TGSI_OPCODE_BFI:
4973 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4974 break;
4975 case TGSI_OPCODE_BREV:
4976 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4977 break;
4978 case TGSI_OPCODE_POPC:
4979 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4980 break;
4981 case TGSI_OPCODE_LSB:
4982 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4983 break;
4984 case TGSI_OPCODE_IMSB:
4985 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4986 break;
4987 case TGSI_OPCODE_UMSB:
4988 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4989 break;
4990
4991 case TGSI_OPCODE_F2D:
4992 exec_f2d(mach, inst);
4993 break;
4994
4995 case TGSI_OPCODE_D2F:
4996 exec_d2f(mach, inst);
4997 break;
4998
4999 case TGSI_OPCODE_DABS:
5000 exec_double_unary(mach, inst, micro_dabs);
5001 break;
5002
5003 case TGSI_OPCODE_DNEG:
5004 exec_double_unary(mach, inst, micro_dneg);
5005 break;
5006
5007 case TGSI_OPCODE_DADD:
5008 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
5009 break;
5010
5011 case TGSI_OPCODE_DMUL:
5012 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
5013 break;
5014
5015 case TGSI_OPCODE_DMAX:
5016 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
5017 break;
5018
5019 case TGSI_OPCODE_DMIN:
5020 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
5021 break;
5022
5023 case TGSI_OPCODE_DSLT:
5024 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
5025 break;
5026
5027 case TGSI_OPCODE_DSGE:
5028 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
5029 break;
5030
5031 case TGSI_OPCODE_DSEQ:
5032 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
5033 break;
5034
5035 case TGSI_OPCODE_DSNE:
5036 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
5037 break;
5038
5039 case TGSI_OPCODE_DRCP:
5040 exec_double_unary(mach, inst, micro_drcp);
5041 break;
5042
5043 case TGSI_OPCODE_DSQRT:
5044 exec_double_unary(mach, inst, micro_dsqrt);
5045 break;
5046
5047 case TGSI_OPCODE_DRSQ:
5048 exec_double_unary(mach, inst, micro_drsq);
5049 break;
5050
5051 case TGSI_OPCODE_DMAD:
5052 exec_double_trinary(mach, inst, micro_dmad);
5053 break;
5054
5055 case TGSI_OPCODE_DFRAC:
5056 exec_double_unary(mach, inst, micro_dfrac);
5057 break;
5058
5059 case TGSI_OPCODE_DLDEXP:
5060 exec_dldexp(mach, inst);
5061 break;
5062
5063 case TGSI_OPCODE_DFRACEXP:
5064 exec_dfracexp(mach, inst);
5065 break;
5066
5067 case TGSI_OPCODE_I2D:
5068 exec_i2d(mach, inst);
5069 break;
5070
5071 case TGSI_OPCODE_D2I:
5072 exec_d2i(mach, inst);
5073 break;
5074
5075 case TGSI_OPCODE_U2D:
5076 exec_u2d(mach, inst);
5077 break;
5078
5079 case TGSI_OPCODE_D2U:
5080 exec_d2u(mach, inst);
5081 break;
5082 default:
5083 assert( 0 );
5084 }
5085 }
5086
5087
5088 /**
5089 * Run TGSI interpreter.
5090 * \return bitmask of "alive" quad components
5091 */
5092 uint
5093 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
5094 {
5095 uint i;
5096 int pc = 0;
5097 uint default_mask = 0xf;
5098
5099 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
5100 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
5101
5102 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
5103 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
5104 mach->Primitives[0] = 0;
5105 /* GS runs on a single primitive for now */
5106 default_mask = 0x1;
5107 }
5108
5109 mach->CondMask = default_mask;
5110 mach->LoopMask = default_mask;
5111 mach->ContMask = default_mask;
5112 mach->FuncMask = default_mask;
5113 mach->ExecMask = default_mask;
5114
5115 mach->Switch.mask = default_mask;
5116
5117 assert(mach->CondStackTop == 0);
5118 assert(mach->LoopStackTop == 0);
5119 assert(mach->ContStackTop == 0);
5120 assert(mach->SwitchStackTop == 0);
5121 assert(mach->BreakStackTop == 0);
5122 assert(mach->CallStackTop == 0);
5123
5124
5125 /* execute declarations (interpolants) */
5126 for (i = 0; i < mach->NumDeclarations; i++) {
5127 exec_declaration( mach, mach->Declarations+i );
5128 }
5129
5130 {
5131 #if DEBUG_EXECUTION
5132 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
5133 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
5134 uint inst = 1;
5135
5136 memset(mach->Temps, 0, sizeof(temps));
5137 memset(mach->Outputs, 0, sizeof(outputs));
5138 memset(temps, 0, sizeof(temps));
5139 memset(outputs, 0, sizeof(outputs));
5140 #endif
5141
5142 /* execute instructions, until pc is set to -1 */
5143 while (pc != -1) {
5144
5145 #if DEBUG_EXECUTION
5146 uint i;
5147
5148 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
5149 #endif
5150
5151 assert(pc < (int) mach->NumInstructions);
5152 exec_instruction(mach, mach->Instructions + pc, &pc);
5153
5154 #if DEBUG_EXECUTION
5155 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
5156 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
5157 uint j;
5158
5159 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
5160 debug_printf("TEMP[%2u] = ", i);
5161 for (j = 0; j < 4; j++) {
5162 if (j > 0) {
5163 debug_printf(" ");
5164 }
5165 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5166 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
5167 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
5168 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
5169 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
5170 }
5171 }
5172 }
5173 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
5174 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
5175 uint j;
5176
5177 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
5178 debug_printf("OUT[%2u] = ", i);
5179 for (j = 0; j < 4; j++) {
5180 if (j > 0) {
5181 debug_printf(" ");
5182 }
5183 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5184 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
5185 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
5186 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
5187 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
5188 }
5189 }
5190 }
5191 #endif
5192 }
5193 }
5194
5195 #if 0
5196 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5197 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
5198 /*
5199 * Scale back depth component.
5200 */
5201 for (i = 0; i < 4; i++)
5202 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
5203 }
5204 #endif
5205
5206 /* Strictly speaking, these assertions aren't really needed but they
5207 * can potentially catch some bugs in the control flow code.
5208 */
5209 assert(mach->CondStackTop == 0);
5210 assert(mach->LoopStackTop == 0);
5211 assert(mach->ContStackTop == 0);
5212 assert(mach->SwitchStackTop == 0);
5213 assert(mach->BreakStackTop == 0);
5214 assert(mach->CallStackTop == 0);
5215
5216 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
5217 }