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gallium/tgsi: remove unused tgsi_exec_labels code
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 1
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_clamp(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src0,
115 const union tgsi_exec_channel *src1,
116 const union tgsi_exec_channel *src2)
117 {
118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
122 }
123
124 static void
125 micro_cmp(union tgsi_exec_channel *dst,
126 const union tgsi_exec_channel *src0,
127 const union tgsi_exec_channel *src1,
128 const union tgsi_exec_channel *src2)
129 {
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
134 }
135
136 static void
137 micro_cnd(union tgsi_exec_channel *dst,
138 const union tgsi_exec_channel *src0,
139 const union tgsi_exec_channel *src1,
140 const union tgsi_exec_channel *src2)
141 {
142 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
143 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
144 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
145 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
146 }
147
148 static void
149 micro_cos(union tgsi_exec_channel *dst,
150 const union tgsi_exec_channel *src)
151 {
152 dst->f[0] = cosf(src->f[0]);
153 dst->f[1] = cosf(src->f[1]);
154 dst->f[2] = cosf(src->f[2]);
155 dst->f[3] = cosf(src->f[3]);
156 }
157
158 static void
159 micro_ddx(union tgsi_exec_channel *dst,
160 const union tgsi_exec_channel *src)
161 {
162 dst->f[0] =
163 dst->f[1] =
164 dst->f[2] =
165 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
166 }
167
168 static void
169 micro_ddy(union tgsi_exec_channel *dst,
170 const union tgsi_exec_channel *src)
171 {
172 dst->f[0] =
173 dst->f[1] =
174 dst->f[2] =
175 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
176 }
177
178 static void
179 micro_exp2(union tgsi_exec_channel *dst,
180 const union tgsi_exec_channel *src)
181 {
182 #if FAST_MATH
183 dst->f[0] = util_fast_exp2(src->f[0]);
184 dst->f[1] = util_fast_exp2(src->f[1]);
185 dst->f[2] = util_fast_exp2(src->f[2]);
186 dst->f[3] = util_fast_exp2(src->f[3]);
187 #else
188 #if DEBUG
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
190 uint i;
191 union tgsi_exec_channel clamped;
192
193 for (i = 0; i < 4; i++) {
194 if (src->f[i] > 127.99999f) {
195 clamped.f[i] = 127.99999f;
196 } else if (src->f[i] < -126.99999f) {
197 clamped.f[i] = -126.99999f;
198 } else {
199 clamped.f[i] = src->f[i];
200 }
201 }
202 src = &clamped;
203 #endif /* DEBUG */
204
205 dst->f[0] = powf(2.0f, src->f[0]);
206 dst->f[1] = powf(2.0f, src->f[1]);
207 dst->f[2] = powf(2.0f, src->f[2]);
208 dst->f[3] = powf(2.0f, src->f[3]);
209 #endif /* FAST_MATH */
210 }
211
212 static void
213 micro_flr(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
215 {
216 dst->f[0] = floorf(src->f[0]);
217 dst->f[1] = floorf(src->f[1]);
218 dst->f[2] = floorf(src->f[2]);
219 dst->f[3] = floorf(src->f[3]);
220 }
221
222 static void
223 micro_frc(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
225 {
226 dst->f[0] = src->f[0] - floorf(src->f[0]);
227 dst->f[1] = src->f[1] - floorf(src->f[1]);
228 dst->f[2] = src->f[2] - floorf(src->f[2]);
229 dst->f[3] = src->f[3] - floorf(src->f[3]);
230 }
231
232 static void
233 micro_iabs(union tgsi_exec_channel *dst,
234 const union tgsi_exec_channel *src)
235 {
236 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
237 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
238 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
239 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
240 }
241
242 static void
243 micro_ineg(union tgsi_exec_channel *dst,
244 const union tgsi_exec_channel *src)
245 {
246 dst->i[0] = -src->i[0];
247 dst->i[1] = -src->i[1];
248 dst->i[2] = -src->i[2];
249 dst->i[3] = -src->i[3];
250 }
251
252 static void
253 micro_lg2(union tgsi_exec_channel *dst,
254 const union tgsi_exec_channel *src)
255 {
256 #if FAST_MATH
257 dst->f[0] = util_fast_log2(src->f[0]);
258 dst->f[1] = util_fast_log2(src->f[1]);
259 dst->f[2] = util_fast_log2(src->f[2]);
260 dst->f[3] = util_fast_log2(src->f[3]);
261 #else
262 dst->f[0] = logf(src->f[0]) * 1.442695f;
263 dst->f[1] = logf(src->f[1]) * 1.442695f;
264 dst->f[2] = logf(src->f[2]) * 1.442695f;
265 dst->f[3] = logf(src->f[3]) * 1.442695f;
266 #endif
267 }
268
269 static void
270 micro_lrp(union tgsi_exec_channel *dst,
271 const union tgsi_exec_channel *src0,
272 const union tgsi_exec_channel *src1,
273 const union tgsi_exec_channel *src2)
274 {
275 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
276 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
277 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
278 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
279 }
280
281 static void
282 micro_mad(union tgsi_exec_channel *dst,
283 const union tgsi_exec_channel *src0,
284 const union tgsi_exec_channel *src1,
285 const union tgsi_exec_channel *src2)
286 {
287 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
288 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
289 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
290 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
291 }
292
293 static void
294 micro_mov(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 dst->u[0] = src->u[0];
298 dst->u[1] = src->u[1];
299 dst->u[2] = src->u[2];
300 dst->u[3] = src->u[3];
301 }
302
303 static void
304 micro_rcp(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
306 {
307 #if 0 /* for debugging */
308 assert(src->f[0] != 0.0f);
309 assert(src->f[1] != 0.0f);
310 assert(src->f[2] != 0.0f);
311 assert(src->f[3] != 0.0f);
312 #endif
313 dst->f[0] = 1.0f / src->f[0];
314 dst->f[1] = 1.0f / src->f[1];
315 dst->f[2] = 1.0f / src->f[2];
316 dst->f[3] = 1.0f / src->f[3];
317 }
318
319 static void
320 micro_rnd(union tgsi_exec_channel *dst,
321 const union tgsi_exec_channel *src)
322 {
323 dst->f[0] = floorf(src->f[0] + 0.5f);
324 dst->f[1] = floorf(src->f[1] + 0.5f);
325 dst->f[2] = floorf(src->f[2] + 0.5f);
326 dst->f[3] = floorf(src->f[3] + 0.5f);
327 }
328
329 static void
330 micro_rsq(union tgsi_exec_channel *dst,
331 const union tgsi_exec_channel *src)
332 {
333 #if 0 /* for debugging */
334 assert(src->f[0] != 0.0f);
335 assert(src->f[1] != 0.0f);
336 assert(src->f[2] != 0.0f);
337 assert(src->f[3] != 0.0f);
338 #endif
339 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
340 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
341 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
342 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
343 }
344
345 static void
346 micro_seq(union tgsi_exec_channel *dst,
347 const union tgsi_exec_channel *src0,
348 const union tgsi_exec_channel *src1)
349 {
350 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
351 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
352 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
353 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
354 }
355
356 static void
357 micro_sge(union tgsi_exec_channel *dst,
358 const union tgsi_exec_channel *src0,
359 const union tgsi_exec_channel *src1)
360 {
361 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
362 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
363 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
364 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
365 }
366
367 static void
368 micro_sgn(union tgsi_exec_channel *dst,
369 const union tgsi_exec_channel *src)
370 {
371 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
372 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
373 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
374 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
375 }
376
377 static void
378 micro_sgt(union tgsi_exec_channel *dst,
379 const union tgsi_exec_channel *src0,
380 const union tgsi_exec_channel *src1)
381 {
382 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
383 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
384 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
385 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
386 }
387
388 static void
389 micro_sin(union tgsi_exec_channel *dst,
390 const union tgsi_exec_channel *src)
391 {
392 dst->f[0] = sinf(src->f[0]);
393 dst->f[1] = sinf(src->f[1]);
394 dst->f[2] = sinf(src->f[2]);
395 dst->f[3] = sinf(src->f[3]);
396 }
397
398 static void
399 micro_sle(union tgsi_exec_channel *dst,
400 const union tgsi_exec_channel *src0,
401 const union tgsi_exec_channel *src1)
402 {
403 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
404 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
405 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
406 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
407 }
408
409 static void
410 micro_slt(union tgsi_exec_channel *dst,
411 const union tgsi_exec_channel *src0,
412 const union tgsi_exec_channel *src1)
413 {
414 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
415 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
416 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
417 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
418 }
419
420 static void
421 micro_sne(union tgsi_exec_channel *dst,
422 const union tgsi_exec_channel *src0,
423 const union tgsi_exec_channel *src1)
424 {
425 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
426 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
427 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
428 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
429 }
430
431 static void
432 micro_trunc(union tgsi_exec_channel *dst,
433 const union tgsi_exec_channel *src)
434 {
435 dst->f[0] = (float)(int)src->f[0];
436 dst->f[1] = (float)(int)src->f[1];
437 dst->f[2] = (float)(int)src->f[2];
438 dst->f[3] = (float)(int)src->f[3];
439 }
440
441
442 #define CHAN_X 0
443 #define CHAN_Y 1
444 #define CHAN_Z 2
445 #define CHAN_W 3
446
447 enum tgsi_exec_datatype {
448 TGSI_EXEC_DATA_FLOAT,
449 TGSI_EXEC_DATA_INT,
450 TGSI_EXEC_DATA_UINT
451 };
452
453 /*
454 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
455 */
456 #define TEMP_0_I TGSI_EXEC_TEMP_00000000_I
457 #define TEMP_0_C TGSI_EXEC_TEMP_00000000_C
458 #define TEMP_7F_I TGSI_EXEC_TEMP_7FFFFFFF_I
459 #define TEMP_7F_C TGSI_EXEC_TEMP_7FFFFFFF_C
460 #define TEMP_80_I TGSI_EXEC_TEMP_80000000_I
461 #define TEMP_80_C TGSI_EXEC_TEMP_80000000_C
462 #define TEMP_FF_I TGSI_EXEC_TEMP_FFFFFFFF_I
463 #define TEMP_FF_C TGSI_EXEC_TEMP_FFFFFFFF_C
464 #define TEMP_1_I TGSI_EXEC_TEMP_ONE_I
465 #define TEMP_1_C TGSI_EXEC_TEMP_ONE_C
466 #define TEMP_2_I TGSI_EXEC_TEMP_TWO_I
467 #define TEMP_2_C TGSI_EXEC_TEMP_TWO_C
468 #define TEMP_128_I TGSI_EXEC_TEMP_128_I
469 #define TEMP_128_C TGSI_EXEC_TEMP_128_C
470 #define TEMP_M128_I TGSI_EXEC_TEMP_MINUS_128_I
471 #define TEMP_M128_C TGSI_EXEC_TEMP_MINUS_128_C
472 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
473 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
474 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
475 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
476 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
477 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
478 #define TEMP_CC_I TGSI_EXEC_TEMP_CC_I
479 #define TEMP_CC_C TGSI_EXEC_TEMP_CC_C
480 #define TEMP_3_I TGSI_EXEC_TEMP_THREE_I
481 #define TEMP_3_C TGSI_EXEC_TEMP_THREE_C
482 #define TEMP_HALF_I TGSI_EXEC_TEMP_HALF_I
483 #define TEMP_HALF_C TGSI_EXEC_TEMP_HALF_C
484 #define TEMP_R0 TGSI_EXEC_TEMP_R0
485 #define TEMP_P0 TGSI_EXEC_TEMP_P0
486
487 #define IS_CHANNEL_ENABLED(INST, CHAN)\
488 ((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
489
490 #define IS_CHANNEL_ENABLED2(INST, CHAN)\
491 ((INST).Dst[1].Register.WriteMask & (1 << (CHAN)))
492
493 #define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
494 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
495 if (IS_CHANNEL_ENABLED( INST, CHAN ))
496
497 #define FOR_EACH_ENABLED_CHANNEL2(INST, CHAN)\
498 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
499 if (IS_CHANNEL_ENABLED2( INST, CHAN ))
500
501
502 /** The execution mask depends on the conditional mask and the loop mask */
503 #define UPDATE_EXEC_MASK(MACH) \
504 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
505
506
507 static const union tgsi_exec_channel ZeroVec =
508 { { 0.0, 0.0, 0.0, 0.0 } };
509
510 static const union tgsi_exec_channel OneVec = {
511 {1.0f, 1.0f, 1.0f, 1.0f}
512 };
513
514
515 /**
516 * Assert that none of the float values in 'chan' are infinite or NaN.
517 * NaN and Inf may occur normally during program execution and should
518 * not lead to crashes, etc. But when debugging, it's helpful to catch
519 * them.
520 */
521 static INLINE void
522 check_inf_or_nan(const union tgsi_exec_channel *chan)
523 {
524 assert(!util_is_inf_or_nan((chan)->f[0]));
525 assert(!util_is_inf_or_nan((chan)->f[1]));
526 assert(!util_is_inf_or_nan((chan)->f[2]));
527 assert(!util_is_inf_or_nan((chan)->f[3]));
528 }
529
530
531 #ifdef DEBUG
532 static void
533 print_chan(const char *msg, const union tgsi_exec_channel *chan)
534 {
535 debug_printf("%s = {%f, %f, %f, %f}\n",
536 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
537 }
538 #endif
539
540
541 #ifdef DEBUG
542 static void
543 print_temp(const struct tgsi_exec_machine *mach, uint index)
544 {
545 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
546 int i;
547 debug_printf("Temp[%u] =\n", index);
548 for (i = 0; i < 4; i++) {
549 debug_printf(" %c: { %f, %f, %f, %f }\n",
550 "XYZW"[i],
551 tmp->xyzw[i].f[0],
552 tmp->xyzw[i].f[1],
553 tmp->xyzw[i].f[2],
554 tmp->xyzw[i].f[3]);
555 }
556 }
557 #endif
558
559
560 /**
561 * Check if there's a potential src/dst register data dependency when
562 * using SOA execution.
563 * Example:
564 * MOV T, T.yxwz;
565 * This would expand into:
566 * MOV t0, t1;
567 * MOV t1, t0;
568 * MOV t2, t3;
569 * MOV t3, t2;
570 * The second instruction will have the wrong value for t0 if executed as-is.
571 */
572 boolean
573 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
574 {
575 uint i, chan;
576
577 uint writemask = inst->Dst[0].Register.WriteMask;
578 if (writemask == TGSI_WRITEMASK_X ||
579 writemask == TGSI_WRITEMASK_Y ||
580 writemask == TGSI_WRITEMASK_Z ||
581 writemask == TGSI_WRITEMASK_W ||
582 writemask == TGSI_WRITEMASK_NONE) {
583 /* no chance of data dependency */
584 return FALSE;
585 }
586
587 /* loop over src regs */
588 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
589 if ((inst->Src[i].Register.File ==
590 inst->Dst[0].Register.File) &&
591 (inst->Src[i].Register.Index ==
592 inst->Dst[0].Register.Index)) {
593 /* loop over dest channels */
594 uint channelsWritten = 0x0;
595 FOR_EACH_ENABLED_CHANNEL(*inst, chan) {
596 /* check if we're reading a channel that's been written */
597 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
598 if (channelsWritten & (1 << swizzle)) {
599 return TRUE;
600 }
601
602 channelsWritten |= (1 << chan);
603 }
604 }
605 }
606 return FALSE;
607 }
608
609
610 /**
611 * Initialize machine state by expanding tokens to full instructions,
612 * allocating temporary storage, setting up constants, etc.
613 * After this, we can call tgsi_exec_machine_run() many times.
614 */
615 void
616 tgsi_exec_machine_bind_shader(
617 struct tgsi_exec_machine *mach,
618 const struct tgsi_token *tokens,
619 uint numSamplers,
620 struct tgsi_sampler **samplers)
621 {
622 uint k;
623 struct tgsi_parse_context parse;
624 struct tgsi_full_instruction *instructions;
625 struct tgsi_full_declaration *declarations;
626 uint maxInstructions = 10, numInstructions = 0;
627 uint maxDeclarations = 10, numDeclarations = 0;
628
629 #if 0
630 tgsi_dump(tokens, 0);
631 #endif
632
633 util_init_math();
634
635 mach->Tokens = tokens;
636 mach->Samplers = samplers;
637
638 k = tgsi_parse_init (&parse, mach->Tokens);
639 if (k != TGSI_PARSE_OK) {
640 debug_printf( "Problem parsing!\n" );
641 return;
642 }
643
644 mach->Processor = parse.FullHeader.Processor.Processor;
645 mach->ImmLimit = 0;
646
647 declarations = (struct tgsi_full_declaration *)
648 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
649
650 if (!declarations) {
651 return;
652 }
653
654 instructions = (struct tgsi_full_instruction *)
655 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
656
657 if (!instructions) {
658 FREE( declarations );
659 return;
660 }
661
662 while( !tgsi_parse_end_of_tokens( &parse ) ) {
663 uint i;
664
665 tgsi_parse_token( &parse );
666 switch( parse.FullToken.Token.Type ) {
667 case TGSI_TOKEN_TYPE_DECLARATION:
668 /* save expanded declaration */
669 if (numDeclarations == maxDeclarations) {
670 declarations = REALLOC(declarations,
671 maxDeclarations
672 * sizeof(struct tgsi_full_declaration),
673 (maxDeclarations + 10)
674 * sizeof(struct tgsi_full_declaration));
675 maxDeclarations += 10;
676 }
677 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
678 unsigned reg;
679 for (reg = parse.FullToken.FullDeclaration.Range.First;
680 reg <= parse.FullToken.FullDeclaration.Range.Last;
681 ++reg) {
682 ++mach->NumOutputs;
683 }
684 }
685 memcpy(declarations + numDeclarations,
686 &parse.FullToken.FullDeclaration,
687 sizeof(declarations[0]));
688 numDeclarations++;
689 break;
690
691 case TGSI_TOKEN_TYPE_IMMEDIATE:
692 {
693 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
694 assert( size <= 4 );
695 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
696
697 for( i = 0; i < size; i++ ) {
698 mach->Imms[mach->ImmLimit][i] =
699 parse.FullToken.FullImmediate.u[i].Float;
700 }
701 mach->ImmLimit += 1;
702 }
703 break;
704
705 case TGSI_TOKEN_TYPE_INSTRUCTION:
706
707 /* save expanded instruction */
708 if (numInstructions == maxInstructions) {
709 instructions = REALLOC(instructions,
710 maxInstructions
711 * sizeof(struct tgsi_full_instruction),
712 (maxInstructions + 10)
713 * sizeof(struct tgsi_full_instruction));
714 maxInstructions += 10;
715 }
716
717 memcpy(instructions + numInstructions,
718 &parse.FullToken.FullInstruction,
719 sizeof(instructions[0]));
720
721 numInstructions++;
722 break;
723
724 case TGSI_TOKEN_TYPE_PROPERTY:
725 break;
726
727 default:
728 assert( 0 );
729 }
730 }
731 tgsi_parse_free (&parse);
732
733 if (mach->Declarations) {
734 FREE( mach->Declarations );
735 }
736 mach->Declarations = declarations;
737 mach->NumDeclarations = numDeclarations;
738
739 if (mach->Instructions) {
740 FREE( mach->Instructions );
741 }
742 mach->Instructions = instructions;
743 mach->NumInstructions = numInstructions;
744 }
745
746
747 struct tgsi_exec_machine *
748 tgsi_exec_machine_create( void )
749 {
750 struct tgsi_exec_machine *mach;
751 uint i;
752
753 mach = align_malloc( sizeof *mach, 16 );
754 if (!mach)
755 goto fail;
756
757 memset(mach, 0, sizeof(*mach));
758
759 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
760 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
761 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
762
763 /* Setup constants. */
764 for( i = 0; i < 4; i++ ) {
765 mach->Temps[TEMP_0_I].xyzw[TEMP_0_C].u[i] = 0x00000000;
766 mach->Temps[TEMP_7F_I].xyzw[TEMP_7F_C].u[i] = 0x7FFFFFFF;
767 mach->Temps[TEMP_80_I].xyzw[TEMP_80_C].u[i] = 0x80000000;
768 mach->Temps[TEMP_FF_I].xyzw[TEMP_FF_C].u[i] = 0xFFFFFFFF;
769 mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].f[i] = 1.0f;
770 mach->Temps[TEMP_2_I].xyzw[TEMP_2_C].f[i] = 2.0f;
771 mach->Temps[TEMP_128_I].xyzw[TEMP_128_C].f[i] = 128.0f;
772 mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C].f[i] = -128.0f;
773 mach->Temps[TEMP_3_I].xyzw[TEMP_3_C].f[i] = 3.0f;
774 mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C].f[i] = 0.5f;
775 }
776
777 #ifdef DEBUG
778 /* silence warnings */
779 (void) print_chan;
780 (void) print_temp;
781 #endif
782
783 return mach;
784
785 fail:
786 align_free(mach);
787 return NULL;
788 }
789
790
791 void
792 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
793 {
794 if (mach) {
795 FREE(mach->Instructions);
796 FREE(mach->Declarations);
797 }
798
799 align_free(mach);
800 }
801
802 static void
803 micro_add(union tgsi_exec_channel *dst,
804 const union tgsi_exec_channel *src0,
805 const union tgsi_exec_channel *src1)
806 {
807 dst->f[0] = src0->f[0] + src1->f[0];
808 dst->f[1] = src0->f[1] + src1->f[1];
809 dst->f[2] = src0->f[2] + src1->f[2];
810 dst->f[3] = src0->f[3] + src1->f[3];
811 }
812
813 static void
814 micro_div(
815 union tgsi_exec_channel *dst,
816 const union tgsi_exec_channel *src0,
817 const union tgsi_exec_channel *src1 )
818 {
819 if (src1->f[0] != 0) {
820 dst->f[0] = src0->f[0] / src1->f[0];
821 }
822 if (src1->f[1] != 0) {
823 dst->f[1] = src0->f[1] / src1->f[1];
824 }
825 if (src1->f[2] != 0) {
826 dst->f[2] = src0->f[2] / src1->f[2];
827 }
828 if (src1->f[3] != 0) {
829 dst->f[3] = src0->f[3] / src1->f[3];
830 }
831 }
832
833 static void
834 micro_float_clamp(union tgsi_exec_channel *dst,
835 const union tgsi_exec_channel *src)
836 {
837 uint i;
838
839 for (i = 0; i < 4; i++) {
840 if (src->f[i] > 0.0f) {
841 if (src->f[i] > 1.884467e+019f)
842 dst->f[i] = 1.884467e+019f;
843 else if (src->f[i] < 5.42101e-020f)
844 dst->f[i] = 5.42101e-020f;
845 else
846 dst->f[i] = src->f[i];
847 }
848 else {
849 if (src->f[i] < -1.884467e+019f)
850 dst->f[i] = -1.884467e+019f;
851 else if (src->f[i] > -5.42101e-020f)
852 dst->f[i] = -5.42101e-020f;
853 else
854 dst->f[i] = src->f[i];
855 }
856 }
857 }
858
859 static void
860 micro_lt(
861 union tgsi_exec_channel *dst,
862 const union tgsi_exec_channel *src0,
863 const union tgsi_exec_channel *src1,
864 const union tgsi_exec_channel *src2,
865 const union tgsi_exec_channel *src3 )
866 {
867 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
868 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
869 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
870 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
871 }
872
873 static void
874 micro_max(union tgsi_exec_channel *dst,
875 const union tgsi_exec_channel *src0,
876 const union tgsi_exec_channel *src1)
877 {
878 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
879 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
880 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
881 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
882 }
883
884 static void
885 micro_min(union tgsi_exec_channel *dst,
886 const union tgsi_exec_channel *src0,
887 const union tgsi_exec_channel *src1)
888 {
889 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
890 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
891 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
892 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
893 }
894
895 static void
896 micro_mul(union tgsi_exec_channel *dst,
897 const union tgsi_exec_channel *src0,
898 const union tgsi_exec_channel *src1)
899 {
900 dst->f[0] = src0->f[0] * src1->f[0];
901 dst->f[1] = src0->f[1] * src1->f[1];
902 dst->f[2] = src0->f[2] * src1->f[2];
903 dst->f[3] = src0->f[3] * src1->f[3];
904 }
905
906 #if 0
907 static void
908 micro_imul64(
909 union tgsi_exec_channel *dst0,
910 union tgsi_exec_channel *dst1,
911 const union tgsi_exec_channel *src0,
912 const union tgsi_exec_channel *src1 )
913 {
914 dst1->i[0] = src0->i[0] * src1->i[0];
915 dst1->i[1] = src0->i[1] * src1->i[1];
916 dst1->i[2] = src0->i[2] * src1->i[2];
917 dst1->i[3] = src0->i[3] * src1->i[3];
918 dst0->i[0] = 0;
919 dst0->i[1] = 0;
920 dst0->i[2] = 0;
921 dst0->i[3] = 0;
922 }
923 #endif
924
925 #if 0
926 static void
927 micro_umul64(
928 union tgsi_exec_channel *dst0,
929 union tgsi_exec_channel *dst1,
930 const union tgsi_exec_channel *src0,
931 const union tgsi_exec_channel *src1 )
932 {
933 dst1->u[0] = src0->u[0] * src1->u[0];
934 dst1->u[1] = src0->u[1] * src1->u[1];
935 dst1->u[2] = src0->u[2] * src1->u[2];
936 dst1->u[3] = src0->u[3] * src1->u[3];
937 dst0->u[0] = 0;
938 dst0->u[1] = 0;
939 dst0->u[2] = 0;
940 dst0->u[3] = 0;
941 }
942 #endif
943
944
945 #if 0
946 static void
947 micro_movc(
948 union tgsi_exec_channel *dst,
949 const union tgsi_exec_channel *src0,
950 const union tgsi_exec_channel *src1,
951 const union tgsi_exec_channel *src2 )
952 {
953 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
954 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
955 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
956 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
957 }
958 #endif
959
960 static void
961 micro_neg(
962 union tgsi_exec_channel *dst,
963 const union tgsi_exec_channel *src )
964 {
965 dst->f[0] = -src->f[0];
966 dst->f[1] = -src->f[1];
967 dst->f[2] = -src->f[2];
968 dst->f[3] = -src->f[3];
969 }
970
971 static void
972 micro_pow(
973 union tgsi_exec_channel *dst,
974 const union tgsi_exec_channel *src0,
975 const union tgsi_exec_channel *src1 )
976 {
977 #if FAST_MATH
978 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
979 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
980 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
981 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
982 #else
983 dst->f[0] = powf( src0->f[0], src1->f[0] );
984 dst->f[1] = powf( src0->f[1], src1->f[1] );
985 dst->f[2] = powf( src0->f[2], src1->f[2] );
986 dst->f[3] = powf( src0->f[3], src1->f[3] );
987 #endif
988 }
989
990 static void
991 micro_sub(union tgsi_exec_channel *dst,
992 const union tgsi_exec_channel *src0,
993 const union tgsi_exec_channel *src1)
994 {
995 dst->f[0] = src0->f[0] - src1->f[0];
996 dst->f[1] = src0->f[1] - src1->f[1];
997 dst->f[2] = src0->f[2] - src1->f[2];
998 dst->f[3] = src0->f[3] - src1->f[3];
999 }
1000
1001 static void
1002 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1003 const uint file,
1004 const uint swizzle,
1005 const union tgsi_exec_channel *index,
1006 const union tgsi_exec_channel *index2D,
1007 union tgsi_exec_channel *chan)
1008 {
1009 uint i;
1010
1011 switch (file) {
1012 case TGSI_FILE_CONSTANT:
1013 for (i = 0; i < QUAD_SIZE; i++) {
1014 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1015 assert(mach->Consts[index2D->i[i]]);
1016
1017 if (index->i[i] < 0) {
1018 chan->u[i] = 0;
1019 } else {
1020 const uint *p = (const uint *)mach->Consts[index2D->i[i]];
1021
1022 chan->u[i] = p[index->i[i] * 4 + swizzle];
1023 }
1024 }
1025 break;
1026
1027 case TGSI_FILE_INPUT:
1028 case TGSI_FILE_SYSTEM_VALUE:
1029 for (i = 0; i < QUAD_SIZE; i++) {
1030 /* XXX: 2D indexing */
1031 chan->u[i] = mach->Inputs[index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i]].xyzw[swizzle].u[i];
1032 }
1033 break;
1034
1035 case TGSI_FILE_TEMPORARY:
1036 for (i = 0; i < QUAD_SIZE; i++) {
1037 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1038 assert(index2D->i[i] == 0);
1039
1040 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1041 }
1042 break;
1043
1044 case TGSI_FILE_IMMEDIATE:
1045 for (i = 0; i < QUAD_SIZE; i++) {
1046 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1047 assert(index2D->i[i] == 0);
1048
1049 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1050 }
1051 break;
1052
1053 case TGSI_FILE_ADDRESS:
1054 for (i = 0; i < QUAD_SIZE; i++) {
1055 assert(index->i[i] >= 0);
1056 assert(index2D->i[i] == 0);
1057
1058 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1059 }
1060 break;
1061
1062 case TGSI_FILE_PREDICATE:
1063 for (i = 0; i < QUAD_SIZE; i++) {
1064 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1065 assert(index2D->i[i] == 0);
1066
1067 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1068 }
1069 break;
1070
1071 case TGSI_FILE_OUTPUT:
1072 /* vertex/fragment output vars can be read too */
1073 for (i = 0; i < QUAD_SIZE; i++) {
1074 assert(index->i[i] >= 0);
1075 assert(index2D->i[i] == 0);
1076
1077 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1078 }
1079 break;
1080
1081 default:
1082 assert(0);
1083 for (i = 0; i < QUAD_SIZE; i++) {
1084 chan->u[i] = 0;
1085 }
1086 }
1087 }
1088
1089 static void
1090 fetch_source(const struct tgsi_exec_machine *mach,
1091 union tgsi_exec_channel *chan,
1092 const struct tgsi_full_src_register *reg,
1093 const uint chan_index,
1094 enum tgsi_exec_datatype src_datatype)
1095 {
1096 union tgsi_exec_channel index;
1097 union tgsi_exec_channel index2D;
1098 uint swizzle;
1099
1100 /* We start with a direct index into a register file.
1101 *
1102 * file[1],
1103 * where:
1104 * file = Register.File
1105 * [1] = Register.Index
1106 */
1107 index.i[0] =
1108 index.i[1] =
1109 index.i[2] =
1110 index.i[3] = reg->Register.Index;
1111
1112 /* There is an extra source register that indirectly subscripts
1113 * a register file. The direct index now becomes an offset
1114 * that is being added to the indirect register.
1115 *
1116 * file[ind[2].x+1],
1117 * where:
1118 * ind = Indirect.File
1119 * [2] = Indirect.Index
1120 * .x = Indirect.SwizzleX
1121 */
1122 if (reg->Register.Indirect) {
1123 union tgsi_exec_channel index2;
1124 union tgsi_exec_channel indir_index;
1125 const uint execmask = mach->ExecMask;
1126 uint i;
1127
1128 /* which address register (always zero now) */
1129 index2.i[0] =
1130 index2.i[1] =
1131 index2.i[2] =
1132 index2.i[3] = reg->Indirect.Index;
1133
1134 /* get current value of address register[swizzle] */
1135 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1136 fetch_src_file_channel(mach,
1137 reg->Indirect.File,
1138 swizzle,
1139 &index2,
1140 &ZeroVec,
1141 &indir_index);
1142
1143 /* add value of address register to the offset */
1144 index.i[0] += indir_index.i[0];
1145 index.i[1] += indir_index.i[1];
1146 index.i[2] += indir_index.i[2];
1147 index.i[3] += indir_index.i[3];
1148
1149 /* for disabled execution channels, zero-out the index to
1150 * avoid using a potential garbage value.
1151 */
1152 for (i = 0; i < QUAD_SIZE; i++) {
1153 if ((execmask & (1 << i)) == 0)
1154 index.i[i] = 0;
1155 }
1156 }
1157
1158 /* There is an extra source register that is a second
1159 * subscript to a register file. Effectively it means that
1160 * the register file is actually a 2D array of registers.
1161 *
1162 * file[3][1],
1163 * where:
1164 * [3] = Dimension.Index
1165 */
1166 if (reg->Register.Dimension) {
1167 index2D.i[0] =
1168 index2D.i[1] =
1169 index2D.i[2] =
1170 index2D.i[3] = reg->Dimension.Index;
1171
1172 /* Again, the second subscript index can be addressed indirectly
1173 * identically to the first one.
1174 * Nothing stops us from indirectly addressing the indirect register,
1175 * but there is no need for that, so we won't exercise it.
1176 *
1177 * file[ind[4].y+3][1],
1178 * where:
1179 * ind = DimIndirect.File
1180 * [4] = DimIndirect.Index
1181 * .y = DimIndirect.SwizzleX
1182 */
1183 if (reg->Dimension.Indirect) {
1184 union tgsi_exec_channel index2;
1185 union tgsi_exec_channel indir_index;
1186 const uint execmask = mach->ExecMask;
1187 uint i;
1188
1189 index2.i[0] =
1190 index2.i[1] =
1191 index2.i[2] =
1192 index2.i[3] = reg->DimIndirect.Index;
1193
1194 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1195 fetch_src_file_channel(mach,
1196 reg->DimIndirect.File,
1197 swizzle,
1198 &index2,
1199 &ZeroVec,
1200 &indir_index);
1201
1202 index2D.i[0] += indir_index.i[0];
1203 index2D.i[1] += indir_index.i[1];
1204 index2D.i[2] += indir_index.i[2];
1205 index2D.i[3] += indir_index.i[3];
1206
1207 /* for disabled execution channels, zero-out the index to
1208 * avoid using a potential garbage value.
1209 */
1210 for (i = 0; i < QUAD_SIZE; i++) {
1211 if ((execmask & (1 << i)) == 0) {
1212 index2D.i[i] = 0;
1213 }
1214 }
1215 }
1216
1217 /* If by any chance there was a need for a 3D array of register
1218 * files, we would have to check whether Dimension is followed
1219 * by a dimension register and continue the saga.
1220 */
1221 } else {
1222 index2D.i[0] =
1223 index2D.i[1] =
1224 index2D.i[2] =
1225 index2D.i[3] = 0;
1226 }
1227
1228 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1229 fetch_src_file_channel(mach,
1230 reg->Register.File,
1231 swizzle,
1232 &index,
1233 &index2D,
1234 chan);
1235
1236 if (reg->Register.Absolute) {
1237 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1238 micro_abs(chan, chan);
1239 } else {
1240 micro_iabs(chan, chan);
1241 }
1242 }
1243
1244 if (reg->Register.Negate) {
1245 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1246 micro_neg(chan, chan);
1247 } else {
1248 micro_ineg(chan, chan);
1249 }
1250 }
1251 }
1252
1253 static void
1254 store_dest(struct tgsi_exec_machine *mach,
1255 const union tgsi_exec_channel *chan,
1256 const struct tgsi_full_dst_register *reg,
1257 const struct tgsi_full_instruction *inst,
1258 uint chan_index,
1259 enum tgsi_exec_datatype dst_datatype)
1260 {
1261 uint i;
1262 union tgsi_exec_channel null;
1263 union tgsi_exec_channel *dst;
1264 uint execmask = mach->ExecMask;
1265 int offset = 0; /* indirection offset */
1266 int index;
1267
1268 /* for debugging */
1269 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1270 check_inf_or_nan(chan);
1271 }
1272
1273 /* There is an extra source register that indirectly subscripts
1274 * a register file. The direct index now becomes an offset
1275 * that is being added to the indirect register.
1276 *
1277 * file[ind[2].x+1],
1278 * where:
1279 * ind = Indirect.File
1280 * [2] = Indirect.Index
1281 * .x = Indirect.SwizzleX
1282 */
1283 if (reg->Register.Indirect) {
1284 union tgsi_exec_channel index;
1285 union tgsi_exec_channel indir_index;
1286 uint swizzle;
1287
1288 /* which address register (always zero for now) */
1289 index.i[0] =
1290 index.i[1] =
1291 index.i[2] =
1292 index.i[3] = reg->Indirect.Index;
1293
1294 /* get current value of address register[swizzle] */
1295 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1296
1297 /* fetch values from the address/indirection register */
1298 fetch_src_file_channel(mach,
1299 reg->Indirect.File,
1300 swizzle,
1301 &index,
1302 &ZeroVec,
1303 &indir_index);
1304
1305 /* save indirection offset */
1306 offset = indir_index.i[0];
1307 }
1308
1309 switch (reg->Register.File) {
1310 case TGSI_FILE_NULL:
1311 dst = &null;
1312 break;
1313
1314 case TGSI_FILE_OUTPUT:
1315 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1316 + reg->Register.Index;
1317 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1318 #if 0
1319 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1320 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1321 for (i = 0; i < QUAD_SIZE; i++)
1322 if (execmask & (1 << i))
1323 fprintf(stderr, "%f, ", chan->f[i]);
1324 fprintf(stderr, ")\n");
1325 }
1326 #endif
1327 break;
1328
1329 case TGSI_FILE_TEMPORARY:
1330 index = reg->Register.Index;
1331 assert( index < TGSI_EXEC_NUM_TEMPS );
1332 dst = &mach->Temps[offset + index].xyzw[chan_index];
1333 break;
1334
1335 case TGSI_FILE_ADDRESS:
1336 index = reg->Register.Index;
1337 dst = &mach->Addrs[index].xyzw[chan_index];
1338 break;
1339
1340 case TGSI_FILE_PREDICATE:
1341 index = reg->Register.Index;
1342 assert(index < TGSI_EXEC_NUM_PREDS);
1343 dst = &mach->Predicates[index].xyzw[chan_index];
1344 break;
1345
1346 default:
1347 assert( 0 );
1348 return;
1349 }
1350
1351 if (inst->Instruction.Predicate) {
1352 uint swizzle;
1353 union tgsi_exec_channel *pred;
1354
1355 switch (chan_index) {
1356 case CHAN_X:
1357 swizzle = inst->Predicate.SwizzleX;
1358 break;
1359 case CHAN_Y:
1360 swizzle = inst->Predicate.SwizzleY;
1361 break;
1362 case CHAN_Z:
1363 swizzle = inst->Predicate.SwizzleZ;
1364 break;
1365 case CHAN_W:
1366 swizzle = inst->Predicate.SwizzleW;
1367 break;
1368 default:
1369 assert(0);
1370 return;
1371 }
1372
1373 assert(inst->Predicate.Index == 0);
1374
1375 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1376
1377 if (inst->Predicate.Negate) {
1378 for (i = 0; i < QUAD_SIZE; i++) {
1379 if (pred->u[i]) {
1380 execmask &= ~(1 << i);
1381 }
1382 }
1383 } else {
1384 for (i = 0; i < QUAD_SIZE; i++) {
1385 if (!pred->u[i]) {
1386 execmask &= ~(1 << i);
1387 }
1388 }
1389 }
1390 }
1391
1392 switch (inst->Instruction.Saturate) {
1393 case TGSI_SAT_NONE:
1394 for (i = 0; i < QUAD_SIZE; i++)
1395 if (execmask & (1 << i))
1396 dst->i[i] = chan->i[i];
1397 break;
1398
1399 case TGSI_SAT_ZERO_ONE:
1400 for (i = 0; i < QUAD_SIZE; i++)
1401 if (execmask & (1 << i)) {
1402 if (chan->f[i] < 0.0f)
1403 dst->f[i] = 0.0f;
1404 else if (chan->f[i] > 1.0f)
1405 dst->f[i] = 1.0f;
1406 else
1407 dst->i[i] = chan->i[i];
1408 }
1409 break;
1410
1411 case TGSI_SAT_MINUS_PLUS_ONE:
1412 for (i = 0; i < QUAD_SIZE; i++)
1413 if (execmask & (1 << i)) {
1414 if (chan->f[i] < -1.0f)
1415 dst->f[i] = -1.0f;
1416 else if (chan->f[i] > 1.0f)
1417 dst->f[i] = 1.0f;
1418 else
1419 dst->i[i] = chan->i[i];
1420 }
1421 break;
1422
1423 default:
1424 assert( 0 );
1425 }
1426 }
1427
1428 #define FETCH(VAL,INDEX,CHAN)\
1429 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1430
1431 #define STORE(VAL,INDEX,CHAN)\
1432 store_dest(mach, VAL, &inst->Dst[INDEX], inst, CHAN, TGSI_EXEC_DATA_FLOAT)
1433
1434
1435 /**
1436 * Execute ARB-style KIL which is predicated by a src register.
1437 * Kill fragment if any of the four values is less than zero.
1438 */
1439 static void
1440 exec_kil(struct tgsi_exec_machine *mach,
1441 const struct tgsi_full_instruction *inst)
1442 {
1443 uint uniquemask;
1444 uint chan_index;
1445 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1446 union tgsi_exec_channel r[1];
1447
1448 /* This mask stores component bits that were already tested. */
1449 uniquemask = 0;
1450
1451 for (chan_index = 0; chan_index < 4; chan_index++)
1452 {
1453 uint swizzle;
1454 uint i;
1455
1456 /* unswizzle channel */
1457 swizzle = tgsi_util_get_full_src_register_swizzle (
1458 &inst->Src[0],
1459 chan_index);
1460
1461 /* check if the component has not been already tested */
1462 if (uniquemask & (1 << swizzle))
1463 continue;
1464 uniquemask |= 1 << swizzle;
1465
1466 FETCH(&r[0], 0, chan_index);
1467 for (i = 0; i < 4; i++)
1468 if (r[0].f[i] < 0.0f)
1469 kilmask |= 1 << i;
1470 }
1471
1472 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1473 }
1474
1475 /**
1476 * Execute NVIDIA-style KIL which is predicated by a condition code.
1477 * Kill fragment if the condition code is TRUE.
1478 */
1479 static void
1480 exec_kilp(struct tgsi_exec_machine *mach,
1481 const struct tgsi_full_instruction *inst)
1482 {
1483 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1484
1485 /* "unconditional" kil */
1486 kilmask = mach->ExecMask;
1487 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1488 }
1489
1490 static void
1491 emit_vertex(struct tgsi_exec_machine *mach)
1492 {
1493 /* FIXME: check for exec mask correctly
1494 unsigned i;
1495 for (i = 0; i < QUAD_SIZE; ++i) {
1496 if ((mach->ExecMask & (1 << i)))
1497 */
1498 if (mach->ExecMask) {
1499 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1500 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1501 }
1502 }
1503
1504 static void
1505 emit_primitive(struct tgsi_exec_machine *mach)
1506 {
1507 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1508 /* FIXME: check for exec mask correctly
1509 unsigned i;
1510 for (i = 0; i < QUAD_SIZE; ++i) {
1511 if ((mach->ExecMask & (1 << i)))
1512 */
1513 if (mach->ExecMask) {
1514 ++(*prim_count);
1515 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1516 mach->Primitives[*prim_count] = 0;
1517 }
1518 }
1519
1520 /*
1521 * Fetch four texture samples using STR texture coordinates.
1522 */
1523 static void
1524 fetch_texel( struct tgsi_sampler *sampler,
1525 const union tgsi_exec_channel *s,
1526 const union tgsi_exec_channel *t,
1527 const union tgsi_exec_channel *p,
1528 const union tgsi_exec_channel *c0,
1529 enum tgsi_sampler_control control,
1530 union tgsi_exec_channel *r,
1531 union tgsi_exec_channel *g,
1532 union tgsi_exec_channel *b,
1533 union tgsi_exec_channel *a )
1534 {
1535 uint j;
1536 float rgba[NUM_CHANNELS][QUAD_SIZE];
1537
1538 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, control, rgba);
1539
1540 for (j = 0; j < 4; j++) {
1541 r->f[j] = rgba[0][j];
1542 g->f[j] = rgba[1][j];
1543 b->f[j] = rgba[2][j];
1544 a->f[j] = rgba[3][j];
1545 }
1546 }
1547
1548
1549 #define TEX_MODIFIER_NONE 0
1550 #define TEX_MODIFIER_PROJECTED 1
1551 #define TEX_MODIFIER_LOD_BIAS 2
1552 #define TEX_MODIFIER_EXPLICIT_LOD 3
1553
1554
1555 static void
1556 exec_tex(struct tgsi_exec_machine *mach,
1557 const struct tgsi_full_instruction *inst,
1558 uint modifier)
1559 {
1560 const uint unit = inst->Src[1].Register.Index;
1561 union tgsi_exec_channel r[4];
1562 const union tgsi_exec_channel *lod = &ZeroVec;
1563 enum tgsi_sampler_control control;
1564 uint chan_index;
1565
1566 if (modifier != TEX_MODIFIER_NONE) {
1567 FETCH(&r[3], 0, CHAN_W);
1568 if (modifier != TEX_MODIFIER_PROJECTED) {
1569 lod = &r[3];
1570 }
1571 }
1572
1573 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1574 control = tgsi_sampler_lod_explicit;
1575 } else {
1576 control = tgsi_sampler_lod_bias;
1577 }
1578
1579 switch (inst->Texture.Texture) {
1580 case TGSI_TEXTURE_1D:
1581 case TGSI_TEXTURE_SHADOW1D:
1582 FETCH(&r[0], 0, CHAN_X);
1583
1584 if (modifier == TEX_MODIFIER_PROJECTED) {
1585 micro_div(&r[0], &r[0], &r[3]);
1586 }
1587
1588 fetch_texel(mach->Samplers[unit],
1589 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1590 control,
1591 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1592 break;
1593
1594 case TGSI_TEXTURE_2D:
1595 case TGSI_TEXTURE_RECT:
1596 case TGSI_TEXTURE_SHADOW2D:
1597 case TGSI_TEXTURE_SHADOWRECT:
1598 FETCH(&r[0], 0, CHAN_X);
1599 FETCH(&r[1], 0, CHAN_Y);
1600 FETCH(&r[2], 0, CHAN_Z);
1601
1602 if (modifier == TEX_MODIFIER_PROJECTED) {
1603 micro_div(&r[0], &r[0], &r[3]);
1604 micro_div(&r[1], &r[1], &r[3]);
1605 micro_div(&r[2], &r[2], &r[3]);
1606 }
1607
1608 fetch_texel(mach->Samplers[unit],
1609 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1610 control,
1611 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1612 break;
1613
1614 case TGSI_TEXTURE_3D:
1615 case TGSI_TEXTURE_CUBE:
1616 FETCH(&r[0], 0, CHAN_X);
1617 FETCH(&r[1], 0, CHAN_Y);
1618 FETCH(&r[2], 0, CHAN_Z);
1619
1620 if (modifier == TEX_MODIFIER_PROJECTED) {
1621 micro_div(&r[0], &r[0], &r[3]);
1622 micro_div(&r[1], &r[1], &r[3]);
1623 micro_div(&r[2], &r[2], &r[3]);
1624 }
1625
1626 fetch_texel(mach->Samplers[unit],
1627 &r[0], &r[1], &r[2], lod,
1628 control,
1629 &r[0], &r[1], &r[2], &r[3]);
1630 break;
1631
1632 default:
1633 assert(0);
1634 }
1635
1636 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1637 STORE(&r[chan_index], 0, chan_index);
1638 }
1639 }
1640
1641 static void
1642 exec_txd(struct tgsi_exec_machine *mach,
1643 const struct tgsi_full_instruction *inst)
1644 {
1645 const uint unit = inst->Src[3].Register.Index;
1646 union tgsi_exec_channel r[4];
1647 uint chan_index;
1648
1649 /*
1650 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1651 */
1652
1653 switch (inst->Texture.Texture) {
1654 case TGSI_TEXTURE_1D:
1655 case TGSI_TEXTURE_SHADOW1D:
1656
1657 FETCH(&r[0], 0, CHAN_X);
1658
1659 fetch_texel(mach->Samplers[unit],
1660 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1661 tgsi_sampler_lod_bias,
1662 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1663 break;
1664
1665 case TGSI_TEXTURE_2D:
1666 case TGSI_TEXTURE_RECT:
1667 case TGSI_TEXTURE_SHADOW2D:
1668 case TGSI_TEXTURE_SHADOWRECT:
1669
1670 FETCH(&r[0], 0, CHAN_X);
1671 FETCH(&r[1], 0, CHAN_Y);
1672 FETCH(&r[2], 0, CHAN_Z);
1673
1674 fetch_texel(mach->Samplers[unit],
1675 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
1676 tgsi_sampler_lod_bias,
1677 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1678 break;
1679
1680 case TGSI_TEXTURE_3D:
1681 case TGSI_TEXTURE_CUBE:
1682
1683 FETCH(&r[0], 0, CHAN_X);
1684 FETCH(&r[1], 0, CHAN_Y);
1685 FETCH(&r[2], 0, CHAN_Z);
1686
1687 fetch_texel(mach->Samplers[unit],
1688 &r[0], &r[1], &r[2], &ZeroVec,
1689 tgsi_sampler_lod_bias,
1690 &r[0], &r[1], &r[2], &r[3]);
1691 break;
1692
1693 default:
1694 assert(0);
1695 }
1696
1697 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1698 STORE(&r[chan_index], 0, chan_index);
1699 }
1700 }
1701
1702
1703 /**
1704 * Evaluate a constant-valued coefficient at the position of the
1705 * current quad.
1706 */
1707 static void
1708 eval_constant_coef(
1709 struct tgsi_exec_machine *mach,
1710 unsigned attrib,
1711 unsigned chan )
1712 {
1713 unsigned i;
1714
1715 for( i = 0; i < QUAD_SIZE; i++ ) {
1716 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
1717 }
1718 }
1719
1720 /**
1721 * Evaluate a linear-valued coefficient at the position of the
1722 * current quad.
1723 */
1724 static void
1725 eval_linear_coef(
1726 struct tgsi_exec_machine *mach,
1727 unsigned attrib,
1728 unsigned chan )
1729 {
1730 const float x = mach->QuadPos.xyzw[0].f[0];
1731 const float y = mach->QuadPos.xyzw[1].f[0];
1732 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1733 const float dady = mach->InterpCoefs[attrib].dady[chan];
1734 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1735 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
1736 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
1737 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
1738 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
1739 }
1740
1741 /**
1742 * Evaluate a perspective-valued coefficient at the position of the
1743 * current quad.
1744 */
1745 static void
1746 eval_perspective_coef(
1747 struct tgsi_exec_machine *mach,
1748 unsigned attrib,
1749 unsigned chan )
1750 {
1751 const float x = mach->QuadPos.xyzw[0].f[0];
1752 const float y = mach->QuadPos.xyzw[1].f[0];
1753 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1754 const float dady = mach->InterpCoefs[attrib].dady[chan];
1755 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1756 const float *w = mach->QuadPos.xyzw[3].f;
1757 /* divide by W here */
1758 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
1759 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
1760 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
1761 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
1762 }
1763
1764
1765 typedef void (* eval_coef_func)(
1766 struct tgsi_exec_machine *mach,
1767 unsigned attrib,
1768 unsigned chan );
1769
1770 static void
1771 exec_declaration(struct tgsi_exec_machine *mach,
1772 const struct tgsi_full_declaration *decl)
1773 {
1774 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
1775 if (decl->Declaration.File == TGSI_FILE_INPUT ||
1776 decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1777 uint first, last, mask;
1778
1779 first = decl->Range.First;
1780 last = decl->Range.Last;
1781 mask = decl->Declaration.UsageMask;
1782
1783 /* XXX we could remove this special-case code since
1784 * mach->InterpCoefs[first].a0 should already have the
1785 * front/back-face value. But we should first update the
1786 * ureg code to emit the right UsageMask value (WRITEMASK_X).
1787 * Then, we could remove the tgsi_exec_machine::Face field.
1788 */
1789 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1790 uint i;
1791
1792 assert(decl->Semantic.Index == 0);
1793 assert(first == last);
1794
1795 for (i = 0; i < QUAD_SIZE; i++) {
1796 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
1797 }
1798 } else {
1799 eval_coef_func eval;
1800 uint i, j;
1801
1802 switch (decl->Declaration.Interpolate) {
1803 case TGSI_INTERPOLATE_CONSTANT:
1804 eval = eval_constant_coef;
1805 break;
1806
1807 case TGSI_INTERPOLATE_LINEAR:
1808 eval = eval_linear_coef;
1809 break;
1810
1811 case TGSI_INTERPOLATE_PERSPECTIVE:
1812 eval = eval_perspective_coef;
1813 break;
1814
1815 default:
1816 assert(0);
1817 return;
1818 }
1819
1820 for (j = 0; j < NUM_CHANNELS; j++) {
1821 if (mask & (1 << j)) {
1822 for (i = first; i <= last; i++) {
1823 eval(mach, i, j);
1824 }
1825 }
1826 }
1827 }
1828 }
1829 }
1830 }
1831
1832 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
1833 const union tgsi_exec_channel *src);
1834
1835 static void
1836 exec_scalar_unary(struct tgsi_exec_machine *mach,
1837 const struct tgsi_full_instruction *inst,
1838 micro_unary_op op,
1839 enum tgsi_exec_datatype dst_datatype,
1840 enum tgsi_exec_datatype src_datatype)
1841 {
1842 unsigned int chan;
1843 union tgsi_exec_channel src;
1844 union tgsi_exec_channel dst;
1845
1846 fetch_source(mach, &src, &inst->Src[0], CHAN_X, src_datatype);
1847 op(&dst, &src);
1848 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1849 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1850 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
1851 }
1852 }
1853 }
1854
1855 static void
1856 exec_vector_unary(struct tgsi_exec_machine *mach,
1857 const struct tgsi_full_instruction *inst,
1858 micro_unary_op op,
1859 enum tgsi_exec_datatype dst_datatype,
1860 enum tgsi_exec_datatype src_datatype)
1861 {
1862 unsigned int chan;
1863 struct tgsi_exec_vector dst;
1864
1865 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1866 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1867 union tgsi_exec_channel src;
1868
1869 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
1870 op(&dst.xyzw[chan], &src);
1871 }
1872 }
1873 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1874 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1875 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
1876 }
1877 }
1878 }
1879
1880 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
1881 const union tgsi_exec_channel *src0,
1882 const union tgsi_exec_channel *src1);
1883
1884 static void
1885 exec_vector_binary(struct tgsi_exec_machine *mach,
1886 const struct tgsi_full_instruction *inst,
1887 micro_binary_op op,
1888 enum tgsi_exec_datatype dst_datatype,
1889 enum tgsi_exec_datatype src_datatype)
1890 {
1891 unsigned int chan;
1892 struct tgsi_exec_vector dst;
1893
1894 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1895 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1896 union tgsi_exec_channel src[2];
1897
1898 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
1899 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
1900 op(&dst.xyzw[chan], &src[0], &src[1]);
1901 }
1902 }
1903 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1904 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1905 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
1906 }
1907 }
1908 }
1909
1910 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
1911 const union tgsi_exec_channel *src0,
1912 const union tgsi_exec_channel *src1,
1913 const union tgsi_exec_channel *src2);
1914
1915 static void
1916 exec_vector_trinary(struct tgsi_exec_machine *mach,
1917 const struct tgsi_full_instruction *inst,
1918 micro_trinary_op op,
1919 enum tgsi_exec_datatype dst_datatype,
1920 enum tgsi_exec_datatype src_datatype)
1921 {
1922 unsigned int chan;
1923 struct tgsi_exec_vector dst;
1924
1925 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1926 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1927 union tgsi_exec_channel src[3];
1928
1929 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
1930 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
1931 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
1932 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
1933 }
1934 }
1935 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1936 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1937 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
1938 }
1939 }
1940 }
1941
1942 static void
1943 exec_dp3(struct tgsi_exec_machine *mach,
1944 const struct tgsi_full_instruction *inst)
1945 {
1946 unsigned int chan;
1947 union tgsi_exec_channel arg[3];
1948
1949 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1950 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1951 micro_mul(&arg[2], &arg[0], &arg[1]);
1952
1953 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
1954 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
1955 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
1956 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
1957 }
1958
1959 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1960 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1961 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1962 }
1963 }
1964 }
1965
1966 static void
1967 exec_dp4(struct tgsi_exec_machine *mach,
1968 const struct tgsi_full_instruction *inst)
1969 {
1970 unsigned int chan;
1971 union tgsi_exec_channel arg[3];
1972
1973 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1974 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1975 micro_mul(&arg[2], &arg[0], &arg[1]);
1976
1977 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
1978 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
1979 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
1980 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
1981 }
1982
1983 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1984 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1985 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1986 }
1987 }
1988 }
1989
1990 static void
1991 exec_dp2a(struct tgsi_exec_machine *mach,
1992 const struct tgsi_full_instruction *inst)
1993 {
1994 unsigned int chan;
1995 union tgsi_exec_channel arg[3];
1996
1997 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1998 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1999 micro_mul(&arg[2], &arg[0], &arg[1]);
2000
2001 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2002 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2003 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2004
2005 fetch_source(mach, &arg[1], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2006 micro_add(&arg[0], &arg[0], &arg[1]);
2007
2008 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2009 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2010 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2011 }
2012 }
2013 }
2014
2015 static void
2016 exec_dph(struct tgsi_exec_machine *mach,
2017 const struct tgsi_full_instruction *inst)
2018 {
2019 unsigned int chan;
2020 union tgsi_exec_channel arg[3];
2021
2022 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2023 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2024 micro_mul(&arg[2], &arg[0], &arg[1]);
2025
2026 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2027 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2028 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2029
2030 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2031 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2032 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2033
2034 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2035 micro_add(&arg[0], &arg[0], &arg[1]);
2036
2037 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2038 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2039 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2040 }
2041 }
2042 }
2043
2044 static void
2045 exec_dp2(struct tgsi_exec_machine *mach,
2046 const struct tgsi_full_instruction *inst)
2047 {
2048 unsigned int chan;
2049 union tgsi_exec_channel arg[3];
2050
2051 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2052 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2053 micro_mul(&arg[2], &arg[0], &arg[1]);
2054
2055 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2056 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2057 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2058
2059 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2060 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2061 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2062 }
2063 }
2064 }
2065
2066 static void
2067 exec_nrm4(struct tgsi_exec_machine *mach,
2068 const struct tgsi_full_instruction *inst)
2069 {
2070 unsigned int chan;
2071 union tgsi_exec_channel arg[4];
2072 union tgsi_exec_channel scale;
2073
2074 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2075 micro_mul(&scale, &arg[0], &arg[0]);
2076
2077 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2078 union tgsi_exec_channel product;
2079
2080 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2081 micro_mul(&product, &arg[chan], &arg[chan]);
2082 micro_add(&scale, &scale, &product);
2083 }
2084
2085 micro_rsq(&scale, &scale);
2086
2087 for (chan = CHAN_X; chan <= CHAN_W; chan++) {
2088 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2089 micro_mul(&arg[chan], &arg[chan], &scale);
2090 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2091 }
2092 }
2093 }
2094
2095 static void
2096 exec_nrm3(struct tgsi_exec_machine *mach,
2097 const struct tgsi_full_instruction *inst)
2098 {
2099 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2100 unsigned int chan;
2101 union tgsi_exec_channel arg[3];
2102 union tgsi_exec_channel scale;
2103
2104 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2105 micro_mul(&scale, &arg[0], &arg[0]);
2106
2107 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2108 union tgsi_exec_channel product;
2109
2110 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2111 micro_mul(&product, &arg[chan], &arg[chan]);
2112 micro_add(&scale, &scale, &product);
2113 }
2114
2115 micro_rsq(&scale, &scale);
2116
2117 for (chan = CHAN_X; chan <= CHAN_Z; chan++) {
2118 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2119 micro_mul(&arg[chan], &arg[chan], &scale);
2120 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2121 }
2122 }
2123 }
2124
2125 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2126 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2127 }
2128 }
2129
2130 static void
2131 exec_break(struct tgsi_exec_machine *mach)
2132 {
2133 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
2134 /* turn off loop channels for each enabled exec channel */
2135 mach->LoopMask &= ~mach->ExecMask;
2136 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2137 UPDATE_EXEC_MASK(mach);
2138 } else {
2139 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
2140
2141 mach->Switch.mask = 0x0;
2142
2143 UPDATE_EXEC_MASK(mach);
2144 }
2145 }
2146
2147 static void
2148 exec_switch(struct tgsi_exec_machine *mach,
2149 const struct tgsi_full_instruction *inst)
2150 {
2151 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
2152 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
2153
2154 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
2155 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2156 mach->Switch.mask = 0x0;
2157 mach->Switch.defaultMask = 0x0;
2158
2159 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
2160 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
2161
2162 UPDATE_EXEC_MASK(mach);
2163 }
2164
2165 static void
2166 exec_case(struct tgsi_exec_machine *mach,
2167 const struct tgsi_full_instruction *inst)
2168 {
2169 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2170 union tgsi_exec_channel src;
2171 uint mask = 0;
2172
2173 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2174
2175 if (mach->Switch.selector.u[0] == src.u[0]) {
2176 mask |= 0x1;
2177 }
2178 if (mach->Switch.selector.u[1] == src.u[1]) {
2179 mask |= 0x2;
2180 }
2181 if (mach->Switch.selector.u[2] == src.u[2]) {
2182 mask |= 0x4;
2183 }
2184 if (mach->Switch.selector.u[3] == src.u[3]) {
2185 mask |= 0x8;
2186 }
2187
2188 mach->Switch.defaultMask |= mask;
2189
2190 mach->Switch.mask |= mask & prevMask;
2191
2192 UPDATE_EXEC_MASK(mach);
2193 }
2194
2195 static void
2196 exec_default(struct tgsi_exec_machine *mach)
2197 {
2198 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2199
2200 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
2201
2202 UPDATE_EXEC_MASK(mach);
2203 }
2204
2205 static void
2206 exec_endswitch(struct tgsi_exec_machine *mach)
2207 {
2208 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
2209 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
2210
2211 UPDATE_EXEC_MASK(mach);
2212 }
2213
2214 static void
2215 micro_i2f(union tgsi_exec_channel *dst,
2216 const union tgsi_exec_channel *src)
2217 {
2218 dst->f[0] = (float)src->i[0];
2219 dst->f[1] = (float)src->i[1];
2220 dst->f[2] = (float)src->i[2];
2221 dst->f[3] = (float)src->i[3];
2222 }
2223
2224 static void
2225 micro_not(union tgsi_exec_channel *dst,
2226 const union tgsi_exec_channel *src)
2227 {
2228 dst->u[0] = ~src->u[0];
2229 dst->u[1] = ~src->u[1];
2230 dst->u[2] = ~src->u[2];
2231 dst->u[3] = ~src->u[3];
2232 }
2233
2234 static void
2235 micro_shl(union tgsi_exec_channel *dst,
2236 const union tgsi_exec_channel *src0,
2237 const union tgsi_exec_channel *src1)
2238 {
2239 dst->u[0] = src0->u[0] << src1->u[0];
2240 dst->u[1] = src0->u[1] << src1->u[1];
2241 dst->u[2] = src0->u[2] << src1->u[2];
2242 dst->u[3] = src0->u[3] << src1->u[3];
2243 }
2244
2245 static void
2246 micro_and(union tgsi_exec_channel *dst,
2247 const union tgsi_exec_channel *src0,
2248 const union tgsi_exec_channel *src1)
2249 {
2250 dst->u[0] = src0->u[0] & src1->u[0];
2251 dst->u[1] = src0->u[1] & src1->u[1];
2252 dst->u[2] = src0->u[2] & src1->u[2];
2253 dst->u[3] = src0->u[3] & src1->u[3];
2254 }
2255
2256 static void
2257 micro_or(union tgsi_exec_channel *dst,
2258 const union tgsi_exec_channel *src0,
2259 const union tgsi_exec_channel *src1)
2260 {
2261 dst->u[0] = src0->u[0] | src1->u[0];
2262 dst->u[1] = src0->u[1] | src1->u[1];
2263 dst->u[2] = src0->u[2] | src1->u[2];
2264 dst->u[3] = src0->u[3] | src1->u[3];
2265 }
2266
2267 static void
2268 micro_xor(union tgsi_exec_channel *dst,
2269 const union tgsi_exec_channel *src0,
2270 const union tgsi_exec_channel *src1)
2271 {
2272 dst->u[0] = src0->u[0] ^ src1->u[0];
2273 dst->u[1] = src0->u[1] ^ src1->u[1];
2274 dst->u[2] = src0->u[2] ^ src1->u[2];
2275 dst->u[3] = src0->u[3] ^ src1->u[3];
2276 }
2277
2278 static void
2279 micro_f2i(union tgsi_exec_channel *dst,
2280 const union tgsi_exec_channel *src)
2281 {
2282 dst->i[0] = (int)src->f[0];
2283 dst->i[1] = (int)src->f[1];
2284 dst->i[2] = (int)src->f[2];
2285 dst->i[3] = (int)src->f[3];
2286 }
2287
2288 static void
2289 micro_idiv(union tgsi_exec_channel *dst,
2290 const union tgsi_exec_channel *src0,
2291 const union tgsi_exec_channel *src1)
2292 {
2293 dst->i[0] = src0->i[0] / src1->i[0];
2294 dst->i[1] = src0->i[1] / src1->i[1];
2295 dst->i[2] = src0->i[2] / src1->i[2];
2296 dst->i[3] = src0->i[3] / src1->i[3];
2297 }
2298
2299 static void
2300 micro_imax(union tgsi_exec_channel *dst,
2301 const union tgsi_exec_channel *src0,
2302 const union tgsi_exec_channel *src1)
2303 {
2304 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
2305 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
2306 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
2307 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
2308 }
2309
2310 static void
2311 micro_imin(union tgsi_exec_channel *dst,
2312 const union tgsi_exec_channel *src0,
2313 const union tgsi_exec_channel *src1)
2314 {
2315 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
2316 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
2317 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
2318 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
2319 }
2320
2321 static void
2322 micro_isge(union tgsi_exec_channel *dst,
2323 const union tgsi_exec_channel *src0,
2324 const union tgsi_exec_channel *src1)
2325 {
2326 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
2327 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
2328 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
2329 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
2330 }
2331
2332 static void
2333 micro_ishr(union tgsi_exec_channel *dst,
2334 const union tgsi_exec_channel *src0,
2335 const union tgsi_exec_channel *src1)
2336 {
2337 dst->i[0] = src0->i[0] >> src1->i[0];
2338 dst->i[1] = src0->i[1] >> src1->i[1];
2339 dst->i[2] = src0->i[2] >> src1->i[2];
2340 dst->i[3] = src0->i[3] >> src1->i[3];
2341 }
2342
2343 static void
2344 micro_islt(union tgsi_exec_channel *dst,
2345 const union tgsi_exec_channel *src0,
2346 const union tgsi_exec_channel *src1)
2347 {
2348 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
2349 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
2350 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
2351 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
2352 }
2353
2354 static void
2355 micro_f2u(union tgsi_exec_channel *dst,
2356 const union tgsi_exec_channel *src)
2357 {
2358 dst->u[0] = (uint)src->f[0];
2359 dst->u[1] = (uint)src->f[1];
2360 dst->u[2] = (uint)src->f[2];
2361 dst->u[3] = (uint)src->f[3];
2362 }
2363
2364 static void
2365 micro_u2f(union tgsi_exec_channel *dst,
2366 const union tgsi_exec_channel *src)
2367 {
2368 dst->f[0] = (float)src->u[0];
2369 dst->f[1] = (float)src->u[1];
2370 dst->f[2] = (float)src->u[2];
2371 dst->f[3] = (float)src->u[3];
2372 }
2373
2374 static void
2375 micro_uadd(union tgsi_exec_channel *dst,
2376 const union tgsi_exec_channel *src0,
2377 const union tgsi_exec_channel *src1)
2378 {
2379 dst->u[0] = src0->u[0] + src1->u[0];
2380 dst->u[1] = src0->u[1] + src1->u[1];
2381 dst->u[2] = src0->u[2] + src1->u[2];
2382 dst->u[3] = src0->u[3] + src1->u[3];
2383 }
2384
2385 static void
2386 micro_udiv(union tgsi_exec_channel *dst,
2387 const union tgsi_exec_channel *src0,
2388 const union tgsi_exec_channel *src1)
2389 {
2390 dst->u[0] = src0->u[0] / src1->u[0];
2391 dst->u[1] = src0->u[1] / src1->u[1];
2392 dst->u[2] = src0->u[2] / src1->u[2];
2393 dst->u[3] = src0->u[3] / src1->u[3];
2394 }
2395
2396 static void
2397 micro_umad(union tgsi_exec_channel *dst,
2398 const union tgsi_exec_channel *src0,
2399 const union tgsi_exec_channel *src1,
2400 const union tgsi_exec_channel *src2)
2401 {
2402 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
2403 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
2404 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
2405 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
2406 }
2407
2408 static void
2409 micro_umax(union tgsi_exec_channel *dst,
2410 const union tgsi_exec_channel *src0,
2411 const union tgsi_exec_channel *src1)
2412 {
2413 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
2414 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
2415 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
2416 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
2417 }
2418
2419 static void
2420 micro_umin(union tgsi_exec_channel *dst,
2421 const union tgsi_exec_channel *src0,
2422 const union tgsi_exec_channel *src1)
2423 {
2424 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
2425 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
2426 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
2427 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
2428 }
2429
2430 static void
2431 micro_umod(union tgsi_exec_channel *dst,
2432 const union tgsi_exec_channel *src0,
2433 const union tgsi_exec_channel *src1)
2434 {
2435 dst->u[0] = src0->u[0] % src1->u[0];
2436 dst->u[1] = src0->u[1] % src1->u[1];
2437 dst->u[2] = src0->u[2] % src1->u[2];
2438 dst->u[3] = src0->u[3] % src1->u[3];
2439 }
2440
2441 static void
2442 micro_umul(union tgsi_exec_channel *dst,
2443 const union tgsi_exec_channel *src0,
2444 const union tgsi_exec_channel *src1)
2445 {
2446 dst->u[0] = src0->u[0] * src1->u[0];
2447 dst->u[1] = src0->u[1] * src1->u[1];
2448 dst->u[2] = src0->u[2] * src1->u[2];
2449 dst->u[3] = src0->u[3] * src1->u[3];
2450 }
2451
2452 static void
2453 micro_useq(union tgsi_exec_channel *dst,
2454 const union tgsi_exec_channel *src0,
2455 const union tgsi_exec_channel *src1)
2456 {
2457 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
2458 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
2459 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
2460 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
2461 }
2462
2463 static void
2464 micro_usge(union tgsi_exec_channel *dst,
2465 const union tgsi_exec_channel *src0,
2466 const union tgsi_exec_channel *src1)
2467 {
2468 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
2469 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
2470 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
2471 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
2472 }
2473
2474 static void
2475 micro_ushr(union tgsi_exec_channel *dst,
2476 const union tgsi_exec_channel *src0,
2477 const union tgsi_exec_channel *src1)
2478 {
2479 dst->u[0] = src0->u[0] >> src1->u[0];
2480 dst->u[1] = src0->u[1] >> src1->u[1];
2481 dst->u[2] = src0->u[2] >> src1->u[2];
2482 dst->u[3] = src0->u[3] >> src1->u[3];
2483 }
2484
2485 static void
2486 micro_uslt(union tgsi_exec_channel *dst,
2487 const union tgsi_exec_channel *src0,
2488 const union tgsi_exec_channel *src1)
2489 {
2490 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
2491 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
2492 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
2493 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
2494 }
2495
2496 static void
2497 micro_usne(union tgsi_exec_channel *dst,
2498 const union tgsi_exec_channel *src0,
2499 const union tgsi_exec_channel *src1)
2500 {
2501 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
2502 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
2503 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
2504 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
2505 }
2506
2507 static void
2508 exec_instruction(
2509 struct tgsi_exec_machine *mach,
2510 const struct tgsi_full_instruction *inst,
2511 int *pc )
2512 {
2513 uint chan_index;
2514 union tgsi_exec_channel r[10];
2515 union tgsi_exec_channel d[8];
2516
2517 (*pc)++;
2518
2519 switch (inst->Instruction.Opcode) {
2520 case TGSI_OPCODE_ARL:
2521 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
2522 break;
2523
2524 case TGSI_OPCODE_MOV:
2525 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
2526 break;
2527
2528 case TGSI_OPCODE_LIT:
2529 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y ) || IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2530 FETCH( &r[0], 0, CHAN_X );
2531 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2532 micro_max(&d[CHAN_Y], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2533 }
2534
2535 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2536 FETCH( &r[1], 0, CHAN_Y );
2537 micro_max( &r[1], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2538
2539 FETCH( &r[2], 0, CHAN_W );
2540 micro_min( &r[2], &r[2], &mach->Temps[TEMP_128_I].xyzw[TEMP_128_C] );
2541 micro_max( &r[2], &r[2], &mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C] );
2542 micro_pow( &r[1], &r[1], &r[2] );
2543 micro_lt(&d[CHAN_Z], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2544 }
2545
2546 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2547 STORE(&d[CHAN_Y], 0, CHAN_Y);
2548 }
2549 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2550 STORE(&d[CHAN_Z], 0, CHAN_Z);
2551 }
2552 }
2553 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2554 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
2555 }
2556 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2557 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2558 }
2559 break;
2560
2561 case TGSI_OPCODE_RCP:
2562 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2563 break;
2564
2565 case TGSI_OPCODE_RSQ:
2566 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2567 break;
2568
2569 case TGSI_OPCODE_EXP:
2570 FETCH( &r[0], 0, CHAN_X );
2571 micro_flr( &r[1], &r[0] ); /* r1 = floor(r0) */
2572 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2573 micro_exp2( &r[2], &r[1] ); /* r2 = 2 ^ r1 */
2574 STORE( &r[2], 0, CHAN_X ); /* store r2 */
2575 }
2576 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2577 micro_sub( &r[2], &r[0], &r[1] ); /* r2 = r0 - r1 */
2578 STORE( &r[2], 0, CHAN_Y ); /* store r2 */
2579 }
2580 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2581 micro_exp2( &r[2], &r[0] ); /* r2 = 2 ^ r0 */
2582 STORE( &r[2], 0, CHAN_Z ); /* store r2 */
2583 }
2584 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2585 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2586 }
2587 break;
2588
2589 case TGSI_OPCODE_LOG:
2590 FETCH( &r[0], 0, CHAN_X );
2591 micro_abs( &r[2], &r[0] ); /* r2 = abs(r0) */
2592 micro_lg2( &r[1], &r[2] ); /* r1 = lg2(r2) */
2593 micro_flr( &r[0], &r[1] ); /* r0 = floor(r1) */
2594 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2595 STORE( &r[0], 0, CHAN_X );
2596 }
2597 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2598 micro_exp2( &r[0], &r[0] ); /* r0 = 2 ^ r0 */
2599 micro_div( &r[0], &r[2], &r[0] ); /* r0 = r2 / r0 */
2600 STORE( &r[0], 0, CHAN_Y );
2601 }
2602 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2603 STORE( &r[1], 0, CHAN_Z );
2604 }
2605 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2606 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2607 }
2608 break;
2609
2610 case TGSI_OPCODE_MUL:
2611 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2612 break;
2613
2614 case TGSI_OPCODE_ADD:
2615 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2616 break;
2617
2618 case TGSI_OPCODE_DP3:
2619 exec_dp3(mach, inst);
2620 break;
2621
2622 case TGSI_OPCODE_DP4:
2623 exec_dp4(mach, inst);
2624 break;
2625
2626 case TGSI_OPCODE_DST:
2627 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2628 FETCH( &r[0], 0, CHAN_Y );
2629 FETCH( &r[1], 1, CHAN_Y);
2630 micro_mul(&d[CHAN_Y], &r[0], &r[1]);
2631 }
2632 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2633 FETCH(&d[CHAN_Z], 0, CHAN_Z);
2634 }
2635 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2636 FETCH(&d[CHAN_W], 1, CHAN_W);
2637 }
2638
2639 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2640 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X);
2641 }
2642 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2643 STORE(&d[CHAN_Y], 0, CHAN_Y);
2644 }
2645 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2646 STORE(&d[CHAN_Z], 0, CHAN_Z);
2647 }
2648 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2649 STORE(&d[CHAN_W], 0, CHAN_W);
2650 }
2651 break;
2652
2653 case TGSI_OPCODE_MIN:
2654 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2655 break;
2656
2657 case TGSI_OPCODE_MAX:
2658 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2659 break;
2660
2661 case TGSI_OPCODE_SLT:
2662 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2663 break;
2664
2665 case TGSI_OPCODE_SGE:
2666 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2667 break;
2668
2669 case TGSI_OPCODE_MAD:
2670 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2671 break;
2672
2673 case TGSI_OPCODE_SUB:
2674 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2675 break;
2676
2677 case TGSI_OPCODE_LRP:
2678 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2679 break;
2680
2681 case TGSI_OPCODE_CND:
2682 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2683 break;
2684
2685 case TGSI_OPCODE_DP2A:
2686 exec_dp2a(mach, inst);
2687 break;
2688
2689 case TGSI_OPCODE_FRC:
2690 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2691 break;
2692
2693 case TGSI_OPCODE_CLAMP:
2694 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2695 break;
2696
2697 case TGSI_OPCODE_FLR:
2698 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2699 break;
2700
2701 case TGSI_OPCODE_ROUND:
2702 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2703 break;
2704
2705 case TGSI_OPCODE_EX2:
2706 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2707 break;
2708
2709 case TGSI_OPCODE_LG2:
2710 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2711 break;
2712
2713 case TGSI_OPCODE_POW:
2714 FETCH(&r[0], 0, CHAN_X);
2715 FETCH(&r[1], 1, CHAN_X);
2716
2717 micro_pow( &r[0], &r[0], &r[1] );
2718
2719 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2720 STORE( &r[0], 0, chan_index );
2721 }
2722 break;
2723
2724 case TGSI_OPCODE_XPD:
2725 FETCH(&r[0], 0, CHAN_Y);
2726 FETCH(&r[1], 1, CHAN_Z);
2727
2728 micro_mul( &r[2], &r[0], &r[1] );
2729
2730 FETCH(&r[3], 0, CHAN_Z);
2731 FETCH(&r[4], 1, CHAN_Y);
2732
2733 micro_mul( &r[5], &r[3], &r[4] );
2734 micro_sub(&d[CHAN_X], &r[2], &r[5]);
2735
2736 FETCH(&r[2], 1, CHAN_X);
2737
2738 micro_mul( &r[3], &r[3], &r[2] );
2739
2740 FETCH(&r[5], 0, CHAN_X);
2741
2742 micro_mul( &r[1], &r[1], &r[5] );
2743 micro_sub(&d[CHAN_Y], &r[3], &r[1]);
2744
2745 micro_mul( &r[5], &r[5], &r[4] );
2746 micro_mul( &r[0], &r[0], &r[2] );
2747 micro_sub(&d[CHAN_Z], &r[5], &r[0]);
2748
2749 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2750 STORE(&d[CHAN_X], 0, CHAN_X);
2751 }
2752 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2753 STORE(&d[CHAN_Y], 0, CHAN_Y);
2754 }
2755 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2756 STORE(&d[CHAN_Z], 0, CHAN_Z);
2757 }
2758 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2759 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2760 }
2761 break;
2762
2763 case TGSI_OPCODE_ABS:
2764 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2765 break;
2766
2767 case TGSI_OPCODE_RCC:
2768 FETCH(&r[0], 0, CHAN_X);
2769 micro_div(&r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0]);
2770 micro_float_clamp(&r[0], &r[0]);
2771 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2772 STORE(&r[0], 0, chan_index);
2773 }
2774 break;
2775
2776 case TGSI_OPCODE_DPH:
2777 exec_dph(mach, inst);
2778 break;
2779
2780 case TGSI_OPCODE_COS:
2781 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2782 break;
2783
2784 case TGSI_OPCODE_DDX:
2785 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2786 break;
2787
2788 case TGSI_OPCODE_DDY:
2789 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2790 break;
2791
2792 case TGSI_OPCODE_KILP:
2793 exec_kilp (mach, inst);
2794 break;
2795
2796 case TGSI_OPCODE_KIL:
2797 exec_kil (mach, inst);
2798 break;
2799
2800 case TGSI_OPCODE_PK2H:
2801 assert (0);
2802 break;
2803
2804 case TGSI_OPCODE_PK2US:
2805 assert (0);
2806 break;
2807
2808 case TGSI_OPCODE_PK4B:
2809 assert (0);
2810 break;
2811
2812 case TGSI_OPCODE_PK4UB:
2813 assert (0);
2814 break;
2815
2816 case TGSI_OPCODE_RFL:
2817 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2818 IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2819 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2820 /* r0 = dp3(src0, src0) */
2821 FETCH(&r[2], 0, CHAN_X);
2822 micro_mul(&r[0], &r[2], &r[2]);
2823 FETCH(&r[4], 0, CHAN_Y);
2824 micro_mul(&r[8], &r[4], &r[4]);
2825 micro_add(&r[0], &r[0], &r[8]);
2826 FETCH(&r[6], 0, CHAN_Z);
2827 micro_mul(&r[8], &r[6], &r[6]);
2828 micro_add(&r[0], &r[0], &r[8]);
2829
2830 /* r1 = dp3(src0, src1) */
2831 FETCH(&r[3], 1, CHAN_X);
2832 micro_mul(&r[1], &r[2], &r[3]);
2833 FETCH(&r[5], 1, CHAN_Y);
2834 micro_mul(&r[8], &r[4], &r[5]);
2835 micro_add(&r[1], &r[1], &r[8]);
2836 FETCH(&r[7], 1, CHAN_Z);
2837 micro_mul(&r[8], &r[6], &r[7]);
2838 micro_add(&r[1], &r[1], &r[8]);
2839
2840 /* r1 = 2 * r1 / r0 */
2841 micro_add(&r[1], &r[1], &r[1]);
2842 micro_div(&r[1], &r[1], &r[0]);
2843
2844 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2845 micro_mul(&r[2], &r[2], &r[1]);
2846 micro_sub(&r[2], &r[2], &r[3]);
2847 STORE(&r[2], 0, CHAN_X);
2848 }
2849 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2850 micro_mul(&r[4], &r[4], &r[1]);
2851 micro_sub(&r[4], &r[4], &r[5]);
2852 STORE(&r[4], 0, CHAN_Y);
2853 }
2854 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2855 micro_mul(&r[6], &r[6], &r[1]);
2856 micro_sub(&r[6], &r[6], &r[7]);
2857 STORE(&r[6], 0, CHAN_Z);
2858 }
2859 }
2860 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2861 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W);
2862 }
2863 break;
2864
2865 case TGSI_OPCODE_SEQ:
2866 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2867 break;
2868
2869 case TGSI_OPCODE_SFL:
2870 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2871 STORE(&mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, chan_index);
2872 }
2873 break;
2874
2875 case TGSI_OPCODE_SGT:
2876 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2877 break;
2878
2879 case TGSI_OPCODE_SIN:
2880 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2881 break;
2882
2883 case TGSI_OPCODE_SLE:
2884 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2885 break;
2886
2887 case TGSI_OPCODE_SNE:
2888 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2889 break;
2890
2891 case TGSI_OPCODE_STR:
2892 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2893 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, chan_index);
2894 }
2895 break;
2896
2897 case TGSI_OPCODE_TEX:
2898 /* simple texture lookup */
2899 /* src[0] = texcoord */
2900 /* src[1] = sampler unit */
2901 exec_tex(mach, inst, TEX_MODIFIER_NONE);
2902 break;
2903
2904 case TGSI_OPCODE_TXB:
2905 /* Texture lookup with lod bias */
2906 /* src[0] = texcoord (src[0].w = LOD bias) */
2907 /* src[1] = sampler unit */
2908 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS);
2909 break;
2910
2911 case TGSI_OPCODE_TXD:
2912 /* Texture lookup with explict partial derivatives */
2913 /* src[0] = texcoord */
2914 /* src[1] = d[strq]/dx */
2915 /* src[2] = d[strq]/dy */
2916 /* src[3] = sampler unit */
2917 exec_txd(mach, inst);
2918 break;
2919
2920 case TGSI_OPCODE_TXL:
2921 /* Texture lookup with explit LOD */
2922 /* src[0] = texcoord (src[0].w = LOD) */
2923 /* src[1] = sampler unit */
2924 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
2925 break;
2926
2927 case TGSI_OPCODE_TXP:
2928 /* Texture lookup with projection */
2929 /* src[0] = texcoord (src[0].w = projection) */
2930 /* src[1] = sampler unit */
2931 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED);
2932 break;
2933
2934 case TGSI_OPCODE_UP2H:
2935 assert (0);
2936 break;
2937
2938 case TGSI_OPCODE_UP2US:
2939 assert (0);
2940 break;
2941
2942 case TGSI_OPCODE_UP4B:
2943 assert (0);
2944 break;
2945
2946 case TGSI_OPCODE_UP4UB:
2947 assert (0);
2948 break;
2949
2950 case TGSI_OPCODE_X2D:
2951 FETCH(&r[0], 1, CHAN_X);
2952 FETCH(&r[1], 1, CHAN_Y);
2953 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2954 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2955 FETCH(&r[2], 2, CHAN_X);
2956 micro_mul(&r[2], &r[2], &r[0]);
2957 FETCH(&r[3], 2, CHAN_Y);
2958 micro_mul(&r[3], &r[3], &r[1]);
2959 micro_add(&r[2], &r[2], &r[3]);
2960 FETCH(&r[3], 0, CHAN_X);
2961 micro_add(&d[CHAN_X], &r[2], &r[3]);
2962
2963 }
2964 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2965 IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2966 FETCH(&r[2], 2, CHAN_Z);
2967 micro_mul(&r[2], &r[2], &r[0]);
2968 FETCH(&r[3], 2, CHAN_W);
2969 micro_mul(&r[3], &r[3], &r[1]);
2970 micro_add(&r[2], &r[2], &r[3]);
2971 FETCH(&r[3], 0, CHAN_Y);
2972 micro_add(&d[CHAN_Y], &r[2], &r[3]);
2973
2974 }
2975 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2976 STORE(&d[CHAN_X], 0, CHAN_X);
2977 }
2978 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2979 STORE(&d[CHAN_Y], 0, CHAN_Y);
2980 }
2981 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2982 STORE(&d[CHAN_X], 0, CHAN_Z);
2983 }
2984 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2985 STORE(&d[CHAN_Y], 0, CHAN_W);
2986 }
2987 break;
2988
2989 case TGSI_OPCODE_ARA:
2990 assert (0);
2991 break;
2992
2993 case TGSI_OPCODE_ARR:
2994 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
2995 break;
2996
2997 case TGSI_OPCODE_BRA:
2998 assert (0);
2999 break;
3000
3001 case TGSI_OPCODE_CAL:
3002 /* skip the call if no execution channels are enabled */
3003 if (mach->ExecMask) {
3004 /* do the call */
3005
3006 /* First, record the depths of the execution stacks.
3007 * This is important for deeply nested/looped return statements.
3008 * We have to unwind the stacks by the correct amount. For a
3009 * real code generator, we could determine the number of entries
3010 * to pop off each stack with simple static analysis and avoid
3011 * implementing this data structure at run time.
3012 */
3013 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3014 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3015 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3016 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3017 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3018 /* note that PC was already incremented above */
3019 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3020
3021 mach->CallStackTop++;
3022
3023 /* Second, push the Cond, Loop, Cont, Func stacks */
3024 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3025 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3026 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3027 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3028 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3029 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3030
3031 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3032 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3033 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3034 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3035 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3036 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3037
3038 /* Finally, jump to the subroutine */
3039 *pc = inst->Label.Label;
3040 }
3041 break;
3042
3043 case TGSI_OPCODE_RET:
3044 mach->FuncMask &= ~mach->ExecMask;
3045 UPDATE_EXEC_MASK(mach);
3046
3047 if (mach->FuncMask == 0x0) {
3048 /* really return now (otherwise, keep executing */
3049
3050 if (mach->CallStackTop == 0) {
3051 /* returning from main() */
3052 *pc = -1;
3053 return;
3054 }
3055
3056 assert(mach->CallStackTop > 0);
3057 mach->CallStackTop--;
3058
3059 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3060 mach->CondMask = mach->CondStack[mach->CondStackTop];
3061
3062 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3063 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3064
3065 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3066 mach->ContMask = mach->ContStack[mach->ContStackTop];
3067
3068 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3069 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3070
3071 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3072 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3073
3074 assert(mach->FuncStackTop > 0);
3075 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3076
3077 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3078
3079 UPDATE_EXEC_MASK(mach);
3080 }
3081 break;
3082
3083 case TGSI_OPCODE_SSG:
3084 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3085 break;
3086
3087 case TGSI_OPCODE_CMP:
3088 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3089 break;
3090
3091 case TGSI_OPCODE_SCS:
3092 if( IS_CHANNEL_ENABLED( *inst, CHAN_X ) || IS_CHANNEL_ENABLED( *inst, CHAN_Y ) ) {
3093 FETCH( &r[0], 0, CHAN_X );
3094 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
3095 micro_cos(&r[1], &r[0]);
3096 STORE(&r[1], 0, CHAN_X);
3097 }
3098 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
3099 micro_sin(&r[1], &r[0]);
3100 STORE(&r[1], 0, CHAN_Y);
3101 }
3102 }
3103 if( IS_CHANNEL_ENABLED( *inst, CHAN_Z ) ) {
3104 STORE( &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, CHAN_Z );
3105 }
3106 if( IS_CHANNEL_ENABLED( *inst, CHAN_W ) ) {
3107 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
3108 }
3109 break;
3110
3111 case TGSI_OPCODE_NRM:
3112 exec_nrm3(mach, inst);
3113 break;
3114
3115 case TGSI_OPCODE_NRM4:
3116 exec_nrm4(mach, inst);
3117 break;
3118
3119 case TGSI_OPCODE_DIV:
3120 assert( 0 );
3121 break;
3122
3123 case TGSI_OPCODE_DP2:
3124 exec_dp2(mach, inst);
3125 break;
3126
3127 case TGSI_OPCODE_IF:
3128 /* push CondMask */
3129 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3130 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3131 FETCH( &r[0], 0, CHAN_X );
3132 /* update CondMask */
3133 if( ! r[0].u[0] ) {
3134 mach->CondMask &= ~0x1;
3135 }
3136 if( ! r[0].u[1] ) {
3137 mach->CondMask &= ~0x2;
3138 }
3139 if( ! r[0].u[2] ) {
3140 mach->CondMask &= ~0x4;
3141 }
3142 if( ! r[0].u[3] ) {
3143 mach->CondMask &= ~0x8;
3144 }
3145 UPDATE_EXEC_MASK(mach);
3146 /* Todo: If CondMask==0, jump to ELSE */
3147 break;
3148
3149 case TGSI_OPCODE_ELSE:
3150 /* invert CondMask wrt previous mask */
3151 {
3152 uint prevMask;
3153 assert(mach->CondStackTop > 0);
3154 prevMask = mach->CondStack[mach->CondStackTop - 1];
3155 mach->CondMask = ~mach->CondMask & prevMask;
3156 UPDATE_EXEC_MASK(mach);
3157 /* Todo: If CondMask==0, jump to ENDIF */
3158 }
3159 break;
3160
3161 case TGSI_OPCODE_ENDIF:
3162 /* pop CondMask */
3163 assert(mach->CondStackTop > 0);
3164 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3165 UPDATE_EXEC_MASK(mach);
3166 break;
3167
3168 case TGSI_OPCODE_END:
3169 /* halt execution */
3170 *pc = -1;
3171 break;
3172
3173 case TGSI_OPCODE_PUSHA:
3174 assert (0);
3175 break;
3176
3177 case TGSI_OPCODE_POPA:
3178 assert (0);
3179 break;
3180
3181 case TGSI_OPCODE_CEIL:
3182 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3183 break;
3184
3185 case TGSI_OPCODE_I2F:
3186 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3187 break;
3188
3189 case TGSI_OPCODE_NOT:
3190 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3191 break;
3192
3193 case TGSI_OPCODE_TRUNC:
3194 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3195 break;
3196
3197 case TGSI_OPCODE_SHL:
3198 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3199 break;
3200
3201 case TGSI_OPCODE_AND:
3202 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3203 break;
3204
3205 case TGSI_OPCODE_OR:
3206 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3207 break;
3208
3209 case TGSI_OPCODE_MOD:
3210 assert (0);
3211 break;
3212
3213 case TGSI_OPCODE_XOR:
3214 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3215 break;
3216
3217 case TGSI_OPCODE_SAD:
3218 assert (0);
3219 break;
3220
3221 case TGSI_OPCODE_TXF:
3222 assert (0);
3223 break;
3224
3225 case TGSI_OPCODE_TXQ:
3226 assert (0);
3227 break;
3228
3229 case TGSI_OPCODE_EMIT:
3230 emit_vertex(mach);
3231 break;
3232
3233 case TGSI_OPCODE_ENDPRIM:
3234 emit_primitive(mach);
3235 break;
3236
3237 case TGSI_OPCODE_BGNLOOP:
3238 /* push LoopMask and ContMasks */
3239 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3240 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3241 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3242 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3243
3244 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3245 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3246 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3247 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3248 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3249 break;
3250
3251 case TGSI_OPCODE_ENDLOOP:
3252 /* Restore ContMask, but don't pop */
3253 assert(mach->ContStackTop > 0);
3254 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3255 UPDATE_EXEC_MASK(mach);
3256 if (mach->ExecMask) {
3257 /* repeat loop: jump to instruction just past BGNLOOP */
3258 assert(mach->LoopLabelStackTop > 0);
3259 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3260 }
3261 else {
3262 /* exit loop: pop LoopMask */
3263 assert(mach->LoopStackTop > 0);
3264 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3265 /* pop ContMask */
3266 assert(mach->ContStackTop > 0);
3267 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3268 assert(mach->LoopLabelStackTop > 0);
3269 --mach->LoopLabelStackTop;
3270
3271 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3272 }
3273 UPDATE_EXEC_MASK(mach);
3274 break;
3275
3276 case TGSI_OPCODE_BRK:
3277 exec_break(mach);
3278 break;
3279
3280 case TGSI_OPCODE_CONT:
3281 /* turn off cont channels for each enabled exec channel */
3282 mach->ContMask &= ~mach->ExecMask;
3283 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3284 UPDATE_EXEC_MASK(mach);
3285 break;
3286
3287 case TGSI_OPCODE_BGNSUB:
3288 /* no-op */
3289 break;
3290
3291 case TGSI_OPCODE_ENDSUB:
3292 /*
3293 * XXX: This really should be a no-op. We should never reach this opcode.
3294 */
3295
3296 assert(mach->CallStackTop > 0);
3297 mach->CallStackTop--;
3298
3299 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3300 mach->CondMask = mach->CondStack[mach->CondStackTop];
3301
3302 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3303 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3304
3305 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3306 mach->ContMask = mach->ContStack[mach->ContStackTop];
3307
3308 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3309 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3310
3311 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3312 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3313
3314 assert(mach->FuncStackTop > 0);
3315 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3316
3317 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3318
3319 UPDATE_EXEC_MASK(mach);
3320 break;
3321
3322 case TGSI_OPCODE_NOP:
3323 break;
3324
3325 case TGSI_OPCODE_BREAKC:
3326 FETCH(&r[0], 0, CHAN_X);
3327 /* update CondMask */
3328 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
3329 mach->LoopMask &= ~0x1;
3330 }
3331 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
3332 mach->LoopMask &= ~0x2;
3333 }
3334 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
3335 mach->LoopMask &= ~0x4;
3336 }
3337 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
3338 mach->LoopMask &= ~0x8;
3339 }
3340 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3341 UPDATE_EXEC_MASK(mach);
3342 break;
3343
3344 case TGSI_OPCODE_F2I:
3345 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3346 break;
3347
3348 case TGSI_OPCODE_IDIV:
3349 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3350 break;
3351
3352 case TGSI_OPCODE_IMAX:
3353 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3354 break;
3355
3356 case TGSI_OPCODE_IMIN:
3357 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3358 break;
3359
3360 case TGSI_OPCODE_INEG:
3361 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3362 break;
3363
3364 case TGSI_OPCODE_ISGE:
3365 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3366 break;
3367
3368 case TGSI_OPCODE_ISHR:
3369 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3370 break;
3371
3372 case TGSI_OPCODE_ISLT:
3373 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3374 break;
3375
3376 case TGSI_OPCODE_F2U:
3377 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3378 break;
3379
3380 case TGSI_OPCODE_U2F:
3381 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
3382 break;
3383
3384 case TGSI_OPCODE_UADD:
3385 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3386 break;
3387
3388 case TGSI_OPCODE_UDIV:
3389 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3390 break;
3391
3392 case TGSI_OPCODE_UMAD:
3393 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3394 break;
3395
3396 case TGSI_OPCODE_UMAX:
3397 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3398 break;
3399
3400 case TGSI_OPCODE_UMIN:
3401 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3402 break;
3403
3404 case TGSI_OPCODE_UMOD:
3405 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3406 break;
3407
3408 case TGSI_OPCODE_UMUL:
3409 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3410 break;
3411
3412 case TGSI_OPCODE_USEQ:
3413 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3414 break;
3415
3416 case TGSI_OPCODE_USGE:
3417 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3418 break;
3419
3420 case TGSI_OPCODE_USHR:
3421 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3422 break;
3423
3424 case TGSI_OPCODE_USLT:
3425 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3426 break;
3427
3428 case TGSI_OPCODE_USNE:
3429 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3430 break;
3431
3432 case TGSI_OPCODE_SWITCH:
3433 exec_switch(mach, inst);
3434 break;
3435
3436 case TGSI_OPCODE_CASE:
3437 exec_case(mach, inst);
3438 break;
3439
3440 case TGSI_OPCODE_DEFAULT:
3441 exec_default(mach);
3442 break;
3443
3444 case TGSI_OPCODE_ENDSWITCH:
3445 exec_endswitch(mach);
3446 break;
3447
3448 default:
3449 assert( 0 );
3450 }
3451 }
3452
3453
3454 #define DEBUG_EXECUTION 0
3455
3456
3457 /**
3458 * Run TGSI interpreter.
3459 * \return bitmask of "alive" quad components
3460 */
3461 uint
3462 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
3463 {
3464 uint i;
3465 int pc = 0;
3466
3467 mach->CondMask = 0xf;
3468 mach->LoopMask = 0xf;
3469 mach->ContMask = 0xf;
3470 mach->FuncMask = 0xf;
3471 mach->ExecMask = 0xf;
3472
3473 mach->Switch.mask = 0xf;
3474
3475 assert(mach->CondStackTop == 0);
3476 assert(mach->LoopStackTop == 0);
3477 assert(mach->ContStackTop == 0);
3478 assert(mach->SwitchStackTop == 0);
3479 assert(mach->BreakStackTop == 0);
3480 assert(mach->CallStackTop == 0);
3481
3482 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
3483 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
3484
3485 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
3486 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
3487 mach->Primitives[0] = 0;
3488 }
3489
3490 for (i = 0; i < QUAD_SIZE; i++) {
3491 mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C].u[i] =
3492 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_X_SHIFT) |
3493 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Y_SHIFT) |
3494 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Z_SHIFT) |
3495 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_W_SHIFT);
3496 }
3497
3498 /* execute declarations (interpolants) */
3499 for (i = 0; i < mach->NumDeclarations; i++) {
3500 exec_declaration( mach, mach->Declarations+i );
3501 }
3502
3503 {
3504 #if DEBUG_EXECUTION
3505 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
3506 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
3507 uint inst = 1;
3508
3509 memcpy(temps, mach->Temps, sizeof(temps));
3510 memcpy(outputs, mach->Outputs, sizeof(outputs));
3511 #endif
3512
3513 /* execute instructions, until pc is set to -1 */
3514 while (pc != -1) {
3515
3516 #if DEBUG_EXECUTION
3517 uint i;
3518
3519 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
3520 #endif
3521
3522 assert(pc < (int) mach->NumInstructions);
3523 exec_instruction(mach, mach->Instructions + pc, &pc);
3524
3525 #if DEBUG_EXECUTION
3526 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
3527 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
3528 uint j;
3529
3530 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
3531 debug_printf("TEMP[%2u] = ", i);
3532 for (j = 0; j < 4; j++) {
3533 if (j > 0) {
3534 debug_printf(" ");
3535 }
3536 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3537 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
3538 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
3539 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
3540 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
3541 }
3542 }
3543 }
3544 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
3545 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
3546 uint j;
3547
3548 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
3549 debug_printf("OUT[%2u] = ", i);
3550 for (j = 0; j < 4; j++) {
3551 if (j > 0) {
3552 debug_printf(" ");
3553 }
3554 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3555 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
3556 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
3557 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
3558 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
3559 }
3560 }
3561 }
3562 #endif
3563 }
3564 }
3565
3566 #if 0
3567 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
3568 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
3569 /*
3570 * Scale back depth component.
3571 */
3572 for (i = 0; i < 4; i++)
3573 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
3574 }
3575 #endif
3576
3577 assert(mach->CondStackTop == 0);
3578 assert(mach->LoopStackTop == 0);
3579 assert(mach->ContStackTop == 0);
3580 assert(mach->SwitchStackTop == 0);
3581 assert(mach->BreakStackTop == 0);
3582 assert(mach->CallStackTop == 0);
3583
3584 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3585 }