1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
65 #define DEBUG_EXECUTION 0
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
76 micro_abs(union tgsi_exec_channel
*dst
,
77 const union tgsi_exec_channel
*src
)
79 dst
->f
[0] = fabsf(src
->f
[0]);
80 dst
->f
[1] = fabsf(src
->f
[1]);
81 dst
->f
[2] = fabsf(src
->f
[2]);
82 dst
->f
[3] = fabsf(src
->f
[3]);
86 micro_arl(union tgsi_exec_channel
*dst
,
87 const union tgsi_exec_channel
*src
)
89 dst
->i
[0] = (int)floorf(src
->f
[0]);
90 dst
->i
[1] = (int)floorf(src
->f
[1]);
91 dst
->i
[2] = (int)floorf(src
->f
[2]);
92 dst
->i
[3] = (int)floorf(src
->f
[3]);
96 micro_arr(union tgsi_exec_channel
*dst
,
97 const union tgsi_exec_channel
*src
)
99 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
100 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
101 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
102 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
106 micro_ceil(union tgsi_exec_channel
*dst
,
107 const union tgsi_exec_channel
*src
)
109 dst
->f
[0] = ceilf(src
->f
[0]);
110 dst
->f
[1] = ceilf(src
->f
[1]);
111 dst
->f
[2] = ceilf(src
->f
[2]);
112 dst
->f
[3] = ceilf(src
->f
[3]);
116 micro_clamp(union tgsi_exec_channel
*dst
,
117 const union tgsi_exec_channel
*src0
,
118 const union tgsi_exec_channel
*src1
,
119 const union tgsi_exec_channel
*src2
)
121 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src1
->f
[0] : src0
->f
[0] > src2
->f
[0] ? src2
->f
[0] : src0
->f
[0];
122 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src1
->f
[1] : src0
->f
[1] > src2
->f
[1] ? src2
->f
[1] : src0
->f
[1];
123 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src1
->f
[2] : src0
->f
[2] > src2
->f
[2] ? src2
->f
[2] : src0
->f
[2];
124 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src1
->f
[3] : src0
->f
[3] > src2
->f
[3] ? src2
->f
[3] : src0
->f
[3];
128 micro_cmp(union tgsi_exec_channel
*dst
,
129 const union tgsi_exec_channel
*src0
,
130 const union tgsi_exec_channel
*src1
,
131 const union tgsi_exec_channel
*src2
)
133 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
134 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
135 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
136 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
140 micro_cnd(union tgsi_exec_channel
*dst
,
141 const union tgsi_exec_channel
*src0
,
142 const union tgsi_exec_channel
*src1
,
143 const union tgsi_exec_channel
*src2
)
145 dst
->f
[0] = src2
->f
[0] > 0.5f
? src0
->f
[0] : src1
->f
[0];
146 dst
->f
[1] = src2
->f
[1] > 0.5f
? src0
->f
[1] : src1
->f
[1];
147 dst
->f
[2] = src2
->f
[2] > 0.5f
? src0
->f
[2] : src1
->f
[2];
148 dst
->f
[3] = src2
->f
[3] > 0.5f
? src0
->f
[3] : src1
->f
[3];
152 micro_cos(union tgsi_exec_channel
*dst
,
153 const union tgsi_exec_channel
*src
)
155 dst
->f
[0] = cosf(src
->f
[0]);
156 dst
->f
[1] = cosf(src
->f
[1]);
157 dst
->f
[2] = cosf(src
->f
[2]);
158 dst
->f
[3] = cosf(src
->f
[3]);
162 micro_ddx(union tgsi_exec_channel
*dst
,
163 const union tgsi_exec_channel
*src
)
168 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
172 micro_ddy(union tgsi_exec_channel
*dst
,
173 const union tgsi_exec_channel
*src
)
178 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
182 micro_exp2(union tgsi_exec_channel
*dst
,
183 const union tgsi_exec_channel
*src
)
186 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
187 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
188 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
189 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
192 /* Inf is okay for this instruction, so clamp it to silence assertions. */
194 union tgsi_exec_channel clamped
;
196 for (i
= 0; i
< 4; i
++) {
197 if (src
->f
[i
] > 127.99999f
) {
198 clamped
.f
[i
] = 127.99999f
;
199 } else if (src
->f
[i
] < -126.99999f
) {
200 clamped
.f
[i
] = -126.99999f
;
202 clamped
.f
[i
] = src
->f
[i
];
208 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
209 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
210 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
211 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
212 #endif /* FAST_MATH */
216 micro_flr(union tgsi_exec_channel
*dst
,
217 const union tgsi_exec_channel
*src
)
219 dst
->f
[0] = floorf(src
->f
[0]);
220 dst
->f
[1] = floorf(src
->f
[1]);
221 dst
->f
[2] = floorf(src
->f
[2]);
222 dst
->f
[3] = floorf(src
->f
[3]);
226 micro_frc(union tgsi_exec_channel
*dst
,
227 const union tgsi_exec_channel
*src
)
229 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
230 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
231 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
232 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
236 micro_iabs(union tgsi_exec_channel
*dst
,
237 const union tgsi_exec_channel
*src
)
239 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
240 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
241 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
242 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
246 micro_ineg(union tgsi_exec_channel
*dst
,
247 const union tgsi_exec_channel
*src
)
249 dst
->i
[0] = -src
->i
[0];
250 dst
->i
[1] = -src
->i
[1];
251 dst
->i
[2] = -src
->i
[2];
252 dst
->i
[3] = -src
->i
[3];
256 micro_lg2(union tgsi_exec_channel
*dst
,
257 const union tgsi_exec_channel
*src
)
260 dst
->f
[0] = util_fast_log2(src
->f
[0]);
261 dst
->f
[1] = util_fast_log2(src
->f
[1]);
262 dst
->f
[2] = util_fast_log2(src
->f
[2]);
263 dst
->f
[3] = util_fast_log2(src
->f
[3]);
265 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
266 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
267 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
268 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
273 micro_lrp(union tgsi_exec_channel
*dst
,
274 const union tgsi_exec_channel
*src0
,
275 const union tgsi_exec_channel
*src1
,
276 const union tgsi_exec_channel
*src2
)
278 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
279 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
280 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
281 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
285 micro_mad(union tgsi_exec_channel
*dst
,
286 const union tgsi_exec_channel
*src0
,
287 const union tgsi_exec_channel
*src1
,
288 const union tgsi_exec_channel
*src2
)
290 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
291 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
292 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
293 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
297 micro_mov(union tgsi_exec_channel
*dst
,
298 const union tgsi_exec_channel
*src
)
300 dst
->u
[0] = src
->u
[0];
301 dst
->u
[1] = src
->u
[1];
302 dst
->u
[2] = src
->u
[2];
303 dst
->u
[3] = src
->u
[3];
307 micro_rcp(union tgsi_exec_channel
*dst
,
308 const union tgsi_exec_channel
*src
)
310 #if 0 /* for debugging */
311 assert(src
->f
[0] != 0.0f
);
312 assert(src
->f
[1] != 0.0f
);
313 assert(src
->f
[2] != 0.0f
);
314 assert(src
->f
[3] != 0.0f
);
316 dst
->f
[0] = 1.0f
/ src
->f
[0];
317 dst
->f
[1] = 1.0f
/ src
->f
[1];
318 dst
->f
[2] = 1.0f
/ src
->f
[2];
319 dst
->f
[3] = 1.0f
/ src
->f
[3];
323 micro_rnd(union tgsi_exec_channel
*dst
,
324 const union tgsi_exec_channel
*src
)
326 dst
->f
[0] = floorf(src
->f
[0] + 0.5f
);
327 dst
->f
[1] = floorf(src
->f
[1] + 0.5f
);
328 dst
->f
[2] = floorf(src
->f
[2] + 0.5f
);
329 dst
->f
[3] = floorf(src
->f
[3] + 0.5f
);
333 micro_rsq(union tgsi_exec_channel
*dst
,
334 const union tgsi_exec_channel
*src
)
336 #if 0 /* for debugging */
337 assert(src
->f
[0] != 0.0f
);
338 assert(src
->f
[1] != 0.0f
);
339 assert(src
->f
[2] != 0.0f
);
340 assert(src
->f
[3] != 0.0f
);
342 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
343 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
344 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
345 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
349 micro_sqrt(union tgsi_exec_channel
*dst
,
350 const union tgsi_exec_channel
*src
)
352 dst
->f
[0] = sqrtf(src
->f
[0]);
353 dst
->f
[1] = sqrtf(src
->f
[1]);
354 dst
->f
[2] = sqrtf(src
->f
[2]);
355 dst
->f
[3] = sqrtf(src
->f
[3]);
359 micro_seq(union tgsi_exec_channel
*dst
,
360 const union tgsi_exec_channel
*src0
,
361 const union tgsi_exec_channel
*src1
)
363 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
364 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
365 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
366 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
370 micro_sge(union tgsi_exec_channel
*dst
,
371 const union tgsi_exec_channel
*src0
,
372 const union tgsi_exec_channel
*src1
)
374 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
375 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
376 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
377 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
381 micro_sgn(union tgsi_exec_channel
*dst
,
382 const union tgsi_exec_channel
*src
)
384 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
385 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
386 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
387 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
391 micro_isgn(union tgsi_exec_channel
*dst
,
392 const union tgsi_exec_channel
*src
)
394 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
395 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
396 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
397 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
401 micro_sgt(union tgsi_exec_channel
*dst
,
402 const union tgsi_exec_channel
*src0
,
403 const union tgsi_exec_channel
*src1
)
405 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
406 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
407 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
408 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
412 micro_sin(union tgsi_exec_channel
*dst
,
413 const union tgsi_exec_channel
*src
)
415 dst
->f
[0] = sinf(src
->f
[0]);
416 dst
->f
[1] = sinf(src
->f
[1]);
417 dst
->f
[2] = sinf(src
->f
[2]);
418 dst
->f
[3] = sinf(src
->f
[3]);
422 micro_sle(union tgsi_exec_channel
*dst
,
423 const union tgsi_exec_channel
*src0
,
424 const union tgsi_exec_channel
*src1
)
426 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
427 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
428 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
429 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
433 micro_slt(union tgsi_exec_channel
*dst
,
434 const union tgsi_exec_channel
*src0
,
435 const union tgsi_exec_channel
*src1
)
437 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
438 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
439 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
440 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
444 micro_sne(union tgsi_exec_channel
*dst
,
445 const union tgsi_exec_channel
*src0
,
446 const union tgsi_exec_channel
*src1
)
448 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
449 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
450 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
451 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
455 micro_sfl(union tgsi_exec_channel
*dst
)
464 micro_str(union tgsi_exec_channel
*dst
)
473 micro_trunc(union tgsi_exec_channel
*dst
,
474 const union tgsi_exec_channel
*src
)
476 dst
->f
[0] = (float)(int)src
->f
[0];
477 dst
->f
[1] = (float)(int)src
->f
[1];
478 dst
->f
[2] = (float)(int)src
->f
[2];
479 dst
->f
[3] = (float)(int)src
->f
[3];
483 enum tgsi_exec_datatype
{
484 TGSI_EXEC_DATA_FLOAT
,
490 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
492 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
493 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
494 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
495 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
496 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
497 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
500 /** The execution mask depends on the conditional mask and the loop mask */
501 #define UPDATE_EXEC_MASK(MACH) \
502 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
505 static const union tgsi_exec_channel ZeroVec
=
506 { { 0.0, 0.0, 0.0, 0.0 } };
508 static const union tgsi_exec_channel OneVec
= {
509 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
512 static const union tgsi_exec_channel P128Vec
= {
513 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
516 static const union tgsi_exec_channel M128Vec
= {
517 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
522 * Assert that none of the float values in 'chan' are infinite or NaN.
523 * NaN and Inf may occur normally during program execution and should
524 * not lead to crashes, etc. But when debugging, it's helpful to catch
528 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
530 assert(!util_is_inf_or_nan((chan
)->f
[0]));
531 assert(!util_is_inf_or_nan((chan
)->f
[1]));
532 assert(!util_is_inf_or_nan((chan
)->f
[2]));
533 assert(!util_is_inf_or_nan((chan
)->f
[3]));
539 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
541 debug_printf("%s = {%f, %f, %f, %f}\n",
542 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
549 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
551 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
553 debug_printf("Temp[%u] =\n", index
);
554 for (i
= 0; i
< 4; i
++) {
555 debug_printf(" %c: { %f, %f, %f, %f }\n",
567 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
570 const unsigned *buf_sizes
)
574 for (i
= 0; i
< num_bufs
; i
++) {
575 mach
->Consts
[i
] = bufs
[i
];
576 mach
->ConstsSize
[i
] = buf_sizes
[i
];
582 * Check if there's a potential src/dst register data dependency when
583 * using SOA execution.
586 * This would expand into:
591 * The second instruction will have the wrong value for t0 if executed as-is.
594 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
598 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
599 if (writemask
== TGSI_WRITEMASK_X
||
600 writemask
== TGSI_WRITEMASK_Y
||
601 writemask
== TGSI_WRITEMASK_Z
||
602 writemask
== TGSI_WRITEMASK_W
||
603 writemask
== TGSI_WRITEMASK_NONE
) {
604 /* no chance of data dependency */
608 /* loop over src regs */
609 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
610 if ((inst
->Src
[i
].Register
.File
==
611 inst
->Dst
[0].Register
.File
) &&
612 ((inst
->Src
[i
].Register
.Index
==
613 inst
->Dst
[0].Register
.Index
) ||
614 inst
->Src
[i
].Register
.Indirect
||
615 inst
->Dst
[0].Register
.Indirect
)) {
616 /* loop over dest channels */
617 uint channelsWritten
= 0x0;
618 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
619 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
620 /* check if we're reading a channel that's been written */
621 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
622 if (channelsWritten
& (1 << swizzle
)) {
626 channelsWritten
|= (1 << chan
);
636 * Initialize machine state by expanding tokens to full instructions,
637 * allocating temporary storage, setting up constants, etc.
638 * After this, we can call tgsi_exec_machine_run() many times.
641 tgsi_exec_machine_bind_shader(
642 struct tgsi_exec_machine
*mach
,
643 const struct tgsi_token
*tokens
,
644 struct tgsi_sampler
*sampler
)
647 struct tgsi_parse_context parse
;
648 struct tgsi_full_instruction
*instructions
;
649 struct tgsi_full_declaration
*declarations
;
650 uint maxInstructions
= 10, numInstructions
= 0;
651 uint maxDeclarations
= 10, numDeclarations
= 0;
654 tgsi_dump(tokens
, 0);
660 mach
->Tokens
= tokens
;
661 mach
->Sampler
= sampler
;
664 /* unbind and free all */
665 FREE(mach
->Declarations
);
666 mach
->Declarations
= NULL
;
667 mach
->NumDeclarations
= 0;
669 FREE(mach
->Instructions
);
670 mach
->Instructions
= NULL
;
671 mach
->NumInstructions
= 0;
676 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
677 if (k
!= TGSI_PARSE_OK
) {
678 debug_printf( "Problem parsing!\n" );
682 mach
->Processor
= parse
.FullHeader
.Processor
.Processor
;
684 mach
->NumOutputs
= 0;
686 if (mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
&&
687 !mach
->UsedGeometryShader
) {
688 struct tgsi_exec_vector
*inputs
;
689 struct tgsi_exec_vector
*outputs
;
691 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
692 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
698 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
699 TGSI_MAX_TOTAL_VERTICES
, 16);
706 align_free(mach
->Inputs
);
707 align_free(mach
->Outputs
);
709 mach
->Inputs
= inputs
;
710 mach
->Outputs
= outputs
;
711 mach
->UsedGeometryShader
= TRUE
;
714 declarations
= (struct tgsi_full_declaration
*)
715 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
721 instructions
= (struct tgsi_full_instruction
*)
722 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
725 FREE( declarations
);
729 while( !tgsi_parse_end_of_tokens( &parse
) ) {
732 tgsi_parse_token( &parse
);
733 switch( parse
.FullToken
.Token
.Type
) {
734 case TGSI_TOKEN_TYPE_DECLARATION
:
735 /* save expanded declaration */
736 if (numDeclarations
== maxDeclarations
) {
737 declarations
= REALLOC(declarations
,
739 * sizeof(struct tgsi_full_declaration
),
740 (maxDeclarations
+ 10)
741 * sizeof(struct tgsi_full_declaration
));
742 maxDeclarations
+= 10;
744 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
746 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
747 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
752 memcpy(declarations
+ numDeclarations
,
753 &parse
.FullToken
.FullDeclaration
,
754 sizeof(declarations
[0]));
758 case TGSI_TOKEN_TYPE_IMMEDIATE
:
760 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
762 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
764 for( i
= 0; i
< size
; i
++ ) {
765 mach
->Imms
[mach
->ImmLimit
][i
] =
766 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
772 case TGSI_TOKEN_TYPE_INSTRUCTION
:
774 /* save expanded instruction */
775 if (numInstructions
== maxInstructions
) {
776 instructions
= REALLOC(instructions
,
778 * sizeof(struct tgsi_full_instruction
),
779 (maxInstructions
+ 10)
780 * sizeof(struct tgsi_full_instruction
));
781 maxInstructions
+= 10;
784 memcpy(instructions
+ numInstructions
,
785 &parse
.FullToken
.FullInstruction
,
786 sizeof(instructions
[0]));
791 case TGSI_TOKEN_TYPE_PROPERTY
:
792 if (mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
) {
793 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
794 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
803 tgsi_parse_free (&parse
);
805 FREE(mach
->Declarations
);
806 mach
->Declarations
= declarations
;
807 mach
->NumDeclarations
= numDeclarations
;
809 FREE(mach
->Instructions
);
810 mach
->Instructions
= instructions
;
811 mach
->NumInstructions
= numInstructions
;
815 struct tgsi_exec_machine
*
816 tgsi_exec_machine_create( void )
818 struct tgsi_exec_machine
*mach
;
821 mach
= align_malloc( sizeof *mach
, 16 );
825 memset(mach
, 0, sizeof(*mach
));
827 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
828 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
829 mach
->Predicates
= &mach
->Temps
[TGSI_EXEC_TEMP_P0
];
831 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
832 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
833 if (!mach
->Inputs
|| !mach
->Outputs
)
836 /* Setup constants needed by the SSE2 executor. */
837 for( i
= 0; i
< 4; i
++ ) {
838 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
839 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
840 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
841 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
842 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
843 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
844 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
845 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
846 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
847 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
851 /* silence warnings */
860 align_free(mach
->Inputs
);
861 align_free(mach
->Outputs
);
869 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
872 FREE(mach
->Instructions
);
873 FREE(mach
->Declarations
);
875 align_free(mach
->Inputs
);
876 align_free(mach
->Outputs
);
883 micro_add(union tgsi_exec_channel
*dst
,
884 const union tgsi_exec_channel
*src0
,
885 const union tgsi_exec_channel
*src1
)
887 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
888 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
889 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
890 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
895 union tgsi_exec_channel
*dst
,
896 const union tgsi_exec_channel
*src0
,
897 const union tgsi_exec_channel
*src1
)
899 if (src1
->f
[0] != 0) {
900 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
902 if (src1
->f
[1] != 0) {
903 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
905 if (src1
->f
[2] != 0) {
906 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
908 if (src1
->f
[3] != 0) {
909 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
915 union tgsi_exec_channel
*dst
,
916 const union tgsi_exec_channel
*src0
,
917 const union tgsi_exec_channel
*src1
,
918 const union tgsi_exec_channel
*src2
,
919 const union tgsi_exec_channel
*src3
)
921 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
922 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
923 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
924 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
928 micro_max(union tgsi_exec_channel
*dst
,
929 const union tgsi_exec_channel
*src0
,
930 const union tgsi_exec_channel
*src1
)
932 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
933 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
934 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
935 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
939 micro_min(union tgsi_exec_channel
*dst
,
940 const union tgsi_exec_channel
*src0
,
941 const union tgsi_exec_channel
*src1
)
943 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
944 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
945 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
946 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
950 micro_mul(union tgsi_exec_channel
*dst
,
951 const union tgsi_exec_channel
*src0
,
952 const union tgsi_exec_channel
*src1
)
954 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
955 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
956 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
957 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
962 union tgsi_exec_channel
*dst
,
963 const union tgsi_exec_channel
*src
)
965 dst
->f
[0] = -src
->f
[0];
966 dst
->f
[1] = -src
->f
[1];
967 dst
->f
[2] = -src
->f
[2];
968 dst
->f
[3] = -src
->f
[3];
973 union tgsi_exec_channel
*dst
,
974 const union tgsi_exec_channel
*src0
,
975 const union tgsi_exec_channel
*src1
)
978 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
979 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
980 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
981 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
983 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
984 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
985 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
986 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
991 micro_sub(union tgsi_exec_channel
*dst
,
992 const union tgsi_exec_channel
*src0
,
993 const union tgsi_exec_channel
*src1
)
995 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
996 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
997 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
998 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1002 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1003 const uint chan_index
,
1006 const union tgsi_exec_channel
*index
,
1007 const union tgsi_exec_channel
*index2D
,
1008 union tgsi_exec_channel
*chan
)
1012 assert(swizzle
< 4);
1015 case TGSI_FILE_CONSTANT
:
1016 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1017 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1018 assert(mach
->Consts
[index2D
->i
[i
]]);
1020 if (index
->i
[i
] < 0) {
1023 /* NOTE: copying the const value as a uint instead of float */
1024 const uint constbuf
= index2D
->i
[i
];
1025 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1026 const int pos
= index
->i
[i
] * 4 + swizzle
;
1027 /* const buffer bounds check */
1028 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1030 /* Debug: print warning */
1031 static int count
= 0;
1033 debug_printf("TGSI Exec: const buffer index %d"
1034 " out of bounds\n", pos
);
1039 chan
->u
[i
] = buf
[pos
];
1044 case TGSI_FILE_INPUT
:
1045 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1047 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1048 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1049 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1050 index2D->i[i], index->i[i]);
1052 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1054 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1055 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1059 case TGSI_FILE_SYSTEM_VALUE
:
1060 /* XXX no swizzling at this point. Will be needed if we put
1061 * gl_FragCoord, for example, in a sys value register.
1063 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1064 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].u
[i
];
1068 case TGSI_FILE_TEMPORARY
:
1069 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1070 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1071 assert(index2D
->i
[i
] == 0);
1073 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1077 case TGSI_FILE_IMMEDIATE
:
1078 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1079 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1080 assert(index2D
->i
[i
] == 0);
1082 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1086 case TGSI_FILE_ADDRESS
:
1087 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1088 assert(index
->i
[i
] >= 0);
1089 assert(index2D
->i
[i
] == 0);
1091 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1095 case TGSI_FILE_PREDICATE
:
1096 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1097 assert(index
->i
[i
] >= 0 && index
->i
[i
] < TGSI_EXEC_NUM_PREDS
);
1098 assert(index2D
->i
[i
] == 0);
1100 chan
->u
[i
] = mach
->Predicates
[0].xyzw
[swizzle
].u
[i
];
1104 case TGSI_FILE_OUTPUT
:
1105 /* vertex/fragment output vars can be read too */
1106 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1107 assert(index
->i
[i
] >= 0);
1108 assert(index2D
->i
[i
] == 0);
1110 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1116 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1123 fetch_source(const struct tgsi_exec_machine
*mach
,
1124 union tgsi_exec_channel
*chan
,
1125 const struct tgsi_full_src_register
*reg
,
1126 const uint chan_index
,
1127 enum tgsi_exec_datatype src_datatype
)
1129 union tgsi_exec_channel index
;
1130 union tgsi_exec_channel index2D
;
1133 /* We start with a direct index into a register file.
1137 * file = Register.File
1138 * [1] = Register.Index
1143 index
.i
[3] = reg
->Register
.Index
;
1145 /* There is an extra source register that indirectly subscripts
1146 * a register file. The direct index now becomes an offset
1147 * that is being added to the indirect register.
1151 * ind = Indirect.File
1152 * [2] = Indirect.Index
1153 * .x = Indirect.SwizzleX
1155 if (reg
->Register
.Indirect
) {
1156 union tgsi_exec_channel index2
;
1157 union tgsi_exec_channel indir_index
;
1158 const uint execmask
= mach
->ExecMask
;
1161 /* which address register (always zero now) */
1165 index2
.i
[3] = reg
->Indirect
.Index
;
1166 /* get current value of address register[swizzle] */
1167 swizzle
= reg
->Indirect
.Swizzle
;
1168 fetch_src_file_channel(mach
,
1176 /* add value of address register to the offset */
1177 index
.i
[0] += indir_index
.i
[0];
1178 index
.i
[1] += indir_index
.i
[1];
1179 index
.i
[2] += indir_index
.i
[2];
1180 index
.i
[3] += indir_index
.i
[3];
1182 /* for disabled execution channels, zero-out the index to
1183 * avoid using a potential garbage value.
1185 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1186 if ((execmask
& (1 << i
)) == 0)
1191 /* There is an extra source register that is a second
1192 * subscript to a register file. Effectively it means that
1193 * the register file is actually a 2D array of registers.
1197 * [3] = Dimension.Index
1199 if (reg
->Register
.Dimension
) {
1203 index2D
.i
[3] = reg
->Dimension
.Index
;
1205 /* Again, the second subscript index can be addressed indirectly
1206 * identically to the first one.
1207 * Nothing stops us from indirectly addressing the indirect register,
1208 * but there is no need for that, so we won't exercise it.
1210 * file[ind[4].y+3][1],
1212 * ind = DimIndirect.File
1213 * [4] = DimIndirect.Index
1214 * .y = DimIndirect.SwizzleX
1216 if (reg
->Dimension
.Indirect
) {
1217 union tgsi_exec_channel index2
;
1218 union tgsi_exec_channel indir_index
;
1219 const uint execmask
= mach
->ExecMask
;
1225 index2
.i
[3] = reg
->DimIndirect
.Index
;
1227 swizzle
= reg
->DimIndirect
.Swizzle
;
1228 fetch_src_file_channel(mach
,
1230 reg
->DimIndirect
.File
,
1236 index2D
.i
[0] += indir_index
.i
[0];
1237 index2D
.i
[1] += indir_index
.i
[1];
1238 index2D
.i
[2] += indir_index
.i
[2];
1239 index2D
.i
[3] += indir_index
.i
[3];
1241 /* for disabled execution channels, zero-out the index to
1242 * avoid using a potential garbage value.
1244 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1245 if ((execmask
& (1 << i
)) == 0) {
1251 /* If by any chance there was a need for a 3D array of register
1252 * files, we would have to check whether Dimension is followed
1253 * by a dimension register and continue the saga.
1262 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1263 fetch_src_file_channel(mach
,
1271 if (reg
->Register
.Absolute
) {
1272 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1273 micro_abs(chan
, chan
);
1275 micro_iabs(chan
, chan
);
1279 if (reg
->Register
.Negate
) {
1280 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1281 micro_neg(chan
, chan
);
1283 micro_ineg(chan
, chan
);
1289 store_dest(struct tgsi_exec_machine
*mach
,
1290 const union tgsi_exec_channel
*chan
,
1291 const struct tgsi_full_dst_register
*reg
,
1292 const struct tgsi_full_instruction
*inst
,
1294 enum tgsi_exec_datatype dst_datatype
)
1297 union tgsi_exec_channel null
;
1298 union tgsi_exec_channel
*dst
;
1299 union tgsi_exec_channel index2D
;
1300 uint execmask
= mach
->ExecMask
;
1301 int offset
= 0; /* indirection offset */
1305 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1306 check_inf_or_nan(chan
);
1309 /* There is an extra source register that indirectly subscripts
1310 * a register file. The direct index now becomes an offset
1311 * that is being added to the indirect register.
1315 * ind = Indirect.File
1316 * [2] = Indirect.Index
1317 * .x = Indirect.SwizzleX
1319 if (reg
->Register
.Indirect
) {
1320 union tgsi_exec_channel index
;
1321 union tgsi_exec_channel indir_index
;
1324 /* which address register (always zero for now) */
1328 index
.i
[3] = reg
->Indirect
.Index
;
1330 /* get current value of address register[swizzle] */
1331 swizzle
= reg
->Indirect
.Swizzle
;
1333 /* fetch values from the address/indirection register */
1334 fetch_src_file_channel(mach
,
1342 /* save indirection offset */
1343 offset
= indir_index
.i
[0];
1346 /* There is an extra source register that is a second
1347 * subscript to a register file. Effectively it means that
1348 * the register file is actually a 2D array of registers.
1352 * [3] = Dimension.Index
1354 if (reg
->Register
.Dimension
) {
1358 index2D
.i
[3] = reg
->Dimension
.Index
;
1360 /* Again, the second subscript index can be addressed indirectly
1361 * identically to the first one.
1362 * Nothing stops us from indirectly addressing the indirect register,
1363 * but there is no need for that, so we won't exercise it.
1365 * file[ind[4].y+3][1],
1367 * ind = DimIndirect.File
1368 * [4] = DimIndirect.Index
1369 * .y = DimIndirect.SwizzleX
1371 if (reg
->Dimension
.Indirect
) {
1372 union tgsi_exec_channel index2
;
1373 union tgsi_exec_channel indir_index
;
1374 const uint execmask
= mach
->ExecMask
;
1381 index2
.i
[3] = reg
->DimIndirect
.Index
;
1383 swizzle
= reg
->DimIndirect
.Swizzle
;
1384 fetch_src_file_channel(mach
,
1386 reg
->DimIndirect
.File
,
1392 index2D
.i
[0] += indir_index
.i
[0];
1393 index2D
.i
[1] += indir_index
.i
[1];
1394 index2D
.i
[2] += indir_index
.i
[2];
1395 index2D
.i
[3] += indir_index
.i
[3];
1397 /* for disabled execution channels, zero-out the index to
1398 * avoid using a potential garbage value.
1400 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1401 if ((execmask
& (1 << i
)) == 0) {
1407 /* If by any chance there was a need for a 3D array of register
1408 * files, we would have to check whether Dimension is followed
1409 * by a dimension register and continue the saga.
1418 switch (reg
->Register
.File
) {
1419 case TGSI_FILE_NULL
:
1423 case TGSI_FILE_OUTPUT
:
1424 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1425 + reg
->Register
.Index
;
1426 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1428 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1429 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1430 reg
->Register
.Index
);
1431 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1432 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1433 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1434 if (execmask
& (1 << i
))
1435 debug_printf("%f, ", chan
->f
[i
]);
1436 debug_printf(")\n");
1441 case TGSI_FILE_TEMPORARY
:
1442 index
= reg
->Register
.Index
;
1443 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1444 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1447 case TGSI_FILE_ADDRESS
:
1448 index
= reg
->Register
.Index
;
1449 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1452 case TGSI_FILE_PREDICATE
:
1453 index
= reg
->Register
.Index
;
1454 assert(index
< TGSI_EXEC_NUM_PREDS
);
1455 dst
= &mach
->Predicates
[index
].xyzw
[chan_index
];
1463 if (inst
->Instruction
.Predicate
) {
1465 union tgsi_exec_channel
*pred
;
1467 switch (chan_index
) {
1469 swizzle
= inst
->Predicate
.SwizzleX
;
1472 swizzle
= inst
->Predicate
.SwizzleY
;
1475 swizzle
= inst
->Predicate
.SwizzleZ
;
1478 swizzle
= inst
->Predicate
.SwizzleW
;
1485 assert(inst
->Predicate
.Index
== 0);
1487 pred
= &mach
->Predicates
[inst
->Predicate
.Index
].xyzw
[swizzle
];
1489 if (inst
->Predicate
.Negate
) {
1490 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1492 execmask
&= ~(1 << i
);
1496 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1498 execmask
&= ~(1 << i
);
1504 switch (inst
->Instruction
.Saturate
) {
1506 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1507 if (execmask
& (1 << i
))
1508 dst
->i
[i
] = chan
->i
[i
];
1511 case TGSI_SAT_ZERO_ONE
:
1512 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1513 if (execmask
& (1 << i
)) {
1514 if (chan
->f
[i
] < 0.0f
)
1516 else if (chan
->f
[i
] > 1.0f
)
1519 dst
->i
[i
] = chan
->i
[i
];
1523 case TGSI_SAT_MINUS_PLUS_ONE
:
1524 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1525 if (execmask
& (1 << i
)) {
1526 if (chan
->f
[i
] < -1.0f
)
1528 else if (chan
->f
[i
] > 1.0f
)
1531 dst
->i
[i
] = chan
->i
[i
];
1540 #define FETCH(VAL,INDEX,CHAN)\
1541 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1543 #define IFETCH(VAL,INDEX,CHAN)\
1544 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1548 * Execute ARB-style KIL which is predicated by a src register.
1549 * Kill fragment if any of the four values is less than zero.
1552 exec_kill_if(struct tgsi_exec_machine
*mach
,
1553 const struct tgsi_full_instruction
*inst
)
1557 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1558 union tgsi_exec_channel r
[1];
1560 /* This mask stores component bits that were already tested. */
1563 for (chan_index
= 0; chan_index
< 4; chan_index
++)
1568 /* unswizzle channel */
1569 swizzle
= tgsi_util_get_full_src_register_swizzle (
1573 /* check if the component has not been already tested */
1574 if (uniquemask
& (1 << swizzle
))
1576 uniquemask
|= 1 << swizzle
;
1578 FETCH(&r
[0], 0, chan_index
);
1579 for (i
= 0; i
< 4; i
++)
1580 if (r
[0].f
[i
] < 0.0f
)
1584 /* restrict to fragments currently executing */
1585 kilmask
&= mach
->ExecMask
;
1587 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1591 * Unconditional fragment kill/discard.
1594 exec_kill(struct tgsi_exec_machine
*mach
,
1595 const struct tgsi_full_instruction
*inst
)
1597 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1599 /* kill fragment for all fragments currently executing */
1600 kilmask
= mach
->ExecMask
;
1601 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1605 emit_vertex(struct tgsi_exec_machine
*mach
)
1607 /* FIXME: check for exec mask correctly
1609 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1610 if ((mach->ExecMask & (1 << i)))
1612 if (mach
->ExecMask
) {
1613 if (mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]] >= mach
->MaxOutputVertices
)
1616 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
1617 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
1622 emit_primitive(struct tgsi_exec_machine
*mach
)
1624 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
1625 /* FIXME: check for exec mask correctly
1627 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1628 if ((mach->ExecMask & (1 << i)))
1630 if (mach
->ExecMask
) {
1632 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
1633 mach
->Primitives
[*prim_count
] = 0;
1638 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
1640 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1642 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
1643 if (emitted_verts
) {
1644 emit_primitive(mach
);
1651 * Fetch four texture samples using STR texture coordinates.
1654 fetch_texel( struct tgsi_sampler
*sampler
,
1655 const unsigned sview_idx
,
1656 const unsigned sampler_idx
,
1657 const union tgsi_exec_channel
*s
,
1658 const union tgsi_exec_channel
*t
,
1659 const union tgsi_exec_channel
*p
,
1660 const union tgsi_exec_channel
*c0
,
1661 const union tgsi_exec_channel
*c1
,
1662 float derivs
[3][2][TGSI_QUAD_SIZE
],
1663 const int8_t offset
[3],
1664 enum tgsi_sampler_control control
,
1665 union tgsi_exec_channel
*r
,
1666 union tgsi_exec_channel
*g
,
1667 union tgsi_exec_channel
*b
,
1668 union tgsi_exec_channel
*a
)
1671 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
1673 /* FIXME: handle explicit derivs, offsets */
1674 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
1675 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
1677 for (j
= 0; j
< 4; j
++) {
1678 r
->f
[j
] = rgba
[0][j
];
1679 g
->f
[j
] = rgba
[1][j
];
1680 b
->f
[j
] = rgba
[2][j
];
1681 a
->f
[j
] = rgba
[3][j
];
1686 #define TEX_MODIFIER_NONE 0
1687 #define TEX_MODIFIER_PROJECTED 1
1688 #define TEX_MODIFIER_LOD_BIAS 2
1689 #define TEX_MODIFIER_EXPLICIT_LOD 3
1690 #define TEX_MODIFIER_LEVEL_ZERO 4
1694 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1697 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
1698 const struct tgsi_full_instruction
*inst
,
1701 if (inst
->Texture
.NumOffsets
== 1) {
1702 union tgsi_exec_channel index
;
1703 union tgsi_exec_channel offset
[3];
1704 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
1705 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1706 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
1707 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1708 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
1709 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1710 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
1711 offsets
[0] = offset
[0].i
[0];
1712 offsets
[1] = offset
[1].i
[0];
1713 offsets
[2] = offset
[2].i
[0];
1715 assert(inst
->Texture
.NumOffsets
== 0);
1716 offsets
[0] = offsets
[1] = offsets
[2] = 0;
1722 * Fetch dx and dy values for one channel (s, t or r).
1723 * Put dx values into one float array, dy values into another.
1726 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
1727 const struct tgsi_full_instruction
*inst
,
1730 float derivs
[2][TGSI_QUAD_SIZE
])
1732 union tgsi_exec_channel d
;
1733 FETCH(&d
, regdsrcx
, chan
);
1734 derivs
[0][0] = d
.f
[0];
1735 derivs
[0][1] = d
.f
[1];
1736 derivs
[0][2] = d
.f
[2];
1737 derivs
[0][3] = d
.f
[3];
1738 FETCH(&d
, regdsrcx
+ 1, chan
);
1739 derivs
[1][0] = d
.f
[0];
1740 derivs
[1][1] = d
.f
[1];
1741 derivs
[1][2] = d
.f
[2];
1742 derivs
[1][3] = d
.f
[3];
1747 * execute a texture instruction.
1749 * modifier is used to control the channel routing for the\
1750 * instruction variants like proj, lod, and texture with lod bias.
1751 * sampler indicates which src register the sampler is contained in.
1754 exec_tex(struct tgsi_exec_machine
*mach
,
1755 const struct tgsi_full_instruction
*inst
,
1756 uint modifier
, uint sampler
)
1758 const uint unit
= inst
->Src
[sampler
].Register
.Index
;
1759 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
1760 union tgsi_exec_channel r
[5];
1761 enum tgsi_sampler_control control
= tgsi_sampler_lod_none
;
1764 int dim
, shadow_ref
, i
;
1766 /* always fetch all 3 offsets, overkill but keeps code simple */
1767 fetch_texel_offsets(mach
, inst
, offsets
);
1769 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
1770 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
1772 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
, &shadow_ref
);
1775 if (shadow_ref
>= 0)
1776 assert(shadow_ref
>= dim
&& shadow_ref
< Elements(args
));
1778 /* fetch modifier to the last argument */
1779 if (modifier
!= TEX_MODIFIER_NONE
) {
1780 const int last
= Elements(args
) - 1;
1782 /* fetch modifier from src0.w or src1.x */
1784 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
1785 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
1788 assert(shadow_ref
!= 4);
1789 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
1792 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
1793 args
[last
] = &r
[last
];
1797 args
[last
] = &ZeroVec
;
1800 /* point unused arguments to zero vector */
1801 for (i
= dim
; i
< last
; i
++)
1804 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
1805 control
= tgsi_sampler_lod_explicit
;
1806 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
1807 control
= tgsi_sampler_lod_bias
;
1810 for (i
= dim
; i
< Elements(args
); i
++)
1814 /* fetch coordinates */
1815 for (i
= 0; i
< dim
; i
++) {
1816 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
1819 micro_div(&r
[i
], &r
[i
], proj
);
1824 /* fetch reference value */
1825 if (shadow_ref
>= 0) {
1826 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
1829 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
1831 args
[shadow_ref
] = &r
[shadow_ref
];
1834 fetch_texel(mach
->Sampler
, unit
, unit
,
1835 args
[0], args
[1], args
[2], args
[3], args
[4],
1836 NULL
, offsets
, control
,
1837 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1840 debug_printf("fetch r: %g %g %g %g\n",
1841 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
1842 debug_printf("fetch g: %g %g %g %g\n",
1843 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
1844 debug_printf("fetch b: %g %g %g %g\n",
1845 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
1846 debug_printf("fetch a: %g %g %g %g\n",
1847 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
1850 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1851 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1852 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
1859 exec_txd(struct tgsi_exec_machine
*mach
,
1860 const struct tgsi_full_instruction
*inst
)
1862 const uint unit
= inst
->Src
[3].Register
.Index
;
1863 union tgsi_exec_channel r
[4];
1864 float derivs
[3][2][TGSI_QUAD_SIZE
];
1868 /* always fetch all 3 offsets, overkill but keeps code simple */
1869 fetch_texel_offsets(mach
, inst
, offsets
);
1871 switch (inst
->Texture
.Texture
) {
1872 case TGSI_TEXTURE_1D
:
1873 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1875 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1877 fetch_texel(mach
->Sampler
, unit
, unit
,
1878 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
1879 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1880 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1883 case TGSI_TEXTURE_SHADOW1D
:
1884 case TGSI_TEXTURE_1D_ARRAY
:
1885 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1886 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
1887 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1888 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1889 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1891 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1893 fetch_texel(mach
->Sampler
, unit
, unit
,
1894 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
1895 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1896 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1899 case TGSI_TEXTURE_2D
:
1900 case TGSI_TEXTURE_RECT
:
1901 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1902 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1904 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1905 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
1907 fetch_texel(mach
->Sampler
, unit
, unit
,
1908 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
1909 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1910 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1914 case TGSI_TEXTURE_SHADOW2D
:
1915 case TGSI_TEXTURE_SHADOWRECT
:
1916 case TGSI_TEXTURE_2D_ARRAY
:
1917 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1918 /* only SHADOW2D_ARRAY actually needs W */
1919 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1920 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1921 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1922 FETCH(&r
[3], 0, TGSI_CHAN_W
);
1924 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1925 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
1927 fetch_texel(mach
->Sampler
, unit
, unit
,
1928 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
1929 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1930 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1933 case TGSI_TEXTURE_3D
:
1934 case TGSI_TEXTURE_CUBE
:
1935 case TGSI_TEXTURE_CUBE_ARRAY
:
1936 case TGSI_TEXTURE_SHADOWCUBE
:
1937 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
1938 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1939 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1940 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1941 FETCH(&r
[3], 0, TGSI_CHAN_W
);
1943 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1944 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
1945 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
1947 fetch_texel(mach
->Sampler
, unit
, unit
,
1948 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
1949 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1950 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1957 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1958 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1959 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
1966 exec_txf(struct tgsi_exec_machine
*mach
,
1967 const struct tgsi_full_instruction
*inst
)
1969 const uint unit
= inst
->Src
[1].Register
.Index
;
1970 union tgsi_exec_channel r
[4];
1972 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
1977 /* always fetch all 3 offsets, overkill but keeps code simple */
1978 fetch_texel_offsets(mach
, inst
, offsets
);
1980 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
1982 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
) {
1983 target
= mach
->SamplerViews
[unit
].Resource
;
1986 target
= inst
->Texture
.Texture
;
1989 case TGSI_TEXTURE_3D
:
1990 case TGSI_TEXTURE_2D_ARRAY
:
1991 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1992 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
1993 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
1995 case TGSI_TEXTURE_2D
:
1996 case TGSI_TEXTURE_RECT
:
1997 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1998 case TGSI_TEXTURE_SHADOW2D
:
1999 case TGSI_TEXTURE_SHADOWRECT
:
2000 case TGSI_TEXTURE_1D_ARRAY
:
2001 case TGSI_TEXTURE_2D_MSAA
:
2002 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2004 case TGSI_TEXTURE_BUFFER
:
2005 case TGSI_TEXTURE_1D
:
2006 case TGSI_TEXTURE_SHADOW1D
:
2007 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2014 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2017 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2018 r
[0].f
[j
] = rgba
[0][j
];
2019 r
[1].f
[j
] = rgba
[1][j
];
2020 r
[2].f
[j
] = rgba
[2][j
];
2021 r
[3].f
[j
] = rgba
[3][j
];
2024 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
) {
2025 unsigned char swizzles
[4];
2026 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2027 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2028 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2029 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2031 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2032 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2033 store_dest(mach
, &r
[swizzles
[chan
]],
2034 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2039 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2040 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2041 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2048 exec_txq(struct tgsi_exec_machine
*mach
,
2049 const struct tgsi_full_instruction
*inst
)
2051 const uint unit
= inst
->Src
[1].Register
.Index
;
2053 union tgsi_exec_channel r
[4], src
;
2057 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2059 /* XXX: This interface can't return per-pixel values */
2060 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2062 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2063 for (j
= 0; j
< 4; j
++) {
2064 r
[j
].i
[i
] = result
[j
];
2068 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2069 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2070 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2071 TGSI_EXEC_DATA_INT
);
2077 exec_sample(struct tgsi_exec_machine
*mach
,
2078 const struct tgsi_full_instruction
*inst
,
2079 uint modifier
, boolean compare
)
2081 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2082 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2083 union tgsi_exec_channel r
[4], c1
;
2084 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2085 enum tgsi_sampler_control control
= tgsi_sampler_lod_none
;
2087 unsigned char swizzles
[4];
2090 /* always fetch all 3 offsets, overkill but keeps code simple */
2091 fetch_texel_offsets(mach
, inst
, offsets
);
2093 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2095 if (modifier
!= TEX_MODIFIER_NONE
) {
2096 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2097 FETCH(&c1
, 3, TGSI_CHAN_X
);
2099 control
= tgsi_sampler_lod_bias
;
2101 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2102 FETCH(&c1
, 3, TGSI_CHAN_X
);
2104 control
= tgsi_sampler_lod_explicit
;
2107 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2108 control
= tgsi_sampler_lod_zero
;
2112 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2114 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2115 case TGSI_TEXTURE_1D
:
2117 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2118 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2119 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2120 NULL
, offsets
, control
,
2121 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2124 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2125 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2126 NULL
, offsets
, control
,
2127 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2131 case TGSI_TEXTURE_1D_ARRAY
:
2132 case TGSI_TEXTURE_2D
:
2133 case TGSI_TEXTURE_RECT
:
2134 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2136 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2137 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2138 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2139 NULL
, offsets
, control
,
2140 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2143 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2144 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2145 NULL
, offsets
, control
,
2146 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2150 case TGSI_TEXTURE_2D_ARRAY
:
2151 case TGSI_TEXTURE_3D
:
2152 case TGSI_TEXTURE_CUBE
:
2153 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2154 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2156 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2157 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2158 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2159 NULL
, offsets
, control
,
2160 &r
[0], &r
[1], &r
[2], &r
[3]);
2163 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2164 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2165 NULL
, offsets
, control
,
2166 &r
[0], &r
[1], &r
[2], &r
[3]);
2170 case TGSI_TEXTURE_CUBE_ARRAY
:
2171 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2172 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2173 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2175 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2176 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2177 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2178 NULL
, offsets
, control
,
2179 &r
[0], &r
[1], &r
[2], &r
[3]);
2182 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2183 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2184 NULL
, offsets
, control
,
2185 &r
[0], &r
[1], &r
[2], &r
[3]);
2194 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2195 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2196 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2197 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2199 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2200 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2201 store_dest(mach
, &r
[swizzles
[chan
]],
2202 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2208 exec_sample_d(struct tgsi_exec_machine
*mach
,
2209 const struct tgsi_full_instruction
*inst
)
2211 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2212 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2213 union tgsi_exec_channel r
[4];
2214 float derivs
[3][2][TGSI_QUAD_SIZE
];
2216 unsigned char swizzles
[4];
2219 /* always fetch all 3 offsets, overkill but keeps code simple */
2220 fetch_texel_offsets(mach
, inst
, offsets
);
2222 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2224 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2225 case TGSI_TEXTURE_1D
:
2226 case TGSI_TEXTURE_1D_ARRAY
:
2227 /* only 1D array actually needs Y */
2228 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2230 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2232 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2233 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2234 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
2235 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2238 case TGSI_TEXTURE_2D
:
2239 case TGSI_TEXTURE_RECT
:
2240 case TGSI_TEXTURE_2D_ARRAY
:
2241 /* only 2D array actually needs Z */
2242 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2243 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2245 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2246 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2248 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2249 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2250 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
2251 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2254 case TGSI_TEXTURE_3D
:
2255 case TGSI_TEXTURE_CUBE
:
2256 case TGSI_TEXTURE_CUBE_ARRAY
:
2257 /* only cube array actually needs W */
2258 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2259 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2260 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2262 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2263 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2264 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2266 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2267 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2268 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
2269 &r
[0], &r
[1], &r
[2], &r
[3]);
2276 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2277 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2278 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2279 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2281 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2282 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2283 store_dest(mach
, &r
[swizzles
[chan
]],
2284 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2291 * Evaluate a constant-valued coefficient at the position of the
2296 struct tgsi_exec_machine
*mach
,
2302 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2303 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2308 * Evaluate a linear-valued coefficient at the position of the
2313 struct tgsi_exec_machine
*mach
,
2317 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2318 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2319 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2320 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2321 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2322 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2323 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2324 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2325 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2329 * Evaluate a perspective-valued coefficient at the position of the
2333 eval_perspective_coef(
2334 struct tgsi_exec_machine
*mach
,
2338 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2339 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2340 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2341 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2342 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2343 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2344 /* divide by W here */
2345 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2346 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2347 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2348 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2352 typedef void (* eval_coef_func
)(
2353 struct tgsi_exec_machine
*mach
,
2358 exec_declaration(struct tgsi_exec_machine
*mach
,
2359 const struct tgsi_full_declaration
*decl
)
2361 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2362 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2366 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
2367 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2368 uint first
, last
, mask
;
2370 first
= decl
->Range
.First
;
2371 last
= decl
->Range
.Last
;
2372 mask
= decl
->Declaration
.UsageMask
;
2374 /* XXX we could remove this special-case code since
2375 * mach->InterpCoefs[first].a0 should already have the
2376 * front/back-face value. But we should first update the
2377 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2378 * Then, we could remove the tgsi_exec_machine::Face field.
2380 /* XXX make FACE a system value */
2381 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2384 assert(decl
->Semantic
.Index
== 0);
2385 assert(first
== last
);
2387 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2388 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2391 eval_coef_func eval
;
2394 switch (decl
->Interp
.Interpolate
) {
2395 case TGSI_INTERPOLATE_CONSTANT
:
2396 eval
= eval_constant_coef
;
2399 case TGSI_INTERPOLATE_LINEAR
:
2400 eval
= eval_linear_coef
;
2403 case TGSI_INTERPOLATE_PERSPECTIVE
:
2404 eval
= eval_perspective_coef
;
2407 case TGSI_INTERPOLATE_COLOR
:
2408 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
2416 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2417 if (mask
& (1 << j
)) {
2418 for (i
= first
; i
<= last
; i
++) {
2425 if (DEBUG_EXECUTION
) {
2427 for (i
= first
; i
<= last
; ++i
) {
2428 debug_printf("IN[%2u] = ", i
);
2429 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2433 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2434 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
2435 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
2436 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
2437 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
2444 if (decl
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
2445 mach
->SysSemanticToIndex
[decl
->Declaration
.Semantic
] = decl
->Range
.First
;
2450 typedef void (* micro_op
)(union tgsi_exec_channel
*dst
);
2453 exec_vector(struct tgsi_exec_machine
*mach
,
2454 const struct tgsi_full_instruction
*inst
,
2456 enum tgsi_exec_datatype dst_datatype
)
2460 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2461 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2462 union tgsi_exec_channel dst
;
2465 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2470 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
2471 const union tgsi_exec_channel
*src
);
2474 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
2475 const struct tgsi_full_instruction
*inst
,
2477 enum tgsi_exec_datatype dst_datatype
,
2478 enum tgsi_exec_datatype src_datatype
)
2481 union tgsi_exec_channel src
;
2482 union tgsi_exec_channel dst
;
2484 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2486 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2487 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2488 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2494 exec_vector_unary(struct tgsi_exec_machine
*mach
,
2495 const struct tgsi_full_instruction
*inst
,
2497 enum tgsi_exec_datatype dst_datatype
,
2498 enum tgsi_exec_datatype src_datatype
)
2501 struct tgsi_exec_vector dst
;
2503 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2504 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2505 union tgsi_exec_channel src
;
2507 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
2508 op(&dst
.xyzw
[chan
], &src
);
2511 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2512 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2513 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2518 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
2519 const union tgsi_exec_channel
*src0
,
2520 const union tgsi_exec_channel
*src1
);
2523 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
2524 const struct tgsi_full_instruction
*inst
,
2526 enum tgsi_exec_datatype dst_datatype
,
2527 enum tgsi_exec_datatype src_datatype
)
2530 union tgsi_exec_channel src
[2];
2531 union tgsi_exec_channel dst
;
2533 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2534 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
2535 op(&dst
, &src
[0], &src
[1]);
2536 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2537 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2538 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2544 exec_vector_binary(struct tgsi_exec_machine
*mach
,
2545 const struct tgsi_full_instruction
*inst
,
2547 enum tgsi_exec_datatype dst_datatype
,
2548 enum tgsi_exec_datatype src_datatype
)
2551 struct tgsi_exec_vector dst
;
2553 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2554 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2555 union tgsi_exec_channel src
[2];
2557 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2558 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2559 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
2562 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2563 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2564 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2569 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
2570 const union tgsi_exec_channel
*src0
,
2571 const union tgsi_exec_channel
*src1
,
2572 const union tgsi_exec_channel
*src2
);
2575 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
2576 const struct tgsi_full_instruction
*inst
,
2577 micro_trinary_op op
,
2578 enum tgsi_exec_datatype dst_datatype
,
2579 enum tgsi_exec_datatype src_datatype
)
2582 struct tgsi_exec_vector dst
;
2584 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2585 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2586 union tgsi_exec_channel src
[3];
2588 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2589 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2590 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2591 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
2594 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2595 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2596 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2601 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
2602 const union tgsi_exec_channel
*src0
,
2603 const union tgsi_exec_channel
*src1
,
2604 const union tgsi_exec_channel
*src2
,
2605 const union tgsi_exec_channel
*src3
);
2608 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
2609 const struct tgsi_full_instruction
*inst
,
2610 micro_quaternary_op op
,
2611 enum tgsi_exec_datatype dst_datatype
,
2612 enum tgsi_exec_datatype src_datatype
)
2615 struct tgsi_exec_vector dst
;
2617 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2618 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2619 union tgsi_exec_channel src
[4];
2621 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2622 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2623 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2624 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
2625 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
2628 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2629 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2630 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2636 exec_dp3(struct tgsi_exec_machine
*mach
,
2637 const struct tgsi_full_instruction
*inst
)
2640 union tgsi_exec_channel arg
[3];
2642 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2643 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2644 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2646 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
2647 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2648 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2649 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2652 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2653 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2654 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2660 exec_dp4(struct tgsi_exec_machine
*mach
,
2661 const struct tgsi_full_instruction
*inst
)
2664 union tgsi_exec_channel arg
[3];
2666 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2667 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2668 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2670 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
2671 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2672 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2673 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2676 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2677 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2678 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2684 exec_dp2a(struct tgsi_exec_machine
*mach
,
2685 const struct tgsi_full_instruction
*inst
)
2688 union tgsi_exec_channel arg
[3];
2690 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2691 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2692 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2694 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2695 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2696 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
2698 fetch_source(mach
, &arg
[1], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2699 micro_add(&arg
[0], &arg
[0], &arg
[1]);
2701 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2702 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2703 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2709 exec_dph(struct tgsi_exec_machine
*mach
,
2710 const struct tgsi_full_instruction
*inst
)
2713 union tgsi_exec_channel arg
[3];
2715 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2716 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2717 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2719 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2720 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2721 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2723 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2724 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2725 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
2727 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2728 micro_add(&arg
[0], &arg
[0], &arg
[1]);
2730 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2731 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2732 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2738 exec_dp2(struct tgsi_exec_machine
*mach
,
2739 const struct tgsi_full_instruction
*inst
)
2742 union tgsi_exec_channel arg
[3];
2744 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2745 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2746 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2748 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2749 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2750 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2752 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2753 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2754 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2760 exec_scs(struct tgsi_exec_machine
*mach
,
2761 const struct tgsi_full_instruction
*inst
)
2763 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
2764 union tgsi_exec_channel arg
;
2765 union tgsi_exec_channel result
;
2767 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2769 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2770 micro_cos(&result
, &arg
);
2771 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2773 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2774 micro_sin(&result
, &arg
);
2775 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2778 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2779 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2781 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2782 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2787 exec_x2d(struct tgsi_exec_machine
*mach
,
2788 const struct tgsi_full_instruction
*inst
)
2790 union tgsi_exec_channel r
[4];
2791 union tgsi_exec_channel d
[2];
2793 fetch_source(mach
, &r
[0], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2794 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2795 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XZ
) {
2796 fetch_source(mach
, &r
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2797 micro_mul(&r
[2], &r
[2], &r
[0]);
2798 fetch_source(mach
, &r
[3], &inst
->Src
[2], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2799 micro_mul(&r
[3], &r
[3], &r
[1]);
2800 micro_add(&r
[2], &r
[2], &r
[3]);
2801 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2802 micro_add(&d
[0], &r
[2], &r
[3]);
2804 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YW
) {
2805 fetch_source(mach
, &r
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2806 micro_mul(&r
[2], &r
[2], &r
[0]);
2807 fetch_source(mach
, &r
[3], &inst
->Src
[2], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2808 micro_mul(&r
[3], &r
[3], &r
[1]);
2809 micro_add(&r
[2], &r
[2], &r
[3]);
2810 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2811 micro_add(&d
[1], &r
[2], &r
[3]);
2813 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2814 store_dest(mach
, &d
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2816 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2817 store_dest(mach
, &d
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2819 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2820 store_dest(mach
, &d
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2822 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2823 store_dest(mach
, &d
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2828 exec_rfl(struct tgsi_exec_machine
*mach
,
2829 const struct tgsi_full_instruction
*inst
)
2831 union tgsi_exec_channel r
[9];
2833 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
2834 /* r0 = dp3(src0, src0) */
2835 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2836 micro_mul(&r
[0], &r
[2], &r
[2]);
2837 fetch_source(mach
, &r
[4], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2838 micro_mul(&r
[8], &r
[4], &r
[4]);
2839 micro_add(&r
[0], &r
[0], &r
[8]);
2840 fetch_source(mach
, &r
[6], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2841 micro_mul(&r
[8], &r
[6], &r
[6]);
2842 micro_add(&r
[0], &r
[0], &r
[8]);
2844 /* r1 = dp3(src0, src1) */
2845 fetch_source(mach
, &r
[3], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2846 micro_mul(&r
[1], &r
[2], &r
[3]);
2847 fetch_source(mach
, &r
[5], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2848 micro_mul(&r
[8], &r
[4], &r
[5]);
2849 micro_add(&r
[1], &r
[1], &r
[8]);
2850 fetch_source(mach
, &r
[7], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2851 micro_mul(&r
[8], &r
[6], &r
[7]);
2852 micro_add(&r
[1], &r
[1], &r
[8]);
2854 /* r1 = 2 * r1 / r0 */
2855 micro_add(&r
[1], &r
[1], &r
[1]);
2856 micro_div(&r
[1], &r
[1], &r
[0]);
2858 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2859 micro_mul(&r
[2], &r
[2], &r
[1]);
2860 micro_sub(&r
[2], &r
[2], &r
[3]);
2861 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2863 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2864 micro_mul(&r
[4], &r
[4], &r
[1]);
2865 micro_sub(&r
[4], &r
[4], &r
[5]);
2866 store_dest(mach
, &r
[4], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2868 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2869 micro_mul(&r
[6], &r
[6], &r
[1]);
2870 micro_sub(&r
[6], &r
[6], &r
[7]);
2871 store_dest(mach
, &r
[6], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2874 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2875 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2880 exec_xpd(struct tgsi_exec_machine
*mach
,
2881 const struct tgsi_full_instruction
*inst
)
2883 union tgsi_exec_channel r
[6];
2884 union tgsi_exec_channel d
[3];
2886 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2887 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2889 micro_mul(&r
[2], &r
[0], &r
[1]);
2891 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2892 fetch_source(mach
, &r
[4], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2894 micro_mul(&r
[5], &r
[3], &r
[4] );
2895 micro_sub(&d
[TGSI_CHAN_X
], &r
[2], &r
[5]);
2897 fetch_source(mach
, &r
[2], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2899 micro_mul(&r
[3], &r
[3], &r
[2]);
2901 fetch_source(mach
, &r
[5], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2903 micro_mul(&r
[1], &r
[1], &r
[5]);
2904 micro_sub(&d
[TGSI_CHAN_Y
], &r
[3], &r
[1]);
2906 micro_mul(&r
[5], &r
[5], &r
[4]);
2907 micro_mul(&r
[0], &r
[0], &r
[2]);
2908 micro_sub(&d
[TGSI_CHAN_Z
], &r
[5], &r
[0]);
2910 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2911 store_dest(mach
, &d
[TGSI_CHAN_X
], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2913 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2914 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2916 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2917 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2919 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2920 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2925 exec_dst(struct tgsi_exec_machine
*mach
,
2926 const struct tgsi_full_instruction
*inst
)
2928 union tgsi_exec_channel r
[2];
2929 union tgsi_exec_channel d
[4];
2931 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2932 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2933 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2934 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
2936 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2937 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2939 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2940 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2943 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2944 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2946 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2947 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2949 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2950 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2952 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2953 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2958 exec_log(struct tgsi_exec_machine
*mach
,
2959 const struct tgsi_full_instruction
*inst
)
2961 union tgsi_exec_channel r
[3];
2963 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2964 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
2965 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
2966 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
2967 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2968 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2970 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2971 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
2972 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
2973 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2975 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2976 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2978 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2979 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2984 exec_exp(struct tgsi_exec_machine
*mach
,
2985 const struct tgsi_full_instruction
*inst
)
2987 union tgsi_exec_channel r
[3];
2989 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2990 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
2991 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2992 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
2993 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2995 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2996 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
2997 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2999 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3000 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3001 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3003 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3004 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3009 exec_lit(struct tgsi_exec_machine
*mach
,
3010 const struct tgsi_full_instruction
*inst
)
3012 union tgsi_exec_channel r
[3];
3013 union tgsi_exec_channel d
[3];
3015 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3016 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3017 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3018 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3019 micro_max(&r
[1], &r
[1], &ZeroVec
);
3021 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3022 micro_min(&r
[2], &r
[2], &P128Vec
);
3023 micro_max(&r
[2], &r
[2], &M128Vec
);
3024 micro_pow(&r
[1], &r
[1], &r
[2]);
3025 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3026 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3028 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3029 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3030 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3033 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3034 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3037 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3038 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3043 exec_break(struct tgsi_exec_machine
*mach
)
3045 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3046 /* turn off loop channels for each enabled exec channel */
3047 mach
->LoopMask
&= ~mach
->ExecMask
;
3048 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3049 UPDATE_EXEC_MASK(mach
);
3051 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3053 mach
->Switch
.mask
= 0x0;
3055 UPDATE_EXEC_MASK(mach
);
3060 exec_switch(struct tgsi_exec_machine
*mach
,
3061 const struct tgsi_full_instruction
*inst
)
3063 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3064 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3066 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3067 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3068 mach
->Switch
.mask
= 0x0;
3069 mach
->Switch
.defaultMask
= 0x0;
3071 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3072 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3074 UPDATE_EXEC_MASK(mach
);
3078 exec_case(struct tgsi_exec_machine
*mach
,
3079 const struct tgsi_full_instruction
*inst
)
3081 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3082 union tgsi_exec_channel src
;
3085 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3087 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3090 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3093 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3096 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3100 mach
->Switch
.defaultMask
|= mask
;
3102 mach
->Switch
.mask
|= mask
& prevMask
;
3104 UPDATE_EXEC_MASK(mach
);
3107 /* FIXME: this will only work if default is last */
3109 exec_default(struct tgsi_exec_machine
*mach
)
3111 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3113 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3115 UPDATE_EXEC_MASK(mach
);
3119 exec_endswitch(struct tgsi_exec_machine
*mach
)
3121 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3122 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3124 UPDATE_EXEC_MASK(mach
);
3128 micro_i2f(union tgsi_exec_channel
*dst
,
3129 const union tgsi_exec_channel
*src
)
3131 dst
->f
[0] = (float)src
->i
[0];
3132 dst
->f
[1] = (float)src
->i
[1];
3133 dst
->f
[2] = (float)src
->i
[2];
3134 dst
->f
[3] = (float)src
->i
[3];
3138 micro_not(union tgsi_exec_channel
*dst
,
3139 const union tgsi_exec_channel
*src
)
3141 dst
->u
[0] = ~src
->u
[0];
3142 dst
->u
[1] = ~src
->u
[1];
3143 dst
->u
[2] = ~src
->u
[2];
3144 dst
->u
[3] = ~src
->u
[3];
3148 micro_shl(union tgsi_exec_channel
*dst
,
3149 const union tgsi_exec_channel
*src0
,
3150 const union tgsi_exec_channel
*src1
)
3152 unsigned masked_count
;
3153 masked_count
= src1
->u
[0] & 0x1f;
3154 dst
->u
[0] = src0
->u
[0] << masked_count
;
3155 masked_count
= src1
->u
[1] & 0x1f;
3156 dst
->u
[1] = src0
->u
[1] << masked_count
;
3157 masked_count
= src1
->u
[2] & 0x1f;
3158 dst
->u
[2] = src0
->u
[2] << masked_count
;
3159 masked_count
= src1
->u
[3] & 0x1f;
3160 dst
->u
[3] = src0
->u
[3] << masked_count
;
3164 micro_and(union tgsi_exec_channel
*dst
,
3165 const union tgsi_exec_channel
*src0
,
3166 const union tgsi_exec_channel
*src1
)
3168 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
3169 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
3170 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
3171 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
3175 micro_or(union tgsi_exec_channel
*dst
,
3176 const union tgsi_exec_channel
*src0
,
3177 const union tgsi_exec_channel
*src1
)
3179 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
3180 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
3181 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
3182 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
3186 micro_xor(union tgsi_exec_channel
*dst
,
3187 const union tgsi_exec_channel
*src0
,
3188 const union tgsi_exec_channel
*src1
)
3190 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
3191 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
3192 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
3193 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
3197 micro_mod(union tgsi_exec_channel
*dst
,
3198 const union tgsi_exec_channel
*src0
,
3199 const union tgsi_exec_channel
*src1
)
3201 dst
->i
[0] = src0
->i
[0] % src1
->i
[0];
3202 dst
->i
[1] = src0
->i
[1] % src1
->i
[1];
3203 dst
->i
[2] = src0
->i
[2] % src1
->i
[2];
3204 dst
->i
[3] = src0
->i
[3] % src1
->i
[3];
3208 micro_f2i(union tgsi_exec_channel
*dst
,
3209 const union tgsi_exec_channel
*src
)
3211 dst
->i
[0] = (int)src
->f
[0];
3212 dst
->i
[1] = (int)src
->f
[1];
3213 dst
->i
[2] = (int)src
->f
[2];
3214 dst
->i
[3] = (int)src
->f
[3];
3218 micro_fseq(union tgsi_exec_channel
*dst
,
3219 const union tgsi_exec_channel
*src0
,
3220 const union tgsi_exec_channel
*src1
)
3222 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
3223 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
3224 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
3225 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
3229 micro_fsge(union tgsi_exec_channel
*dst
,
3230 const union tgsi_exec_channel
*src0
,
3231 const union tgsi_exec_channel
*src1
)
3233 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
3234 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
3235 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
3236 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
3240 micro_fslt(union tgsi_exec_channel
*dst
,
3241 const union tgsi_exec_channel
*src0
,
3242 const union tgsi_exec_channel
*src1
)
3244 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
3245 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
3246 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
3247 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
3251 micro_fsne(union tgsi_exec_channel
*dst
,
3252 const union tgsi_exec_channel
*src0
,
3253 const union tgsi_exec_channel
*src1
)
3255 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
3256 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
3257 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
3258 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
3262 micro_idiv(union tgsi_exec_channel
*dst
,
3263 const union tgsi_exec_channel
*src0
,
3264 const union tgsi_exec_channel
*src1
)
3266 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
3267 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
3268 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
3269 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
3273 micro_imax(union tgsi_exec_channel
*dst
,
3274 const union tgsi_exec_channel
*src0
,
3275 const union tgsi_exec_channel
*src1
)
3277 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
3278 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
3279 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
3280 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
3284 micro_imin(union tgsi_exec_channel
*dst
,
3285 const union tgsi_exec_channel
*src0
,
3286 const union tgsi_exec_channel
*src1
)
3288 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
3289 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
3290 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
3291 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
3295 micro_isge(union tgsi_exec_channel
*dst
,
3296 const union tgsi_exec_channel
*src0
,
3297 const union tgsi_exec_channel
*src1
)
3299 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
3300 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
3301 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
3302 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
3306 micro_ishr(union tgsi_exec_channel
*dst
,
3307 const union tgsi_exec_channel
*src0
,
3308 const union tgsi_exec_channel
*src1
)
3310 unsigned masked_count
;
3311 masked_count
= src1
->i
[0] & 0x1f;
3312 dst
->i
[0] = src0
->i
[0] >> masked_count
;
3313 masked_count
= src1
->i
[1] & 0x1f;
3314 dst
->i
[1] = src0
->i
[1] >> masked_count
;
3315 masked_count
= src1
->i
[2] & 0x1f;
3316 dst
->i
[2] = src0
->i
[2] >> masked_count
;
3317 masked_count
= src1
->i
[3] & 0x1f;
3318 dst
->i
[3] = src0
->i
[3] >> masked_count
;
3322 micro_islt(union tgsi_exec_channel
*dst
,
3323 const union tgsi_exec_channel
*src0
,
3324 const union tgsi_exec_channel
*src1
)
3326 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
3327 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
3328 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
3329 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
3333 micro_f2u(union tgsi_exec_channel
*dst
,
3334 const union tgsi_exec_channel
*src
)
3336 dst
->u
[0] = (uint
)src
->f
[0];
3337 dst
->u
[1] = (uint
)src
->f
[1];
3338 dst
->u
[2] = (uint
)src
->f
[2];
3339 dst
->u
[3] = (uint
)src
->f
[3];
3343 micro_u2f(union tgsi_exec_channel
*dst
,
3344 const union tgsi_exec_channel
*src
)
3346 dst
->f
[0] = (float)src
->u
[0];
3347 dst
->f
[1] = (float)src
->u
[1];
3348 dst
->f
[2] = (float)src
->u
[2];
3349 dst
->f
[3] = (float)src
->u
[3];
3353 micro_uadd(union tgsi_exec_channel
*dst
,
3354 const union tgsi_exec_channel
*src0
,
3355 const union tgsi_exec_channel
*src1
)
3357 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
3358 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
3359 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
3360 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
3364 micro_udiv(union tgsi_exec_channel
*dst
,
3365 const union tgsi_exec_channel
*src0
,
3366 const union tgsi_exec_channel
*src1
)
3368 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
3369 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
3370 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
3371 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
3375 micro_umad(union tgsi_exec_channel
*dst
,
3376 const union tgsi_exec_channel
*src0
,
3377 const union tgsi_exec_channel
*src1
,
3378 const union tgsi_exec_channel
*src2
)
3380 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
3381 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
3382 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
3383 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
3387 micro_umax(union tgsi_exec_channel
*dst
,
3388 const union tgsi_exec_channel
*src0
,
3389 const union tgsi_exec_channel
*src1
)
3391 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
3392 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
3393 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
3394 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
3398 micro_umin(union tgsi_exec_channel
*dst
,
3399 const union tgsi_exec_channel
*src0
,
3400 const union tgsi_exec_channel
*src1
)
3402 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
3403 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
3404 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
3405 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
3409 micro_umod(union tgsi_exec_channel
*dst
,
3410 const union tgsi_exec_channel
*src0
,
3411 const union tgsi_exec_channel
*src1
)
3413 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
3414 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
3415 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
3416 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
3420 micro_umul(union tgsi_exec_channel
*dst
,
3421 const union tgsi_exec_channel
*src0
,
3422 const union tgsi_exec_channel
*src1
)
3424 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
3425 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
3426 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
3427 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
3431 micro_imul_hi(union tgsi_exec_channel
*dst
,
3432 const union tgsi_exec_channel
*src0
,
3433 const union tgsi_exec_channel
*src1
)
3435 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3436 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
3437 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
3438 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
3439 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
3444 micro_umul_hi(union tgsi_exec_channel
*dst
,
3445 const union tgsi_exec_channel
*src0
,
3446 const union tgsi_exec_channel
*src1
)
3448 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3449 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
3450 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
3451 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
3452 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
3457 micro_useq(union tgsi_exec_channel
*dst
,
3458 const union tgsi_exec_channel
*src0
,
3459 const union tgsi_exec_channel
*src1
)
3461 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
3462 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
3463 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
3464 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
3468 micro_usge(union tgsi_exec_channel
*dst
,
3469 const union tgsi_exec_channel
*src0
,
3470 const union tgsi_exec_channel
*src1
)
3472 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
3473 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
3474 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
3475 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
3479 micro_ushr(union tgsi_exec_channel
*dst
,
3480 const union tgsi_exec_channel
*src0
,
3481 const union tgsi_exec_channel
*src1
)
3483 unsigned masked_count
;
3484 masked_count
= src1
->u
[0] & 0x1f;
3485 dst
->u
[0] = src0
->u
[0] >> masked_count
;
3486 masked_count
= src1
->u
[1] & 0x1f;
3487 dst
->u
[1] = src0
->u
[1] >> masked_count
;
3488 masked_count
= src1
->u
[2] & 0x1f;
3489 dst
->u
[2] = src0
->u
[2] >> masked_count
;
3490 masked_count
= src1
->u
[3] & 0x1f;
3491 dst
->u
[3] = src0
->u
[3] >> masked_count
;
3495 micro_uslt(union tgsi_exec_channel
*dst
,
3496 const union tgsi_exec_channel
*src0
,
3497 const union tgsi_exec_channel
*src1
)
3499 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
3500 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
3501 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
3502 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
3506 micro_usne(union tgsi_exec_channel
*dst
,
3507 const union tgsi_exec_channel
*src0
,
3508 const union tgsi_exec_channel
*src1
)
3510 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
3511 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
3512 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
3513 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
3517 micro_uarl(union tgsi_exec_channel
*dst
,
3518 const union tgsi_exec_channel
*src
)
3520 dst
->i
[0] = src
->u
[0];
3521 dst
->i
[1] = src
->u
[1];
3522 dst
->i
[2] = src
->u
[2];
3523 dst
->i
[3] = src
->u
[3];
3527 micro_ucmp(union tgsi_exec_channel
*dst
,
3528 const union tgsi_exec_channel
*src0
,
3529 const union tgsi_exec_channel
*src1
,
3530 const union tgsi_exec_channel
*src2
)
3532 dst
->u
[0] = src0
->u
[0] ? src1
->u
[0] : src2
->u
[0];
3533 dst
->u
[1] = src0
->u
[1] ? src1
->u
[1] : src2
->u
[1];
3534 dst
->u
[2] = src0
->u
[2] ? src1
->u
[2] : src2
->u
[2];
3535 dst
->u
[3] = src0
->u
[3] ? src1
->u
[3] : src2
->u
[3];
3539 * Signed bitfield extract (i.e. sign-extend the extracted bits)
3542 micro_ibfe(union tgsi_exec_channel
*dst
,
3543 const union tgsi_exec_channel
*src0
,
3544 const union tgsi_exec_channel
*src1
,
3545 const union tgsi_exec_channel
*src2
)
3548 for (i
= 0; i
< 4; i
++) {
3549 int width
= src2
->i
[i
] & 0x1f;
3550 int offset
= src1
->i
[i
] & 0x1f;
3553 else if (width
+ offset
< 32)
3554 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
3556 dst
->i
[i
] = src0
->i
[i
] >> offset
;
3561 * Unsigned bitfield extract
3564 micro_ubfe(union tgsi_exec_channel
*dst
,
3565 const union tgsi_exec_channel
*src0
,
3566 const union tgsi_exec_channel
*src1
,
3567 const union tgsi_exec_channel
*src2
)
3570 for (i
= 0; i
< 4; i
++) {
3571 int width
= src2
->u
[i
] & 0x1f;
3572 int offset
= src1
->u
[i
] & 0x1f;
3575 else if (width
+ offset
< 32)
3576 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
3578 dst
->u
[i
] = src0
->u
[i
] >> offset
;
3583 * Bitfield insert: copy low bits from src1 into a region of src0.
3586 micro_bfi(union tgsi_exec_channel
*dst
,
3587 const union tgsi_exec_channel
*src0
,
3588 const union tgsi_exec_channel
*src1
,
3589 const union tgsi_exec_channel
*src2
,
3590 const union tgsi_exec_channel
*src3
)
3593 for (i
= 0; i
< 4; i
++) {
3594 int width
= src3
->u
[i
] & 0x1f;
3595 int offset
= src2
->u
[i
] & 0x1f;
3596 int bitmask
= ((1 << width
) - 1) << offset
;
3597 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
3602 micro_brev(union tgsi_exec_channel
*dst
,
3603 const union tgsi_exec_channel
*src
)
3605 dst
->u
[0] = util_bitreverse(src
->u
[0]);
3606 dst
->u
[1] = util_bitreverse(src
->u
[1]);
3607 dst
->u
[2] = util_bitreverse(src
->u
[2]);
3608 dst
->u
[3] = util_bitreverse(src
->u
[3]);
3612 micro_popc(union tgsi_exec_channel
*dst
,
3613 const union tgsi_exec_channel
*src
)
3615 dst
->u
[0] = util_bitcount(src
->u
[0]);
3616 dst
->u
[1] = util_bitcount(src
->u
[1]);
3617 dst
->u
[2] = util_bitcount(src
->u
[2]);
3618 dst
->u
[3] = util_bitcount(src
->u
[3]);
3622 micro_lsb(union tgsi_exec_channel
*dst
,
3623 const union tgsi_exec_channel
*src
)
3625 dst
->i
[0] = ffs(src
->u
[0]) - 1;
3626 dst
->i
[1] = ffs(src
->u
[1]) - 1;
3627 dst
->i
[2] = ffs(src
->u
[2]) - 1;
3628 dst
->i
[3] = ffs(src
->u
[3]) - 1;
3632 micro_imsb(union tgsi_exec_channel
*dst
,
3633 const union tgsi_exec_channel
*src
)
3635 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
3636 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
3637 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
3638 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
3642 micro_umsb(union tgsi_exec_channel
*dst
,
3643 const union tgsi_exec_channel
*src
)
3645 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
3646 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
3647 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
3648 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
3653 struct tgsi_exec_machine
*mach
,
3654 const struct tgsi_full_instruction
*inst
,
3657 union tgsi_exec_channel r
[10];
3661 switch (inst
->Instruction
.Opcode
) {
3662 case TGSI_OPCODE_ARL
:
3663 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
3666 case TGSI_OPCODE_MOV
:
3667 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
3670 case TGSI_OPCODE_LIT
:
3671 exec_lit(mach
, inst
);
3674 case TGSI_OPCODE_RCP
:
3675 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3678 case TGSI_OPCODE_RSQ
:
3679 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3682 case TGSI_OPCODE_EXP
:
3683 exec_exp(mach
, inst
);
3686 case TGSI_OPCODE_LOG
:
3687 exec_log(mach
, inst
);
3690 case TGSI_OPCODE_MUL
:
3691 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3694 case TGSI_OPCODE_ADD
:
3695 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3698 case TGSI_OPCODE_DP3
:
3699 exec_dp3(mach
, inst
);
3702 case TGSI_OPCODE_DP4
:
3703 exec_dp4(mach
, inst
);
3706 case TGSI_OPCODE_DST
:
3707 exec_dst(mach
, inst
);
3710 case TGSI_OPCODE_MIN
:
3711 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3714 case TGSI_OPCODE_MAX
:
3715 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3718 case TGSI_OPCODE_SLT
:
3719 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3722 case TGSI_OPCODE_SGE
:
3723 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3726 case TGSI_OPCODE_MAD
:
3727 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3730 case TGSI_OPCODE_SUB
:
3731 exec_vector_binary(mach
, inst
, micro_sub
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3734 case TGSI_OPCODE_LRP
:
3735 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3738 case TGSI_OPCODE_CND
:
3739 exec_vector_trinary(mach
, inst
, micro_cnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3742 case TGSI_OPCODE_SQRT
:
3743 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3746 case TGSI_OPCODE_DP2A
:
3747 exec_dp2a(mach
, inst
);
3750 case TGSI_OPCODE_FRC
:
3751 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3754 case TGSI_OPCODE_CLAMP
:
3755 exec_vector_trinary(mach
, inst
, micro_clamp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3758 case TGSI_OPCODE_FLR
:
3759 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3762 case TGSI_OPCODE_ROUND
:
3763 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3766 case TGSI_OPCODE_EX2
:
3767 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3770 case TGSI_OPCODE_LG2
:
3771 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3774 case TGSI_OPCODE_POW
:
3775 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3778 case TGSI_OPCODE_XPD
:
3779 exec_xpd(mach
, inst
);
3782 case TGSI_OPCODE_ABS
:
3783 exec_vector_unary(mach
, inst
, micro_abs
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3786 case TGSI_OPCODE_DPH
:
3787 exec_dph(mach
, inst
);
3790 case TGSI_OPCODE_COS
:
3791 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3794 case TGSI_OPCODE_DDX
:
3795 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3798 case TGSI_OPCODE_DDY
:
3799 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3802 case TGSI_OPCODE_KILL
:
3803 exec_kill (mach
, inst
);
3806 case TGSI_OPCODE_KILL_IF
:
3807 exec_kill_if (mach
, inst
);
3810 case TGSI_OPCODE_PK2H
:
3814 case TGSI_OPCODE_PK2US
:
3818 case TGSI_OPCODE_PK4B
:
3822 case TGSI_OPCODE_PK4UB
:
3826 case TGSI_OPCODE_RFL
:
3827 exec_rfl(mach
, inst
);
3830 case TGSI_OPCODE_SEQ
:
3831 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3834 case TGSI_OPCODE_SFL
:
3835 exec_vector(mach
, inst
, micro_sfl
, TGSI_EXEC_DATA_FLOAT
);
3838 case TGSI_OPCODE_SGT
:
3839 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3842 case TGSI_OPCODE_SIN
:
3843 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3846 case TGSI_OPCODE_SLE
:
3847 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3850 case TGSI_OPCODE_SNE
:
3851 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3854 case TGSI_OPCODE_STR
:
3855 exec_vector(mach
, inst
, micro_str
, TGSI_EXEC_DATA_FLOAT
);
3858 case TGSI_OPCODE_TEX
:
3859 /* simple texture lookup */
3860 /* src[0] = texcoord */
3861 /* src[1] = sampler unit */
3862 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
3865 case TGSI_OPCODE_TXB
:
3866 /* Texture lookup with lod bias */
3867 /* src[0] = texcoord (src[0].w = LOD bias) */
3868 /* src[1] = sampler unit */
3869 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
3872 case TGSI_OPCODE_TXD
:
3873 /* Texture lookup with explict partial derivatives */
3874 /* src[0] = texcoord */
3875 /* src[1] = d[strq]/dx */
3876 /* src[2] = d[strq]/dy */
3877 /* src[3] = sampler unit */
3878 exec_txd(mach
, inst
);
3881 case TGSI_OPCODE_TXL
:
3882 /* Texture lookup with explit LOD */
3883 /* src[0] = texcoord (src[0].w = LOD) */
3884 /* src[1] = sampler unit */
3885 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
3888 case TGSI_OPCODE_TXP
:
3889 /* Texture lookup with projection */
3890 /* src[0] = texcoord (src[0].w = projection) */
3891 /* src[1] = sampler unit */
3892 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
3895 case TGSI_OPCODE_UP2H
:
3899 case TGSI_OPCODE_UP2US
:
3903 case TGSI_OPCODE_UP4B
:
3907 case TGSI_OPCODE_UP4UB
:
3911 case TGSI_OPCODE_X2D
:
3912 exec_x2d(mach
, inst
);
3915 case TGSI_OPCODE_ARR
:
3916 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
3919 case TGSI_OPCODE_BRA
:
3923 case TGSI_OPCODE_CAL
:
3924 /* skip the call if no execution channels are enabled */
3925 if (mach
->ExecMask
) {
3928 /* First, record the depths of the execution stacks.
3929 * This is important for deeply nested/looped return statements.
3930 * We have to unwind the stacks by the correct amount. For a
3931 * real code generator, we could determine the number of entries
3932 * to pop off each stack with simple static analysis and avoid
3933 * implementing this data structure at run time.
3935 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
3936 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
3937 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
3938 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
3939 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
3940 /* note that PC was already incremented above */
3941 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
3943 mach
->CallStackTop
++;
3945 /* Second, push the Cond, Loop, Cont, Func stacks */
3946 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
3947 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3948 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3949 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3950 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3951 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
3953 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
3954 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
3955 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
3956 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3957 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3958 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
3960 /* Finally, jump to the subroutine */
3961 *pc
= inst
->Label
.Label
;
3965 case TGSI_OPCODE_RET
:
3966 mach
->FuncMask
&= ~mach
->ExecMask
;
3967 UPDATE_EXEC_MASK(mach
);
3969 if (mach
->FuncMask
== 0x0) {
3970 /* really return now (otherwise, keep executing */
3972 if (mach
->CallStackTop
== 0) {
3973 /* returning from main() */
3974 mach
->CondStackTop
= 0;
3975 mach
->LoopStackTop
= 0;
3980 assert(mach
->CallStackTop
> 0);
3981 mach
->CallStackTop
--;
3983 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
3984 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
3986 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
3987 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
3989 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
3990 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
3992 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
3993 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
3995 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
3996 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
3998 assert(mach
->FuncStackTop
> 0);
3999 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
4001 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
4003 UPDATE_EXEC_MASK(mach
);
4007 case TGSI_OPCODE_SSG
:
4008 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4011 case TGSI_OPCODE_CMP
:
4012 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4015 case TGSI_OPCODE_SCS
:
4016 exec_scs(mach
, inst
);
4019 case TGSI_OPCODE_DIV
:
4020 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4023 case TGSI_OPCODE_DP2
:
4024 exec_dp2(mach
, inst
);
4027 case TGSI_OPCODE_IF
:
4029 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
4030 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
4031 FETCH( &r
[0], 0, TGSI_CHAN_X
);
4032 /* update CondMask */
4034 mach
->CondMask
&= ~0x1;
4037 mach
->CondMask
&= ~0x2;
4040 mach
->CondMask
&= ~0x4;
4043 mach
->CondMask
&= ~0x8;
4045 UPDATE_EXEC_MASK(mach
);
4046 /* Todo: If CondMask==0, jump to ELSE */
4049 case TGSI_OPCODE_UIF
:
4051 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
4052 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
4053 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
4054 /* update CondMask */
4056 mach
->CondMask
&= ~0x1;
4059 mach
->CondMask
&= ~0x2;
4062 mach
->CondMask
&= ~0x4;
4065 mach
->CondMask
&= ~0x8;
4067 UPDATE_EXEC_MASK(mach
);
4068 /* Todo: If CondMask==0, jump to ELSE */
4071 case TGSI_OPCODE_ELSE
:
4072 /* invert CondMask wrt previous mask */
4075 assert(mach
->CondStackTop
> 0);
4076 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
4077 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
4078 UPDATE_EXEC_MASK(mach
);
4079 /* Todo: If CondMask==0, jump to ENDIF */
4083 case TGSI_OPCODE_ENDIF
:
4085 assert(mach
->CondStackTop
> 0);
4086 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
4087 UPDATE_EXEC_MASK(mach
);
4090 case TGSI_OPCODE_END
:
4091 /* make sure we end primitives which haven't
4092 * been explicitly emitted */
4093 conditional_emit_primitive(mach
);
4094 /* halt execution */
4098 case TGSI_OPCODE_PUSHA
:
4102 case TGSI_OPCODE_POPA
:
4106 case TGSI_OPCODE_CEIL
:
4107 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4110 case TGSI_OPCODE_I2F
:
4111 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
4114 case TGSI_OPCODE_NOT
:
4115 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4118 case TGSI_OPCODE_TRUNC
:
4119 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4122 case TGSI_OPCODE_SHL
:
4123 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4126 case TGSI_OPCODE_AND
:
4127 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4130 case TGSI_OPCODE_OR
:
4131 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4134 case TGSI_OPCODE_MOD
:
4135 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4138 case TGSI_OPCODE_XOR
:
4139 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4142 case TGSI_OPCODE_SAD
:
4146 case TGSI_OPCODE_TXF
:
4147 exec_txf(mach
, inst
);
4150 case TGSI_OPCODE_TXQ
:
4151 exec_txq(mach
, inst
);
4154 case TGSI_OPCODE_EMIT
:
4158 case TGSI_OPCODE_ENDPRIM
:
4159 emit_primitive(mach
);
4162 case TGSI_OPCODE_BGNLOOP
:
4163 /* push LoopMask and ContMasks */
4164 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4165 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4166 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4167 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
4169 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
4170 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
4171 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
4172 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
4173 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
4176 case TGSI_OPCODE_ENDLOOP
:
4177 /* Restore ContMask, but don't pop */
4178 assert(mach
->ContStackTop
> 0);
4179 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
4180 UPDATE_EXEC_MASK(mach
);
4181 if (mach
->ExecMask
) {
4182 /* repeat loop: jump to instruction just past BGNLOOP */
4183 assert(mach
->LoopLabelStackTop
> 0);
4184 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
4187 /* exit loop: pop LoopMask */
4188 assert(mach
->LoopStackTop
> 0);
4189 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
4191 assert(mach
->ContStackTop
> 0);
4192 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
4193 assert(mach
->LoopLabelStackTop
> 0);
4194 --mach
->LoopLabelStackTop
;
4196 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
4198 UPDATE_EXEC_MASK(mach
);
4201 case TGSI_OPCODE_BRK
:
4205 case TGSI_OPCODE_CONT
:
4206 /* turn off cont channels for each enabled exec channel */
4207 mach
->ContMask
&= ~mach
->ExecMask
;
4208 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4209 UPDATE_EXEC_MASK(mach
);
4212 case TGSI_OPCODE_BGNSUB
:
4216 case TGSI_OPCODE_ENDSUB
:
4218 * XXX: This really should be a no-op. We should never reach this opcode.
4221 assert(mach
->CallStackTop
> 0);
4222 mach
->CallStackTop
--;
4224 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
4225 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
4227 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
4228 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
4230 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
4231 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
4233 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
4234 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
4236 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
4237 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
4239 assert(mach
->FuncStackTop
> 0);
4240 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
4242 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
4244 UPDATE_EXEC_MASK(mach
);
4247 case TGSI_OPCODE_NOP
:
4250 case TGSI_OPCODE_BREAKC
:
4251 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4252 /* update CondMask */
4253 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
4254 mach
->LoopMask
&= ~0x1;
4256 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
4257 mach
->LoopMask
&= ~0x2;
4259 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
4260 mach
->LoopMask
&= ~0x4;
4262 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
4263 mach
->LoopMask
&= ~0x8;
4265 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4266 UPDATE_EXEC_MASK(mach
);
4269 case TGSI_OPCODE_F2I
:
4270 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4273 case TGSI_OPCODE_FSEQ
:
4274 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4277 case TGSI_OPCODE_FSGE
:
4278 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4281 case TGSI_OPCODE_FSLT
:
4282 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4285 case TGSI_OPCODE_FSNE
:
4286 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4289 case TGSI_OPCODE_IDIV
:
4290 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4293 case TGSI_OPCODE_IMAX
:
4294 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4297 case TGSI_OPCODE_IMIN
:
4298 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4301 case TGSI_OPCODE_INEG
:
4302 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4305 case TGSI_OPCODE_ISGE
:
4306 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4309 case TGSI_OPCODE_ISHR
:
4310 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4313 case TGSI_OPCODE_ISLT
:
4314 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4317 case TGSI_OPCODE_F2U
:
4318 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4321 case TGSI_OPCODE_U2F
:
4322 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
4325 case TGSI_OPCODE_UADD
:
4326 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4329 case TGSI_OPCODE_UDIV
:
4330 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4333 case TGSI_OPCODE_UMAD
:
4334 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4337 case TGSI_OPCODE_UMAX
:
4338 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4341 case TGSI_OPCODE_UMIN
:
4342 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4345 case TGSI_OPCODE_UMOD
:
4346 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4349 case TGSI_OPCODE_UMUL
:
4350 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4353 case TGSI_OPCODE_IMUL_HI
:
4354 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4357 case TGSI_OPCODE_UMUL_HI
:
4358 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4361 case TGSI_OPCODE_USEQ
:
4362 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4365 case TGSI_OPCODE_USGE
:
4366 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4369 case TGSI_OPCODE_USHR
:
4370 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4373 case TGSI_OPCODE_USLT
:
4374 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4377 case TGSI_OPCODE_USNE
:
4378 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4381 case TGSI_OPCODE_SWITCH
:
4382 exec_switch(mach
, inst
);
4385 case TGSI_OPCODE_CASE
:
4386 exec_case(mach
, inst
);
4389 case TGSI_OPCODE_DEFAULT
:
4393 case TGSI_OPCODE_ENDSWITCH
:
4394 exec_endswitch(mach
);
4397 case TGSI_OPCODE_SAMPLE_I
:
4398 exec_txf(mach
, inst
);
4401 case TGSI_OPCODE_SAMPLE_I_MS
:
4405 case TGSI_OPCODE_SAMPLE
:
4406 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
4409 case TGSI_OPCODE_SAMPLE_B
:
4410 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
4413 case TGSI_OPCODE_SAMPLE_C
:
4414 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
4417 case TGSI_OPCODE_SAMPLE_C_LZ
:
4418 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
4421 case TGSI_OPCODE_SAMPLE_D
:
4422 exec_sample_d(mach
, inst
);
4425 case TGSI_OPCODE_SAMPLE_L
:
4426 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
4429 case TGSI_OPCODE_GATHER4
:
4433 case TGSI_OPCODE_SVIEWINFO
:
4434 exec_txq(mach
, inst
);
4437 case TGSI_OPCODE_SAMPLE_POS
:
4441 case TGSI_OPCODE_SAMPLE_INFO
:
4445 case TGSI_OPCODE_UARL
:
4446 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
4449 case TGSI_OPCODE_UCMP
:
4450 exec_vector_trinary(mach
, inst
, micro_ucmp
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4453 case TGSI_OPCODE_IABS
:
4454 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4457 case TGSI_OPCODE_ISSG
:
4458 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4461 case TGSI_OPCODE_TEX2
:
4462 /* simple texture lookup */
4463 /* src[0] = texcoord */
4464 /* src[1] = compare */
4465 /* src[2] = sampler unit */
4466 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
4468 case TGSI_OPCODE_TXB2
:
4469 /* simple texture lookup */
4470 /* src[0] = texcoord */
4472 /* src[2] = sampler unit */
4473 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
4475 case TGSI_OPCODE_TXL2
:
4476 /* simple texture lookup */
4477 /* src[0] = texcoord */
4479 /* src[2] = sampler unit */
4480 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
4483 case TGSI_OPCODE_IBFE
:
4484 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4486 case TGSI_OPCODE_UBFE
:
4487 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4489 case TGSI_OPCODE_BFI
:
4490 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4492 case TGSI_OPCODE_BREV
:
4493 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4495 case TGSI_OPCODE_POPC
:
4496 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4498 case TGSI_OPCODE_LSB
:
4499 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
4501 case TGSI_OPCODE_IMSB
:
4502 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4504 case TGSI_OPCODE_UMSB
:
4505 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
4514 * Run TGSI interpreter.
4515 * \return bitmask of "alive" quad components
4518 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
)
4522 uint default_mask
= 0xf;
4524 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
4525 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
4527 if( mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
) {
4528 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
4529 mach
->Primitives
[0] = 0;
4530 /* GS runs on a single primitive for now */
4534 mach
->CondMask
= default_mask
;
4535 mach
->LoopMask
= default_mask
;
4536 mach
->ContMask
= default_mask
;
4537 mach
->FuncMask
= default_mask
;
4538 mach
->ExecMask
= default_mask
;
4540 mach
->Switch
.mask
= default_mask
;
4542 assert(mach
->CondStackTop
== 0);
4543 assert(mach
->LoopStackTop
== 0);
4544 assert(mach
->ContStackTop
== 0);
4545 assert(mach
->SwitchStackTop
== 0);
4546 assert(mach
->BreakStackTop
== 0);
4547 assert(mach
->CallStackTop
== 0);
4550 /* execute declarations (interpolants) */
4551 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
4552 exec_declaration( mach
, mach
->Declarations
+i
);
4557 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
4558 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
4561 memset(mach
->Temps
, 0, sizeof(temps
));
4562 memset(mach
->Outputs
, 0, sizeof(outputs
));
4563 memset(temps
, 0, sizeof(temps
));
4564 memset(outputs
, 0, sizeof(outputs
));
4567 /* execute instructions, until pc is set to -1 */
4573 tgsi_dump_instruction(&mach
->Instructions
[pc
], inst
++);
4576 assert(pc
< (int) mach
->NumInstructions
);
4577 exec_instruction(mach
, mach
->Instructions
+ pc
, &pc
);
4580 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
4581 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
4584 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
4585 debug_printf("TEMP[%2u] = ", i
);
4586 for (j
= 0; j
< 4; j
++) {
4590 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4591 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
4592 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
4593 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
4594 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
4598 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
4599 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
4602 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
4603 debug_printf("OUT[%2u] = ", i
);
4604 for (j
= 0; j
< 4; j
++) {
4608 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4609 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
4610 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
4611 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
4612 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
4621 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4622 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
4624 * Scale back depth component.
4626 for (i
= 0; i
< 4; i
++)
4627 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
4631 /* Strictly speaking, these assertions aren't really needed but they
4632 * can potentially catch some bugs in the control flow code.
4634 assert(mach
->CondStackTop
== 0);
4635 assert(mach
->LoopStackTop
== 0);
4636 assert(mach
->ContStackTop
== 0);
4637 assert(mach
->SwitchStackTop
== 0);
4638 assert(mach
->BreakStackTop
== 0);
4639 assert(mach
->CallStackTop
== 0);
4641 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];