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gallivm,tgsi: fix idiv by zero crash
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define DEBUG_EXECUTION 0
66
67
68 #define FAST_MATH 0
69
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
74
75 static void
76 micro_abs(union tgsi_exec_channel *dst,
77 const union tgsi_exec_channel *src)
78 {
79 dst->f[0] = fabsf(src->f[0]);
80 dst->f[1] = fabsf(src->f[1]);
81 dst->f[2] = fabsf(src->f[2]);
82 dst->f[3] = fabsf(src->f[3]);
83 }
84
85 static void
86 micro_arl(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
88 {
89 dst->i[0] = (int)floorf(src->f[0]);
90 dst->i[1] = (int)floorf(src->f[1]);
91 dst->i[2] = (int)floorf(src->f[2]);
92 dst->i[3] = (int)floorf(src->f[3]);
93 }
94
95 static void
96 micro_arr(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
98 {
99 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
100 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
101 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
102 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
103 }
104
105 static void
106 micro_ceil(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
108 {
109 dst->f[0] = ceilf(src->f[0]);
110 dst->f[1] = ceilf(src->f[1]);
111 dst->f[2] = ceilf(src->f[2]);
112 dst->f[3] = ceilf(src->f[3]);
113 }
114
115 static void
116 micro_clamp(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src0,
118 const union tgsi_exec_channel *src1,
119 const union tgsi_exec_channel *src2)
120 {
121 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
122 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
123 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
124 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
125 }
126
127 static void
128 micro_cmp(union tgsi_exec_channel *dst,
129 const union tgsi_exec_channel *src0,
130 const union tgsi_exec_channel *src1,
131 const union tgsi_exec_channel *src2)
132 {
133 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
134 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
135 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
136 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
137 }
138
139 static void
140 micro_cnd(union tgsi_exec_channel *dst,
141 const union tgsi_exec_channel *src0,
142 const union tgsi_exec_channel *src1,
143 const union tgsi_exec_channel *src2)
144 {
145 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
146 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
147 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
148 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
149 }
150
151 static void
152 micro_cos(union tgsi_exec_channel *dst,
153 const union tgsi_exec_channel *src)
154 {
155 dst->f[0] = cosf(src->f[0]);
156 dst->f[1] = cosf(src->f[1]);
157 dst->f[2] = cosf(src->f[2]);
158 dst->f[3] = cosf(src->f[3]);
159 }
160
161 static void
162 micro_ddx(union tgsi_exec_channel *dst,
163 const union tgsi_exec_channel *src)
164 {
165 dst->f[0] =
166 dst->f[1] =
167 dst->f[2] =
168 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
169 }
170
171 static void
172 micro_ddy(union tgsi_exec_channel *dst,
173 const union tgsi_exec_channel *src)
174 {
175 dst->f[0] =
176 dst->f[1] =
177 dst->f[2] =
178 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
179 }
180
181 static void
182 micro_exp2(union tgsi_exec_channel *dst,
183 const union tgsi_exec_channel *src)
184 {
185 #if FAST_MATH
186 dst->f[0] = util_fast_exp2(src->f[0]);
187 dst->f[1] = util_fast_exp2(src->f[1]);
188 dst->f[2] = util_fast_exp2(src->f[2]);
189 dst->f[3] = util_fast_exp2(src->f[3]);
190 #else
191 #if DEBUG
192 /* Inf is okay for this instruction, so clamp it to silence assertions. */
193 uint i;
194 union tgsi_exec_channel clamped;
195
196 for (i = 0; i < 4; i++) {
197 if (src->f[i] > 127.99999f) {
198 clamped.f[i] = 127.99999f;
199 } else if (src->f[i] < -126.99999f) {
200 clamped.f[i] = -126.99999f;
201 } else {
202 clamped.f[i] = src->f[i];
203 }
204 }
205 src = &clamped;
206 #endif /* DEBUG */
207
208 dst->f[0] = powf(2.0f, src->f[0]);
209 dst->f[1] = powf(2.0f, src->f[1]);
210 dst->f[2] = powf(2.0f, src->f[2]);
211 dst->f[3] = powf(2.0f, src->f[3]);
212 #endif /* FAST_MATH */
213 }
214
215 static void
216 micro_flr(union tgsi_exec_channel *dst,
217 const union tgsi_exec_channel *src)
218 {
219 dst->f[0] = floorf(src->f[0]);
220 dst->f[1] = floorf(src->f[1]);
221 dst->f[2] = floorf(src->f[2]);
222 dst->f[3] = floorf(src->f[3]);
223 }
224
225 static void
226 micro_frc(union tgsi_exec_channel *dst,
227 const union tgsi_exec_channel *src)
228 {
229 dst->f[0] = src->f[0] - floorf(src->f[0]);
230 dst->f[1] = src->f[1] - floorf(src->f[1]);
231 dst->f[2] = src->f[2] - floorf(src->f[2]);
232 dst->f[3] = src->f[3] - floorf(src->f[3]);
233 }
234
235 static void
236 micro_iabs(union tgsi_exec_channel *dst,
237 const union tgsi_exec_channel *src)
238 {
239 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
240 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
241 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
242 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
243 }
244
245 static void
246 micro_ineg(union tgsi_exec_channel *dst,
247 const union tgsi_exec_channel *src)
248 {
249 dst->i[0] = -src->i[0];
250 dst->i[1] = -src->i[1];
251 dst->i[2] = -src->i[2];
252 dst->i[3] = -src->i[3];
253 }
254
255 static void
256 micro_lg2(union tgsi_exec_channel *dst,
257 const union tgsi_exec_channel *src)
258 {
259 #if FAST_MATH
260 dst->f[0] = util_fast_log2(src->f[0]);
261 dst->f[1] = util_fast_log2(src->f[1]);
262 dst->f[2] = util_fast_log2(src->f[2]);
263 dst->f[3] = util_fast_log2(src->f[3]);
264 #else
265 dst->f[0] = logf(src->f[0]) * 1.442695f;
266 dst->f[1] = logf(src->f[1]) * 1.442695f;
267 dst->f[2] = logf(src->f[2]) * 1.442695f;
268 dst->f[3] = logf(src->f[3]) * 1.442695f;
269 #endif
270 }
271
272 static void
273 micro_lrp(union tgsi_exec_channel *dst,
274 const union tgsi_exec_channel *src0,
275 const union tgsi_exec_channel *src1,
276 const union tgsi_exec_channel *src2)
277 {
278 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
279 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
280 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
281 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
282 }
283
284 static void
285 micro_mad(union tgsi_exec_channel *dst,
286 const union tgsi_exec_channel *src0,
287 const union tgsi_exec_channel *src1,
288 const union tgsi_exec_channel *src2)
289 {
290 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
291 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
292 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
293 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
294 }
295
296 static void
297 micro_mov(union tgsi_exec_channel *dst,
298 const union tgsi_exec_channel *src)
299 {
300 dst->u[0] = src->u[0];
301 dst->u[1] = src->u[1];
302 dst->u[2] = src->u[2];
303 dst->u[3] = src->u[3];
304 }
305
306 static void
307 micro_rcp(union tgsi_exec_channel *dst,
308 const union tgsi_exec_channel *src)
309 {
310 #if 0 /* for debugging */
311 assert(src->f[0] != 0.0f);
312 assert(src->f[1] != 0.0f);
313 assert(src->f[2] != 0.0f);
314 assert(src->f[3] != 0.0f);
315 #endif
316 dst->f[0] = 1.0f / src->f[0];
317 dst->f[1] = 1.0f / src->f[1];
318 dst->f[2] = 1.0f / src->f[2];
319 dst->f[3] = 1.0f / src->f[3];
320 }
321
322 static void
323 micro_rnd(union tgsi_exec_channel *dst,
324 const union tgsi_exec_channel *src)
325 {
326 dst->f[0] = floorf(src->f[0] + 0.5f);
327 dst->f[1] = floorf(src->f[1] + 0.5f);
328 dst->f[2] = floorf(src->f[2] + 0.5f);
329 dst->f[3] = floorf(src->f[3] + 0.5f);
330 }
331
332 static void
333 micro_rsq(union tgsi_exec_channel *dst,
334 const union tgsi_exec_channel *src)
335 {
336 #if 0 /* for debugging */
337 assert(src->f[0] != 0.0f);
338 assert(src->f[1] != 0.0f);
339 assert(src->f[2] != 0.0f);
340 assert(src->f[3] != 0.0f);
341 #endif
342 dst->f[0] = 1.0f / sqrtf(src->f[0]);
343 dst->f[1] = 1.0f / sqrtf(src->f[1]);
344 dst->f[2] = 1.0f / sqrtf(src->f[2]);
345 dst->f[3] = 1.0f / sqrtf(src->f[3]);
346 }
347
348 static void
349 micro_sqrt(union tgsi_exec_channel *dst,
350 const union tgsi_exec_channel *src)
351 {
352 dst->f[0] = sqrtf(src->f[0]);
353 dst->f[1] = sqrtf(src->f[1]);
354 dst->f[2] = sqrtf(src->f[2]);
355 dst->f[3] = sqrtf(src->f[3]);
356 }
357
358 static void
359 micro_seq(union tgsi_exec_channel *dst,
360 const union tgsi_exec_channel *src0,
361 const union tgsi_exec_channel *src1)
362 {
363 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
364 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
365 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
366 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
367 }
368
369 static void
370 micro_sge(union tgsi_exec_channel *dst,
371 const union tgsi_exec_channel *src0,
372 const union tgsi_exec_channel *src1)
373 {
374 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
375 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
376 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
377 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
378 }
379
380 static void
381 micro_sgn(union tgsi_exec_channel *dst,
382 const union tgsi_exec_channel *src)
383 {
384 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
385 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
386 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
387 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
388 }
389
390 static void
391 micro_isgn(union tgsi_exec_channel *dst,
392 const union tgsi_exec_channel *src)
393 {
394 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
395 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
396 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
397 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
398 }
399
400 static void
401 micro_sgt(union tgsi_exec_channel *dst,
402 const union tgsi_exec_channel *src0,
403 const union tgsi_exec_channel *src1)
404 {
405 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
406 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
407 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
408 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
409 }
410
411 static void
412 micro_sin(union tgsi_exec_channel *dst,
413 const union tgsi_exec_channel *src)
414 {
415 dst->f[0] = sinf(src->f[0]);
416 dst->f[1] = sinf(src->f[1]);
417 dst->f[2] = sinf(src->f[2]);
418 dst->f[3] = sinf(src->f[3]);
419 }
420
421 static void
422 micro_sle(union tgsi_exec_channel *dst,
423 const union tgsi_exec_channel *src0,
424 const union tgsi_exec_channel *src1)
425 {
426 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
427 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
428 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
429 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
430 }
431
432 static void
433 micro_slt(union tgsi_exec_channel *dst,
434 const union tgsi_exec_channel *src0,
435 const union tgsi_exec_channel *src1)
436 {
437 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
438 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
439 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
440 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
441 }
442
443 static void
444 micro_sne(union tgsi_exec_channel *dst,
445 const union tgsi_exec_channel *src0,
446 const union tgsi_exec_channel *src1)
447 {
448 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
449 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
450 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
451 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
452 }
453
454 static void
455 micro_sfl(union tgsi_exec_channel *dst)
456 {
457 dst->f[0] = 0.0f;
458 dst->f[1] = 0.0f;
459 dst->f[2] = 0.0f;
460 dst->f[3] = 0.0f;
461 }
462
463 static void
464 micro_str(union tgsi_exec_channel *dst)
465 {
466 dst->f[0] = 1.0f;
467 dst->f[1] = 1.0f;
468 dst->f[2] = 1.0f;
469 dst->f[3] = 1.0f;
470 }
471
472 static void
473 micro_trunc(union tgsi_exec_channel *dst,
474 const union tgsi_exec_channel *src)
475 {
476 dst->f[0] = (float)(int)src->f[0];
477 dst->f[1] = (float)(int)src->f[1];
478 dst->f[2] = (float)(int)src->f[2];
479 dst->f[3] = (float)(int)src->f[3];
480 }
481
482
483 enum tgsi_exec_datatype {
484 TGSI_EXEC_DATA_FLOAT,
485 TGSI_EXEC_DATA_INT,
486 TGSI_EXEC_DATA_UINT
487 };
488
489 /*
490 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
491 */
492 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
493 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
494 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
495 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
496 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
497 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
498
499
500 /** The execution mask depends on the conditional mask and the loop mask */
501 #define UPDATE_EXEC_MASK(MACH) \
502 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
503
504
505 static const union tgsi_exec_channel ZeroVec =
506 { { 0.0, 0.0, 0.0, 0.0 } };
507
508 static const union tgsi_exec_channel OneVec = {
509 {1.0f, 1.0f, 1.0f, 1.0f}
510 };
511
512 static const union tgsi_exec_channel P128Vec = {
513 {128.0f, 128.0f, 128.0f, 128.0f}
514 };
515
516 static const union tgsi_exec_channel M128Vec = {
517 {-128.0f, -128.0f, -128.0f, -128.0f}
518 };
519
520
521 /**
522 * Assert that none of the float values in 'chan' are infinite or NaN.
523 * NaN and Inf may occur normally during program execution and should
524 * not lead to crashes, etc. But when debugging, it's helpful to catch
525 * them.
526 */
527 static INLINE void
528 check_inf_or_nan(const union tgsi_exec_channel *chan)
529 {
530 assert(!util_is_inf_or_nan((chan)->f[0]));
531 assert(!util_is_inf_or_nan((chan)->f[1]));
532 assert(!util_is_inf_or_nan((chan)->f[2]));
533 assert(!util_is_inf_or_nan((chan)->f[3]));
534 }
535
536
537 #ifdef DEBUG
538 static void
539 print_chan(const char *msg, const union tgsi_exec_channel *chan)
540 {
541 debug_printf("%s = {%f, %f, %f, %f}\n",
542 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
543 }
544 #endif
545
546
547 #ifdef DEBUG
548 static void
549 print_temp(const struct tgsi_exec_machine *mach, uint index)
550 {
551 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
552 int i;
553 debug_printf("Temp[%u] =\n", index);
554 for (i = 0; i < 4; i++) {
555 debug_printf(" %c: { %f, %f, %f, %f }\n",
556 "XYZW"[i],
557 tmp->xyzw[i].f[0],
558 tmp->xyzw[i].f[1],
559 tmp->xyzw[i].f[2],
560 tmp->xyzw[i].f[3]);
561 }
562 }
563 #endif
564
565
566 void
567 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
568 unsigned num_bufs,
569 const void **bufs,
570 const unsigned *buf_sizes)
571 {
572 unsigned i;
573
574 for (i = 0; i < num_bufs; i++) {
575 mach->Consts[i] = bufs[i];
576 mach->ConstsSize[i] = buf_sizes[i];
577 }
578 }
579
580
581 /**
582 * Check if there's a potential src/dst register data dependency when
583 * using SOA execution.
584 * Example:
585 * MOV T, T.yxwz;
586 * This would expand into:
587 * MOV t0, t1;
588 * MOV t1, t0;
589 * MOV t2, t3;
590 * MOV t3, t2;
591 * The second instruction will have the wrong value for t0 if executed as-is.
592 */
593 boolean
594 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
595 {
596 uint i, chan;
597
598 uint writemask = inst->Dst[0].Register.WriteMask;
599 if (writemask == TGSI_WRITEMASK_X ||
600 writemask == TGSI_WRITEMASK_Y ||
601 writemask == TGSI_WRITEMASK_Z ||
602 writemask == TGSI_WRITEMASK_W ||
603 writemask == TGSI_WRITEMASK_NONE) {
604 /* no chance of data dependency */
605 return FALSE;
606 }
607
608 /* loop over src regs */
609 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
610 if ((inst->Src[i].Register.File ==
611 inst->Dst[0].Register.File) &&
612 ((inst->Src[i].Register.Index ==
613 inst->Dst[0].Register.Index) ||
614 inst->Src[i].Register.Indirect ||
615 inst->Dst[0].Register.Indirect)) {
616 /* loop over dest channels */
617 uint channelsWritten = 0x0;
618 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
619 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
620 /* check if we're reading a channel that's been written */
621 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
622 if (channelsWritten & (1 << swizzle)) {
623 return TRUE;
624 }
625
626 channelsWritten |= (1 << chan);
627 }
628 }
629 }
630 }
631 return FALSE;
632 }
633
634
635 /**
636 * Initialize machine state by expanding tokens to full instructions,
637 * allocating temporary storage, setting up constants, etc.
638 * After this, we can call tgsi_exec_machine_run() many times.
639 */
640 void
641 tgsi_exec_machine_bind_shader(
642 struct tgsi_exec_machine *mach,
643 const struct tgsi_token *tokens,
644 struct tgsi_sampler *sampler)
645 {
646 uint k;
647 struct tgsi_parse_context parse;
648 struct tgsi_full_instruction *instructions;
649 struct tgsi_full_declaration *declarations;
650 uint maxInstructions = 10, numInstructions = 0;
651 uint maxDeclarations = 10, numDeclarations = 0;
652
653 #if 0
654 tgsi_dump(tokens, 0);
655 #endif
656
657 util_init_math();
658
659
660 mach->Tokens = tokens;
661 mach->Sampler = sampler;
662
663 if (!tokens) {
664 /* unbind and free all */
665 FREE(mach->Declarations);
666 mach->Declarations = NULL;
667 mach->NumDeclarations = 0;
668
669 FREE(mach->Instructions);
670 mach->Instructions = NULL;
671 mach->NumInstructions = 0;
672
673 return;
674 }
675
676 k = tgsi_parse_init (&parse, mach->Tokens);
677 if (k != TGSI_PARSE_OK) {
678 debug_printf( "Problem parsing!\n" );
679 return;
680 }
681
682 mach->Processor = parse.FullHeader.Processor.Processor;
683 mach->ImmLimit = 0;
684 mach->NumOutputs = 0;
685
686 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
687 !mach->UsedGeometryShader) {
688 struct tgsi_exec_vector *inputs;
689 struct tgsi_exec_vector *outputs;
690
691 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
692 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
693 16);
694
695 if (!inputs)
696 return;
697
698 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
699 TGSI_MAX_TOTAL_VERTICES, 16);
700
701 if (!outputs) {
702 align_free(inputs);
703 return;
704 }
705
706 align_free(mach->Inputs);
707 align_free(mach->Outputs);
708
709 mach->Inputs = inputs;
710 mach->Outputs = outputs;
711 mach->UsedGeometryShader = TRUE;
712 }
713
714 declarations = (struct tgsi_full_declaration *)
715 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
716
717 if (!declarations) {
718 return;
719 }
720
721 instructions = (struct tgsi_full_instruction *)
722 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
723
724 if (!instructions) {
725 FREE( declarations );
726 return;
727 }
728
729 while( !tgsi_parse_end_of_tokens( &parse ) ) {
730 uint i;
731
732 tgsi_parse_token( &parse );
733 switch( parse.FullToken.Token.Type ) {
734 case TGSI_TOKEN_TYPE_DECLARATION:
735 /* save expanded declaration */
736 if (numDeclarations == maxDeclarations) {
737 declarations = REALLOC(declarations,
738 maxDeclarations
739 * sizeof(struct tgsi_full_declaration),
740 (maxDeclarations + 10)
741 * sizeof(struct tgsi_full_declaration));
742 maxDeclarations += 10;
743 }
744 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
745 unsigned reg;
746 for (reg = parse.FullToken.FullDeclaration.Range.First;
747 reg <= parse.FullToken.FullDeclaration.Range.Last;
748 ++reg) {
749 ++mach->NumOutputs;
750 }
751 }
752 memcpy(declarations + numDeclarations,
753 &parse.FullToken.FullDeclaration,
754 sizeof(declarations[0]));
755 numDeclarations++;
756 break;
757
758 case TGSI_TOKEN_TYPE_IMMEDIATE:
759 {
760 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
761 assert( size <= 4 );
762 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
763
764 for( i = 0; i < size; i++ ) {
765 mach->Imms[mach->ImmLimit][i] =
766 parse.FullToken.FullImmediate.u[i].Float;
767 }
768 mach->ImmLimit += 1;
769 }
770 break;
771
772 case TGSI_TOKEN_TYPE_INSTRUCTION:
773
774 /* save expanded instruction */
775 if (numInstructions == maxInstructions) {
776 instructions = REALLOC(instructions,
777 maxInstructions
778 * sizeof(struct tgsi_full_instruction),
779 (maxInstructions + 10)
780 * sizeof(struct tgsi_full_instruction));
781 maxInstructions += 10;
782 }
783
784 memcpy(instructions + numInstructions,
785 &parse.FullToken.FullInstruction,
786 sizeof(instructions[0]));
787
788 numInstructions++;
789 break;
790
791 case TGSI_TOKEN_TYPE_PROPERTY:
792 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY) {
793 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
794 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
795 }
796 }
797 break;
798
799 default:
800 assert( 0 );
801 }
802 }
803 tgsi_parse_free (&parse);
804
805 FREE(mach->Declarations);
806 mach->Declarations = declarations;
807 mach->NumDeclarations = numDeclarations;
808
809 FREE(mach->Instructions);
810 mach->Instructions = instructions;
811 mach->NumInstructions = numInstructions;
812 }
813
814
815 struct tgsi_exec_machine *
816 tgsi_exec_machine_create( void )
817 {
818 struct tgsi_exec_machine *mach;
819 uint i;
820
821 mach = align_malloc( sizeof *mach, 16 );
822 if (!mach)
823 goto fail;
824
825 memset(mach, 0, sizeof(*mach));
826
827 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
828 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
829 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
830
831 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
832 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
833 if (!mach->Inputs || !mach->Outputs)
834 goto fail;
835
836 /* Setup constants needed by the SSE2 executor. */
837 for( i = 0; i < 4; i++ ) {
838 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
839 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
840 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
841 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
842 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
843 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
844 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
845 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
846 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
847 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
848 }
849
850 #ifdef DEBUG
851 /* silence warnings */
852 (void) print_chan;
853 (void) print_temp;
854 #endif
855
856 return mach;
857
858 fail:
859 if (mach) {
860 align_free(mach->Inputs);
861 align_free(mach->Outputs);
862 align_free(mach);
863 }
864 return NULL;
865 }
866
867
868 void
869 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
870 {
871 if (mach) {
872 FREE(mach->Instructions);
873 FREE(mach->Declarations);
874
875 align_free(mach->Inputs);
876 align_free(mach->Outputs);
877
878 align_free(mach);
879 }
880 }
881
882 static void
883 micro_add(union tgsi_exec_channel *dst,
884 const union tgsi_exec_channel *src0,
885 const union tgsi_exec_channel *src1)
886 {
887 dst->f[0] = src0->f[0] + src1->f[0];
888 dst->f[1] = src0->f[1] + src1->f[1];
889 dst->f[2] = src0->f[2] + src1->f[2];
890 dst->f[3] = src0->f[3] + src1->f[3];
891 }
892
893 static void
894 micro_div(
895 union tgsi_exec_channel *dst,
896 const union tgsi_exec_channel *src0,
897 const union tgsi_exec_channel *src1 )
898 {
899 if (src1->f[0] != 0) {
900 dst->f[0] = src0->f[0] / src1->f[0];
901 }
902 if (src1->f[1] != 0) {
903 dst->f[1] = src0->f[1] / src1->f[1];
904 }
905 if (src1->f[2] != 0) {
906 dst->f[2] = src0->f[2] / src1->f[2];
907 }
908 if (src1->f[3] != 0) {
909 dst->f[3] = src0->f[3] / src1->f[3];
910 }
911 }
912
913 static void
914 micro_rcc(union tgsi_exec_channel *dst,
915 const union tgsi_exec_channel *src)
916 {
917 uint i;
918
919 for (i = 0; i < 4; i++) {
920 float recip = 1.0f / src->f[i];
921
922 if (recip > 0.0f)
923 dst->f[i] = CLAMP(recip, 5.42101e-020f, 1.84467e+019f);
924 else
925 dst->f[i] = CLAMP(recip, -1.84467e+019f, -5.42101e-020f);
926 }
927 }
928
929 static void
930 micro_lt(
931 union tgsi_exec_channel *dst,
932 const union tgsi_exec_channel *src0,
933 const union tgsi_exec_channel *src1,
934 const union tgsi_exec_channel *src2,
935 const union tgsi_exec_channel *src3 )
936 {
937 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
938 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
939 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
940 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
941 }
942
943 static void
944 micro_max(union tgsi_exec_channel *dst,
945 const union tgsi_exec_channel *src0,
946 const union tgsi_exec_channel *src1)
947 {
948 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
949 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
950 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
951 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
952 }
953
954 static void
955 micro_min(union tgsi_exec_channel *dst,
956 const union tgsi_exec_channel *src0,
957 const union tgsi_exec_channel *src1)
958 {
959 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
960 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
961 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
962 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
963 }
964
965 static void
966 micro_mul(union tgsi_exec_channel *dst,
967 const union tgsi_exec_channel *src0,
968 const union tgsi_exec_channel *src1)
969 {
970 dst->f[0] = src0->f[0] * src1->f[0];
971 dst->f[1] = src0->f[1] * src1->f[1];
972 dst->f[2] = src0->f[2] * src1->f[2];
973 dst->f[3] = src0->f[3] * src1->f[3];
974 }
975
976 static void
977 micro_neg(
978 union tgsi_exec_channel *dst,
979 const union tgsi_exec_channel *src )
980 {
981 dst->f[0] = -src->f[0];
982 dst->f[1] = -src->f[1];
983 dst->f[2] = -src->f[2];
984 dst->f[3] = -src->f[3];
985 }
986
987 static void
988 micro_pow(
989 union tgsi_exec_channel *dst,
990 const union tgsi_exec_channel *src0,
991 const union tgsi_exec_channel *src1 )
992 {
993 #if FAST_MATH
994 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
995 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
996 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
997 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
998 #else
999 dst->f[0] = powf( src0->f[0], src1->f[0] );
1000 dst->f[1] = powf( src0->f[1], src1->f[1] );
1001 dst->f[2] = powf( src0->f[2], src1->f[2] );
1002 dst->f[3] = powf( src0->f[3], src1->f[3] );
1003 #endif
1004 }
1005
1006 static void
1007 micro_sub(union tgsi_exec_channel *dst,
1008 const union tgsi_exec_channel *src0,
1009 const union tgsi_exec_channel *src1)
1010 {
1011 dst->f[0] = src0->f[0] - src1->f[0];
1012 dst->f[1] = src0->f[1] - src1->f[1];
1013 dst->f[2] = src0->f[2] - src1->f[2];
1014 dst->f[3] = src0->f[3] - src1->f[3];
1015 }
1016
1017 static void
1018 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1019 const uint chan_index,
1020 const uint file,
1021 const uint swizzle,
1022 const union tgsi_exec_channel *index,
1023 const union tgsi_exec_channel *index2D,
1024 union tgsi_exec_channel *chan)
1025 {
1026 uint i;
1027
1028 assert(swizzle < 4);
1029
1030 switch (file) {
1031 case TGSI_FILE_CONSTANT:
1032 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1033 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1034 assert(mach->Consts[index2D->i[i]]);
1035
1036 if (index->i[i] < 0) {
1037 chan->u[i] = 0;
1038 } else {
1039 /* NOTE: copying the const value as a uint instead of float */
1040 const uint constbuf = index2D->i[i];
1041 const uint *buf = (const uint *)mach->Consts[constbuf];
1042 const int pos = index->i[i] * 4 + swizzle;
1043 /* const buffer bounds check */
1044 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1045 if (0) {
1046 /* Debug: print warning */
1047 static int count = 0;
1048 if (count++ < 100)
1049 debug_printf("TGSI Exec: const buffer index %d"
1050 " out of bounds\n", pos);
1051 }
1052 chan->u[i] = 0;
1053 }
1054 else
1055 chan->u[i] = buf[pos];
1056 }
1057 }
1058 break;
1059
1060 case TGSI_FILE_INPUT:
1061 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1062 /*
1063 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1064 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1065 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1066 index2D->i[i], index->i[i]);
1067 }*/
1068 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1069 assert(pos >= 0);
1070 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1071 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1072 }
1073 break;
1074
1075 case TGSI_FILE_SYSTEM_VALUE:
1076 /* XXX no swizzling at this point. Will be needed if we put
1077 * gl_FragCoord, for example, in a sys value register.
1078 */
1079 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1080 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1081 }
1082 break;
1083
1084 case TGSI_FILE_TEMPORARY:
1085 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1086 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1087 assert(index2D->i[i] == 0);
1088
1089 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1090 }
1091 break;
1092
1093 case TGSI_FILE_IMMEDIATE:
1094 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1095 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1096 assert(index2D->i[i] == 0);
1097
1098 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1099 }
1100 break;
1101
1102 case TGSI_FILE_ADDRESS:
1103 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1104 assert(index->i[i] >= 0);
1105 assert(index2D->i[i] == 0);
1106
1107 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1108 }
1109 break;
1110
1111 case TGSI_FILE_PREDICATE:
1112 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1113 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1114 assert(index2D->i[i] == 0);
1115
1116 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1117 }
1118 break;
1119
1120 case TGSI_FILE_OUTPUT:
1121 /* vertex/fragment output vars can be read too */
1122 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1123 assert(index->i[i] >= 0);
1124 assert(index2D->i[i] == 0);
1125
1126 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1127 }
1128 break;
1129
1130 default:
1131 assert(0);
1132 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1133 chan->u[i] = 0;
1134 }
1135 }
1136 }
1137
1138 static void
1139 fetch_source(const struct tgsi_exec_machine *mach,
1140 union tgsi_exec_channel *chan,
1141 const struct tgsi_full_src_register *reg,
1142 const uint chan_index,
1143 enum tgsi_exec_datatype src_datatype)
1144 {
1145 union tgsi_exec_channel index;
1146 union tgsi_exec_channel index2D;
1147 uint swizzle;
1148
1149 /* We start with a direct index into a register file.
1150 *
1151 * file[1],
1152 * where:
1153 * file = Register.File
1154 * [1] = Register.Index
1155 */
1156 index.i[0] =
1157 index.i[1] =
1158 index.i[2] =
1159 index.i[3] = reg->Register.Index;
1160
1161 /* There is an extra source register that indirectly subscripts
1162 * a register file. The direct index now becomes an offset
1163 * that is being added to the indirect register.
1164 *
1165 * file[ind[2].x+1],
1166 * where:
1167 * ind = Indirect.File
1168 * [2] = Indirect.Index
1169 * .x = Indirect.SwizzleX
1170 */
1171 if (reg->Register.Indirect) {
1172 union tgsi_exec_channel index2;
1173 union tgsi_exec_channel indir_index;
1174 const uint execmask = mach->ExecMask;
1175 uint i;
1176
1177 /* which address register (always zero now) */
1178 index2.i[0] =
1179 index2.i[1] =
1180 index2.i[2] =
1181 index2.i[3] = reg->Indirect.Index;
1182 /* get current value of address register[swizzle] */
1183 swizzle = reg->Indirect.Swizzle;
1184 fetch_src_file_channel(mach,
1185 chan_index,
1186 reg->Indirect.File,
1187 swizzle,
1188 &index2,
1189 &ZeroVec,
1190 &indir_index);
1191
1192 /* add value of address register to the offset */
1193 index.i[0] += indir_index.i[0];
1194 index.i[1] += indir_index.i[1];
1195 index.i[2] += indir_index.i[2];
1196 index.i[3] += indir_index.i[3];
1197
1198 /* for disabled execution channels, zero-out the index to
1199 * avoid using a potential garbage value.
1200 */
1201 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1202 if ((execmask & (1 << i)) == 0)
1203 index.i[i] = 0;
1204 }
1205 }
1206
1207 /* There is an extra source register that is a second
1208 * subscript to a register file. Effectively it means that
1209 * the register file is actually a 2D array of registers.
1210 *
1211 * file[3][1],
1212 * where:
1213 * [3] = Dimension.Index
1214 */
1215 if (reg->Register.Dimension) {
1216 index2D.i[0] =
1217 index2D.i[1] =
1218 index2D.i[2] =
1219 index2D.i[3] = reg->Dimension.Index;
1220
1221 /* Again, the second subscript index can be addressed indirectly
1222 * identically to the first one.
1223 * Nothing stops us from indirectly addressing the indirect register,
1224 * but there is no need for that, so we won't exercise it.
1225 *
1226 * file[ind[4].y+3][1],
1227 * where:
1228 * ind = DimIndirect.File
1229 * [4] = DimIndirect.Index
1230 * .y = DimIndirect.SwizzleX
1231 */
1232 if (reg->Dimension.Indirect) {
1233 union tgsi_exec_channel index2;
1234 union tgsi_exec_channel indir_index;
1235 const uint execmask = mach->ExecMask;
1236 uint i;
1237
1238 index2.i[0] =
1239 index2.i[1] =
1240 index2.i[2] =
1241 index2.i[3] = reg->DimIndirect.Index;
1242
1243 swizzle = reg->DimIndirect.Swizzle;
1244 fetch_src_file_channel(mach,
1245 chan_index,
1246 reg->DimIndirect.File,
1247 swizzle,
1248 &index2,
1249 &ZeroVec,
1250 &indir_index);
1251
1252 index2D.i[0] += indir_index.i[0];
1253 index2D.i[1] += indir_index.i[1];
1254 index2D.i[2] += indir_index.i[2];
1255 index2D.i[3] += indir_index.i[3];
1256
1257 /* for disabled execution channels, zero-out the index to
1258 * avoid using a potential garbage value.
1259 */
1260 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1261 if ((execmask & (1 << i)) == 0) {
1262 index2D.i[i] = 0;
1263 }
1264 }
1265 }
1266
1267 /* If by any chance there was a need for a 3D array of register
1268 * files, we would have to check whether Dimension is followed
1269 * by a dimension register and continue the saga.
1270 */
1271 } else {
1272 index2D.i[0] =
1273 index2D.i[1] =
1274 index2D.i[2] =
1275 index2D.i[3] = 0;
1276 }
1277
1278 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1279 fetch_src_file_channel(mach,
1280 chan_index,
1281 reg->Register.File,
1282 swizzle,
1283 &index,
1284 &index2D,
1285 chan);
1286
1287 if (reg->Register.Absolute) {
1288 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1289 micro_abs(chan, chan);
1290 } else {
1291 micro_iabs(chan, chan);
1292 }
1293 }
1294
1295 if (reg->Register.Negate) {
1296 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1297 micro_neg(chan, chan);
1298 } else {
1299 micro_ineg(chan, chan);
1300 }
1301 }
1302 }
1303
1304 static void
1305 store_dest(struct tgsi_exec_machine *mach,
1306 const union tgsi_exec_channel *chan,
1307 const struct tgsi_full_dst_register *reg,
1308 const struct tgsi_full_instruction *inst,
1309 uint chan_index,
1310 enum tgsi_exec_datatype dst_datatype)
1311 {
1312 uint i;
1313 union tgsi_exec_channel null;
1314 union tgsi_exec_channel *dst;
1315 union tgsi_exec_channel index2D;
1316 uint execmask = mach->ExecMask;
1317 int offset = 0; /* indirection offset */
1318 int index;
1319
1320 /* for debugging */
1321 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1322 check_inf_or_nan(chan);
1323 }
1324
1325 /* There is an extra source register that indirectly subscripts
1326 * a register file. The direct index now becomes an offset
1327 * that is being added to the indirect register.
1328 *
1329 * file[ind[2].x+1],
1330 * where:
1331 * ind = Indirect.File
1332 * [2] = Indirect.Index
1333 * .x = Indirect.SwizzleX
1334 */
1335 if (reg->Register.Indirect) {
1336 union tgsi_exec_channel index;
1337 union tgsi_exec_channel indir_index;
1338 uint swizzle;
1339
1340 /* which address register (always zero for now) */
1341 index.i[0] =
1342 index.i[1] =
1343 index.i[2] =
1344 index.i[3] = reg->Indirect.Index;
1345
1346 /* get current value of address register[swizzle] */
1347 swizzle = reg->Indirect.Swizzle;
1348
1349 /* fetch values from the address/indirection register */
1350 fetch_src_file_channel(mach,
1351 chan_index,
1352 reg->Indirect.File,
1353 swizzle,
1354 &index,
1355 &ZeroVec,
1356 &indir_index);
1357
1358 /* save indirection offset */
1359 offset = indir_index.i[0];
1360 }
1361
1362 /* There is an extra source register that is a second
1363 * subscript to a register file. Effectively it means that
1364 * the register file is actually a 2D array of registers.
1365 *
1366 * file[3][1],
1367 * where:
1368 * [3] = Dimension.Index
1369 */
1370 if (reg->Register.Dimension) {
1371 index2D.i[0] =
1372 index2D.i[1] =
1373 index2D.i[2] =
1374 index2D.i[3] = reg->Dimension.Index;
1375
1376 /* Again, the second subscript index can be addressed indirectly
1377 * identically to the first one.
1378 * Nothing stops us from indirectly addressing the indirect register,
1379 * but there is no need for that, so we won't exercise it.
1380 *
1381 * file[ind[4].y+3][1],
1382 * where:
1383 * ind = DimIndirect.File
1384 * [4] = DimIndirect.Index
1385 * .y = DimIndirect.SwizzleX
1386 */
1387 if (reg->Dimension.Indirect) {
1388 union tgsi_exec_channel index2;
1389 union tgsi_exec_channel indir_index;
1390 const uint execmask = mach->ExecMask;
1391 unsigned swizzle;
1392 uint i;
1393
1394 index2.i[0] =
1395 index2.i[1] =
1396 index2.i[2] =
1397 index2.i[3] = reg->DimIndirect.Index;
1398
1399 swizzle = reg->DimIndirect.Swizzle;
1400 fetch_src_file_channel(mach,
1401 chan_index,
1402 reg->DimIndirect.File,
1403 swizzle,
1404 &index2,
1405 &ZeroVec,
1406 &indir_index);
1407
1408 index2D.i[0] += indir_index.i[0];
1409 index2D.i[1] += indir_index.i[1];
1410 index2D.i[2] += indir_index.i[2];
1411 index2D.i[3] += indir_index.i[3];
1412
1413 /* for disabled execution channels, zero-out the index to
1414 * avoid using a potential garbage value.
1415 */
1416 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1417 if ((execmask & (1 << i)) == 0) {
1418 index2D.i[i] = 0;
1419 }
1420 }
1421 }
1422
1423 /* If by any chance there was a need for a 3D array of register
1424 * files, we would have to check whether Dimension is followed
1425 * by a dimension register and continue the saga.
1426 */
1427 } else {
1428 index2D.i[0] =
1429 index2D.i[1] =
1430 index2D.i[2] =
1431 index2D.i[3] = 0;
1432 }
1433
1434 switch (reg->Register.File) {
1435 case TGSI_FILE_NULL:
1436 dst = &null;
1437 break;
1438
1439 case TGSI_FILE_OUTPUT:
1440 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1441 + reg->Register.Index;
1442 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1443 #if 0
1444 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1445 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1446 reg->Register.Index);
1447 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1448 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1449 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1450 if (execmask & (1 << i))
1451 debug_printf("%f, ", chan->f[i]);
1452 debug_printf(")\n");
1453 }
1454 #endif
1455 break;
1456
1457 case TGSI_FILE_TEMPORARY:
1458 index = reg->Register.Index;
1459 assert( index < TGSI_EXEC_NUM_TEMPS );
1460 dst = &mach->Temps[offset + index].xyzw[chan_index];
1461 break;
1462
1463 case TGSI_FILE_ADDRESS:
1464 index = reg->Register.Index;
1465 dst = &mach->Addrs[index].xyzw[chan_index];
1466 break;
1467
1468 case TGSI_FILE_PREDICATE:
1469 index = reg->Register.Index;
1470 assert(index < TGSI_EXEC_NUM_PREDS);
1471 dst = &mach->Predicates[index].xyzw[chan_index];
1472 break;
1473
1474 default:
1475 assert( 0 );
1476 return;
1477 }
1478
1479 if (inst->Instruction.Predicate) {
1480 uint swizzle;
1481 union tgsi_exec_channel *pred;
1482
1483 switch (chan_index) {
1484 case TGSI_CHAN_X:
1485 swizzle = inst->Predicate.SwizzleX;
1486 break;
1487 case TGSI_CHAN_Y:
1488 swizzle = inst->Predicate.SwizzleY;
1489 break;
1490 case TGSI_CHAN_Z:
1491 swizzle = inst->Predicate.SwizzleZ;
1492 break;
1493 case TGSI_CHAN_W:
1494 swizzle = inst->Predicate.SwizzleW;
1495 break;
1496 default:
1497 assert(0);
1498 return;
1499 }
1500
1501 assert(inst->Predicate.Index == 0);
1502
1503 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1504
1505 if (inst->Predicate.Negate) {
1506 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1507 if (pred->u[i]) {
1508 execmask &= ~(1 << i);
1509 }
1510 }
1511 } else {
1512 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1513 if (!pred->u[i]) {
1514 execmask &= ~(1 << i);
1515 }
1516 }
1517 }
1518 }
1519
1520 switch (inst->Instruction.Saturate) {
1521 case TGSI_SAT_NONE:
1522 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1523 if (execmask & (1 << i))
1524 dst->i[i] = chan->i[i];
1525 break;
1526
1527 case TGSI_SAT_ZERO_ONE:
1528 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1529 if (execmask & (1 << i)) {
1530 if (chan->f[i] < 0.0f)
1531 dst->f[i] = 0.0f;
1532 else if (chan->f[i] > 1.0f)
1533 dst->f[i] = 1.0f;
1534 else
1535 dst->i[i] = chan->i[i];
1536 }
1537 break;
1538
1539 case TGSI_SAT_MINUS_PLUS_ONE:
1540 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1541 if (execmask & (1 << i)) {
1542 if (chan->f[i] < -1.0f)
1543 dst->f[i] = -1.0f;
1544 else if (chan->f[i] > 1.0f)
1545 dst->f[i] = 1.0f;
1546 else
1547 dst->i[i] = chan->i[i];
1548 }
1549 break;
1550
1551 default:
1552 assert( 0 );
1553 }
1554 }
1555
1556 #define FETCH(VAL,INDEX,CHAN)\
1557 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1558
1559 #define IFETCH(VAL,INDEX,CHAN)\
1560 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1561
1562
1563 /**
1564 * Execute ARB-style KIL which is predicated by a src register.
1565 * Kill fragment if any of the four values is less than zero.
1566 */
1567 static void
1568 exec_kill_if(struct tgsi_exec_machine *mach,
1569 const struct tgsi_full_instruction *inst)
1570 {
1571 uint uniquemask;
1572 uint chan_index;
1573 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1574 union tgsi_exec_channel r[1];
1575
1576 /* This mask stores component bits that were already tested. */
1577 uniquemask = 0;
1578
1579 for (chan_index = 0; chan_index < 4; chan_index++)
1580 {
1581 uint swizzle;
1582 uint i;
1583
1584 /* unswizzle channel */
1585 swizzle = tgsi_util_get_full_src_register_swizzle (
1586 &inst->Src[0],
1587 chan_index);
1588
1589 /* check if the component has not been already tested */
1590 if (uniquemask & (1 << swizzle))
1591 continue;
1592 uniquemask |= 1 << swizzle;
1593
1594 FETCH(&r[0], 0, chan_index);
1595 for (i = 0; i < 4; i++)
1596 if (r[0].f[i] < 0.0f)
1597 kilmask |= 1 << i;
1598 }
1599
1600 /* restrict to fragments currently executing */
1601 kilmask &= mach->ExecMask;
1602
1603 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1604 }
1605
1606 /**
1607 * Unconditional fragment kill/discard.
1608 */
1609 static void
1610 exec_kill(struct tgsi_exec_machine *mach,
1611 const struct tgsi_full_instruction *inst)
1612 {
1613 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1614
1615 /* kill fragment for all fragments currently executing */
1616 kilmask = mach->ExecMask;
1617 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1618 }
1619
1620 static void
1621 emit_vertex(struct tgsi_exec_machine *mach)
1622 {
1623 /* FIXME: check for exec mask correctly
1624 unsigned i;
1625 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1626 if ((mach->ExecMask & (1 << i)))
1627 */
1628 if (mach->ExecMask) {
1629 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1630 return;
1631
1632 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1633 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1634 }
1635 }
1636
1637 static void
1638 emit_primitive(struct tgsi_exec_machine *mach)
1639 {
1640 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1641 /* FIXME: check for exec mask correctly
1642 unsigned i;
1643 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1644 if ((mach->ExecMask & (1 << i)))
1645 */
1646 if (mach->ExecMask) {
1647 ++(*prim_count);
1648 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1649 mach->Primitives[*prim_count] = 0;
1650 }
1651 }
1652
1653 static void
1654 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1655 {
1656 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1657 int emitted_verts =
1658 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1659 if (emitted_verts) {
1660 emit_primitive(mach);
1661 }
1662 }
1663 }
1664
1665
1666 /*
1667 * Fetch four texture samples using STR texture coordinates.
1668 */
1669 static void
1670 fetch_texel( struct tgsi_sampler *sampler,
1671 const unsigned sview_idx,
1672 const unsigned sampler_idx,
1673 const union tgsi_exec_channel *s,
1674 const union tgsi_exec_channel *t,
1675 const union tgsi_exec_channel *p,
1676 const union tgsi_exec_channel *c0,
1677 const union tgsi_exec_channel *c1,
1678 float derivs[3][2][TGSI_QUAD_SIZE],
1679 const int8_t offset[3],
1680 enum tgsi_sampler_control control,
1681 union tgsi_exec_channel *r,
1682 union tgsi_exec_channel *g,
1683 union tgsi_exec_channel *b,
1684 union tgsi_exec_channel *a )
1685 {
1686 uint j;
1687 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1688
1689 /* FIXME: handle explicit derivs, offsets */
1690 sampler->get_samples(sampler, sview_idx, sampler_idx,
1691 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1692
1693 for (j = 0; j < 4; j++) {
1694 r->f[j] = rgba[0][j];
1695 g->f[j] = rgba[1][j];
1696 b->f[j] = rgba[2][j];
1697 a->f[j] = rgba[3][j];
1698 }
1699 }
1700
1701
1702 #define TEX_MODIFIER_NONE 0
1703 #define TEX_MODIFIER_PROJECTED 1
1704 #define TEX_MODIFIER_LOD_BIAS 2
1705 #define TEX_MODIFIER_EXPLICIT_LOD 3
1706 #define TEX_MODIFIER_LEVEL_ZERO 4
1707
1708
1709 /*
1710 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1711 */
1712 static void
1713 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1714 const struct tgsi_full_instruction *inst,
1715 int8_t offsets[3])
1716 {
1717 if (inst->Texture.NumOffsets == 1) {
1718 union tgsi_exec_channel index;
1719 union tgsi_exec_channel offset[3];
1720 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1721 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1722 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1723 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1724 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1725 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1726 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1727 offsets[0] = offset[0].i[0];
1728 offsets[1] = offset[1].i[0];
1729 offsets[2] = offset[2].i[0];
1730 } else {
1731 assert(inst->Texture.NumOffsets == 0);
1732 offsets[0] = offsets[1] = offsets[2] = 0;
1733 }
1734 }
1735
1736
1737 /*
1738 * Fetch dx and dy values for one channel (s, t or r).
1739 * Put dx values into one float array, dy values into another.
1740 */
1741 static void
1742 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1743 const struct tgsi_full_instruction *inst,
1744 unsigned regdsrcx,
1745 unsigned chan,
1746 float derivs[2][TGSI_QUAD_SIZE])
1747 {
1748 union tgsi_exec_channel d;
1749 FETCH(&d, regdsrcx, chan);
1750 derivs[0][0] = d.f[0];
1751 derivs[0][1] = d.f[1];
1752 derivs[0][2] = d.f[2];
1753 derivs[0][3] = d.f[3];
1754 FETCH(&d, regdsrcx + 1, chan);
1755 derivs[1][0] = d.f[0];
1756 derivs[1][1] = d.f[1];
1757 derivs[1][2] = d.f[2];
1758 derivs[1][3] = d.f[3];
1759 }
1760
1761
1762 /*
1763 * execute a texture instruction.
1764 *
1765 * modifier is used to control the channel routing for the\
1766 * instruction variants like proj, lod, and texture with lod bias.
1767 * sampler indicates which src register the sampler is contained in.
1768 */
1769 static void
1770 exec_tex(struct tgsi_exec_machine *mach,
1771 const struct tgsi_full_instruction *inst,
1772 uint modifier, uint sampler)
1773 {
1774 const uint unit = inst->Src[sampler].Register.Index;
1775 const union tgsi_exec_channel *args[5], *proj = NULL;
1776 union tgsi_exec_channel r[5];
1777 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
1778 uint chan;
1779 int8_t offsets[3];
1780 int dim, shadow_ref, i;
1781
1782 /* always fetch all 3 offsets, overkill but keeps code simple */
1783 fetch_texel_offsets(mach, inst, offsets);
1784
1785 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
1786 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
1787
1788 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
1789
1790 assert(dim <= 4);
1791 if (shadow_ref >= 0)
1792 assert(shadow_ref >= dim && shadow_ref < Elements(args));
1793
1794 /* fetch modifier to the last argument */
1795 if (modifier != TEX_MODIFIER_NONE) {
1796 const int last = Elements(args) - 1;
1797
1798 /* fetch modifier from src0.w or src1.x */
1799 if (sampler == 1) {
1800 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
1801 FETCH(&r[last], 0, TGSI_CHAN_W);
1802 }
1803 else {
1804 assert(shadow_ref != 4);
1805 FETCH(&r[last], 1, TGSI_CHAN_X);
1806 }
1807
1808 if (modifier != TEX_MODIFIER_PROJECTED) {
1809 args[last] = &r[last];
1810 }
1811 else {
1812 proj = &r[last];
1813 args[last] = &ZeroVec;
1814 }
1815
1816 /* point unused arguments to zero vector */
1817 for (i = dim; i < last; i++)
1818 args[i] = &ZeroVec;
1819
1820 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
1821 control = tgsi_sampler_lod_explicit;
1822 else if (modifier == TEX_MODIFIER_LOD_BIAS)
1823 control = tgsi_sampler_lod_bias;
1824 }
1825 else {
1826 for (i = dim; i < Elements(args); i++)
1827 args[i] = &ZeroVec;
1828 }
1829
1830 /* fetch coordinates */
1831 for (i = 0; i < dim; i++) {
1832 FETCH(&r[i], 0, TGSI_CHAN_X + i);
1833
1834 if (proj)
1835 micro_div(&r[i], &r[i], proj);
1836
1837 args[i] = &r[i];
1838 }
1839
1840 /* fetch reference value */
1841 if (shadow_ref >= 0) {
1842 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
1843
1844 if (proj)
1845 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
1846
1847 args[shadow_ref] = &r[shadow_ref];
1848 }
1849
1850 fetch_texel(mach->Sampler, unit, unit,
1851 args[0], args[1], args[2], args[3], args[4],
1852 NULL, offsets, control,
1853 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1854
1855 #if 0
1856 debug_printf("fetch r: %g %g %g %g\n",
1857 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1858 debug_printf("fetch g: %g %g %g %g\n",
1859 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1860 debug_printf("fetch b: %g %g %g %g\n",
1861 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1862 debug_printf("fetch a: %g %g %g %g\n",
1863 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1864 #endif
1865
1866 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1867 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1868 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1869 }
1870 }
1871 }
1872
1873
1874 static void
1875 exec_txd(struct tgsi_exec_machine *mach,
1876 const struct tgsi_full_instruction *inst)
1877 {
1878 const uint unit = inst->Src[3].Register.Index;
1879 union tgsi_exec_channel r[4];
1880 float derivs[3][2][TGSI_QUAD_SIZE];
1881 uint chan;
1882 int8_t offsets[3];
1883
1884 /* always fetch all 3 offsets, overkill but keeps code simple */
1885 fetch_texel_offsets(mach, inst, offsets);
1886
1887 switch (inst->Texture.Texture) {
1888 case TGSI_TEXTURE_1D:
1889 FETCH(&r[0], 0, TGSI_CHAN_X);
1890
1891 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1892
1893 fetch_texel(mach->Sampler, unit, unit,
1894 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1895 derivs, offsets, tgsi_sampler_derivs_explicit,
1896 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1897 break;
1898
1899 case TGSI_TEXTURE_SHADOW1D:
1900 case TGSI_TEXTURE_1D_ARRAY:
1901 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1902 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
1903 FETCH(&r[0], 0, TGSI_CHAN_X);
1904 FETCH(&r[1], 0, TGSI_CHAN_Y);
1905 FETCH(&r[2], 0, TGSI_CHAN_Z);
1906
1907 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1908
1909 fetch_texel(mach->Sampler, unit, unit,
1910 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1911 derivs, offsets, tgsi_sampler_derivs_explicit,
1912 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1913 break;
1914
1915 case TGSI_TEXTURE_2D:
1916 case TGSI_TEXTURE_RECT:
1917 FETCH(&r[0], 0, TGSI_CHAN_X);
1918 FETCH(&r[1], 0, TGSI_CHAN_Y);
1919
1920 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1921 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1922
1923 fetch_texel(mach->Sampler, unit, unit,
1924 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1925 derivs, offsets, tgsi_sampler_derivs_explicit,
1926 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1927 break;
1928
1929
1930 case TGSI_TEXTURE_SHADOW2D:
1931 case TGSI_TEXTURE_SHADOWRECT:
1932 case TGSI_TEXTURE_2D_ARRAY:
1933 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1934 /* only SHADOW2D_ARRAY actually needs W */
1935 FETCH(&r[0], 0, TGSI_CHAN_X);
1936 FETCH(&r[1], 0, TGSI_CHAN_Y);
1937 FETCH(&r[2], 0, TGSI_CHAN_Z);
1938 FETCH(&r[3], 0, TGSI_CHAN_W);
1939
1940 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1941 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1942
1943 fetch_texel(mach->Sampler, unit, unit,
1944 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1945 derivs, offsets, tgsi_sampler_derivs_explicit,
1946 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1947 break;
1948
1949 case TGSI_TEXTURE_3D:
1950 case TGSI_TEXTURE_CUBE:
1951 case TGSI_TEXTURE_CUBE_ARRAY:
1952 case TGSI_TEXTURE_SHADOWCUBE:
1953 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
1954 FETCH(&r[0], 0, TGSI_CHAN_X);
1955 FETCH(&r[1], 0, TGSI_CHAN_Y);
1956 FETCH(&r[2], 0, TGSI_CHAN_Z);
1957 FETCH(&r[3], 0, TGSI_CHAN_W);
1958
1959 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1960 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1961 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
1962
1963 fetch_texel(mach->Sampler, unit, unit,
1964 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1965 derivs, offsets, tgsi_sampler_derivs_explicit,
1966 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1967 break;
1968
1969 default:
1970 assert(0);
1971 }
1972
1973 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1974 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1975 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1976 }
1977 }
1978 }
1979
1980
1981 static void
1982 exec_txf(struct tgsi_exec_machine *mach,
1983 const struct tgsi_full_instruction *inst)
1984 {
1985 const uint unit = inst->Src[1].Register.Index;
1986 union tgsi_exec_channel r[4];
1987 uint chan;
1988 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1989 int j;
1990 int8_t offsets[3];
1991 unsigned target;
1992
1993 /* always fetch all 3 offsets, overkill but keeps code simple */
1994 fetch_texel_offsets(mach, inst, offsets);
1995
1996 IFETCH(&r[3], 0, TGSI_CHAN_W);
1997
1998 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
1999 target = mach->SamplerViews[unit].Resource;
2000 }
2001 else {
2002 target = inst->Texture.Texture;
2003 }
2004 switch(target) {
2005 case TGSI_TEXTURE_3D:
2006 case TGSI_TEXTURE_2D_ARRAY:
2007 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2008 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2009 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2010 /* fallthrough */
2011 case TGSI_TEXTURE_2D:
2012 case TGSI_TEXTURE_RECT:
2013 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2014 case TGSI_TEXTURE_SHADOW2D:
2015 case TGSI_TEXTURE_SHADOWRECT:
2016 case TGSI_TEXTURE_1D_ARRAY:
2017 case TGSI_TEXTURE_2D_MSAA:
2018 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2019 /* fallthrough */
2020 case TGSI_TEXTURE_BUFFER:
2021 case TGSI_TEXTURE_1D:
2022 case TGSI_TEXTURE_SHADOW1D:
2023 IFETCH(&r[0], 0, TGSI_CHAN_X);
2024 break;
2025 default:
2026 assert(0);
2027 break;
2028 }
2029
2030 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2031 offsets, rgba);
2032
2033 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2034 r[0].f[j] = rgba[0][j];
2035 r[1].f[j] = rgba[1][j];
2036 r[2].f[j] = rgba[2][j];
2037 r[3].f[j] = rgba[3][j];
2038 }
2039
2040 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2041 unsigned char swizzles[4];
2042 swizzles[0] = inst->Src[1].Register.SwizzleX;
2043 swizzles[1] = inst->Src[1].Register.SwizzleY;
2044 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2045 swizzles[3] = inst->Src[1].Register.SwizzleW;
2046
2047 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2048 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2049 store_dest(mach, &r[swizzles[chan]],
2050 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2051 }
2052 }
2053 }
2054 else {
2055 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2056 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2057 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2058 }
2059 }
2060 }
2061 }
2062
2063 static void
2064 exec_txq(struct tgsi_exec_machine *mach,
2065 const struct tgsi_full_instruction *inst)
2066 {
2067 const uint unit = inst->Src[1].Register.Index;
2068 int result[4];
2069 union tgsi_exec_channel r[4], src;
2070 uint chan;
2071 int i,j;
2072
2073 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2074
2075 /* XXX: This interface can't return per-pixel values */
2076 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2077
2078 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2079 for (j = 0; j < 4; j++) {
2080 r[j].i[i] = result[j];
2081 }
2082 }
2083
2084 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2085 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2086 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2087 TGSI_EXEC_DATA_INT);
2088 }
2089 }
2090 }
2091
2092 static void
2093 exec_sample(struct tgsi_exec_machine *mach,
2094 const struct tgsi_full_instruction *inst,
2095 uint modifier, boolean compare)
2096 {
2097 const uint resource_unit = inst->Src[1].Register.Index;
2098 const uint sampler_unit = inst->Src[2].Register.Index;
2099 union tgsi_exec_channel r[4], c1;
2100 const union tgsi_exec_channel *lod = &ZeroVec;
2101 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2102 uint chan;
2103 unsigned char swizzles[4];
2104 int8_t offsets[3];
2105
2106 /* always fetch all 3 offsets, overkill but keeps code simple */
2107 fetch_texel_offsets(mach, inst, offsets);
2108
2109 assert(modifier != TEX_MODIFIER_PROJECTED);
2110
2111 if (modifier != TEX_MODIFIER_NONE) {
2112 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2113 FETCH(&c1, 3, TGSI_CHAN_X);
2114 lod = &c1;
2115 control = tgsi_sampler_lod_bias;
2116 }
2117 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2118 FETCH(&c1, 3, TGSI_CHAN_X);
2119 lod = &c1;
2120 control = tgsi_sampler_lod_explicit;
2121 }
2122 else {
2123 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2124 control = tgsi_sampler_lod_zero;
2125 }
2126 }
2127
2128 FETCH(&r[0], 0, TGSI_CHAN_X);
2129
2130 switch (mach->SamplerViews[resource_unit].Resource) {
2131 case TGSI_TEXTURE_1D:
2132 if (compare) {
2133 FETCH(&r[2], 3, TGSI_CHAN_X);
2134 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2135 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2136 NULL, offsets, control,
2137 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2138 }
2139 else {
2140 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2141 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2142 NULL, offsets, control,
2143 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2144 }
2145 break;
2146
2147 case TGSI_TEXTURE_1D_ARRAY:
2148 case TGSI_TEXTURE_2D:
2149 case TGSI_TEXTURE_RECT:
2150 FETCH(&r[1], 0, TGSI_CHAN_Y);
2151 if (compare) {
2152 FETCH(&r[2], 3, TGSI_CHAN_X);
2153 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2154 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2155 NULL, offsets, control,
2156 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2157 }
2158 else {
2159 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2160 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2161 NULL, offsets, control,
2162 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2163 }
2164 break;
2165
2166 case TGSI_TEXTURE_2D_ARRAY:
2167 case TGSI_TEXTURE_3D:
2168 case TGSI_TEXTURE_CUBE:
2169 FETCH(&r[1], 0, TGSI_CHAN_Y);
2170 FETCH(&r[2], 0, TGSI_CHAN_Z);
2171 if(compare) {
2172 FETCH(&r[3], 3, TGSI_CHAN_X);
2173 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2174 &r[0], &r[1], &r[2], &r[3], lod,
2175 NULL, offsets, control,
2176 &r[0], &r[1], &r[2], &r[3]);
2177 }
2178 else {
2179 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2180 &r[0], &r[1], &r[2], &ZeroVec, lod,
2181 NULL, offsets, control,
2182 &r[0], &r[1], &r[2], &r[3]);
2183 }
2184 break;
2185
2186 case TGSI_TEXTURE_CUBE_ARRAY:
2187 FETCH(&r[1], 0, TGSI_CHAN_Y);
2188 FETCH(&r[2], 0, TGSI_CHAN_Z);
2189 FETCH(&r[3], 0, TGSI_CHAN_W);
2190 if(compare) {
2191 FETCH(&r[4], 3, TGSI_CHAN_X);
2192 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2193 &r[0], &r[1], &r[2], &r[3], &r[4],
2194 NULL, offsets, control,
2195 &r[0], &r[1], &r[2], &r[3]);
2196 }
2197 else {
2198 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2199 &r[0], &r[1], &r[2], &r[3], lod,
2200 NULL, offsets, control,
2201 &r[0], &r[1], &r[2], &r[3]);
2202 }
2203 break;
2204
2205
2206 default:
2207 assert(0);
2208 }
2209
2210 swizzles[0] = inst->Src[1].Register.SwizzleX;
2211 swizzles[1] = inst->Src[1].Register.SwizzleY;
2212 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2213 swizzles[3] = inst->Src[1].Register.SwizzleW;
2214
2215 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2216 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2217 store_dest(mach, &r[swizzles[chan]],
2218 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2219 }
2220 }
2221 }
2222
2223 static void
2224 exec_sample_d(struct tgsi_exec_machine *mach,
2225 const struct tgsi_full_instruction *inst)
2226 {
2227 const uint resource_unit = inst->Src[1].Register.Index;
2228 const uint sampler_unit = inst->Src[2].Register.Index;
2229 union tgsi_exec_channel r[4];
2230 float derivs[3][2][TGSI_QUAD_SIZE];
2231 uint chan;
2232 unsigned char swizzles[4];
2233 int8_t offsets[3];
2234
2235 /* always fetch all 3 offsets, overkill but keeps code simple */
2236 fetch_texel_offsets(mach, inst, offsets);
2237
2238 FETCH(&r[0], 0, TGSI_CHAN_X);
2239
2240 switch (mach->SamplerViews[resource_unit].Resource) {
2241 case TGSI_TEXTURE_1D:
2242 case TGSI_TEXTURE_1D_ARRAY:
2243 /* only 1D array actually needs Y */
2244 FETCH(&r[1], 0, TGSI_CHAN_Y);
2245
2246 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2247
2248 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2249 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2250 derivs, offsets, tgsi_sampler_derivs_explicit,
2251 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2252 break;
2253
2254 case TGSI_TEXTURE_2D:
2255 case TGSI_TEXTURE_RECT:
2256 case TGSI_TEXTURE_2D_ARRAY:
2257 /* only 2D array actually needs Z */
2258 FETCH(&r[1], 0, TGSI_CHAN_Y);
2259 FETCH(&r[2], 0, TGSI_CHAN_Z);
2260
2261 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2262 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2263
2264 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2265 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2266 derivs, offsets, tgsi_sampler_derivs_explicit,
2267 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2268 break;
2269
2270 case TGSI_TEXTURE_3D:
2271 case TGSI_TEXTURE_CUBE:
2272 case TGSI_TEXTURE_CUBE_ARRAY:
2273 /* only cube array actually needs W */
2274 FETCH(&r[1], 0, TGSI_CHAN_Y);
2275 FETCH(&r[2], 0, TGSI_CHAN_Z);
2276 FETCH(&r[3], 0, TGSI_CHAN_W);
2277
2278 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2279 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2280 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2281
2282 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2283 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2284 derivs, offsets, tgsi_sampler_derivs_explicit,
2285 &r[0], &r[1], &r[2], &r[3]);
2286 break;
2287
2288 default:
2289 assert(0);
2290 }
2291
2292 swizzles[0] = inst->Src[1].Register.SwizzleX;
2293 swizzles[1] = inst->Src[1].Register.SwizzleY;
2294 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2295 swizzles[3] = inst->Src[1].Register.SwizzleW;
2296
2297 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2298 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2299 store_dest(mach, &r[swizzles[chan]],
2300 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2301 }
2302 }
2303 }
2304
2305
2306 /**
2307 * Evaluate a constant-valued coefficient at the position of the
2308 * current quad.
2309 */
2310 static void
2311 eval_constant_coef(
2312 struct tgsi_exec_machine *mach,
2313 unsigned attrib,
2314 unsigned chan )
2315 {
2316 unsigned i;
2317
2318 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2319 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2320 }
2321 }
2322
2323 /**
2324 * Evaluate a linear-valued coefficient at the position of the
2325 * current quad.
2326 */
2327 static void
2328 eval_linear_coef(
2329 struct tgsi_exec_machine *mach,
2330 unsigned attrib,
2331 unsigned chan )
2332 {
2333 const float x = mach->QuadPos.xyzw[0].f[0];
2334 const float y = mach->QuadPos.xyzw[1].f[0];
2335 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2336 const float dady = mach->InterpCoefs[attrib].dady[chan];
2337 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2338 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2339 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2340 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2341 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2342 }
2343
2344 /**
2345 * Evaluate a perspective-valued coefficient at the position of the
2346 * current quad.
2347 */
2348 static void
2349 eval_perspective_coef(
2350 struct tgsi_exec_machine *mach,
2351 unsigned attrib,
2352 unsigned chan )
2353 {
2354 const float x = mach->QuadPos.xyzw[0].f[0];
2355 const float y = mach->QuadPos.xyzw[1].f[0];
2356 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2357 const float dady = mach->InterpCoefs[attrib].dady[chan];
2358 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2359 const float *w = mach->QuadPos.xyzw[3].f;
2360 /* divide by W here */
2361 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2362 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2363 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2364 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2365 }
2366
2367
2368 typedef void (* eval_coef_func)(
2369 struct tgsi_exec_machine *mach,
2370 unsigned attrib,
2371 unsigned chan );
2372
2373 static void
2374 exec_declaration(struct tgsi_exec_machine *mach,
2375 const struct tgsi_full_declaration *decl)
2376 {
2377 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2378 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2379 return;
2380 }
2381
2382 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2383 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2384 uint first, last, mask;
2385
2386 first = decl->Range.First;
2387 last = decl->Range.Last;
2388 mask = decl->Declaration.UsageMask;
2389
2390 /* XXX we could remove this special-case code since
2391 * mach->InterpCoefs[first].a0 should already have the
2392 * front/back-face value. But we should first update the
2393 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2394 * Then, we could remove the tgsi_exec_machine::Face field.
2395 */
2396 /* XXX make FACE a system value */
2397 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2398 uint i;
2399
2400 assert(decl->Semantic.Index == 0);
2401 assert(first == last);
2402
2403 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2404 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2405 }
2406 } else {
2407 eval_coef_func eval;
2408 uint i, j;
2409
2410 switch (decl->Interp.Interpolate) {
2411 case TGSI_INTERPOLATE_CONSTANT:
2412 eval = eval_constant_coef;
2413 break;
2414
2415 case TGSI_INTERPOLATE_LINEAR:
2416 eval = eval_linear_coef;
2417 break;
2418
2419 case TGSI_INTERPOLATE_PERSPECTIVE:
2420 eval = eval_perspective_coef;
2421 break;
2422
2423 case TGSI_INTERPOLATE_COLOR:
2424 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2425 break;
2426
2427 default:
2428 assert(0);
2429 return;
2430 }
2431
2432 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2433 if (mask & (1 << j)) {
2434 for (i = first; i <= last; i++) {
2435 eval(mach, i, j);
2436 }
2437 }
2438 }
2439 }
2440
2441 if (DEBUG_EXECUTION) {
2442 uint i, j;
2443 for (i = first; i <= last; ++i) {
2444 debug_printf("IN[%2u] = ", i);
2445 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2446 if (j > 0) {
2447 debug_printf(" ");
2448 }
2449 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2450 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2451 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2452 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2453 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2454 }
2455 }
2456 }
2457 }
2458 }
2459
2460 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2461 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2462 }
2463 }
2464
2465
2466 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2467
2468 static void
2469 exec_vector(struct tgsi_exec_machine *mach,
2470 const struct tgsi_full_instruction *inst,
2471 micro_op op,
2472 enum tgsi_exec_datatype dst_datatype)
2473 {
2474 unsigned int chan;
2475
2476 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2477 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2478 union tgsi_exec_channel dst;
2479
2480 op(&dst);
2481 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2482 }
2483 }
2484 }
2485
2486 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2487 const union tgsi_exec_channel *src);
2488
2489 static void
2490 exec_scalar_unary(struct tgsi_exec_machine *mach,
2491 const struct tgsi_full_instruction *inst,
2492 micro_unary_op op,
2493 enum tgsi_exec_datatype dst_datatype,
2494 enum tgsi_exec_datatype src_datatype)
2495 {
2496 unsigned int chan;
2497 union tgsi_exec_channel src;
2498 union tgsi_exec_channel dst;
2499
2500 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2501 op(&dst, &src);
2502 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2503 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2504 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2505 }
2506 }
2507 }
2508
2509 static void
2510 exec_vector_unary(struct tgsi_exec_machine *mach,
2511 const struct tgsi_full_instruction *inst,
2512 micro_unary_op op,
2513 enum tgsi_exec_datatype dst_datatype,
2514 enum tgsi_exec_datatype src_datatype)
2515 {
2516 unsigned int chan;
2517 struct tgsi_exec_vector dst;
2518
2519 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2520 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2521 union tgsi_exec_channel src;
2522
2523 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2524 op(&dst.xyzw[chan], &src);
2525 }
2526 }
2527 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2528 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2529 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2530 }
2531 }
2532 }
2533
2534 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2535 const union tgsi_exec_channel *src0,
2536 const union tgsi_exec_channel *src1);
2537
2538 static void
2539 exec_scalar_binary(struct tgsi_exec_machine *mach,
2540 const struct tgsi_full_instruction *inst,
2541 micro_binary_op op,
2542 enum tgsi_exec_datatype dst_datatype,
2543 enum tgsi_exec_datatype src_datatype)
2544 {
2545 unsigned int chan;
2546 union tgsi_exec_channel src[2];
2547 union tgsi_exec_channel dst;
2548
2549 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2550 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2551 op(&dst, &src[0], &src[1]);
2552 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2553 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2554 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2555 }
2556 }
2557 }
2558
2559 static void
2560 exec_vector_binary(struct tgsi_exec_machine *mach,
2561 const struct tgsi_full_instruction *inst,
2562 micro_binary_op op,
2563 enum tgsi_exec_datatype dst_datatype,
2564 enum tgsi_exec_datatype src_datatype)
2565 {
2566 unsigned int chan;
2567 struct tgsi_exec_vector dst;
2568
2569 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2570 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2571 union tgsi_exec_channel src[2];
2572
2573 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2574 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2575 op(&dst.xyzw[chan], &src[0], &src[1]);
2576 }
2577 }
2578 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2579 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2580 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2581 }
2582 }
2583 }
2584
2585 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2586 const union tgsi_exec_channel *src0,
2587 const union tgsi_exec_channel *src1,
2588 const union tgsi_exec_channel *src2);
2589
2590 static void
2591 exec_vector_trinary(struct tgsi_exec_machine *mach,
2592 const struct tgsi_full_instruction *inst,
2593 micro_trinary_op op,
2594 enum tgsi_exec_datatype dst_datatype,
2595 enum tgsi_exec_datatype src_datatype)
2596 {
2597 unsigned int chan;
2598 struct tgsi_exec_vector dst;
2599
2600 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2601 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2602 union tgsi_exec_channel src[3];
2603
2604 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2605 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2606 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2607 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2608 }
2609 }
2610 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2611 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2612 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2613 }
2614 }
2615 }
2616
2617 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2618 const union tgsi_exec_channel *src0,
2619 const union tgsi_exec_channel *src1,
2620 const union tgsi_exec_channel *src2,
2621 const union tgsi_exec_channel *src3);
2622
2623 static void
2624 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2625 const struct tgsi_full_instruction *inst,
2626 micro_quaternary_op op,
2627 enum tgsi_exec_datatype dst_datatype,
2628 enum tgsi_exec_datatype src_datatype)
2629 {
2630 unsigned int chan;
2631 struct tgsi_exec_vector dst;
2632
2633 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2634 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2635 union tgsi_exec_channel src[4];
2636
2637 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2638 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2639 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2640 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2641 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2642 }
2643 }
2644 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2645 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2646 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2647 }
2648 }
2649 }
2650
2651 static void
2652 exec_dp3(struct tgsi_exec_machine *mach,
2653 const struct tgsi_full_instruction *inst)
2654 {
2655 unsigned int chan;
2656 union tgsi_exec_channel arg[3];
2657
2658 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2659 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2660 micro_mul(&arg[2], &arg[0], &arg[1]);
2661
2662 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2663 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2664 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2665 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2666 }
2667
2668 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2669 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2670 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2671 }
2672 }
2673 }
2674
2675 static void
2676 exec_dp4(struct tgsi_exec_machine *mach,
2677 const struct tgsi_full_instruction *inst)
2678 {
2679 unsigned int chan;
2680 union tgsi_exec_channel arg[3];
2681
2682 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2683 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2684 micro_mul(&arg[2], &arg[0], &arg[1]);
2685
2686 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2687 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2688 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2689 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2690 }
2691
2692 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2693 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2694 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2695 }
2696 }
2697 }
2698
2699 static void
2700 exec_dp2a(struct tgsi_exec_machine *mach,
2701 const struct tgsi_full_instruction *inst)
2702 {
2703 unsigned int chan;
2704 union tgsi_exec_channel arg[3];
2705
2706 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2707 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2708 micro_mul(&arg[2], &arg[0], &arg[1]);
2709
2710 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2711 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2712 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2713
2714 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2715 micro_add(&arg[0], &arg[0], &arg[1]);
2716
2717 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2718 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2719 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2720 }
2721 }
2722 }
2723
2724 static void
2725 exec_dph(struct tgsi_exec_machine *mach,
2726 const struct tgsi_full_instruction *inst)
2727 {
2728 unsigned int chan;
2729 union tgsi_exec_channel arg[3];
2730
2731 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2732 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2733 micro_mul(&arg[2], &arg[0], &arg[1]);
2734
2735 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2736 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2737 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2738
2739 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2740 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2741 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2742
2743 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2744 micro_add(&arg[0], &arg[0], &arg[1]);
2745
2746 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2747 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2748 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2749 }
2750 }
2751 }
2752
2753 static void
2754 exec_dp2(struct tgsi_exec_machine *mach,
2755 const struct tgsi_full_instruction *inst)
2756 {
2757 unsigned int chan;
2758 union tgsi_exec_channel arg[3];
2759
2760 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2761 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2762 micro_mul(&arg[2], &arg[0], &arg[1]);
2763
2764 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2765 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2766 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2767
2768 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2769 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2770 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2771 }
2772 }
2773 }
2774
2775 static void
2776 exec_nrm4(struct tgsi_exec_machine *mach,
2777 const struct tgsi_full_instruction *inst)
2778 {
2779 unsigned int chan;
2780 union tgsi_exec_channel arg[4];
2781 union tgsi_exec_channel scale;
2782
2783 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2784 micro_mul(&scale, &arg[0], &arg[0]);
2785
2786 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2787 union tgsi_exec_channel product;
2788
2789 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2790 micro_mul(&product, &arg[chan], &arg[chan]);
2791 micro_add(&scale, &scale, &product);
2792 }
2793
2794 micro_rsq(&scale, &scale);
2795
2796 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_W; chan++) {
2797 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2798 micro_mul(&arg[chan], &arg[chan], &scale);
2799 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2800 }
2801 }
2802 }
2803
2804 static void
2805 exec_nrm3(struct tgsi_exec_machine *mach,
2806 const struct tgsi_full_instruction *inst)
2807 {
2808 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2809 unsigned int chan;
2810 union tgsi_exec_channel arg[3];
2811 union tgsi_exec_channel scale;
2812
2813 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2814 micro_mul(&scale, &arg[0], &arg[0]);
2815
2816 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2817 union tgsi_exec_channel product;
2818
2819 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2820 micro_mul(&product, &arg[chan], &arg[chan]);
2821 micro_add(&scale, &scale, &product);
2822 }
2823
2824 micro_rsq(&scale, &scale);
2825
2826 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_Z; chan++) {
2827 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2828 micro_mul(&arg[chan], &arg[chan], &scale);
2829 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2830 }
2831 }
2832 }
2833
2834 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2835 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2836 }
2837 }
2838
2839 static void
2840 exec_scs(struct tgsi_exec_machine *mach,
2841 const struct tgsi_full_instruction *inst)
2842 {
2843 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2844 union tgsi_exec_channel arg;
2845 union tgsi_exec_channel result;
2846
2847 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2848
2849 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2850 micro_cos(&result, &arg);
2851 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2852 }
2853 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2854 micro_sin(&result, &arg);
2855 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2856 }
2857 }
2858 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2859 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2860 }
2861 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2862 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2863 }
2864 }
2865
2866 static void
2867 exec_x2d(struct tgsi_exec_machine *mach,
2868 const struct tgsi_full_instruction *inst)
2869 {
2870 union tgsi_exec_channel r[4];
2871 union tgsi_exec_channel d[2];
2872
2873 fetch_source(mach, &r[0], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2874 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2875 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2876 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2877 micro_mul(&r[2], &r[2], &r[0]);
2878 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2879 micro_mul(&r[3], &r[3], &r[1]);
2880 micro_add(&r[2], &r[2], &r[3]);
2881 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2882 micro_add(&d[0], &r[2], &r[3]);
2883 }
2884 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2885 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2886 micro_mul(&r[2], &r[2], &r[0]);
2887 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2888 micro_mul(&r[3], &r[3], &r[1]);
2889 micro_add(&r[2], &r[2], &r[3]);
2890 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2891 micro_add(&d[1], &r[2], &r[3]);
2892 }
2893 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2894 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2895 }
2896 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2897 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2898 }
2899 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2900 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2901 }
2902 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2903 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2904 }
2905 }
2906
2907 static void
2908 exec_rfl(struct tgsi_exec_machine *mach,
2909 const struct tgsi_full_instruction *inst)
2910 {
2911 union tgsi_exec_channel r[9];
2912
2913 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2914 /* r0 = dp3(src0, src0) */
2915 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2916 micro_mul(&r[0], &r[2], &r[2]);
2917 fetch_source(mach, &r[4], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2918 micro_mul(&r[8], &r[4], &r[4]);
2919 micro_add(&r[0], &r[0], &r[8]);
2920 fetch_source(mach, &r[6], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2921 micro_mul(&r[8], &r[6], &r[6]);
2922 micro_add(&r[0], &r[0], &r[8]);
2923
2924 /* r1 = dp3(src0, src1) */
2925 fetch_source(mach, &r[3], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2926 micro_mul(&r[1], &r[2], &r[3]);
2927 fetch_source(mach, &r[5], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2928 micro_mul(&r[8], &r[4], &r[5]);
2929 micro_add(&r[1], &r[1], &r[8]);
2930 fetch_source(mach, &r[7], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2931 micro_mul(&r[8], &r[6], &r[7]);
2932 micro_add(&r[1], &r[1], &r[8]);
2933
2934 /* r1 = 2 * r1 / r0 */
2935 micro_add(&r[1], &r[1], &r[1]);
2936 micro_div(&r[1], &r[1], &r[0]);
2937
2938 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2939 micro_mul(&r[2], &r[2], &r[1]);
2940 micro_sub(&r[2], &r[2], &r[3]);
2941 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2942 }
2943 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2944 micro_mul(&r[4], &r[4], &r[1]);
2945 micro_sub(&r[4], &r[4], &r[5]);
2946 store_dest(mach, &r[4], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2947 }
2948 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2949 micro_mul(&r[6], &r[6], &r[1]);
2950 micro_sub(&r[6], &r[6], &r[7]);
2951 store_dest(mach, &r[6], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2952 }
2953 }
2954 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2955 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2956 }
2957 }
2958
2959 static void
2960 exec_xpd(struct tgsi_exec_machine *mach,
2961 const struct tgsi_full_instruction *inst)
2962 {
2963 union tgsi_exec_channel r[6];
2964 union tgsi_exec_channel d[3];
2965
2966 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2967 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2968
2969 micro_mul(&r[2], &r[0], &r[1]);
2970
2971 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2972 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2973
2974 micro_mul(&r[5], &r[3], &r[4] );
2975 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
2976
2977 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2978
2979 micro_mul(&r[3], &r[3], &r[2]);
2980
2981 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2982
2983 micro_mul(&r[1], &r[1], &r[5]);
2984 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
2985
2986 micro_mul(&r[5], &r[5], &r[4]);
2987 micro_mul(&r[0], &r[0], &r[2]);
2988 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
2989
2990 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2991 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2992 }
2993 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2994 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2995 }
2996 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2997 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2998 }
2999 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3000 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3001 }
3002 }
3003
3004 static void
3005 exec_dst(struct tgsi_exec_machine *mach,
3006 const struct tgsi_full_instruction *inst)
3007 {
3008 union tgsi_exec_channel r[2];
3009 union tgsi_exec_channel d[4];
3010
3011 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3012 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3013 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3014 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3015 }
3016 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3017 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3018 }
3019 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3020 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3021 }
3022
3023 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3024 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3025 }
3026 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3027 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3028 }
3029 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3030 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3031 }
3032 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3033 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3034 }
3035 }
3036
3037 static void
3038 exec_log(struct tgsi_exec_machine *mach,
3039 const struct tgsi_full_instruction *inst)
3040 {
3041 union tgsi_exec_channel r[3];
3042
3043 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3044 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3045 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3046 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3047 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3048 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3049 }
3050 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3051 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3052 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3053 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3054 }
3055 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3056 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3057 }
3058 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3059 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3060 }
3061 }
3062
3063 static void
3064 exec_exp(struct tgsi_exec_machine *mach,
3065 const struct tgsi_full_instruction *inst)
3066 {
3067 union tgsi_exec_channel r[3];
3068
3069 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3070 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3071 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3072 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3073 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3074 }
3075 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3076 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3077 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3078 }
3079 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3080 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3081 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3082 }
3083 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3084 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3085 }
3086 }
3087
3088 static void
3089 exec_lit(struct tgsi_exec_machine *mach,
3090 const struct tgsi_full_instruction *inst)
3091 {
3092 union tgsi_exec_channel r[3];
3093 union tgsi_exec_channel d[3];
3094
3095 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3096 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3097 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3098 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3099 micro_max(&r[1], &r[1], &ZeroVec);
3100
3101 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3102 micro_min(&r[2], &r[2], &P128Vec);
3103 micro_max(&r[2], &r[2], &M128Vec);
3104 micro_pow(&r[1], &r[1], &r[2]);
3105 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3106 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3107 }
3108 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3109 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3110 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3111 }
3112 }
3113 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3114 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3115 }
3116
3117 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3118 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3119 }
3120 }
3121
3122 static void
3123 exec_break(struct tgsi_exec_machine *mach)
3124 {
3125 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3126 /* turn off loop channels for each enabled exec channel */
3127 mach->LoopMask &= ~mach->ExecMask;
3128 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3129 UPDATE_EXEC_MASK(mach);
3130 } else {
3131 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3132
3133 mach->Switch.mask = 0x0;
3134
3135 UPDATE_EXEC_MASK(mach);
3136 }
3137 }
3138
3139 static void
3140 exec_switch(struct tgsi_exec_machine *mach,
3141 const struct tgsi_full_instruction *inst)
3142 {
3143 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3144 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3145
3146 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3147 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3148 mach->Switch.mask = 0x0;
3149 mach->Switch.defaultMask = 0x0;
3150
3151 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3152 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3153
3154 UPDATE_EXEC_MASK(mach);
3155 }
3156
3157 static void
3158 exec_case(struct tgsi_exec_machine *mach,
3159 const struct tgsi_full_instruction *inst)
3160 {
3161 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3162 union tgsi_exec_channel src;
3163 uint mask = 0;
3164
3165 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3166
3167 if (mach->Switch.selector.u[0] == src.u[0]) {
3168 mask |= 0x1;
3169 }
3170 if (mach->Switch.selector.u[1] == src.u[1]) {
3171 mask |= 0x2;
3172 }
3173 if (mach->Switch.selector.u[2] == src.u[2]) {
3174 mask |= 0x4;
3175 }
3176 if (mach->Switch.selector.u[3] == src.u[3]) {
3177 mask |= 0x8;
3178 }
3179
3180 mach->Switch.defaultMask |= mask;
3181
3182 mach->Switch.mask |= mask & prevMask;
3183
3184 UPDATE_EXEC_MASK(mach);
3185 }
3186
3187 /* FIXME: this will only work if default is last */
3188 static void
3189 exec_default(struct tgsi_exec_machine *mach)
3190 {
3191 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3192
3193 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3194
3195 UPDATE_EXEC_MASK(mach);
3196 }
3197
3198 static void
3199 exec_endswitch(struct tgsi_exec_machine *mach)
3200 {
3201 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3202 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3203
3204 UPDATE_EXEC_MASK(mach);
3205 }
3206
3207 static void
3208 micro_i2f(union tgsi_exec_channel *dst,
3209 const union tgsi_exec_channel *src)
3210 {
3211 dst->f[0] = (float)src->i[0];
3212 dst->f[1] = (float)src->i[1];
3213 dst->f[2] = (float)src->i[2];
3214 dst->f[3] = (float)src->i[3];
3215 }
3216
3217 static void
3218 micro_not(union tgsi_exec_channel *dst,
3219 const union tgsi_exec_channel *src)
3220 {
3221 dst->u[0] = ~src->u[0];
3222 dst->u[1] = ~src->u[1];
3223 dst->u[2] = ~src->u[2];
3224 dst->u[3] = ~src->u[3];
3225 }
3226
3227 static void
3228 micro_shl(union tgsi_exec_channel *dst,
3229 const union tgsi_exec_channel *src0,
3230 const union tgsi_exec_channel *src1)
3231 {
3232 unsigned masked_count;
3233 masked_count = src1->u[0] & 0x1f;
3234 dst->u[0] = src0->u[0] << masked_count;
3235 masked_count = src1->u[1] & 0x1f;
3236 dst->u[1] = src0->u[1] << masked_count;
3237 masked_count = src1->u[2] & 0x1f;
3238 dst->u[2] = src0->u[2] << masked_count;
3239 masked_count = src1->u[3] & 0x1f;
3240 dst->u[3] = src0->u[3] << masked_count;
3241 }
3242
3243 static void
3244 micro_and(union tgsi_exec_channel *dst,
3245 const union tgsi_exec_channel *src0,
3246 const union tgsi_exec_channel *src1)
3247 {
3248 dst->u[0] = src0->u[0] & src1->u[0];
3249 dst->u[1] = src0->u[1] & src1->u[1];
3250 dst->u[2] = src0->u[2] & src1->u[2];
3251 dst->u[3] = src0->u[3] & src1->u[3];
3252 }
3253
3254 static void
3255 micro_or(union tgsi_exec_channel *dst,
3256 const union tgsi_exec_channel *src0,
3257 const union tgsi_exec_channel *src1)
3258 {
3259 dst->u[0] = src0->u[0] | src1->u[0];
3260 dst->u[1] = src0->u[1] | src1->u[1];
3261 dst->u[2] = src0->u[2] | src1->u[2];
3262 dst->u[3] = src0->u[3] | src1->u[3];
3263 }
3264
3265 static void
3266 micro_xor(union tgsi_exec_channel *dst,
3267 const union tgsi_exec_channel *src0,
3268 const union tgsi_exec_channel *src1)
3269 {
3270 dst->u[0] = src0->u[0] ^ src1->u[0];
3271 dst->u[1] = src0->u[1] ^ src1->u[1];
3272 dst->u[2] = src0->u[2] ^ src1->u[2];
3273 dst->u[3] = src0->u[3] ^ src1->u[3];
3274 }
3275
3276 static void
3277 micro_mod(union tgsi_exec_channel *dst,
3278 const union tgsi_exec_channel *src0,
3279 const union tgsi_exec_channel *src1)
3280 {
3281 dst->i[0] = src0->i[0] % src1->i[0];
3282 dst->i[1] = src0->i[1] % src1->i[1];
3283 dst->i[2] = src0->i[2] % src1->i[2];
3284 dst->i[3] = src0->i[3] % src1->i[3];
3285 }
3286
3287 static void
3288 micro_f2i(union tgsi_exec_channel *dst,
3289 const union tgsi_exec_channel *src)
3290 {
3291 dst->i[0] = (int)src->f[0];
3292 dst->i[1] = (int)src->f[1];
3293 dst->i[2] = (int)src->f[2];
3294 dst->i[3] = (int)src->f[3];
3295 }
3296
3297 static void
3298 micro_fseq(union tgsi_exec_channel *dst,
3299 const union tgsi_exec_channel *src0,
3300 const union tgsi_exec_channel *src1)
3301 {
3302 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
3303 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
3304 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
3305 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
3306 }
3307
3308 static void
3309 micro_fsge(union tgsi_exec_channel *dst,
3310 const union tgsi_exec_channel *src0,
3311 const union tgsi_exec_channel *src1)
3312 {
3313 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
3314 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
3315 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
3316 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
3317 }
3318
3319 static void
3320 micro_fslt(union tgsi_exec_channel *dst,
3321 const union tgsi_exec_channel *src0,
3322 const union tgsi_exec_channel *src1)
3323 {
3324 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
3325 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
3326 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
3327 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
3328 }
3329
3330 static void
3331 micro_fsne(union tgsi_exec_channel *dst,
3332 const union tgsi_exec_channel *src0,
3333 const union tgsi_exec_channel *src1)
3334 {
3335 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
3336 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
3337 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
3338 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
3339 }
3340
3341 static void
3342 micro_idiv(union tgsi_exec_channel *dst,
3343 const union tgsi_exec_channel *src0,
3344 const union tgsi_exec_channel *src1)
3345 {
3346 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
3347 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
3348 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
3349 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
3350 }
3351
3352 static void
3353 micro_imax(union tgsi_exec_channel *dst,
3354 const union tgsi_exec_channel *src0,
3355 const union tgsi_exec_channel *src1)
3356 {
3357 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3358 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3359 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3360 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3361 }
3362
3363 static void
3364 micro_imin(union tgsi_exec_channel *dst,
3365 const union tgsi_exec_channel *src0,
3366 const union tgsi_exec_channel *src1)
3367 {
3368 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3369 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3370 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3371 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3372 }
3373
3374 static void
3375 micro_isge(union tgsi_exec_channel *dst,
3376 const union tgsi_exec_channel *src0,
3377 const union tgsi_exec_channel *src1)
3378 {
3379 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3380 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3381 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3382 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3383 }
3384
3385 static void
3386 micro_ishr(union tgsi_exec_channel *dst,
3387 const union tgsi_exec_channel *src0,
3388 const union tgsi_exec_channel *src1)
3389 {
3390 unsigned masked_count;
3391 masked_count = src1->i[0] & 0x1f;
3392 dst->i[0] = src0->i[0] >> masked_count;
3393 masked_count = src1->i[1] & 0x1f;
3394 dst->i[1] = src0->i[1] >> masked_count;
3395 masked_count = src1->i[2] & 0x1f;
3396 dst->i[2] = src0->i[2] >> masked_count;
3397 masked_count = src1->i[3] & 0x1f;
3398 dst->i[3] = src0->i[3] >> masked_count;
3399 }
3400
3401 static void
3402 micro_islt(union tgsi_exec_channel *dst,
3403 const union tgsi_exec_channel *src0,
3404 const union tgsi_exec_channel *src1)
3405 {
3406 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3407 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3408 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3409 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3410 }
3411
3412 static void
3413 micro_f2u(union tgsi_exec_channel *dst,
3414 const union tgsi_exec_channel *src)
3415 {
3416 dst->u[0] = (uint)src->f[0];
3417 dst->u[1] = (uint)src->f[1];
3418 dst->u[2] = (uint)src->f[2];
3419 dst->u[3] = (uint)src->f[3];
3420 }
3421
3422 static void
3423 micro_u2f(union tgsi_exec_channel *dst,
3424 const union tgsi_exec_channel *src)
3425 {
3426 dst->f[0] = (float)src->u[0];
3427 dst->f[1] = (float)src->u[1];
3428 dst->f[2] = (float)src->u[2];
3429 dst->f[3] = (float)src->u[3];
3430 }
3431
3432 static void
3433 micro_uadd(union tgsi_exec_channel *dst,
3434 const union tgsi_exec_channel *src0,
3435 const union tgsi_exec_channel *src1)
3436 {
3437 dst->u[0] = src0->u[0] + src1->u[0];
3438 dst->u[1] = src0->u[1] + src1->u[1];
3439 dst->u[2] = src0->u[2] + src1->u[2];
3440 dst->u[3] = src0->u[3] + src1->u[3];
3441 }
3442
3443 static void
3444 micro_udiv(union tgsi_exec_channel *dst,
3445 const union tgsi_exec_channel *src0,
3446 const union tgsi_exec_channel *src1)
3447 {
3448 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
3449 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
3450 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
3451 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
3452 }
3453
3454 static void
3455 micro_umad(union tgsi_exec_channel *dst,
3456 const union tgsi_exec_channel *src0,
3457 const union tgsi_exec_channel *src1,
3458 const union tgsi_exec_channel *src2)
3459 {
3460 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3461 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3462 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3463 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3464 }
3465
3466 static void
3467 micro_umax(union tgsi_exec_channel *dst,
3468 const union tgsi_exec_channel *src0,
3469 const union tgsi_exec_channel *src1)
3470 {
3471 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3472 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3473 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3474 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3475 }
3476
3477 static void
3478 micro_umin(union tgsi_exec_channel *dst,
3479 const union tgsi_exec_channel *src0,
3480 const union tgsi_exec_channel *src1)
3481 {
3482 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3483 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3484 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3485 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3486 }
3487
3488 static void
3489 micro_umod(union tgsi_exec_channel *dst,
3490 const union tgsi_exec_channel *src0,
3491 const union tgsi_exec_channel *src1)
3492 {
3493 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
3494 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
3495 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
3496 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
3497 }
3498
3499 static void
3500 micro_umul(union tgsi_exec_channel *dst,
3501 const union tgsi_exec_channel *src0,
3502 const union tgsi_exec_channel *src1)
3503 {
3504 dst->u[0] = src0->u[0] * src1->u[0];
3505 dst->u[1] = src0->u[1] * src1->u[1];
3506 dst->u[2] = src0->u[2] * src1->u[2];
3507 dst->u[3] = src0->u[3] * src1->u[3];
3508 }
3509
3510 static void
3511 micro_imul_hi(union tgsi_exec_channel *dst,
3512 const union tgsi_exec_channel *src0,
3513 const union tgsi_exec_channel *src1)
3514 {
3515 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3516 dst->i[0] = I64M(src0->i[0], src1->i[0]);
3517 dst->i[1] = I64M(src0->i[1], src1->i[1]);
3518 dst->i[2] = I64M(src0->i[2], src1->i[2]);
3519 dst->i[3] = I64M(src0->i[3], src1->i[3]);
3520 #undef I64M
3521 }
3522
3523 static void
3524 micro_umul_hi(union tgsi_exec_channel *dst,
3525 const union tgsi_exec_channel *src0,
3526 const union tgsi_exec_channel *src1)
3527 {
3528 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3529 dst->u[0] = U64M(src0->u[0], src1->u[0]);
3530 dst->u[1] = U64M(src0->u[1], src1->u[1]);
3531 dst->u[2] = U64M(src0->u[2], src1->u[2]);
3532 dst->u[3] = U64M(src0->u[3], src1->u[3]);
3533 #undef U64M
3534 }
3535
3536 static void
3537 micro_useq(union tgsi_exec_channel *dst,
3538 const union tgsi_exec_channel *src0,
3539 const union tgsi_exec_channel *src1)
3540 {
3541 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3542 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3543 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3544 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3545 }
3546
3547 static void
3548 micro_usge(union tgsi_exec_channel *dst,
3549 const union tgsi_exec_channel *src0,
3550 const union tgsi_exec_channel *src1)
3551 {
3552 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3553 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3554 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3555 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3556 }
3557
3558 static void
3559 micro_ushr(union tgsi_exec_channel *dst,
3560 const union tgsi_exec_channel *src0,
3561 const union tgsi_exec_channel *src1)
3562 {
3563 unsigned masked_count;
3564 masked_count = src1->u[0] & 0x1f;
3565 dst->u[0] = src0->u[0] >> masked_count;
3566 masked_count = src1->u[1] & 0x1f;
3567 dst->u[1] = src0->u[1] >> masked_count;
3568 masked_count = src1->u[2] & 0x1f;
3569 dst->u[2] = src0->u[2] >> masked_count;
3570 masked_count = src1->u[3] & 0x1f;
3571 dst->u[3] = src0->u[3] >> masked_count;
3572 }
3573
3574 static void
3575 micro_uslt(union tgsi_exec_channel *dst,
3576 const union tgsi_exec_channel *src0,
3577 const union tgsi_exec_channel *src1)
3578 {
3579 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3580 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3581 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3582 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3583 }
3584
3585 static void
3586 micro_usne(union tgsi_exec_channel *dst,
3587 const union tgsi_exec_channel *src0,
3588 const union tgsi_exec_channel *src1)
3589 {
3590 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3591 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3592 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3593 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3594 }
3595
3596 static void
3597 micro_uarl(union tgsi_exec_channel *dst,
3598 const union tgsi_exec_channel *src)
3599 {
3600 dst->i[0] = src->u[0];
3601 dst->i[1] = src->u[1];
3602 dst->i[2] = src->u[2];
3603 dst->i[3] = src->u[3];
3604 }
3605
3606 static void
3607 micro_ucmp(union tgsi_exec_channel *dst,
3608 const union tgsi_exec_channel *src0,
3609 const union tgsi_exec_channel *src1,
3610 const union tgsi_exec_channel *src2)
3611 {
3612 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3613 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3614 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3615 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3616 }
3617
3618 /**
3619 * Signed bitfield extract (i.e. sign-extend the extracted bits)
3620 */
3621 static void
3622 micro_ibfe(union tgsi_exec_channel *dst,
3623 const union tgsi_exec_channel *src0,
3624 const union tgsi_exec_channel *src1,
3625 const union tgsi_exec_channel *src2)
3626 {
3627 int i;
3628 for (i = 0; i < 4; i++) {
3629 int width = src2->i[i] & 0x1f;
3630 int offset = src1->i[i] & 0x1f;
3631 if (width == 0)
3632 dst->i[i] = 0;
3633 else if (width + offset < 32)
3634 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
3635 else
3636 dst->i[i] = src0->i[i] >> offset;
3637 }
3638 }
3639
3640 /**
3641 * Unsigned bitfield extract
3642 */
3643 static void
3644 micro_ubfe(union tgsi_exec_channel *dst,
3645 const union tgsi_exec_channel *src0,
3646 const union tgsi_exec_channel *src1,
3647 const union tgsi_exec_channel *src2)
3648 {
3649 int i;
3650 for (i = 0; i < 4; i++) {
3651 int width = src2->u[i] & 0x1f;
3652 int offset = src1->u[i] & 0x1f;
3653 if (width == 0)
3654 dst->u[i] = 0;
3655 else if (width + offset < 32)
3656 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
3657 else
3658 dst->u[i] = src0->u[i] >> offset;
3659 }
3660 }
3661
3662 /**
3663 * Bitfield insert: copy low bits from src1 into a region of src0.
3664 */
3665 static void
3666 micro_bfi(union tgsi_exec_channel *dst,
3667 const union tgsi_exec_channel *src0,
3668 const union tgsi_exec_channel *src1,
3669 const union tgsi_exec_channel *src2,
3670 const union tgsi_exec_channel *src3)
3671 {
3672 int i;
3673 for (i = 0; i < 4; i++) {
3674 int width = src3->u[i] & 0x1f;
3675 int offset = src2->u[i] & 0x1f;
3676 int bitmask = ((1 << width) - 1) << offset;
3677 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
3678 }
3679 }
3680
3681 static void
3682 micro_brev(union tgsi_exec_channel *dst,
3683 const union tgsi_exec_channel *src)
3684 {
3685 dst->u[0] = util_bitreverse(src->u[0]);
3686 dst->u[1] = util_bitreverse(src->u[1]);
3687 dst->u[2] = util_bitreverse(src->u[2]);
3688 dst->u[3] = util_bitreverse(src->u[3]);
3689 }
3690
3691 static void
3692 micro_popc(union tgsi_exec_channel *dst,
3693 const union tgsi_exec_channel *src)
3694 {
3695 dst->u[0] = util_bitcount(src->u[0]);
3696 dst->u[1] = util_bitcount(src->u[1]);
3697 dst->u[2] = util_bitcount(src->u[2]);
3698 dst->u[3] = util_bitcount(src->u[3]);
3699 }
3700
3701 static void
3702 micro_lsb(union tgsi_exec_channel *dst,
3703 const union tgsi_exec_channel *src)
3704 {
3705 dst->i[0] = ffs(src->u[0]) - 1;
3706 dst->i[1] = ffs(src->u[1]) - 1;
3707 dst->i[2] = ffs(src->u[2]) - 1;
3708 dst->i[3] = ffs(src->u[3]) - 1;
3709 }
3710
3711 static void
3712 micro_imsb(union tgsi_exec_channel *dst,
3713 const union tgsi_exec_channel *src)
3714 {
3715 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
3716 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
3717 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
3718 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
3719 }
3720
3721 static void
3722 micro_umsb(union tgsi_exec_channel *dst,
3723 const union tgsi_exec_channel *src)
3724 {
3725 dst->i[0] = util_last_bit(src->u[0]) - 1;
3726 dst->i[1] = util_last_bit(src->u[1]) - 1;
3727 dst->i[2] = util_last_bit(src->u[2]) - 1;
3728 dst->i[3] = util_last_bit(src->u[3]) - 1;
3729 }
3730
3731 static void
3732 exec_instruction(
3733 struct tgsi_exec_machine *mach,
3734 const struct tgsi_full_instruction *inst,
3735 int *pc )
3736 {
3737 union tgsi_exec_channel r[10];
3738
3739 (*pc)++;
3740
3741 switch (inst->Instruction.Opcode) {
3742 case TGSI_OPCODE_ARL:
3743 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3744 break;
3745
3746 case TGSI_OPCODE_MOV:
3747 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3748 break;
3749
3750 case TGSI_OPCODE_LIT:
3751 exec_lit(mach, inst);
3752 break;
3753
3754 case TGSI_OPCODE_RCP:
3755 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3756 break;
3757
3758 case TGSI_OPCODE_RSQ:
3759 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3760 break;
3761
3762 case TGSI_OPCODE_EXP:
3763 exec_exp(mach, inst);
3764 break;
3765
3766 case TGSI_OPCODE_LOG:
3767 exec_log(mach, inst);
3768 break;
3769
3770 case TGSI_OPCODE_MUL:
3771 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3772 break;
3773
3774 case TGSI_OPCODE_ADD:
3775 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3776 break;
3777
3778 case TGSI_OPCODE_DP3:
3779 exec_dp3(mach, inst);
3780 break;
3781
3782 case TGSI_OPCODE_DP4:
3783 exec_dp4(mach, inst);
3784 break;
3785
3786 case TGSI_OPCODE_DST:
3787 exec_dst(mach, inst);
3788 break;
3789
3790 case TGSI_OPCODE_MIN:
3791 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3792 break;
3793
3794 case TGSI_OPCODE_MAX:
3795 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3796 break;
3797
3798 case TGSI_OPCODE_SLT:
3799 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3800 break;
3801
3802 case TGSI_OPCODE_SGE:
3803 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3804 break;
3805
3806 case TGSI_OPCODE_MAD:
3807 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3808 break;
3809
3810 case TGSI_OPCODE_SUB:
3811 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3812 break;
3813
3814 case TGSI_OPCODE_LRP:
3815 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3816 break;
3817
3818 case TGSI_OPCODE_CND:
3819 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3820 break;
3821
3822 case TGSI_OPCODE_SQRT:
3823 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3824 break;
3825
3826 case TGSI_OPCODE_DP2A:
3827 exec_dp2a(mach, inst);
3828 break;
3829
3830 case TGSI_OPCODE_FRC:
3831 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3832 break;
3833
3834 case TGSI_OPCODE_CLAMP:
3835 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3836 break;
3837
3838 case TGSI_OPCODE_FLR:
3839 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3840 break;
3841
3842 case TGSI_OPCODE_ROUND:
3843 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3844 break;
3845
3846 case TGSI_OPCODE_EX2:
3847 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3848 break;
3849
3850 case TGSI_OPCODE_LG2:
3851 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3852 break;
3853
3854 case TGSI_OPCODE_POW:
3855 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3856 break;
3857
3858 case TGSI_OPCODE_XPD:
3859 exec_xpd(mach, inst);
3860 break;
3861
3862 case TGSI_OPCODE_ABS:
3863 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3864 break;
3865
3866 case TGSI_OPCODE_RCC:
3867 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3868 break;
3869
3870 case TGSI_OPCODE_DPH:
3871 exec_dph(mach, inst);
3872 break;
3873
3874 case TGSI_OPCODE_COS:
3875 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3876 break;
3877
3878 case TGSI_OPCODE_DDX:
3879 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3880 break;
3881
3882 case TGSI_OPCODE_DDY:
3883 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3884 break;
3885
3886 case TGSI_OPCODE_KILL:
3887 exec_kill (mach, inst);
3888 break;
3889
3890 case TGSI_OPCODE_KILL_IF:
3891 exec_kill_if (mach, inst);
3892 break;
3893
3894 case TGSI_OPCODE_PK2H:
3895 assert (0);
3896 break;
3897
3898 case TGSI_OPCODE_PK2US:
3899 assert (0);
3900 break;
3901
3902 case TGSI_OPCODE_PK4B:
3903 assert (0);
3904 break;
3905
3906 case TGSI_OPCODE_PK4UB:
3907 assert (0);
3908 break;
3909
3910 case TGSI_OPCODE_RFL:
3911 exec_rfl(mach, inst);
3912 break;
3913
3914 case TGSI_OPCODE_SEQ:
3915 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3916 break;
3917
3918 case TGSI_OPCODE_SFL:
3919 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3920 break;
3921
3922 case TGSI_OPCODE_SGT:
3923 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3924 break;
3925
3926 case TGSI_OPCODE_SIN:
3927 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3928 break;
3929
3930 case TGSI_OPCODE_SLE:
3931 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3932 break;
3933
3934 case TGSI_OPCODE_SNE:
3935 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3936 break;
3937
3938 case TGSI_OPCODE_STR:
3939 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3940 break;
3941
3942 case TGSI_OPCODE_TEX:
3943 /* simple texture lookup */
3944 /* src[0] = texcoord */
3945 /* src[1] = sampler unit */
3946 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
3947 break;
3948
3949 case TGSI_OPCODE_TXB:
3950 /* Texture lookup with lod bias */
3951 /* src[0] = texcoord (src[0].w = LOD bias) */
3952 /* src[1] = sampler unit */
3953 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
3954 break;
3955
3956 case TGSI_OPCODE_TXD:
3957 /* Texture lookup with explict partial derivatives */
3958 /* src[0] = texcoord */
3959 /* src[1] = d[strq]/dx */
3960 /* src[2] = d[strq]/dy */
3961 /* src[3] = sampler unit */
3962 exec_txd(mach, inst);
3963 break;
3964
3965 case TGSI_OPCODE_TXL:
3966 /* Texture lookup with explit LOD */
3967 /* src[0] = texcoord (src[0].w = LOD) */
3968 /* src[1] = sampler unit */
3969 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
3970 break;
3971
3972 case TGSI_OPCODE_TXP:
3973 /* Texture lookup with projection */
3974 /* src[0] = texcoord (src[0].w = projection) */
3975 /* src[1] = sampler unit */
3976 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
3977 break;
3978
3979 case TGSI_OPCODE_UP2H:
3980 assert (0);
3981 break;
3982
3983 case TGSI_OPCODE_UP2US:
3984 assert (0);
3985 break;
3986
3987 case TGSI_OPCODE_UP4B:
3988 assert (0);
3989 break;
3990
3991 case TGSI_OPCODE_UP4UB:
3992 assert (0);
3993 break;
3994
3995 case TGSI_OPCODE_X2D:
3996 exec_x2d(mach, inst);
3997 break;
3998
3999 case TGSI_OPCODE_ARA:
4000 assert (0);
4001 break;
4002
4003 case TGSI_OPCODE_ARR:
4004 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4005 break;
4006
4007 case TGSI_OPCODE_BRA:
4008 assert (0);
4009 break;
4010
4011 case TGSI_OPCODE_CAL:
4012 /* skip the call if no execution channels are enabled */
4013 if (mach->ExecMask) {
4014 /* do the call */
4015
4016 /* First, record the depths of the execution stacks.
4017 * This is important for deeply nested/looped return statements.
4018 * We have to unwind the stacks by the correct amount. For a
4019 * real code generator, we could determine the number of entries
4020 * to pop off each stack with simple static analysis and avoid
4021 * implementing this data structure at run time.
4022 */
4023 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
4024 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
4025 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
4026 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
4027 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
4028 /* note that PC was already incremented above */
4029 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
4030
4031 mach->CallStackTop++;
4032
4033 /* Second, push the Cond, Loop, Cont, Func stacks */
4034 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4035 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4036 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4037 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
4038 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4039 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
4040
4041 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4042 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4043 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4044 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
4045 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4046 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
4047
4048 /* Finally, jump to the subroutine */
4049 *pc = inst->Label.Label;
4050 }
4051 break;
4052
4053 case TGSI_OPCODE_RET:
4054 mach->FuncMask &= ~mach->ExecMask;
4055 UPDATE_EXEC_MASK(mach);
4056
4057 if (mach->FuncMask == 0x0) {
4058 /* really return now (otherwise, keep executing */
4059
4060 if (mach->CallStackTop == 0) {
4061 /* returning from main() */
4062 mach->CondStackTop = 0;
4063 mach->LoopStackTop = 0;
4064 *pc = -1;
4065 return;
4066 }
4067
4068 assert(mach->CallStackTop > 0);
4069 mach->CallStackTop--;
4070
4071 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4072 mach->CondMask = mach->CondStack[mach->CondStackTop];
4073
4074 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4075 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4076
4077 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4078 mach->ContMask = mach->ContStack[mach->ContStackTop];
4079
4080 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4081 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4082
4083 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4084 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4085
4086 assert(mach->FuncStackTop > 0);
4087 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4088
4089 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4090
4091 UPDATE_EXEC_MASK(mach);
4092 }
4093 break;
4094
4095 case TGSI_OPCODE_SSG:
4096 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4097 break;
4098
4099 case TGSI_OPCODE_CMP:
4100 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4101 break;
4102
4103 case TGSI_OPCODE_SCS:
4104 exec_scs(mach, inst);
4105 break;
4106
4107 case TGSI_OPCODE_NRM:
4108 exec_nrm3(mach, inst);
4109 break;
4110
4111 case TGSI_OPCODE_NRM4:
4112 exec_nrm4(mach, inst);
4113 break;
4114
4115 case TGSI_OPCODE_DIV:
4116 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4117 break;
4118
4119 case TGSI_OPCODE_DP2:
4120 exec_dp2(mach, inst);
4121 break;
4122
4123 case TGSI_OPCODE_IF:
4124 /* push CondMask */
4125 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4126 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4127 FETCH( &r[0], 0, TGSI_CHAN_X );
4128 /* update CondMask */
4129 if( ! r[0].f[0] ) {
4130 mach->CondMask &= ~0x1;
4131 }
4132 if( ! r[0].f[1] ) {
4133 mach->CondMask &= ~0x2;
4134 }
4135 if( ! r[0].f[2] ) {
4136 mach->CondMask &= ~0x4;
4137 }
4138 if( ! r[0].f[3] ) {
4139 mach->CondMask &= ~0x8;
4140 }
4141 UPDATE_EXEC_MASK(mach);
4142 /* Todo: If CondMask==0, jump to ELSE */
4143 break;
4144
4145 case TGSI_OPCODE_UIF:
4146 /* push CondMask */
4147 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4148 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4149 IFETCH( &r[0], 0, TGSI_CHAN_X );
4150 /* update CondMask */
4151 if( ! r[0].u[0] ) {
4152 mach->CondMask &= ~0x1;
4153 }
4154 if( ! r[0].u[1] ) {
4155 mach->CondMask &= ~0x2;
4156 }
4157 if( ! r[0].u[2] ) {
4158 mach->CondMask &= ~0x4;
4159 }
4160 if( ! r[0].u[3] ) {
4161 mach->CondMask &= ~0x8;
4162 }
4163 UPDATE_EXEC_MASK(mach);
4164 /* Todo: If CondMask==0, jump to ELSE */
4165 break;
4166
4167 case TGSI_OPCODE_ELSE:
4168 /* invert CondMask wrt previous mask */
4169 {
4170 uint prevMask;
4171 assert(mach->CondStackTop > 0);
4172 prevMask = mach->CondStack[mach->CondStackTop - 1];
4173 mach->CondMask = ~mach->CondMask & prevMask;
4174 UPDATE_EXEC_MASK(mach);
4175 /* Todo: If CondMask==0, jump to ENDIF */
4176 }
4177 break;
4178
4179 case TGSI_OPCODE_ENDIF:
4180 /* pop CondMask */
4181 assert(mach->CondStackTop > 0);
4182 mach->CondMask = mach->CondStack[--mach->CondStackTop];
4183 UPDATE_EXEC_MASK(mach);
4184 break;
4185
4186 case TGSI_OPCODE_END:
4187 /* make sure we end primitives which haven't
4188 * been explicitly emitted */
4189 conditional_emit_primitive(mach);
4190 /* halt execution */
4191 *pc = -1;
4192 break;
4193
4194 case TGSI_OPCODE_PUSHA:
4195 assert (0);
4196 break;
4197
4198 case TGSI_OPCODE_POPA:
4199 assert (0);
4200 break;
4201
4202 case TGSI_OPCODE_CEIL:
4203 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4204 break;
4205
4206 case TGSI_OPCODE_I2F:
4207 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
4208 break;
4209
4210 case TGSI_OPCODE_NOT:
4211 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4212 break;
4213
4214 case TGSI_OPCODE_TRUNC:
4215 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4216 break;
4217
4218 case TGSI_OPCODE_SHL:
4219 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4220 break;
4221
4222 case TGSI_OPCODE_AND:
4223 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4224 break;
4225
4226 case TGSI_OPCODE_OR:
4227 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4228 break;
4229
4230 case TGSI_OPCODE_MOD:
4231 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4232 break;
4233
4234 case TGSI_OPCODE_XOR:
4235 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4236 break;
4237
4238 case TGSI_OPCODE_SAD:
4239 assert (0);
4240 break;
4241
4242 case TGSI_OPCODE_TXF:
4243 exec_txf(mach, inst);
4244 break;
4245
4246 case TGSI_OPCODE_TXQ:
4247 exec_txq(mach, inst);
4248 break;
4249
4250 case TGSI_OPCODE_EMIT:
4251 emit_vertex(mach);
4252 break;
4253
4254 case TGSI_OPCODE_ENDPRIM:
4255 emit_primitive(mach);
4256 break;
4257
4258 case TGSI_OPCODE_BGNLOOP:
4259 /* push LoopMask and ContMasks */
4260 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4261 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4262 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4263 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4264
4265 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4266 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4267 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4268 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4269 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4270 break;
4271
4272 case TGSI_OPCODE_ENDLOOP:
4273 /* Restore ContMask, but don't pop */
4274 assert(mach->ContStackTop > 0);
4275 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4276 UPDATE_EXEC_MASK(mach);
4277 if (mach->ExecMask) {
4278 /* repeat loop: jump to instruction just past BGNLOOP */
4279 assert(mach->LoopLabelStackTop > 0);
4280 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4281 }
4282 else {
4283 /* exit loop: pop LoopMask */
4284 assert(mach->LoopStackTop > 0);
4285 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4286 /* pop ContMask */
4287 assert(mach->ContStackTop > 0);
4288 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4289 assert(mach->LoopLabelStackTop > 0);
4290 --mach->LoopLabelStackTop;
4291
4292 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4293 }
4294 UPDATE_EXEC_MASK(mach);
4295 break;
4296
4297 case TGSI_OPCODE_BRK:
4298 exec_break(mach);
4299 break;
4300
4301 case TGSI_OPCODE_CONT:
4302 /* turn off cont channels for each enabled exec channel */
4303 mach->ContMask &= ~mach->ExecMask;
4304 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4305 UPDATE_EXEC_MASK(mach);
4306 break;
4307
4308 case TGSI_OPCODE_BGNSUB:
4309 /* no-op */
4310 break;
4311
4312 case TGSI_OPCODE_ENDSUB:
4313 /*
4314 * XXX: This really should be a no-op. We should never reach this opcode.
4315 */
4316
4317 assert(mach->CallStackTop > 0);
4318 mach->CallStackTop--;
4319
4320 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4321 mach->CondMask = mach->CondStack[mach->CondStackTop];
4322
4323 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4324 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4325
4326 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4327 mach->ContMask = mach->ContStack[mach->ContStackTop];
4328
4329 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4330 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4331
4332 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4333 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4334
4335 assert(mach->FuncStackTop > 0);
4336 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4337
4338 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4339
4340 UPDATE_EXEC_MASK(mach);
4341 break;
4342
4343 case TGSI_OPCODE_NOP:
4344 break;
4345
4346 case TGSI_OPCODE_BREAKC:
4347 IFETCH(&r[0], 0, TGSI_CHAN_X);
4348 /* update CondMask */
4349 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4350 mach->LoopMask &= ~0x1;
4351 }
4352 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4353 mach->LoopMask &= ~0x2;
4354 }
4355 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4356 mach->LoopMask &= ~0x4;
4357 }
4358 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4359 mach->LoopMask &= ~0x8;
4360 }
4361 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4362 UPDATE_EXEC_MASK(mach);
4363 break;
4364
4365 case TGSI_OPCODE_F2I:
4366 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4367 break;
4368
4369 case TGSI_OPCODE_FSEQ:
4370 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4371 break;
4372
4373 case TGSI_OPCODE_FSGE:
4374 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4375 break;
4376
4377 case TGSI_OPCODE_FSLT:
4378 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4379 break;
4380
4381 case TGSI_OPCODE_FSNE:
4382 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4383 break;
4384
4385 case TGSI_OPCODE_IDIV:
4386 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4387 break;
4388
4389 case TGSI_OPCODE_IMAX:
4390 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4391 break;
4392
4393 case TGSI_OPCODE_IMIN:
4394 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4395 break;
4396
4397 case TGSI_OPCODE_INEG:
4398 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4399 break;
4400
4401 case TGSI_OPCODE_ISGE:
4402 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4403 break;
4404
4405 case TGSI_OPCODE_ISHR:
4406 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4407 break;
4408
4409 case TGSI_OPCODE_ISLT:
4410 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4411 break;
4412
4413 case TGSI_OPCODE_F2U:
4414 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4415 break;
4416
4417 case TGSI_OPCODE_U2F:
4418 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4419 break;
4420
4421 case TGSI_OPCODE_UADD:
4422 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4423 break;
4424
4425 case TGSI_OPCODE_UDIV:
4426 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4427 break;
4428
4429 case TGSI_OPCODE_UMAD:
4430 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4431 break;
4432
4433 case TGSI_OPCODE_UMAX:
4434 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4435 break;
4436
4437 case TGSI_OPCODE_UMIN:
4438 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4439 break;
4440
4441 case TGSI_OPCODE_UMOD:
4442 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4443 break;
4444
4445 case TGSI_OPCODE_UMUL:
4446 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4447 break;
4448
4449 case TGSI_OPCODE_IMUL_HI:
4450 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4451 break;
4452
4453 case TGSI_OPCODE_UMUL_HI:
4454 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4455 break;
4456
4457 case TGSI_OPCODE_USEQ:
4458 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4459 break;
4460
4461 case TGSI_OPCODE_USGE:
4462 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4463 break;
4464
4465 case TGSI_OPCODE_USHR:
4466 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4467 break;
4468
4469 case TGSI_OPCODE_USLT:
4470 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4471 break;
4472
4473 case TGSI_OPCODE_USNE:
4474 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4475 break;
4476
4477 case TGSI_OPCODE_SWITCH:
4478 exec_switch(mach, inst);
4479 break;
4480
4481 case TGSI_OPCODE_CASE:
4482 exec_case(mach, inst);
4483 break;
4484
4485 case TGSI_OPCODE_DEFAULT:
4486 exec_default(mach);
4487 break;
4488
4489 case TGSI_OPCODE_ENDSWITCH:
4490 exec_endswitch(mach);
4491 break;
4492
4493 case TGSI_OPCODE_SAMPLE_I:
4494 exec_txf(mach, inst);
4495 break;
4496
4497 case TGSI_OPCODE_SAMPLE_I_MS:
4498 assert(0);
4499 break;
4500
4501 case TGSI_OPCODE_SAMPLE:
4502 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4503 break;
4504
4505 case TGSI_OPCODE_SAMPLE_B:
4506 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4507 break;
4508
4509 case TGSI_OPCODE_SAMPLE_C:
4510 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4511 break;
4512
4513 case TGSI_OPCODE_SAMPLE_C_LZ:
4514 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4515 break;
4516
4517 case TGSI_OPCODE_SAMPLE_D:
4518 exec_sample_d(mach, inst);
4519 break;
4520
4521 case TGSI_OPCODE_SAMPLE_L:
4522 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4523 break;
4524
4525 case TGSI_OPCODE_GATHER4:
4526 assert(0);
4527 break;
4528
4529 case TGSI_OPCODE_SVIEWINFO:
4530 exec_txq(mach, inst);
4531 break;
4532
4533 case TGSI_OPCODE_SAMPLE_POS:
4534 assert(0);
4535 break;
4536
4537 case TGSI_OPCODE_SAMPLE_INFO:
4538 assert(0);
4539 break;
4540
4541 case TGSI_OPCODE_UARL:
4542 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4543 break;
4544
4545 case TGSI_OPCODE_UCMP:
4546 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4547 break;
4548
4549 case TGSI_OPCODE_IABS:
4550 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4551 break;
4552
4553 case TGSI_OPCODE_ISSG:
4554 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4555 break;
4556
4557 case TGSI_OPCODE_TEX2:
4558 /* simple texture lookup */
4559 /* src[0] = texcoord */
4560 /* src[1] = compare */
4561 /* src[2] = sampler unit */
4562 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4563 break;
4564 case TGSI_OPCODE_TXB2:
4565 /* simple texture lookup */
4566 /* src[0] = texcoord */
4567 /* src[1] = bias */
4568 /* src[2] = sampler unit */
4569 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4570 break;
4571 case TGSI_OPCODE_TXL2:
4572 /* simple texture lookup */
4573 /* src[0] = texcoord */
4574 /* src[1] = lod */
4575 /* src[2] = sampler unit */
4576 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4577 break;
4578
4579 case TGSI_OPCODE_IBFE:
4580 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4581 break;
4582 case TGSI_OPCODE_UBFE:
4583 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4584 break;
4585 case TGSI_OPCODE_BFI:
4586 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4587 break;
4588 case TGSI_OPCODE_BREV:
4589 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4590 break;
4591 case TGSI_OPCODE_POPC:
4592 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4593 break;
4594 case TGSI_OPCODE_LSB:
4595 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4596 break;
4597 case TGSI_OPCODE_IMSB:
4598 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4599 break;
4600 case TGSI_OPCODE_UMSB:
4601 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4602 break;
4603 default:
4604 assert( 0 );
4605 }
4606 }
4607
4608
4609 /**
4610 * Run TGSI interpreter.
4611 * \return bitmask of "alive" quad components
4612 */
4613 uint
4614 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4615 {
4616 uint i;
4617 int pc = 0;
4618 uint default_mask = 0xf;
4619
4620 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4621 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4622
4623 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4624 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4625 mach->Primitives[0] = 0;
4626 /* GS runs on a single primitive for now */
4627 default_mask = 0x1;
4628 }
4629
4630 mach->CondMask = default_mask;
4631 mach->LoopMask = default_mask;
4632 mach->ContMask = default_mask;
4633 mach->FuncMask = default_mask;
4634 mach->ExecMask = default_mask;
4635
4636 mach->Switch.mask = default_mask;
4637
4638 assert(mach->CondStackTop == 0);
4639 assert(mach->LoopStackTop == 0);
4640 assert(mach->ContStackTop == 0);
4641 assert(mach->SwitchStackTop == 0);
4642 assert(mach->BreakStackTop == 0);
4643 assert(mach->CallStackTop == 0);
4644
4645
4646 /* execute declarations (interpolants) */
4647 for (i = 0; i < mach->NumDeclarations; i++) {
4648 exec_declaration( mach, mach->Declarations+i );
4649 }
4650
4651 {
4652 #if DEBUG_EXECUTION
4653 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4654 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4655 uint inst = 1;
4656
4657 memset(mach->Temps, 0, sizeof(temps));
4658 memset(mach->Outputs, 0, sizeof(outputs));
4659 memset(temps, 0, sizeof(temps));
4660 memset(outputs, 0, sizeof(outputs));
4661 #endif
4662
4663 /* execute instructions, until pc is set to -1 */
4664 while (pc != -1) {
4665
4666 #if DEBUG_EXECUTION
4667 uint i;
4668
4669 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4670 #endif
4671
4672 assert(pc < (int) mach->NumInstructions);
4673 exec_instruction(mach, mach->Instructions + pc, &pc);
4674
4675 #if DEBUG_EXECUTION
4676 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4677 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4678 uint j;
4679
4680 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4681 debug_printf("TEMP[%2u] = ", i);
4682 for (j = 0; j < 4; j++) {
4683 if (j > 0) {
4684 debug_printf(" ");
4685 }
4686 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4687 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4688 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4689 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4690 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4691 }
4692 }
4693 }
4694 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4695 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4696 uint j;
4697
4698 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4699 debug_printf("OUT[%2u] = ", i);
4700 for (j = 0; j < 4; j++) {
4701 if (j > 0) {
4702 debug_printf(" ");
4703 }
4704 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4705 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4706 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4707 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4708 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4709 }
4710 }
4711 }
4712 #endif
4713 }
4714 }
4715
4716 #if 0
4717 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4718 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4719 /*
4720 * Scale back depth component.
4721 */
4722 for (i = 0; i < 4; i++)
4723 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4724 }
4725 #endif
4726
4727 /* Strictly speaking, these assertions aren't really needed but they
4728 * can potentially catch some bugs in the control flow code.
4729 */
4730 assert(mach->CondStackTop == 0);
4731 assert(mach->LoopStackTop == 0);
4732 assert(mach->ContStackTop == 0);
4733 assert(mach->SwitchStackTop == 0);
4734 assert(mach->BreakStackTop == 0);
4735 assert(mach->CallStackTop == 0);
4736
4737 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4738 }