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[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_scan.c
1 /**************************************************************************
2 *
3 * Copyright 2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2008 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI program scan utility.
31 * Used to determine which registers and instructions are used by a shader.
32 *
33 * Authors: Brian Paul
34 */
35
36
37 #include "util/u_debug.h"
38 #include "util/u_math.h"
39 #include "util/u_memory.h"
40 #include "util/u_prim.h"
41 #include "tgsi/tgsi_info.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_scan.h"
45
46
47 static bool
48 is_memory_file(unsigned file)
49 {
50 return file == TGSI_FILE_SAMPLER ||
51 file == TGSI_FILE_SAMPLER_VIEW ||
52 file == TGSI_FILE_IMAGE ||
53 file == TGSI_FILE_BUFFER;
54 }
55
56
57 static bool
58 is_mem_query_inst(unsigned opcode)
59 {
60 return opcode == TGSI_OPCODE_RESQ ||
61 opcode == TGSI_OPCODE_TXQ ||
62 opcode == TGSI_OPCODE_TXQS ||
63 opcode == TGSI_OPCODE_LODQ;
64 }
65
66 /**
67 * Is the opcode a "true" texture instruction which samples from a
68 * texture map?
69 */
70 static bool
71 is_texture_inst(unsigned opcode)
72 {
73 return (!is_mem_query_inst(opcode) &&
74 tgsi_get_opcode_info(opcode)->is_tex);
75 }
76
77
78 /**
79 * Is the opcode an instruction which computes a derivative explicitly or
80 * implicitly?
81 */
82 static bool
83 computes_derivative(unsigned opcode)
84 {
85 if (tgsi_get_opcode_info(opcode)->is_tex) {
86 return opcode != TGSI_OPCODE_TG4 &&
87 opcode != TGSI_OPCODE_TXD &&
88 opcode != TGSI_OPCODE_TXF &&
89 opcode != TGSI_OPCODE_TXF_LZ &&
90 opcode != TGSI_OPCODE_TEX_LZ &&
91 opcode != TGSI_OPCODE_TXL &&
92 opcode != TGSI_OPCODE_TXL2 &&
93 opcode != TGSI_OPCODE_TXQ &&
94 opcode != TGSI_OPCODE_TXQS;
95 }
96
97 return opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE ||
98 opcode == TGSI_OPCODE_DDY || opcode == TGSI_OPCODE_DDY_FINE ||
99 opcode == TGSI_OPCODE_SAMPLE ||
100 opcode == TGSI_OPCODE_SAMPLE_B ||
101 opcode == TGSI_OPCODE_SAMPLE_C;
102 }
103
104
105 static void
106 scan_src_operand(struct tgsi_shader_info *info,
107 const struct tgsi_full_instruction *fullinst,
108 const struct tgsi_full_src_register *src,
109 unsigned src_index,
110 unsigned usage_mask_after_swizzle,
111 bool is_interp_instruction,
112 bool *is_mem_inst)
113 {
114 int ind = src->Register.Index;
115
116 if (info->processor == PIPE_SHADER_COMPUTE &&
117 src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
118 unsigned name, mask;
119
120 name = info->system_value_semantic_name[src->Register.Index];
121
122 switch (name) {
123 case TGSI_SEMANTIC_THREAD_ID:
124 case TGSI_SEMANTIC_BLOCK_ID:
125 mask = usage_mask_after_swizzle & TGSI_WRITEMASK_XYZ;
126 while (mask) {
127 unsigned i = u_bit_scan(&mask);
128
129 if (name == TGSI_SEMANTIC_THREAD_ID)
130 info->uses_thread_id[i] = true;
131 else
132 info->uses_block_id[i] = true;
133 }
134 break;
135 case TGSI_SEMANTIC_BLOCK_SIZE:
136 /* The block size is translated to IMM with a fixed block size. */
137 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
138 info->uses_block_size = true;
139 break;
140 case TGSI_SEMANTIC_GRID_SIZE:
141 info->uses_grid_size = true;
142 break;
143 }
144 }
145
146 /* Mark which inputs are effectively used */
147 if (src->Register.File == TGSI_FILE_INPUT) {
148 if (src->Register.Indirect) {
149 for (ind = 0; ind < info->num_inputs; ++ind) {
150 info->input_usage_mask[ind] |= usage_mask_after_swizzle;
151 }
152 } else {
153 assert(ind >= 0);
154 assert(ind < PIPE_MAX_SHADER_INPUTS);
155 info->input_usage_mask[ind] |= usage_mask_after_swizzle;
156 }
157
158 if (info->processor == PIPE_SHADER_FRAGMENT) {
159 unsigned name, index, input;
160
161 if (src->Register.Indirect && src->Indirect.ArrayID)
162 input = info->input_array_first[src->Indirect.ArrayID];
163 else
164 input = src->Register.Index;
165
166 name = info->input_semantic_name[input];
167 index = info->input_semantic_index[input];
168
169 if (name == TGSI_SEMANTIC_POSITION &&
170 usage_mask_after_swizzle & TGSI_WRITEMASK_Z)
171 info->reads_z = true;
172
173 if (name == TGSI_SEMANTIC_COLOR)
174 info->colors_read |= usage_mask_after_swizzle << (index * 4);
175
176 /* Process only interpolated varyings. Don't include POSITION.
177 * Don't include integer varyings, because they are not
178 * interpolated. Don't process inputs interpolated by INTERP
179 * opcodes. Those are tracked separately.
180 */
181 if ((!is_interp_instruction || src_index != 0) &&
182 (name == TGSI_SEMANTIC_GENERIC ||
183 name == TGSI_SEMANTIC_TEXCOORD ||
184 name == TGSI_SEMANTIC_COLOR ||
185 name == TGSI_SEMANTIC_BCOLOR ||
186 name == TGSI_SEMANTIC_FOG ||
187 name == TGSI_SEMANTIC_CLIPDIST)) {
188 switch (info->input_interpolate[input]) {
189 case TGSI_INTERPOLATE_COLOR:
190 case TGSI_INTERPOLATE_PERSPECTIVE:
191 switch (info->input_interpolate_loc[input]) {
192 case TGSI_INTERPOLATE_LOC_CENTER:
193 info->uses_persp_center = TRUE;
194 break;
195 case TGSI_INTERPOLATE_LOC_CENTROID:
196 info->uses_persp_centroid = TRUE;
197 break;
198 case TGSI_INTERPOLATE_LOC_SAMPLE:
199 info->uses_persp_sample = TRUE;
200 break;
201 }
202 break;
203 case TGSI_INTERPOLATE_LINEAR:
204 switch (info->input_interpolate_loc[input]) {
205 case TGSI_INTERPOLATE_LOC_CENTER:
206 info->uses_linear_center = TRUE;
207 break;
208 case TGSI_INTERPOLATE_LOC_CENTROID:
209 info->uses_linear_centroid = TRUE;
210 break;
211 case TGSI_INTERPOLATE_LOC_SAMPLE:
212 info->uses_linear_sample = TRUE;
213 break;
214 }
215 break;
216 /* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
217 }
218 }
219 }
220 }
221
222 if (info->processor == PIPE_SHADER_TESS_CTRL &&
223 src->Register.File == TGSI_FILE_OUTPUT) {
224 unsigned input;
225
226 if (src->Register.Indirect && src->Indirect.ArrayID)
227 input = info->output_array_first[src->Indirect.ArrayID];
228 else
229 input = src->Register.Index;
230
231 switch (info->output_semantic_name[input]) {
232 case TGSI_SEMANTIC_PATCH:
233 info->reads_perpatch_outputs = true;
234 break;
235 case TGSI_SEMANTIC_TESSINNER:
236 case TGSI_SEMANTIC_TESSOUTER:
237 info->reads_tessfactor_outputs = true;
238 break;
239 default:
240 info->reads_pervertex_outputs = true;
241 }
242 }
243
244 /* check for indirect register reads */
245 if (src->Register.Indirect) {
246 info->indirect_files |= (1 << src->Register.File);
247 info->indirect_files_read |= (1 << src->Register.File);
248
249 /* record indirect constant buffer indexing */
250 if (src->Register.File == TGSI_FILE_CONSTANT) {
251 if (src->Register.Dimension) {
252 if (src->Dimension.Indirect)
253 info->const_buffers_indirect = info->const_buffers_declared;
254 else
255 info->const_buffers_indirect |= 1u << src->Dimension.Index;
256 } else {
257 info->const_buffers_indirect |= 1;
258 }
259 }
260 }
261
262 if (src->Register.Dimension && src->Dimension.Indirect)
263 info->dim_indirect_files |= 1u << src->Register.File;
264
265 /* Texture samplers */
266 if (src->Register.File == TGSI_FILE_SAMPLER) {
267 const unsigned index = src->Register.Index;
268
269 assert(fullinst->Instruction.Texture);
270 assert(index < PIPE_MAX_SAMPLERS);
271
272 if (is_texture_inst(fullinst->Instruction.Opcode)) {
273 const unsigned target = fullinst->Texture.Texture;
274 assert(target < TGSI_TEXTURE_UNKNOWN);
275 /* for texture instructions, check that the texture instruction
276 * target matches the previous sampler view declaration (if there
277 * was one.)
278 */
279 if (info->sampler_targets[index] == TGSI_TEXTURE_UNKNOWN) {
280 /* probably no sampler view declaration */
281 info->sampler_targets[index] = target;
282 } else {
283 /* Make sure the texture instruction's sampler/target info
284 * agrees with the sampler view declaration.
285 */
286 assert(info->sampler_targets[index] == target);
287 }
288 }
289 }
290
291 if (is_memory_file(src->Register.File) &&
292 !is_mem_query_inst(fullinst->Instruction.Opcode)) {
293 *is_mem_inst = true;
294
295 if (tgsi_get_opcode_info(fullinst->Instruction.Opcode)->is_store) {
296 info->writes_memory = TRUE;
297
298 if (src->Register.File == TGSI_FILE_IMAGE) {
299 if (src->Register.Indirect)
300 info->images_atomic = info->images_declared;
301 else
302 info->images_atomic |= 1 << src->Register.Index;
303 } else if (src->Register.File == TGSI_FILE_BUFFER) {
304 if (src->Register.Indirect)
305 info->shader_buffers_atomic = info->shader_buffers_declared;
306 else
307 info->shader_buffers_atomic |= 1 << src->Register.Index;
308 }
309 } else {
310 if (src->Register.File == TGSI_FILE_IMAGE) {
311 if (src->Register.Indirect)
312 info->images_load = info->images_declared;
313 else
314 info->images_load |= 1 << src->Register.Index;
315 } else if (src->Register.File == TGSI_FILE_BUFFER) {
316 if (src->Register.Indirect)
317 info->shader_buffers_load = info->shader_buffers_declared;
318 else
319 info->shader_buffers_load |= 1 << src->Register.Index;
320 }
321 }
322 }
323 }
324
325
326 static void
327 scan_instruction(struct tgsi_shader_info *info,
328 const struct tgsi_full_instruction *fullinst,
329 unsigned *current_depth)
330 {
331 unsigned i;
332 bool is_mem_inst = false;
333 bool is_interp_instruction = false;
334 unsigned sampler_src;
335
336 assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
337 info->opcode_count[fullinst->Instruction.Opcode]++;
338
339 switch (fullinst->Instruction.Opcode) {
340 case TGSI_OPCODE_IF:
341 case TGSI_OPCODE_UIF:
342 case TGSI_OPCODE_BGNLOOP:
343 (*current_depth)++;
344 info->max_depth = MAX2(info->max_depth, *current_depth);
345 break;
346 case TGSI_OPCODE_ENDIF:
347 case TGSI_OPCODE_ENDLOOP:
348 (*current_depth)--;
349 break;
350 case TGSI_OPCODE_TEX:
351 case TGSI_OPCODE_TEX_LZ:
352 case TGSI_OPCODE_TXB:
353 case TGSI_OPCODE_TXD:
354 case TGSI_OPCODE_TXL:
355 case TGSI_OPCODE_TXP:
356 case TGSI_OPCODE_TXQ:
357 case TGSI_OPCODE_TXQS:
358 case TGSI_OPCODE_TXF:
359 case TGSI_OPCODE_TXF_LZ:
360 case TGSI_OPCODE_TEX2:
361 case TGSI_OPCODE_TXB2:
362 case TGSI_OPCODE_TXL2:
363 case TGSI_OPCODE_TG4:
364 case TGSI_OPCODE_LODQ:
365 sampler_src = fullinst->Instruction.NumSrcRegs - 1;
366 if (fullinst->Src[sampler_src].Register.File != TGSI_FILE_SAMPLER)
367 info->uses_bindless_samplers = true;
368 break;
369 case TGSI_OPCODE_RESQ:
370 case TGSI_OPCODE_LOAD:
371 case TGSI_OPCODE_ATOMUADD:
372 case TGSI_OPCODE_ATOMXCHG:
373 case TGSI_OPCODE_ATOMCAS:
374 case TGSI_OPCODE_ATOMAND:
375 case TGSI_OPCODE_ATOMOR:
376 case TGSI_OPCODE_ATOMXOR:
377 case TGSI_OPCODE_ATOMUMIN:
378 case TGSI_OPCODE_ATOMUMAX:
379 case TGSI_OPCODE_ATOMIMIN:
380 case TGSI_OPCODE_ATOMIMAX:
381 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File))
382 info->uses_bindless_images = true;
383 break;
384 case TGSI_OPCODE_STORE:
385 if (tgsi_is_bindless_image_file(fullinst->Dst[0].Register.File))
386 info->uses_bindless_images = true;
387 break;
388 default:
389 break;
390 }
391
392 if (fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID ||
393 fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
394 fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
395 const struct tgsi_full_src_register *src0 = &fullinst->Src[0];
396 unsigned input;
397
398 is_interp_instruction = true;
399
400 if (src0->Register.Indirect && src0->Indirect.ArrayID)
401 input = info->input_array_first[src0->Indirect.ArrayID];
402 else
403 input = src0->Register.Index;
404
405 /* For the INTERP opcodes, the interpolation is always
406 * PERSPECTIVE unless LINEAR is specified.
407 */
408 switch (info->input_interpolate[input]) {
409 case TGSI_INTERPOLATE_COLOR:
410 case TGSI_INTERPOLATE_CONSTANT:
411 case TGSI_INTERPOLATE_PERSPECTIVE:
412 switch (fullinst->Instruction.Opcode) {
413 case TGSI_OPCODE_INTERP_CENTROID:
414 info->uses_persp_opcode_interp_centroid = TRUE;
415 break;
416 case TGSI_OPCODE_INTERP_OFFSET:
417 info->uses_persp_opcode_interp_offset = TRUE;
418 break;
419 case TGSI_OPCODE_INTERP_SAMPLE:
420 info->uses_persp_opcode_interp_sample = TRUE;
421 break;
422 }
423 break;
424
425 case TGSI_INTERPOLATE_LINEAR:
426 switch (fullinst->Instruction.Opcode) {
427 case TGSI_OPCODE_INTERP_CENTROID:
428 info->uses_linear_opcode_interp_centroid = TRUE;
429 break;
430 case TGSI_OPCODE_INTERP_OFFSET:
431 info->uses_linear_opcode_interp_offset = TRUE;
432 break;
433 case TGSI_OPCODE_INTERP_SAMPLE:
434 info->uses_linear_opcode_interp_sample = TRUE;
435 break;
436 }
437 break;
438 }
439 }
440
441 if ((fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D &&
442 fullinst->Instruction.Opcode <= TGSI_OPCODE_DSSG) ||
443 fullinst->Instruction.Opcode == TGSI_OPCODE_DFMA ||
444 fullinst->Instruction.Opcode == TGSI_OPCODE_DDIV ||
445 fullinst->Instruction.Opcode == TGSI_OPCODE_D2U64 ||
446 fullinst->Instruction.Opcode == TGSI_OPCODE_D2I64 ||
447 fullinst->Instruction.Opcode == TGSI_OPCODE_U642D ||
448 fullinst->Instruction.Opcode == TGSI_OPCODE_I642D)
449 info->uses_doubles = TRUE;
450
451 for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
452 scan_src_operand(info, fullinst, &fullinst->Src[i], i,
453 tgsi_util_get_inst_usage_mask(fullinst, i),
454 is_interp_instruction, &is_mem_inst);
455
456 if (fullinst->Src[i].Register.Indirect) {
457 struct tgsi_full_src_register src = {{0}};
458
459 src.Register.File = fullinst->Src[i].Indirect.File;
460 src.Register.Index = fullinst->Src[i].Indirect.Index;
461
462 scan_src_operand(info, fullinst, &src, -1,
463 1 << fullinst->Src[i].Indirect.Swizzle,
464 false, NULL);
465 }
466
467 if (fullinst->Src[i].Register.Dimension &&
468 fullinst->Src[i].Dimension.Indirect) {
469 struct tgsi_full_src_register src = {{0}};
470
471 src.Register.File = fullinst->Src[i].DimIndirect.File;
472 src.Register.Index = fullinst->Src[i].DimIndirect.Index;
473
474 scan_src_operand(info, fullinst, &src, -1,
475 1 << fullinst->Src[i].DimIndirect.Swizzle,
476 false, NULL);
477 }
478 }
479
480 if (fullinst->Instruction.Texture) {
481 for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
482 struct tgsi_full_src_register src = {{0}};
483
484 src.Register.File = fullinst->TexOffsets[i].File;
485 src.Register.Index = fullinst->TexOffsets[i].Index;
486
487 /* The usage mask is suboptimal but should be safe. */
488 scan_src_operand(info, fullinst, &src, -1,
489 (1 << fullinst->TexOffsets[i].SwizzleX) |
490 (1 << fullinst->TexOffsets[i].SwizzleY) |
491 (1 << fullinst->TexOffsets[i].SwizzleZ),
492 false, &is_mem_inst);
493 }
494 }
495
496 /* check for indirect register writes */
497 for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
498 const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
499
500 if (dst->Register.Indirect) {
501 struct tgsi_full_src_register src = {{0}};
502
503 src.Register.File = dst->Indirect.File;
504 src.Register.Index = dst->Indirect.Index;
505
506 scan_src_operand(info, fullinst, &src, -1,
507 1 << dst->Indirect.Swizzle, false, NULL);
508
509 info->indirect_files |= (1 << dst->Register.File);
510 info->indirect_files_written |= (1 << dst->Register.File);
511 }
512
513 if (dst->Register.Dimension && dst->Dimension.Indirect) {
514 struct tgsi_full_src_register src = {{0}};
515
516 src.Register.File = dst->DimIndirect.File;
517 src.Register.Index = dst->DimIndirect.Index;
518
519 scan_src_operand(info, fullinst, &src, -1,
520 1 << dst->DimIndirect.Swizzle, false, NULL);
521
522 info->dim_indirect_files |= 1u << dst->Register.File;
523 }
524
525 if (is_memory_file(dst->Register.File)) {
526 assert(fullinst->Instruction.Opcode == TGSI_OPCODE_STORE);
527
528 is_mem_inst = true;
529 info->writes_memory = TRUE;
530
531 if (dst->Register.File == TGSI_FILE_IMAGE) {
532 if (dst->Register.Indirect)
533 info->images_store = info->images_declared;
534 else
535 info->images_store |= 1 << dst->Register.Index;
536 } else if (dst->Register.File == TGSI_FILE_BUFFER) {
537 if (dst->Register.Indirect)
538 info->shader_buffers_store = info->shader_buffers_declared;
539 else
540 info->shader_buffers_store |= 1 << dst->Register.Index;
541 }
542 }
543 }
544
545 if (is_mem_inst)
546 info->num_memory_instructions++;
547
548 if (computes_derivative(fullinst->Instruction.Opcode))
549 info->uses_derivatives = true;
550
551 info->num_instructions++;
552 }
553
554
555 static void
556 scan_declaration(struct tgsi_shader_info *info,
557 const struct tgsi_full_declaration *fulldecl)
558 {
559 const uint file = fulldecl->Declaration.File;
560 const unsigned procType = info->processor;
561 uint reg;
562
563 if (fulldecl->Declaration.Array) {
564 unsigned array_id = fulldecl->Array.ArrayID;
565
566 switch (file) {
567 case TGSI_FILE_INPUT:
568 assert(array_id < ARRAY_SIZE(info->input_array_first));
569 info->input_array_first[array_id] = fulldecl->Range.First;
570 info->input_array_last[array_id] = fulldecl->Range.Last;
571 break;
572 case TGSI_FILE_OUTPUT:
573 assert(array_id < ARRAY_SIZE(info->output_array_first));
574 info->output_array_first[array_id] = fulldecl->Range.First;
575 info->output_array_last[array_id] = fulldecl->Range.Last;
576 break;
577 }
578 info->array_max[file] = MAX2(info->array_max[file], array_id);
579 }
580
581 for (reg = fulldecl->Range.First; reg <= fulldecl->Range.Last; reg++) {
582 unsigned semName = fulldecl->Semantic.Name;
583 unsigned semIndex = fulldecl->Semantic.Index +
584 (reg - fulldecl->Range.First);
585 int buffer;
586 unsigned index, target, type;
587
588 /* only first 32 regs will appear in this bitfield */
589 info->file_mask[file] |= (1 << reg);
590 info->file_count[file]++;
591 info->file_max[file] = MAX2(info->file_max[file], (int)reg);
592
593 switch (file) {
594 case TGSI_FILE_CONSTANT:
595 buffer = 0;
596
597 if (fulldecl->Declaration.Dimension)
598 buffer = fulldecl->Dim.Index2D;
599
600 info->const_file_max[buffer] =
601 MAX2(info->const_file_max[buffer], (int)reg);
602 info->const_buffers_declared |= 1u << buffer;
603 break;
604
605 case TGSI_FILE_IMAGE:
606 info->images_declared |= 1u << reg;
607 if (fulldecl->Image.Resource == TGSI_TEXTURE_BUFFER)
608 info->images_buffers |= 1 << reg;
609 break;
610
611 case TGSI_FILE_BUFFER:
612 info->shader_buffers_declared |= 1u << reg;
613 break;
614
615 case TGSI_FILE_INPUT:
616 info->input_semantic_name[reg] = (ubyte) semName;
617 info->input_semantic_index[reg] = (ubyte) semIndex;
618 info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate;
619 info->input_interpolate_loc[reg] = (ubyte)fulldecl->Interp.Location;
620 info->input_cylindrical_wrap[reg] = (ubyte)fulldecl->Interp.CylindricalWrap;
621
622 /* Vertex shaders can have inputs with holes between them. */
623 info->num_inputs = MAX2(info->num_inputs, reg + 1);
624
625 switch (semName) {
626 case TGSI_SEMANTIC_PRIMID:
627 info->uses_primid = true;
628 break;
629 case TGSI_SEMANTIC_POSITION:
630 info->reads_position = true;
631 break;
632 case TGSI_SEMANTIC_FACE:
633 info->uses_frontface = true;
634 break;
635 }
636 break;
637
638 case TGSI_FILE_SYSTEM_VALUE:
639 index = fulldecl->Range.First;
640
641 info->system_value_semantic_name[index] = semName;
642 info->num_system_values = MAX2(info->num_system_values, index + 1);
643
644 switch (semName) {
645 case TGSI_SEMANTIC_INSTANCEID:
646 info->uses_instanceid = TRUE;
647 break;
648 case TGSI_SEMANTIC_VERTEXID:
649 info->uses_vertexid = TRUE;
650 break;
651 case TGSI_SEMANTIC_VERTEXID_NOBASE:
652 info->uses_vertexid_nobase = TRUE;
653 break;
654 case TGSI_SEMANTIC_BASEVERTEX:
655 info->uses_basevertex = TRUE;
656 break;
657 case TGSI_SEMANTIC_PRIMID:
658 info->uses_primid = TRUE;
659 break;
660 case TGSI_SEMANTIC_INVOCATIONID:
661 info->uses_invocationid = TRUE;
662 break;
663 case TGSI_SEMANTIC_POSITION:
664 info->reads_position = TRUE;
665 break;
666 case TGSI_SEMANTIC_FACE:
667 info->uses_frontface = TRUE;
668 break;
669 case TGSI_SEMANTIC_SAMPLEMASK:
670 info->reads_samplemask = TRUE;
671 break;
672 case TGSI_SEMANTIC_TESSINNER:
673 case TGSI_SEMANTIC_TESSOUTER:
674 info->reads_tess_factors = true;
675 break;
676 }
677 break;
678
679 case TGSI_FILE_OUTPUT:
680 info->output_semantic_name[reg] = (ubyte) semName;
681 info->output_semantic_index[reg] = (ubyte) semIndex;
682 info->output_usagemask[reg] |= fulldecl->Declaration.UsageMask;
683 info->num_outputs = MAX2(info->num_outputs, reg + 1);
684
685 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_X) {
686 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamX;
687 info->num_stream_output_components[fulldecl->Semantic.StreamX]++;
688 }
689 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Y) {
690 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamY << 2;
691 info->num_stream_output_components[fulldecl->Semantic.StreamY]++;
692 }
693 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Z) {
694 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamZ << 4;
695 info->num_stream_output_components[fulldecl->Semantic.StreamZ]++;
696 }
697 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_W) {
698 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamW << 6;
699 info->num_stream_output_components[fulldecl->Semantic.StreamW]++;
700 }
701
702 switch (semName) {
703 case TGSI_SEMANTIC_PRIMID:
704 info->writes_primid = true;
705 break;
706 case TGSI_SEMANTIC_VIEWPORT_INDEX:
707 info->writes_viewport_index = true;
708 break;
709 case TGSI_SEMANTIC_LAYER:
710 info->writes_layer = true;
711 break;
712 case TGSI_SEMANTIC_PSIZE:
713 info->writes_psize = true;
714 break;
715 case TGSI_SEMANTIC_CLIPVERTEX:
716 info->writes_clipvertex = true;
717 break;
718 case TGSI_SEMANTIC_COLOR:
719 info->colors_written |= 1 << semIndex;
720 break;
721 case TGSI_SEMANTIC_STENCIL:
722 info->writes_stencil = true;
723 break;
724 case TGSI_SEMANTIC_SAMPLEMASK:
725 info->writes_samplemask = true;
726 break;
727 case TGSI_SEMANTIC_EDGEFLAG:
728 info->writes_edgeflag = true;
729 break;
730 case TGSI_SEMANTIC_POSITION:
731 if (procType == PIPE_SHADER_FRAGMENT)
732 info->writes_z = true;
733 else
734 info->writes_position = true;
735 break;
736 }
737 break;
738
739 case TGSI_FILE_SAMPLER:
740 STATIC_ASSERT(sizeof(info->samplers_declared) * 8 >= PIPE_MAX_SAMPLERS);
741 info->samplers_declared |= 1u << reg;
742 break;
743
744 case TGSI_FILE_SAMPLER_VIEW:
745 target = fulldecl->SamplerView.Resource;
746 type = fulldecl->SamplerView.ReturnTypeX;
747
748 assert(target < TGSI_TEXTURE_UNKNOWN);
749 if (info->sampler_targets[reg] == TGSI_TEXTURE_UNKNOWN) {
750 /* Save sampler target for this sampler index */
751 info->sampler_targets[reg] = target;
752 info->sampler_type[reg] = type;
753 } else {
754 /* if previously declared, make sure targets agree */
755 assert(info->sampler_targets[reg] == target);
756 assert(info->sampler_type[reg] == type);
757 }
758 break;
759 }
760 }
761 }
762
763
764 static void
765 scan_immediate(struct tgsi_shader_info *info)
766 {
767 uint reg = info->immediate_count++;
768 uint file = TGSI_FILE_IMMEDIATE;
769
770 info->file_mask[file] |= (1 << reg);
771 info->file_count[file]++;
772 info->file_max[file] = MAX2(info->file_max[file], (int)reg);
773 }
774
775
776 static void
777 scan_property(struct tgsi_shader_info *info,
778 const struct tgsi_full_property *fullprop)
779 {
780 unsigned name = fullprop->Property.PropertyName;
781 unsigned value = fullprop->u[0].Data;
782
783 assert(name < ARRAY_SIZE(info->properties));
784 info->properties[name] = value;
785
786 switch (name) {
787 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
788 info->num_written_clipdistance = value;
789 info->clipdist_writemask |= (1 << value) - 1;
790 break;
791 case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
792 info->num_written_culldistance = value;
793 info->culldist_writemask |= (1 << value) - 1;
794 break;
795 }
796 }
797
798
799 /**
800 * Scan the given TGSI shader to collect information such as number of
801 * registers used, special instructions used, etc.
802 * \return info the result of the scan
803 */
804 void
805 tgsi_scan_shader(const struct tgsi_token *tokens,
806 struct tgsi_shader_info *info)
807 {
808 uint procType, i;
809 struct tgsi_parse_context parse;
810 unsigned current_depth = 0;
811
812 memset(info, 0, sizeof(*info));
813 for (i = 0; i < TGSI_FILE_COUNT; i++)
814 info->file_max[i] = -1;
815 for (i = 0; i < ARRAY_SIZE(info->const_file_max); i++)
816 info->const_file_max[i] = -1;
817 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = 1;
818 for (i = 0; i < ARRAY_SIZE(info->sampler_targets); i++)
819 info->sampler_targets[i] = TGSI_TEXTURE_UNKNOWN;
820
821 /**
822 ** Setup to begin parsing input shader
823 **/
824 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
825 debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
826 return;
827 }
828 procType = parse.FullHeader.Processor.Processor;
829 assert(procType == PIPE_SHADER_FRAGMENT ||
830 procType == PIPE_SHADER_VERTEX ||
831 procType == PIPE_SHADER_GEOMETRY ||
832 procType == PIPE_SHADER_TESS_CTRL ||
833 procType == PIPE_SHADER_TESS_EVAL ||
834 procType == PIPE_SHADER_COMPUTE);
835 info->processor = procType;
836
837 /**
838 ** Loop over incoming program tokens/instructions
839 */
840 while (!tgsi_parse_end_of_tokens(&parse)) {
841 info->num_tokens++;
842
843 tgsi_parse_token( &parse );
844
845 switch( parse.FullToken.Token.Type ) {
846 case TGSI_TOKEN_TYPE_INSTRUCTION:
847 scan_instruction(info, &parse.FullToken.FullInstruction,
848 &current_depth);
849 break;
850 case TGSI_TOKEN_TYPE_DECLARATION:
851 scan_declaration(info, &parse.FullToken.FullDeclaration);
852 break;
853 case TGSI_TOKEN_TYPE_IMMEDIATE:
854 scan_immediate(info);
855 break;
856 case TGSI_TOKEN_TYPE_PROPERTY:
857 scan_property(info, &parse.FullToken.FullProperty);
858 break;
859 default:
860 assert(!"Unexpected TGSI token type");
861 }
862 }
863
864 info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
865 info->opcode_count[TGSI_OPCODE_KILL]);
866
867 /* The dimensions of the IN decleration in geometry shader have
868 * to be deduced from the type of the input primitive.
869 */
870 if (procType == PIPE_SHADER_GEOMETRY) {
871 unsigned input_primitive =
872 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
873 int num_verts = u_vertices_per_prim(input_primitive);
874 int j;
875 info->file_count[TGSI_FILE_INPUT] = num_verts;
876 info->file_max[TGSI_FILE_INPUT] =
877 MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
878 for (j = 0; j < num_verts; ++j) {
879 info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
880 }
881 }
882
883 tgsi_parse_free(&parse);
884 }
885
886 /**
887 * Collect information about the arrays of a given register file.
888 *
889 * @param tokens TGSI shader
890 * @param file the register file to scan through
891 * @param max_array_id number of entries in @p arrays; should be equal to the
892 * highest array id, i.e. tgsi_shader_info::array_max[file].
893 * @param arrays info for array of each ID will be written to arrays[ID - 1].
894 */
895 void
896 tgsi_scan_arrays(const struct tgsi_token *tokens,
897 unsigned file,
898 unsigned max_array_id,
899 struct tgsi_array_info *arrays)
900 {
901 struct tgsi_parse_context parse;
902
903 if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
904 debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
905 return;
906 }
907
908 memset(arrays, 0, sizeof(arrays[0]) * max_array_id);
909
910 while (!tgsi_parse_end_of_tokens(&parse)) {
911 struct tgsi_full_instruction *inst;
912
913 tgsi_parse_token(&parse);
914
915 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
916 struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
917
918 if (decl->Declaration.Array && decl->Declaration.File == file &&
919 decl->Array.ArrayID > 0 && decl->Array.ArrayID <= max_array_id) {
920 struct tgsi_array_info *array = &arrays[decl->Array.ArrayID - 1];
921 assert(!array->declared);
922 array->declared = true;
923 array->range = decl->Range;
924 }
925 }
926
927 if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
928 continue;
929
930 inst = &parse.FullToken.FullInstruction;
931 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
932 const struct tgsi_full_dst_register *dst = &inst->Dst[i];
933 if (dst->Register.File != file)
934 continue;
935
936 if (dst->Register.Indirect) {
937 if (dst->Indirect.ArrayID > 0 &&
938 dst->Indirect.ArrayID <= max_array_id) {
939 arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask;
940 } else {
941 /* Indirect writes without an ArrayID can write anywhere. */
942 for (unsigned j = 0; j < max_array_id; ++j)
943 arrays[j].writemask |= dst->Register.WriteMask;
944 }
945 } else {
946 /* Check whether the write falls into any of the arrays anyway. */
947 for (unsigned j = 0; j < max_array_id; ++j) {
948 struct tgsi_array_info *array = &arrays[j];
949 if (array->declared &&
950 dst->Register.Index >= array->range.First &&
951 dst->Register.Index <= array->range.Last)
952 array->writemask |= dst->Register.WriteMask;
953 }
954 }
955 }
956 }
957
958 tgsi_parse_free(&parse);
959
960 return;
961 }
962
963 static void
964 check_no_subroutines(const struct tgsi_full_instruction *inst)
965 {
966 switch (inst->Instruction.Opcode) {
967 case TGSI_OPCODE_BGNSUB:
968 case TGSI_OPCODE_ENDSUB:
969 case TGSI_OPCODE_CAL:
970 unreachable("subroutines unhandled");
971 }
972 }
973
974 static unsigned
975 get_inst_tessfactor_writemask(const struct tgsi_shader_info *info,
976 const struct tgsi_full_instruction *inst)
977 {
978 unsigned writemask = 0;
979
980 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
981 const struct tgsi_full_dst_register *dst = &inst->Dst[i];
982
983 if (dst->Register.File == TGSI_FILE_OUTPUT &&
984 !dst->Register.Indirect) {
985 unsigned name = info->output_semantic_name[dst->Register.Index];
986
987 if (name == TGSI_SEMANTIC_TESSINNER)
988 writemask |= dst->Register.WriteMask;
989 else if (name == TGSI_SEMANTIC_TESSOUTER)
990 writemask |= dst->Register.WriteMask << 4;
991 }
992 }
993 return writemask;
994 }
995
996 static unsigned
997 get_block_tessfactor_writemask(const struct tgsi_shader_info *info,
998 struct tgsi_parse_context *parse,
999 unsigned end_opcode)
1000 {
1001 struct tgsi_full_instruction *inst;
1002 unsigned writemask = 0;
1003
1004 do {
1005 tgsi_parse_token(parse);
1006 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1007 inst = &parse->FullToken.FullInstruction;
1008 check_no_subroutines(inst);
1009
1010 /* Recursively process nested blocks. */
1011 switch (inst->Instruction.Opcode) {
1012 case TGSI_OPCODE_IF:
1013 case TGSI_OPCODE_UIF:
1014 writemask |=
1015 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDIF);
1016 continue;
1017
1018 case TGSI_OPCODE_BGNLOOP:
1019 writemask |=
1020 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
1021 continue;
1022
1023 case TGSI_OPCODE_BARRIER:
1024 unreachable("nested BARRIER is illegal");
1025 continue;
1026 }
1027
1028 writemask |= get_inst_tessfactor_writemask(info, inst);
1029 } while (inst->Instruction.Opcode != end_opcode);
1030
1031 return writemask;
1032 }
1033
1034 static void
1035 get_if_block_tessfactor_writemask(const struct tgsi_shader_info *info,
1036 struct tgsi_parse_context *parse,
1037 unsigned *upper_block_tf_writemask,
1038 unsigned *cond_block_tf_writemask)
1039 {
1040 struct tgsi_full_instruction *inst;
1041 unsigned then_tessfactor_writemask = 0;
1042 unsigned else_tessfactor_writemask = 0;
1043 bool is_then = true;
1044
1045 do {
1046 tgsi_parse_token(parse);
1047 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1048 inst = &parse->FullToken.FullInstruction;
1049 check_no_subroutines(inst);
1050
1051 switch (inst->Instruction.Opcode) {
1052 case TGSI_OPCODE_ELSE:
1053 is_then = false;
1054 continue;
1055
1056 /* Recursively process nested blocks. */
1057 case TGSI_OPCODE_IF:
1058 case TGSI_OPCODE_UIF:
1059 get_if_block_tessfactor_writemask(info, parse,
1060 is_then ? &then_tessfactor_writemask :
1061 &else_tessfactor_writemask,
1062 cond_block_tf_writemask);
1063 continue;
1064
1065 case TGSI_OPCODE_BGNLOOP:
1066 *cond_block_tf_writemask |=
1067 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
1068 continue;
1069
1070 case TGSI_OPCODE_BARRIER:
1071 unreachable("nested BARRIER is illegal");
1072 continue;
1073 }
1074
1075 /* Process an instruction in the current block. */
1076 unsigned writemask = get_inst_tessfactor_writemask(info, inst);
1077
1078 if (writemask) {
1079 if (is_then)
1080 then_tessfactor_writemask |= writemask;
1081 else
1082 else_tessfactor_writemask |= writemask;
1083 }
1084 } while (inst->Instruction.Opcode != TGSI_OPCODE_ENDIF);
1085
1086 if (then_tessfactor_writemask || else_tessfactor_writemask) {
1087 /* If both statements write the same tess factor channels,
1088 * we can say that the upper block writes them too. */
1089 *upper_block_tf_writemask |= then_tessfactor_writemask &
1090 else_tessfactor_writemask;
1091 *cond_block_tf_writemask |= then_tessfactor_writemask |
1092 else_tessfactor_writemask;
1093 }
1094 }
1095
1096 void
1097 tgsi_scan_tess_ctrl(const struct tgsi_token *tokens,
1098 const struct tgsi_shader_info *info,
1099 struct tgsi_tessctrl_info *out)
1100 {
1101 memset(out, 0, sizeof(*out));
1102
1103 if (info->processor != PIPE_SHADER_TESS_CTRL)
1104 return;
1105
1106 struct tgsi_parse_context parse;
1107 if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
1108 debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
1109 return;
1110 }
1111
1112 /* The pass works as follows:
1113 * If all codepaths write tess factors, we can say that all invocations
1114 * define tess factors.
1115 *
1116 * Each tess factor channel is tracked separately.
1117 */
1118 unsigned main_block_tf_writemask = 0; /* if main block writes tess factors */
1119 unsigned cond_block_tf_writemask = 0; /* if cond block writes tess factors */
1120
1121 /* Initial value = true. Here the pass will accumulate results from multiple
1122 * segments surrounded by barriers. If tess factors aren't written at all,
1123 * it's a shader bug and we don't care if this will be true.
1124 */
1125 out->tessfactors_are_def_in_all_invocs = true;
1126
1127 while (!tgsi_parse_end_of_tokens(&parse)) {
1128 tgsi_parse_token(&parse);
1129
1130 if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
1131 continue;
1132
1133 struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1134 check_no_subroutines(inst);
1135
1136 /* Process nested blocks. */
1137 switch (inst->Instruction.Opcode) {
1138 case TGSI_OPCODE_IF:
1139 case TGSI_OPCODE_UIF:
1140 get_if_block_tessfactor_writemask(info, &parse,
1141 &main_block_tf_writemask,
1142 &cond_block_tf_writemask);
1143 continue;
1144
1145 case TGSI_OPCODE_BGNLOOP:
1146 cond_block_tf_writemask |=
1147 get_block_tessfactor_writemask(info, &parse, TGSI_OPCODE_ENDIF);
1148 continue;
1149
1150 case TGSI_OPCODE_BARRIER:
1151 /* The following case must be prevented:
1152 * gl_TessLevelInner = ...;
1153 * barrier();
1154 * if (gl_InvocationID == 1)
1155 * gl_TessLevelInner = ...;
1156 *
1157 * If you consider disjoint code segments separated by barriers, each
1158 * such segment that writes tess factor channels should write the same
1159 * channels in all codepaths within that segment.
1160 */
1161 if (main_block_tf_writemask || cond_block_tf_writemask) {
1162 /* Accumulate the result: */
1163 out->tessfactors_are_def_in_all_invocs &=
1164 !(cond_block_tf_writemask & ~main_block_tf_writemask);
1165
1166 /* Analyze the next code segment from scratch. */
1167 main_block_tf_writemask = 0;
1168 cond_block_tf_writemask = 0;
1169 }
1170 continue;
1171 }
1172
1173 main_block_tf_writemask |= get_inst_tessfactor_writemask(info, inst);
1174 }
1175
1176 /* Accumulate the result for the last code segment separated by a barrier. */
1177 if (main_block_tf_writemask || cond_block_tf_writemask) {
1178 out->tessfactors_are_def_in_all_invocs &=
1179 !(cond_block_tf_writemask & ~main_block_tf_writemask);
1180 }
1181
1182 tgsi_parse_free(&parse);
1183 }