2 * Copyright (c) 2019 Zodiac Inflight Innovations
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Jonathan Marek <jonathan@marek.ca>
27 #include "etnaviv_asm.h"
28 #include "etnaviv_context.h"
29 #include "etnaviv_compiler_nir.h"
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir/nir_builder.h"
33 #include "util/register_allocate.h"
35 #define ALU_SWIZ(s) INST_SWIZ((s)->swizzle[0], (s)->swizzle[1], (s)->swizzle[2], (s)->swizzle[3])
36 #define SRC_DISABLE ((hw_src){})
37 #define SRC_CONST(idx, s) ((hw_src){.use=1, .rgroup = INST_RGROUP_UNIFORM_0, .reg=idx, .swiz=s})
38 #define SRC_REG(idx, s) ((hw_src){.use=1, .rgroup = INST_RGROUP_TEMP, .reg=idx, .swiz=s})
40 #define emit(type, args...) etna_emit_##type(state->c, args)
42 typedef struct etna_inst_dst hw_dst
;
43 typedef struct etna_inst_src hw_src
;
46 struct etna_compile
*c
;
51 nir_function_impl
*impl
;
61 src_swizzle(hw_src src
, unsigned swizzle
)
63 if (src
.rgroup
!= INST_RGROUP_IMMEDIATE
)
64 src
.swiz
= inst_swiz_compose(src
.swiz
, swizzle
);
69 /* constants are represented as 64-bit ints
70 * 32-bit for the value and 32-bit for the type (imm, uniform, etc)
73 #define CONST_VAL(a, b) (nir_const_value) {.u64 = (uint64_t)(a) << 32 | (uint64_t)(b)}
74 #define CONST(x) CONST_VAL(ETNA_IMMEDIATE_CONSTANT, x)
75 #define UNIFORM(x) CONST_VAL(ETNA_IMMEDIATE_UNIFORM, x)
76 #define TEXSCALE(x, i) CONST_VAL(ETNA_IMMEDIATE_TEXRECT_SCALE_X + (i), x)
79 const_add(uint64_t *c
, uint64_t value
)
81 for (unsigned i
= 0; i
< 4; i
++) {
82 if (c
[i
] == value
|| !c
[i
]) {
91 const_src(struct state
*state
, nir_const_value
*value
, unsigned num_components
)
93 /* use inline immediates if possible */
94 if (state
->c
->specs
->halti
>= 2 && num_components
== 1 &&
95 value
[0].u64
>> 32 == ETNA_IMMEDIATE_CONSTANT
) {
96 uint32_t bits
= value
[0].u32
;
98 /* "float" - shifted by 12 */
99 if ((bits
& 0xfff) == 0)
100 return etna_immediate_src(0, bits
>> 12);
102 /* "unsigned" - raw 20 bit value */
103 if (bits
< (1 << 20))
104 return etna_immediate_src(2, bits
);
106 /* "signed" - sign extended 20-bit (sign included) value */
107 if (bits
>= 0xfff80000)
108 return etna_immediate_src(1, bits
);
113 for (i
= 0; swiz
< 0; i
++) {
114 uint64_t *a
= &state
->c
->consts
[i
*4];
116 memcpy(save
, a
, sizeof(save
));
118 for (unsigned j
= 0; j
< num_components
; j
++) {
119 int c
= const_add(a
, value
[j
].u64
);
121 memcpy(a
, save
, sizeof(save
));
129 assert(i
<= ETNA_MAX_IMM
/ 4);
130 state
->const_count
= MAX2(state
->const_count
, i
);
132 return SRC_CONST(i
- 1, swiz
);
135 /* Swizzles and write masks can be used to layer virtual non-interfering
136 * registers on top of the real VEC4 registers. For example, the virtual
137 * VEC3_XYZ register and the virtual SCALAR_W register that use the same
138 * physical VEC4 base register do not interfere.
141 REG_CLASS_VIRT_SCALAR
,
145 /* special vec2 class for fast transcendentals, limited to XY or ZW */
146 REG_CLASS_VIRT_VEC2T
,
147 /* special classes for LOAD - contiguous components */
148 REG_CLASS_VIRT_VEC2C
,
149 REG_CLASS_VIRT_VEC3C
,
155 REG_TYPE_VIRT_VEC3_XYZ
,
156 REG_TYPE_VIRT_VEC3_XYW
,
157 REG_TYPE_VIRT_VEC3_XZW
,
158 REG_TYPE_VIRT_VEC3_YZW
,
159 REG_TYPE_VIRT_VEC2_XY
,
160 REG_TYPE_VIRT_VEC2_XZ
,
161 REG_TYPE_VIRT_VEC2_XW
,
162 REG_TYPE_VIRT_VEC2_YZ
,
163 REG_TYPE_VIRT_VEC2_YW
,
164 REG_TYPE_VIRT_VEC2_ZW
,
165 REG_TYPE_VIRT_SCALAR_X
,
166 REG_TYPE_VIRT_SCALAR_Y
,
167 REG_TYPE_VIRT_SCALAR_Z
,
168 REG_TYPE_VIRT_SCALAR_W
,
169 REG_TYPE_VIRT_VEC2T_XY
,
170 REG_TYPE_VIRT_VEC2T_ZW
,
171 REG_TYPE_VIRT_VEC2C_XY
,
172 REG_TYPE_VIRT_VEC2C_YZ
,
173 REG_TYPE_VIRT_VEC2C_ZW
,
174 REG_TYPE_VIRT_VEC3C_XYZ
,
175 REG_TYPE_VIRT_VEC3C_YZW
,
179 /* writemask when used as dest */
181 reg_writemask
[NUM_REG_TYPES
] = {
182 [REG_TYPE_VEC4
] = 0xf,
183 [REG_TYPE_VIRT_SCALAR_X
] = 0x1,
184 [REG_TYPE_VIRT_SCALAR_Y
] = 0x2,
185 [REG_TYPE_VIRT_VEC2_XY
] = 0x3,
186 [REG_TYPE_VIRT_VEC2T_XY
] = 0x3,
187 [REG_TYPE_VIRT_VEC2C_XY
] = 0x3,
188 [REG_TYPE_VIRT_SCALAR_Z
] = 0x4,
189 [REG_TYPE_VIRT_VEC2_XZ
] = 0x5,
190 [REG_TYPE_VIRT_VEC2_YZ
] = 0x6,
191 [REG_TYPE_VIRT_VEC2C_YZ
] = 0x6,
192 [REG_TYPE_VIRT_VEC3_XYZ
] = 0x7,
193 [REG_TYPE_VIRT_VEC3C_XYZ
] = 0x7,
194 [REG_TYPE_VIRT_SCALAR_W
] = 0x8,
195 [REG_TYPE_VIRT_VEC2_XW
] = 0x9,
196 [REG_TYPE_VIRT_VEC2_YW
] = 0xa,
197 [REG_TYPE_VIRT_VEC3_XYW
] = 0xb,
198 [REG_TYPE_VIRT_VEC2_ZW
] = 0xc,
199 [REG_TYPE_VIRT_VEC2T_ZW
] = 0xc,
200 [REG_TYPE_VIRT_VEC2C_ZW
] = 0xc,
201 [REG_TYPE_VIRT_VEC3_XZW
] = 0xd,
202 [REG_TYPE_VIRT_VEC3_YZW
] = 0xe,
203 [REG_TYPE_VIRT_VEC3C_YZW
] = 0xe,
206 /* how to swizzle when used as a src */
208 reg_swiz
[NUM_REG_TYPES
] = {
209 [REG_TYPE_VEC4
] = INST_SWIZ_IDENTITY
,
210 [REG_TYPE_VIRT_SCALAR_X
] = INST_SWIZ_IDENTITY
,
211 [REG_TYPE_VIRT_SCALAR_Y
] = SWIZZLE(Y
, Y
, Y
, Y
),
212 [REG_TYPE_VIRT_VEC2_XY
] = INST_SWIZ_IDENTITY
,
213 [REG_TYPE_VIRT_VEC2T_XY
] = INST_SWIZ_IDENTITY
,
214 [REG_TYPE_VIRT_VEC2C_XY
] = INST_SWIZ_IDENTITY
,
215 [REG_TYPE_VIRT_SCALAR_Z
] = SWIZZLE(Z
, Z
, Z
, Z
),
216 [REG_TYPE_VIRT_VEC2_XZ
] = SWIZZLE(X
, Z
, X
, Z
),
217 [REG_TYPE_VIRT_VEC2_YZ
] = SWIZZLE(Y
, Z
, Y
, Z
),
218 [REG_TYPE_VIRT_VEC2C_YZ
] = SWIZZLE(Y
, Z
, Y
, Z
),
219 [REG_TYPE_VIRT_VEC3_XYZ
] = INST_SWIZ_IDENTITY
,
220 [REG_TYPE_VIRT_VEC3C_XYZ
] = INST_SWIZ_IDENTITY
,
221 [REG_TYPE_VIRT_SCALAR_W
] = SWIZZLE(W
, W
, W
, W
),
222 [REG_TYPE_VIRT_VEC2_XW
] = SWIZZLE(X
, W
, X
, W
),
223 [REG_TYPE_VIRT_VEC2_YW
] = SWIZZLE(Y
, W
, Y
, W
),
224 [REG_TYPE_VIRT_VEC3_XYW
] = SWIZZLE(X
, Y
, W
, X
),
225 [REG_TYPE_VIRT_VEC2_ZW
] = SWIZZLE(Z
, W
, Z
, W
),
226 [REG_TYPE_VIRT_VEC2T_ZW
] = SWIZZLE(Z
, W
, Z
, W
),
227 [REG_TYPE_VIRT_VEC2C_ZW
] = SWIZZLE(Z
, W
, Z
, W
),
228 [REG_TYPE_VIRT_VEC3_XZW
] = SWIZZLE(X
, Z
, W
, X
),
229 [REG_TYPE_VIRT_VEC3_YZW
] = SWIZZLE(Y
, Z
, W
, X
),
230 [REG_TYPE_VIRT_VEC3C_YZW
] = SWIZZLE(Y
, Z
, W
, X
),
233 /* how to swizzle when used as a dest */
235 reg_dst_swiz
[NUM_REG_TYPES
] = {
236 [REG_TYPE_VEC4
] = INST_SWIZ_IDENTITY
,
237 [REG_TYPE_VIRT_SCALAR_X
] = INST_SWIZ_IDENTITY
,
238 [REG_TYPE_VIRT_SCALAR_Y
] = SWIZZLE(X
, X
, X
, X
),
239 [REG_TYPE_VIRT_VEC2_XY
] = INST_SWIZ_IDENTITY
,
240 [REG_TYPE_VIRT_VEC2T_XY
] = INST_SWIZ_IDENTITY
,
241 [REG_TYPE_VIRT_VEC2C_XY
] = INST_SWIZ_IDENTITY
,
242 [REG_TYPE_VIRT_SCALAR_Z
] = SWIZZLE(X
, X
, X
, X
),
243 [REG_TYPE_VIRT_VEC2_XZ
] = SWIZZLE(X
, X
, Y
, Y
),
244 [REG_TYPE_VIRT_VEC2_YZ
] = SWIZZLE(X
, X
, Y
, Y
),
245 [REG_TYPE_VIRT_VEC2C_YZ
] = SWIZZLE(X
, X
, Y
, Y
),
246 [REG_TYPE_VIRT_VEC3_XYZ
] = INST_SWIZ_IDENTITY
,
247 [REG_TYPE_VIRT_VEC3C_XYZ
] = INST_SWIZ_IDENTITY
,
248 [REG_TYPE_VIRT_SCALAR_W
] = SWIZZLE(X
, X
, X
, X
),
249 [REG_TYPE_VIRT_VEC2_XW
] = SWIZZLE(X
, X
, Y
, Y
),
250 [REG_TYPE_VIRT_VEC2_YW
] = SWIZZLE(X
, X
, Y
, Y
),
251 [REG_TYPE_VIRT_VEC3_XYW
] = SWIZZLE(X
, Y
, Z
, Z
),
252 [REG_TYPE_VIRT_VEC2_ZW
] = SWIZZLE(X
, X
, X
, Y
),
253 [REG_TYPE_VIRT_VEC2T_ZW
] = SWIZZLE(X
, X
, X
, Y
),
254 [REG_TYPE_VIRT_VEC2C_ZW
] = SWIZZLE(X
, X
, X
, Y
),
255 [REG_TYPE_VIRT_VEC3_XZW
] = SWIZZLE(X
, Y
, Y
, Z
),
256 [REG_TYPE_VIRT_VEC3_YZW
] = SWIZZLE(X
, X
, Y
, Z
),
257 [REG_TYPE_VIRT_VEC3C_YZW
] = SWIZZLE(X
, X
, Y
, Z
),
260 static inline int reg_get_type(int virt_reg
)
262 return virt_reg
% NUM_REG_TYPES
;
265 static inline int reg_get_base(struct state
*state
, int virt_reg
)
267 /* offset by 1 to avoid reserved position register */
268 if (state
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
)
269 return (virt_reg
/ NUM_REG_TYPES
+ 1) % ETNA_MAX_TEMPS
;
270 return virt_reg
/ NUM_REG_TYPES
;
273 /* use "r63.z" for depth reg, it will wrap around to r0.z by reg_get_base
274 * (fs registers are offset by 1 to avoid reserving r0)
276 #define REG_FRAG_DEPTH ((ETNA_MAX_TEMPS - 1) * NUM_REG_TYPES + REG_TYPE_VIRT_SCALAR_Z)
278 static inline int reg_get_class(int virt_reg
)
280 switch (reg_get_type(virt_reg
)) {
282 return REG_CLASS_VEC4
;
283 case REG_TYPE_VIRT_VEC3_XYZ
:
284 case REG_TYPE_VIRT_VEC3_XYW
:
285 case REG_TYPE_VIRT_VEC3_XZW
:
286 case REG_TYPE_VIRT_VEC3_YZW
:
287 return REG_CLASS_VIRT_VEC3
;
288 case REG_TYPE_VIRT_VEC2_XY
:
289 case REG_TYPE_VIRT_VEC2_XZ
:
290 case REG_TYPE_VIRT_VEC2_XW
:
291 case REG_TYPE_VIRT_VEC2_YZ
:
292 case REG_TYPE_VIRT_VEC2_YW
:
293 case REG_TYPE_VIRT_VEC2_ZW
:
294 return REG_CLASS_VIRT_VEC2
;
295 case REG_TYPE_VIRT_SCALAR_X
:
296 case REG_TYPE_VIRT_SCALAR_Y
:
297 case REG_TYPE_VIRT_SCALAR_Z
:
298 case REG_TYPE_VIRT_SCALAR_W
:
299 return REG_CLASS_VIRT_SCALAR
;
300 case REG_TYPE_VIRT_VEC2T_XY
:
301 case REG_TYPE_VIRT_VEC2T_ZW
:
302 return REG_CLASS_VIRT_VEC2T
;
303 case REG_TYPE_VIRT_VEC2C_XY
:
304 case REG_TYPE_VIRT_VEC2C_YZ
:
305 case REG_TYPE_VIRT_VEC2C_ZW
:
306 return REG_CLASS_VIRT_VEC2C
;
307 case REG_TYPE_VIRT_VEC3C_XYZ
:
308 case REG_TYPE_VIRT_VEC3C_YZW
:
309 return REG_CLASS_VIRT_VEC3C
;
316 /* nir_src to allocated register */
318 ra_src(struct state
*state
, nir_src
*src
)
320 unsigned reg
= ra_get_node_reg(state
->g
, state
->live_map
[src_index(state
->impl
, src
)]);
321 return SRC_REG(reg_get_base(state
, reg
), reg_swiz
[reg_get_type(reg
)]);
325 get_src(struct state
*state
, nir_src
*src
)
328 return ra_src(state
, src
);
330 nir_instr
*instr
= src
->ssa
->parent_instr
;
332 if (instr
->pass_flags
& BYPASS_SRC
) {
333 assert(instr
->type
== nir_instr_type_alu
);
334 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
335 assert(alu
->op
== nir_op_mov
);
336 return src_swizzle(get_src(state
, &alu
->src
[0].src
), ALU_SWIZ(&alu
->src
[0]));
339 switch (instr
->type
) {
340 case nir_instr_type_load_const
:
341 return const_src(state
, nir_instr_as_load_const(instr
)->value
, src
->ssa
->num_components
);
342 case nir_instr_type_intrinsic
: {
343 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
344 switch (intr
->intrinsic
) {
345 case nir_intrinsic_load_input
:
346 case nir_intrinsic_load_instance_id
:
347 case nir_intrinsic_load_uniform
:
348 case nir_intrinsic_load_ubo
:
349 return ra_src(state
, src
);
350 case nir_intrinsic_load_front_face
:
351 return (hw_src
) { .use
= 1, .rgroup
= INST_RGROUP_INTERNAL
};
352 case nir_intrinsic_load_frag_coord
:
353 return SRC_REG(0, INST_SWIZ_IDENTITY
);
355 compile_error(state
->c
, "Unhandled NIR intrinsic type: %s\n",
356 nir_intrinsic_infos
[intr
->intrinsic
].name
);
360 case nir_instr_type_alu
:
361 case nir_instr_type_tex
:
362 return ra_src(state
, src
);
363 case nir_instr_type_ssa_undef
: {
364 /* return zero to deal with broken Blur demo */
365 nir_const_value value
= CONST(0);
366 return src_swizzle(const_src(state
, &value
, 1), SWIZZLE(X
,X
,X
,X
));
369 compile_error(state
->c
, "Unhandled NIR instruction type: %d\n", instr
->type
);
377 vec_dest_has_swizzle(nir_alu_instr
*vec
, nir_ssa_def
*ssa
)
379 for (unsigned i
= 0; i
< 4; i
++) {
380 if (!(vec
->dest
.write_mask
& (1 << i
)) || vec
->src
[i
].src
.ssa
!= ssa
)
383 if (vec
->src
[i
].swizzle
[0] != i
)
387 /* don't deal with possible bypassed vec/mov chain */
388 nir_foreach_use(use_src
, ssa
) {
389 nir_instr
*instr
= use_src
->parent_instr
;
390 if (instr
->type
!= nir_instr_type_alu
)
393 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
408 /* get allocated dest register for nir_dest
409 * *p_swiz tells how the components need to be placed into register
412 ra_dest(struct state
*state
, nir_dest
*dest
, unsigned *p_swiz
)
414 unsigned swiz
= INST_SWIZ_IDENTITY
, mask
= 0xf;
415 dest
= real_dest(dest
, &swiz
, &mask
);
417 unsigned r
= ra_get_node_reg(state
->g
, state
->live_map
[dest_index(state
->impl
, dest
)]);
418 unsigned t
= reg_get_type(r
);
420 *p_swiz
= inst_swiz_compose(swiz
, reg_dst_swiz
[t
]);
424 .reg
= reg_get_base(state
, r
),
425 .write_mask
= inst_write_mask_compose(mask
, reg_writemask
[t
]),
429 /* precomputed by register_allocate */
430 static unsigned int *q_values
[] = {
431 (unsigned int[]) {1, 2, 3, 4, 2, 2, 3, },
432 (unsigned int[]) {3, 5, 6, 6, 5, 5, 6, },
433 (unsigned int[]) {3, 4, 4, 4, 4, 4, 4, },
434 (unsigned int[]) {1, 1, 1, 1, 1, 1, 1, },
435 (unsigned int[]) {1, 2, 2, 2, 1, 2, 2, },
436 (unsigned int[]) {2, 3, 3, 3, 2, 3, 3, },
437 (unsigned int[]) {2, 2, 2, 2, 2, 2, 2, },
441 ra_assign(struct state
*state
, nir_shader
*shader
)
443 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, ETNA_MAX_TEMPS
*
444 NUM_REG_TYPES
, false);
446 /* classes always be created from index 0, so equal to the class enum
447 * which represents a register with (c+1) components
449 for (int c
= 0; c
< NUM_REG_CLASSES
; c
++)
450 ra_alloc_reg_class(regs
);
451 /* add each register of each class */
452 for (int r
= 0; r
< NUM_REG_TYPES
* ETNA_MAX_TEMPS
; r
++)
453 ra_class_add_reg(regs
, reg_get_class(r
), r
);
455 for (int r
= 0; r
< ETNA_MAX_TEMPS
; r
++) {
456 for (int i
= 0; i
< NUM_REG_TYPES
; i
++) {
457 for (int j
= 0; j
< i
; j
++) {
458 if (reg_writemask
[i
] & reg_writemask
[j
]) {
459 ra_add_reg_conflict(regs
, NUM_REG_TYPES
* r
+ i
,
460 NUM_REG_TYPES
* r
+ j
);
465 ra_set_finalize(regs
, q_values
);
467 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
469 /* liveness and interference */
471 nir_index_blocks(impl
);
472 nir_index_ssa_defs(impl
);
473 nir_foreach_block(block
, impl
) {
474 nir_foreach_instr(instr
, block
)
475 instr
->pass_flags
= 0;
478 /* this gives an approximation/upper limit on how many nodes are needed
479 * (some ssa values do not represent an allocated register)
481 unsigned max_nodes
= impl
->ssa_alloc
+ impl
->reg_alloc
;
482 unsigned *live_map
= ralloc_array(NULL
, unsigned, max_nodes
);
483 memset(live_map
, 0xff, sizeof(unsigned) * max_nodes
);
484 struct live_def
*defs
= rzalloc_array(NULL
, struct live_def
, max_nodes
);
486 unsigned num_nodes
= etna_live_defs(impl
, defs
, live_map
);
487 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, num_nodes
);
489 /* set classes from num_components */
490 for (unsigned i
= 0; i
< num_nodes
; i
++) {
491 nir_instr
*instr
= defs
[i
].instr
;
492 nir_dest
*dest
= defs
[i
].dest
;
493 unsigned c
= nir_dest_num_components(*dest
) - 1;
495 if (instr
->type
== nir_instr_type_alu
&&
496 state
->c
->specs
->has_new_transcendentals
) {
497 switch (nir_instr_as_alu(instr
)->op
) {
502 assert(dest
->is_ssa
);
503 c
= REG_CLASS_VIRT_VEC2T
;
509 if (instr
->type
== nir_instr_type_intrinsic
) {
510 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
511 /* can't have dst swizzle or sparse writemask on UBO loads */
512 if (intr
->intrinsic
== nir_intrinsic_load_ubo
) {
513 assert(dest
== &intr
->dest
);
514 if (dest
->ssa
.num_components
== 2)
515 c
= REG_CLASS_VIRT_VEC2C
;
516 if (dest
->ssa
.num_components
== 3)
517 c
= REG_CLASS_VIRT_VEC3C
;
521 ra_set_node_class(g
, i
, c
);
524 nir_foreach_block(block
, impl
) {
525 nir_foreach_instr(instr
, block
) {
526 if (instr
->type
!= nir_instr_type_intrinsic
)
529 nir_dest
*dest
= dest_for_instr(instr
);
530 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
533 switch (intr
->intrinsic
) {
534 case nir_intrinsic_store_deref
: {
535 /* don't want outputs to be swizzled
536 * TODO: better would be to set the type to X/XY/XYZ/XYZW
537 * TODO: what if fragcoord.z is read after writing fragdepth?
539 nir_deref_instr
*deref
= nir_src_as_deref(intr
->src
[0]);
540 unsigned index
= live_map
[src_index(impl
, &intr
->src
[1])];
542 if (shader
->info
.stage
== MESA_SHADER_FRAGMENT
&&
543 deref
->var
->data
.location
== FRAG_RESULT_DEPTH
) {
544 ra_set_node_reg(g
, index
, REG_FRAG_DEPTH
);
546 ra_set_node_class(g
, index
, REG_CLASS_VEC4
);
549 case nir_intrinsic_load_input
:
550 reg
= nir_intrinsic_base(intr
) * NUM_REG_TYPES
+ (unsigned[]) {
551 REG_TYPE_VIRT_SCALAR_X
,
552 REG_TYPE_VIRT_VEC2_XY
,
553 REG_TYPE_VIRT_VEC3_XYZ
,
555 }[nir_dest_num_components(*dest
) - 1];
557 case nir_intrinsic_load_instance_id
:
558 reg
= state
->c
->variant
->infile
.num_reg
* NUM_REG_TYPES
+ REG_TYPE_VIRT_SCALAR_Y
;
564 ra_set_node_reg(g
, live_map
[dest_index(impl
, dest
)], reg
);
568 /* add interference for intersecting live ranges */
569 for (unsigned i
= 0; i
< num_nodes
; i
++) {
570 assert(defs
[i
].live_start
< defs
[i
].live_end
);
571 for (unsigned j
= 0; j
< i
; j
++) {
572 if (defs
[i
].live_start
>= defs
[j
].live_end
|| defs
[j
].live_start
>= defs
[i
].live_end
)
574 ra_add_node_interference(g
, i
, j
);
580 /* Allocate registers */
581 ASSERTED
bool ok
= ra_allocate(g
);
586 state
->live_map
= live_map
;
587 state
->num_nodes
= num_nodes
;
591 ra_finish(struct state
*state
)
593 /* TODO: better way to get number of registers used? */
595 for (unsigned i
= 0; i
< state
->num_nodes
; i
++) {
596 j
= MAX2(j
, reg_get_base(state
, ra_get_node_reg(state
->g
, i
)) + 1);
599 ralloc_free(state
->g
);
600 ralloc_free(state
->regs
);
601 ralloc_free(state
->live_map
);
607 emit_alu(struct state
*state
, nir_alu_instr
* alu
)
609 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
611 /* marked as dead instruction (vecN and other bypassed instr) */
612 if (alu
->instr
.pass_flags
)
615 assert(!(alu
->op
>= nir_op_vec2
&& alu
->op
<= nir_op_vec4
));
618 hw_dst dst
= ra_dest(state
, &alu
->dest
.dest
, &dst_swiz
);
620 /* compose alu write_mask with RA write mask */
621 if (!alu
->dest
.dest
.is_ssa
)
622 dst
.write_mask
= inst_write_mask_compose(alu
->dest
.write_mask
, dst
.write_mask
);
628 /* not per-component - don't compose dst_swiz */
629 dst_swiz
= INST_SWIZ_IDENTITY
;
637 for (int i
= 0; i
< info
->num_inputs
; i
++) {
638 nir_alu_src
*asrc
= &alu
->src
[i
];
641 src
= src_swizzle(get_src(state
, &asrc
->src
), ALU_SWIZ(asrc
));
642 src
= src_swizzle(src
, dst_swiz
);
644 if (src
.rgroup
!= INST_RGROUP_IMMEDIATE
) {
645 src
.neg
= asrc
->negate
|| (alu
->op
== nir_op_fneg
);
646 src
.abs
= asrc
->abs
|| (alu
->op
== nir_op_fabs
);
648 assert(!asrc
->negate
&& alu
->op
!= nir_op_fneg
);
649 assert(!asrc
->abs
&& alu
->op
!= nir_op_fabs
);
655 emit(alu
, alu
->op
, dst
, srcs
, alu
->dest
.saturate
|| (alu
->op
== nir_op_fsat
));
659 emit_tex(struct state
*state
, nir_tex_instr
* tex
)
662 hw_dst dst
= ra_dest(state
, &tex
->dest
, &dst_swiz
);
663 nir_src
*coord
= NULL
, *lod_bias
= NULL
, *compare
= NULL
;
665 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
666 switch (tex
->src
[i
].src_type
) {
667 case nir_tex_src_coord
:
668 coord
= &tex
->src
[i
].src
;
670 case nir_tex_src_bias
:
671 case nir_tex_src_lod
:
673 lod_bias
= &tex
->src
[i
].src
;
675 case nir_tex_src_comparator
:
676 compare
= &tex
->src
[i
].src
;
679 compile_error(state
->c
, "Unhandled NIR tex src type: %d\n",
680 tex
->src
[i
].src_type
);
685 emit(tex
, tex
->op
, tex
->sampler_index
, dst_swiz
, dst
, get_src(state
, coord
),
686 lod_bias
? get_src(state
, lod_bias
) : SRC_DISABLE
,
687 compare
? get_src(state
, compare
) : SRC_DISABLE
);
691 emit_intrinsic(struct state
*state
, nir_intrinsic_instr
* intr
)
693 switch (intr
->intrinsic
) {
694 case nir_intrinsic_store_deref
:
695 emit(output
, nir_src_as_deref(intr
->src
[0])->var
, get_src(state
, &intr
->src
[1]));
697 case nir_intrinsic_discard_if
:
698 emit(discard
, get_src(state
, &intr
->src
[0]));
700 case nir_intrinsic_discard
:
701 emit(discard
, SRC_DISABLE
);
703 case nir_intrinsic_load_uniform
: {
705 struct etna_inst_dst dst
= ra_dest(state
, &intr
->dest
, &dst_swiz
);
707 /* TODO: rework so extra MOV isn't required, load up to 4 addresses at once */
708 emit_inst(state
->c
, &(struct etna_inst
) {
709 .opcode
= INST_OPCODE_MOVAR
,
710 .dst
.write_mask
= 0x1,
711 .src
[2] = get_src(state
, &intr
->src
[0]),
713 emit_inst(state
->c
, &(struct etna_inst
) {
714 .opcode
= INST_OPCODE_MOV
,
718 .rgroup
= INST_RGROUP_UNIFORM_0
,
719 .reg
= nir_intrinsic_base(intr
),
721 .amode
= INST_AMODE_ADD_A_X
,
725 case nir_intrinsic_load_ubo
: {
726 /* TODO: if offset is of the form (x + C) then add C to the base instead */
727 unsigned idx
= nir_src_as_const_value(intr
->src
[0])[0].u32
;
729 emit_inst(state
->c
, &(struct etna_inst
) {
730 .opcode
= INST_OPCODE_LOAD
,
731 .type
= INST_TYPE_U32
,
732 .dst
= ra_dest(state
, &intr
->dest
, &dst_swiz
),
733 .src
[0] = get_src(state
, &intr
->src
[1]),
734 .src
[1] = const_src(state
, &CONST_VAL(ETNA_IMMEDIATE_UBO0_ADDR
+ idx
, 0), 1),
737 case nir_intrinsic_load_front_face
:
738 case nir_intrinsic_load_frag_coord
:
739 assert(intr
->dest
.is_ssa
); /* TODO - lower phis could cause this */
741 case nir_intrinsic_load_input
:
742 case nir_intrinsic_load_instance_id
:
745 compile_error(state
->c
, "Unhandled NIR intrinsic type: %s\n",
746 nir_intrinsic_infos
[intr
->intrinsic
].name
);
751 emit_instr(struct state
*state
, nir_instr
* instr
)
753 switch (instr
->type
) {
754 case nir_instr_type_alu
:
755 emit_alu(state
, nir_instr_as_alu(instr
));
757 case nir_instr_type_tex
:
758 emit_tex(state
, nir_instr_as_tex(instr
));
760 case nir_instr_type_intrinsic
:
761 emit_intrinsic(state
, nir_instr_as_intrinsic(instr
));
763 case nir_instr_type_jump
:
764 assert(nir_instr_is_last(instr
));
765 case nir_instr_type_load_const
:
766 case nir_instr_type_ssa_undef
:
767 case nir_instr_type_deref
:
770 compile_error(state
->c
, "Unhandled NIR instruction type: %d\n", instr
->type
);
776 emit_block(struct state
*state
, nir_block
* block
)
778 emit(block_start
, block
->index
);
780 nir_foreach_instr(instr
, block
)
781 emit_instr(state
, instr
);
783 /* succs->index < block->index is for the loop case */
784 nir_block
*succs
= block
->successors
[0];
785 if (nir_block_ends_in_jump(block
) || succs
->index
< block
->index
)
786 emit(jump
, succs
->index
, SRC_DISABLE
);
790 emit_cf_list(struct state
*state
, struct exec_list
*list
);
793 emit_if(struct state
*state
, nir_if
* nif
)
795 emit(jump
, nir_if_first_else_block(nif
)->index
, get_src(state
, &nif
->condition
));
796 emit_cf_list(state
, &nif
->then_list
);
798 /* jump at end of then_list to skip else_list
799 * not needed if then_list already ends with a jump or else_list is empty
801 if (!nir_block_ends_in_jump(nir_if_last_then_block(nif
)) &&
802 !nir_cf_list_is_empty_block(&nif
->else_list
))
803 emit(jump
, nir_if_last_else_block(nif
)->successors
[0]->index
, SRC_DISABLE
);
805 emit_cf_list(state
, &nif
->else_list
);
809 emit_cf_list(struct state
*state
, struct exec_list
*list
)
811 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
812 switch (node
->type
) {
813 case nir_cf_node_block
:
814 emit_block(state
, nir_cf_node_as_block(node
));
817 emit_if(state
, nir_cf_node_as_if(node
));
819 case nir_cf_node_loop
:
820 emit_cf_list(state
, &nir_cf_node_as_loop(node
)->body
);
823 compile_error(state
->c
, "Unknown NIR node type\n");
829 /* based on nir_lower_vec_to_movs */
831 insert_vec_mov(nir_alu_instr
*vec
, unsigned start_idx
, nir_shader
*shader
)
833 assert(start_idx
< nir_op_infos
[vec
->op
].num_inputs
);
834 unsigned write_mask
= (1u << start_idx
);
836 nir_alu_instr
*mov
= nir_alu_instr_create(shader
, nir_op_mov
);
837 nir_alu_src_copy(&mov
->src
[0], &vec
->src
[start_idx
], mov
);
839 mov
->src
[0].swizzle
[0] = vec
->src
[start_idx
].swizzle
[0];
840 mov
->src
[0].negate
= vec
->src
[start_idx
].negate
;
841 mov
->src
[0].abs
= vec
->src
[start_idx
].abs
;
843 unsigned num_components
= 1;
845 for (unsigned i
= start_idx
+ 1; i
< 4; i
++) {
846 if (!(vec
->dest
.write_mask
& (1 << i
)))
849 if (nir_srcs_equal(vec
->src
[i
].src
, vec
->src
[start_idx
].src
) &&
850 vec
->src
[i
].negate
== vec
->src
[start_idx
].negate
&&
851 vec
->src
[i
].abs
== vec
->src
[start_idx
].abs
) {
852 write_mask
|= (1 << i
);
853 mov
->src
[0].swizzle
[num_components
] = vec
->src
[i
].swizzle
[0];
858 mov
->dest
.write_mask
= (1 << num_components
) - 1;
859 nir_ssa_dest_init(&mov
->instr
, &mov
->dest
.dest
, num_components
, 32, NULL
);
861 /* replace vec srcs with inserted mov */
862 for (unsigned i
= 0, j
= 0; i
< 4; i
++) {
863 if (!(write_mask
& (1 << i
)))
866 nir_instr_rewrite_src(&vec
->instr
, &vec
->src
[i
].src
, nir_src_for_ssa(&mov
->dest
.dest
.ssa
));
867 vec
->src
[i
].swizzle
[0] = j
++;
870 nir_instr_insert_before(&vec
->instr
, &mov
->instr
);
876 * for vecN instructions:
877 * -merge constant sources into a single src
878 * -insert movs (nir_lower_vec_to_movs equivalent)
879 * for non-vecN instructions:
880 * -try to merge constants as single constant
881 * -insert movs for multiple constants (pre-HALTI5)
884 lower_alu(struct state
*state
, nir_alu_instr
*alu
)
886 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
889 nir_builder_init(&b
, state
->impl
);
890 b
.cursor
= nir_before_instr(&alu
->instr
);
898 /* pre-GC7000L can only have 1 uniform src per instruction */
899 if (state
->c
->specs
->halti
>= 5)
902 nir_const_value value
[4] = {};
903 uint8_t swizzle
[4][4] = {};
904 unsigned swiz_max
= 0, num_const
= 0;
906 for (unsigned i
= 0; i
< info
->num_inputs
; i
++) {
907 nir_const_value
*cv
= nir_src_as_const_value(alu
->src
[i
].src
);
911 unsigned num_components
= info
->input_sizes
[i
] ?: alu
->dest
.dest
.ssa
.num_components
;
912 for (unsigned j
= 0; j
< num_components
; j
++) {
913 int idx
= const_add(&value
[0].u64
, cv
[alu
->src
[i
].swizzle
[j
]].u64
);
915 swiz_max
= MAX2(swiz_max
, (unsigned) idx
);
924 /* resolve with single combined const src */
926 nir_ssa_def
*def
= nir_build_imm(&b
, swiz_max
+ 1, 32, value
);
928 for (unsigned i
= 0; i
< info
->num_inputs
; i
++) {
929 nir_const_value
*cv
= nir_src_as_const_value(alu
->src
[i
].src
);
933 nir_instr_rewrite_src(&alu
->instr
, &alu
->src
[i
].src
, nir_src_for_ssa(def
));
935 for (unsigned j
= 0; j
< 4; j
++)
936 alu
->src
[i
].swizzle
[j
] = swizzle
[i
][j
];
941 /* resolve with movs */
943 for (unsigned i
= 0; i
< info
->num_inputs
; i
++) {
944 nir_const_value
*cv
= nir_src_as_const_value(alu
->src
[i
].src
);
952 nir_ssa_def
*mov
= nir_mov(&b
, alu
->src
[i
].src
.ssa
);
953 nir_instr_rewrite_src(&alu
->instr
, &alu
->src
[i
].src
, nir_src_for_ssa(mov
));
958 nir_const_value value
[4];
959 unsigned num_components
= 0;
961 for (unsigned i
= 0; i
< info
->num_inputs
; i
++) {
962 nir_const_value
*cv
= nir_src_as_const_value(alu
->src
[i
].src
);
964 value
[num_components
++] = cv
[alu
->src
[i
].swizzle
[0]];
967 /* if there is more than one constant source to the vecN, combine them
968 * into a single load_const (removing the vecN completely if all components
971 if (num_components
> 1) {
972 nir_ssa_def
*def
= nir_build_imm(&b
, num_components
, 32, value
);
974 if (num_components
== info
->num_inputs
) {
975 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(def
));
976 nir_instr_remove(&alu
->instr
);
980 for (unsigned i
= 0, j
= 0; i
< info
->num_inputs
; i
++) {
981 nir_const_value
*cv
= nir_src_as_const_value(alu
->src
[i
].src
);
985 nir_instr_rewrite_src(&alu
->instr
, &alu
->src
[i
].src
, nir_src_for_ssa(def
));
986 alu
->src
[i
].swizzle
[0] = j
++;
990 unsigned finished_write_mask
= 0;
991 for (unsigned i
= 0; i
< 4; i
++) {
992 if (!(alu
->dest
.write_mask
& (1 << i
)))
995 nir_ssa_def
*ssa
= alu
->src
[i
].src
.ssa
;
997 /* check that vecN instruction is only user of this */
998 bool need_mov
= list_length(&ssa
->if_uses
) != 0;
999 nir_foreach_use(use_src
, ssa
) {
1000 if (use_src
->parent_instr
!= &alu
->instr
)
1004 nir_instr
*instr
= ssa
->parent_instr
;
1005 switch (instr
->type
) {
1006 case nir_instr_type_alu
:
1007 case nir_instr_type_tex
:
1009 case nir_instr_type_intrinsic
:
1010 if (nir_instr_as_intrinsic(instr
)->intrinsic
== nir_intrinsic_load_input
) {
1011 need_mov
= vec_dest_has_swizzle(alu
, &nir_instr_as_intrinsic(instr
)->dest
.ssa
);
1018 if (need_mov
&& !(finished_write_mask
& (1 << i
)))
1019 finished_write_mask
|= insert_vec_mov(alu
, i
, state
->shader
);
1024 emit_shader(struct etna_compile
*c
, unsigned *num_temps
, unsigned *num_consts
)
1026 nir_shader
*shader
= c
->nir
;
1028 struct state state
= {
1031 .impl
= nir_shader_get_entrypoint(shader
),
1033 bool have_indirect_uniform
= false;
1034 unsigned indirect_max
= 0;
1037 nir_builder_init(&b
, state
.impl
);
1039 /* convert non-dynamic uniform loads to constants, etc */
1040 nir_foreach_block(block
, state
.impl
) {
1041 nir_foreach_instr_safe(instr
, block
) {
1042 switch(instr
->type
) {
1043 case nir_instr_type_alu
:
1044 /* deals with vecN and const srcs */
1045 lower_alu(&state
, nir_instr_as_alu(instr
));
1047 case nir_instr_type_load_const
: {
1048 nir_load_const_instr
*load_const
= nir_instr_as_load_const(instr
);
1049 for (unsigned i
= 0; i
< load_const
->def
.num_components
; i
++)
1050 load_const
->value
[i
] = CONST(load_const
->value
[i
].u32
);
1052 case nir_instr_type_intrinsic
: {
1053 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1054 /* TODO: load_ubo can also become a constant in some cases
1055 * (at the moment it can end up emitting a LOAD with two
1056 * uniform sources, which could be a problem on HALTI2)
1058 if (intr
->intrinsic
!= nir_intrinsic_load_uniform
)
1060 nir_const_value
*off
= nir_src_as_const_value(intr
->src
[0]);
1061 if (!off
|| off
[0].u64
>> 32 != ETNA_IMMEDIATE_CONSTANT
) {
1062 have_indirect_uniform
= true;
1063 indirect_max
= nir_intrinsic_base(intr
) + nir_intrinsic_range(intr
);
1067 unsigned base
= nir_intrinsic_base(intr
);
1068 /* pre halti2 uniform offset will be float */
1069 if (c
->specs
->halti
< 2)
1070 base
+= (unsigned) off
[0].f32
;
1073 nir_const_value value
[4];
1075 for (unsigned i
= 0; i
< intr
->dest
.ssa
.num_components
; i
++) {
1076 if (nir_intrinsic_base(intr
) < 0)
1077 value
[i
] = TEXSCALE(~nir_intrinsic_base(intr
), i
);
1079 value
[i
] = UNIFORM(base
* 4 + i
);
1082 b
.cursor
= nir_after_instr(instr
);
1083 nir_ssa_def
*def
= nir_build_imm(&b
, intr
->dest
.ssa
.num_components
, 32, value
);
1085 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(def
));
1086 nir_instr_remove(instr
);
1094 /* TODO: only emit required indirect uniform ranges */
1095 if (have_indirect_uniform
) {
1096 for (unsigned i
= 0; i
< indirect_max
* 4; i
++)
1097 c
->consts
[i
] = UNIFORM(i
).u64
;
1098 state
.const_count
= indirect_max
;
1101 /* add mov for any store output using sysval/const */
1102 nir_foreach_block(block
, state
.impl
) {
1103 nir_foreach_instr_safe(instr
, block
) {
1104 if (instr
->type
!= nir_instr_type_intrinsic
)
1107 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1109 switch (intr
->intrinsic
) {
1110 case nir_intrinsic_store_deref
: {
1111 nir_src
*src
= &intr
->src
[1];
1112 if (nir_src_is_const(*src
) || is_sysval(src
->ssa
->parent_instr
)) {
1113 b
.cursor
= nir_before_instr(instr
);
1114 nir_instr_rewrite_src(instr
, src
, nir_src_for_ssa(nir_mov(&b
, src
->ssa
)));
1123 /* call directly to avoid validation (load_const don't pass validation at this point) */
1124 nir_convert_from_ssa(shader
, true);
1125 nir_opt_dce(shader
);
1127 ra_assign(&state
, shader
);
1129 emit_cf_list(&state
, &nir_shader_get_entrypoint(shader
)->body
);
1131 *num_temps
= ra_finish(&state
);
1132 *num_consts
= state
.const_count
;