src/gallium/drivers/etnaviv/etnaviv_internal.h

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #ifndef H_ETNA_INTERNAL
  25 #define H_ETNA_INTERNAL
  26
  27 #include <assert.h>
  28 #include <stdbool.h>
  29 #include <stdint.h>
  30
  31 #include "hw/state.xml.h"
  32 #include "hw/state_3d.xml.h"
  33
  34 #include "drm/etnaviv_drmif.h"
  35
  36 #define ETNA_NUM_INPUTS (16)
  37 #define ETNA_NUM_VARYINGS 8
  38 #define ETNA_NUM_LOD (14)
  39 #define ETNA_NUM_LAYERS (6)
  40 #define ETNA_MAX_UNIFORMS (256)
  41 #define ETNA_MAX_CONST_BUF 16
  42 #define ETNA_MAX_PIXELPIPES 2
  43
  44 /* All RS operations must have width%16 = 0 */
  45 #define ETNA_RS_WIDTH_MASK (16 - 1)
  46 /* RS tiled operations must have height%4 = 0 */
  47 #define ETNA_RS_HEIGHT_MASK (3)
  48 /* PE render targets must be aligned to 64 bytes */
  49 #define ETNA_PE_ALIGNMENT (64)
  50
  51 /* These demarcate the margin (fixp16) between the computed sizes and the
  52   value sent to the chip. These have been set to the numbers used by the
  53   Vivante driver on gc2000. They used to be -1 for scissor right and bottom. I
  54   am not sure whether older hardware was relying on these or they were just a
  55   guess. But if so, these need to be moved to the _specs structure.
  56 */
  57 #define ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119)
  58 #define ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111)
  59 #define ETNA_SE_CLIP_MARGIN_RIGHT (0xffff)
  60 #define ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff)
  61
  62 /* GPU chip 3D specs */
  63 struct etna_specs {
  64    /* HALTI (gross architecture) level. -1 for pre-HALTI. */
  65    int halti : 8;
  66    /* supports SUPERTILE (64x64) tiling? */
  67    unsigned can_supertile : 1;
  68    /* needs z=(z+w)/2, for older GCxxx */
  69    unsigned vs_need_z_div : 1;
  70    /* supports trigonometric instructions */
  71    unsigned has_sin_cos_sqrt : 1;
  72    /* has SIGN/FLOOR/CEIL instructions */
  73    unsigned has_sign_floor_ceil : 1;
  74    /* can use VS_RANGE, PS_RANGE registers*/
  75    unsigned has_shader_range_registers : 1;
  76    /* has the new sin/cos/log functions */
  77    unsigned has_new_transcendentals : 1;
  78    /* has the new dp2/dpX_norm instructions, among others */
  79    unsigned has_halti2_instructions : 1;
  80    /* has V4_COMPRESSION */
  81    unsigned v4_compression : 1;
  82    /* supports single-buffer rendering with multiple pixel pipes */
  83    unsigned single_buffer : 1;
  84    /* has unified uniforms memory */
  85    unsigned has_unified_uniforms : 1;
  86    /* can load shader instructions from memory */
  87    unsigned has_icache : 1;
  88    /* ASTC texture support (and has associated states) */
  89    unsigned tex_astc : 1;
  90    /* has BLT engine instead of RS */
  91    unsigned use_blt : 1;
  92    /* can use any kind of wrapping mode on npot textures */
  93    unsigned npot_tex_any_wrap : 1;
  94    /* number of bits per TS tile */
  95    unsigned bits_per_tile;
  96    /* clear value for TS (dependent on bits_per_tile) */
  97    uint32_t ts_clear_value;
  98    /* base of vertex texture units */
  99    unsigned vertex_sampler_offset;
 100    /* number of fragment sampler units */
 101    unsigned fragment_sampler_count;
 102    /* number of vertex sampler units */
 103    unsigned vertex_sampler_count;
 104    /* size of vertex shader output buffer */
 105    unsigned vertex_output_buffer_size;
 106    /* maximum number of vertex element configurations */
 107    unsigned vertex_max_elements;
 108    /* size of a cached vertex (?) */
 109    unsigned vertex_cache_size;
 110    /* number of shader cores */
 111    unsigned shader_core_count;
 112    /* number of vertex streams */
 113    unsigned stream_count;
 114    /* vertex shader memory address*/
 115    uint32_t vs_offset;
 116    /* pixel shader memory address*/
 117    uint32_t ps_offset;
 118    /* vertex shader uniforms address*/
 119    uint32_t vs_uniforms_offset;
 120    /* pixel shader uniforms address*/
 121    uint32_t ps_uniforms_offset;
 122    /* vertex/fragment shader max instructions */
 123    uint32_t max_instructions;
 124    /* maximum number of varyings */
 125    unsigned max_varyings;
 126    /* maximum number of registers */
 127    unsigned max_registers;
 128    /* maximum vertex uniforms */
 129    unsigned max_vs_uniforms;
 130    /* maximum pixel uniforms */
 131    unsigned max_ps_uniforms;
 132    /* maximum texture size */
 133    unsigned max_texture_size;
 134    /* maximum texture size */
 135    unsigned max_rendertarget_size;
 136    /* available pixel pipes */
 137    unsigned pixel_pipes;
 138    /* number of constants */
 139    unsigned num_constants;
 140 };
 141
 142 /* Compiled Gallium state. All the different compiled state atoms are woven
 143  * together and uploaded only when it is necessary to synchronize the state,
 144  * for example before rendering. */
 145
 146 /* Compiled pipe_blend_color */
 147 struct compiled_blend_color {
 148    float color[4];
 149    uint32_t PE_ALPHA_BLEND_COLOR;
 150    uint32_t PE_ALPHA_COLOR_EXT0;
 151    uint32_t PE_ALPHA_COLOR_EXT1;
 152 };
 153
 154 /* Compiled pipe_stencil_ref */
 155 struct compiled_stencil_ref {
 156    uint32_t PE_STENCIL_CONFIG[2];
 157    uint32_t PE_STENCIL_CONFIG_EXT[2];
 158 };
 159
 160 /* Compiled pipe_scissor_state */
 161 struct compiled_scissor_state {
 162    uint32_t SE_SCISSOR_LEFT;
 163    uint32_t SE_SCISSOR_TOP;
 164    uint32_t SE_SCISSOR_RIGHT;
 165    uint32_t SE_SCISSOR_BOTTOM;
 166    uint32_t SE_CLIP_RIGHT;
 167    uint32_t SE_CLIP_BOTTOM;
 168 };
 169
 170 /* Compiled pipe_viewport_state */
 171 struct compiled_viewport_state {
 172    uint32_t PA_VIEWPORT_SCALE_X;
 173    uint32_t PA_VIEWPORT_SCALE_Y;
 174    uint32_t PA_VIEWPORT_SCALE_Z;
 175    uint32_t PA_VIEWPORT_OFFSET_X;
 176    uint32_t PA_VIEWPORT_OFFSET_Y;
 177    uint32_t PA_VIEWPORT_OFFSET_Z;
 178    uint32_t SE_SCISSOR_LEFT;
 179    uint32_t SE_SCISSOR_TOP;
 180    uint32_t SE_SCISSOR_RIGHT;
 181    uint32_t SE_SCISSOR_BOTTOM;
 182    uint32_t SE_CLIP_RIGHT;
 183    uint32_t SE_CLIP_BOTTOM;
 184    uint32_t PE_DEPTH_NEAR;
 185    uint32_t PE_DEPTH_FAR;
 186 };
 187
 188 /* Compiled pipe_framebuffer_state */
 189 struct compiled_framebuffer_state {
 190    uint32_t GL_MULTI_SAMPLE_CONFIG;
 191    uint32_t PE_COLOR_FORMAT;
 192    uint32_t PE_DEPTH_CONFIG;
 193    struct etna_reloc PE_DEPTH_ADDR;
 194    struct etna_reloc PE_PIPE_DEPTH_ADDR[ETNA_MAX_PIXELPIPES];
 195    uint32_t PE_DEPTH_STRIDE;
 196    uint32_t PE_HDEPTH_CONTROL;
 197    uint32_t PE_DEPTH_NORMALIZE;
 198    struct etna_reloc PE_COLOR_ADDR;
 199    struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
 200    uint32_t PE_COLOR_STRIDE;
 201    uint32_t PE_MEM_CONFIG;
 202    uint32_t SE_SCISSOR_LEFT;
 203    uint32_t SE_SCISSOR_TOP;
 204    uint32_t SE_SCISSOR_RIGHT;
 205    uint32_t SE_SCISSOR_BOTTOM;
 206    uint32_t SE_CLIP_RIGHT;
 207    uint32_t SE_CLIP_BOTTOM;
 208    uint32_t RA_MULTISAMPLE_UNK00E04;
 209    uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
 210    uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];
 211    uint32_t TS_MEM_CONFIG;
 212    uint32_t TS_DEPTH_CLEAR_VALUE;
 213    struct etna_reloc TS_DEPTH_STATUS_BASE;
 214    struct etna_reloc TS_DEPTH_SURFACE_BASE;
 215    uint32_t TS_COLOR_CLEAR_VALUE;
 216    uint32_t TS_COLOR_CLEAR_VALUE_EXT;
 217    struct etna_reloc TS_COLOR_STATUS_BASE;
 218    struct etna_reloc TS_COLOR_SURFACE_BASE;
 219    uint32_t PE_LOGIC_OP;
 220    uint32_t PS_CONTROL;
 221    uint32_t PS_CONTROL_EXT;
 222    bool msaa_mode; /* adds input (and possible temp) to PS */
 223 };
 224
 225 /* Compiled context->create_vertex_elements_state */
 226 struct compiled_vertex_elements_state {
 227    unsigned num_elements;
 228    uint32_t FE_VERTEX_ELEMENT_CONFIG[VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN];
 229    uint32_t NFE_GENERIC_ATTRIB_CONFIG0[VIVS_NFE_GENERIC_ATTRIB__LEN];
 230    uint32_t NFE_GENERIC_ATTRIB_SCALE[VIVS_NFE_GENERIC_ATTRIB__LEN];
 231    uint32_t NFE_GENERIC_ATTRIB_CONFIG1[VIVS_NFE_GENERIC_ATTRIB__LEN];
 232    unsigned num_buffers;
 233    uint32_t NFE_VERTEX_STREAMS_VERTEX_DIVISOR[VIVS_NFE_VERTEX_STREAMS__LEN];
 234 };
 235
 236 /* Compiled context->set_vertex_buffer result */
 237 struct compiled_set_vertex_buffer {
 238    uint32_t FE_VERTEX_STREAM_CONTROL;
 239    struct etna_reloc FE_VERTEX_STREAM_BASE_ADDR;
 240 };
 241
 242 /* Compiled linked VS+PS shader state */
 243 struct compiled_shader_state {
 244    uint32_t RA_CONTROL;
 245    uint32_t PA_ATTRIBUTE_ELEMENT_COUNT;
 246    uint32_t PA_CONFIG;
 247    uint32_t PA_SHADER_ATTRIBUTES[VIVS_PA_SHADER_ATTRIBUTES__LEN];
 248    uint32_t VS_END_PC;
 249    uint32_t VS_OUTPUT_COUNT; /* number of outputs if point size per vertex disabled */
 250    uint32_t VS_OUTPUT_COUNT_PSIZE; /* number of outputs of point size per vertex enabled */
 251    uint32_t VS_INPUT_COUNT;
 252    uint32_t VS_TEMP_REGISTER_CONTROL;
 253    uint32_t VS_OUTPUT[4];
 254    uint32_t VS_INPUT[4];
 255    uint32_t VS_LOAD_BALANCING;
 256    uint32_t VS_START_PC;
 257    uint32_t PS_END_PC;
 258    uint32_t PS_OUTPUT_REG;
 259    uint32_t PS_INPUT_COUNT;
 260    uint32_t PS_INPUT_COUNT_MSAA; /* Adds an input */
 261    uint32_t PS_TEMP_REGISTER_CONTROL;
 262    uint32_t PS_TEMP_REGISTER_CONTROL_MSAA; /* Adds a temporary if needed to make space for extra input */
 263    uint32_t PS_START_PC;
 264    uint32_t PE_DEPTH_CONFIG;
 265    uint32_t GL_VARYING_TOTAL_COMPONENTS;
 266    uint32_t GL_VARYING_NUM_COMPONENTS;
 267    uint32_t GL_VARYING_COMPONENT_USE[2];
 268    uint32_t GL_HALTI5_SH_SPECIALS;
 269    uint32_t FE_HALTI5_ID_CONFIG;
 270    unsigned vs_inst_mem_size;
 271    unsigned ps_inst_mem_size;
 272    uint32_t *VS_INST_MEM;
 273    uint32_t *PS_INST_MEM;
 274    struct etna_reloc PS_INST_ADDR;
 275    struct etna_reloc VS_INST_ADDR;
 276 };
 277
 278 /* Helpers to assist creating and setting bitarrays (eg, for varyings).
 279  * field_size must be a power of two, and <= 32. */
 280 #define DEFINE_ETNA_BITARRAY(name, num, field_size) \
 281    uint32_t name[(num) * (field_size) / 32]
 282
 283 static inline void
 284 etna_bitarray_set(uint32_t *array, size_t array_size, size_t field_size,
 285                   size_t index, uint32_t value)
 286 {
 287    size_t shift = (index * field_size) % 32;
 288    size_t offset = (index * field_size) / 32;
 289
 290    assert(index < array_size * 32 / field_size);
 291    assert(value < 1 << field_size);
 292
 293    array[offset] |= value << shift;
 294 }
 295
 296 #define etna_bitarray_set(array, field_size, index, value) \
 297    etna_bitarray_set((array), ARRAY_SIZE(array), field_size, index, value)
 298
 299 #endif