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[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_rs.c
1 /*
2 * Copyright (c) 2012-2017 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_rs.h"
28
29 #include "hw/common.xml.h"
30
31 #include "etnaviv_clear_blit.h"
32 #include "etnaviv_context.h"
33 #include "etnaviv_emit.h"
34 #include "etnaviv_format.h"
35 #include "etnaviv_resource.h"
36 #include "etnaviv_screen.h"
37 #include "etnaviv_surface.h"
38 #include "etnaviv_tiling.h"
39 #include "etnaviv_translate.h"
40 #include "etnaviv_util.h"
41
42 #include "pipe/p_defines.h"
43 #include "pipe/p_state.h"
44 #include "util/u_blitter.h"
45 #include "util/u_inlines.h"
46 #include "util/u_memory.h"
47 #include "util/u_surface.h"
48
49 #include "hw/common.xml.h"
50 #include "hw/state.xml.h"
51 #include "hw/state_3d.xml.h"
52
53 #include <assert.h>
54
55 void
56 etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs,
57 const struct rs_state *rs)
58 {
59 memset(cs, 0, sizeof(*cs));
60
61 /* TILED and SUPERTILED layout have their strides multiplied with 4 in RS */
62 unsigned source_stride_shift = COND(rs->source_tiling != ETNA_LAYOUT_LINEAR, 2);
63 unsigned dest_stride_shift = COND(rs->dest_tiling != ETNA_LAYOUT_LINEAR, 2);
64
65 /* tiling == ETNA_LAYOUT_MULTI_TILED or ETNA_LAYOUT_MULTI_SUPERTILED? */
66 int source_multi = COND(rs->source_tiling & ETNA_LAYOUT_BIT_MULTI, 1);
67 int dest_multi = COND(rs->dest_tiling & ETNA_LAYOUT_BIT_MULTI, 1);
68
69 /* Vivante RS needs widths to be a multiple of 16 or bad things
70 * happen, such as scribbing over memory, or the GPU hanging,
71 * even for non-tiled formats. As this is serious, use abort().
72 */
73 if (rs->width & ETNA_RS_WIDTH_MASK)
74 abort();
75
76 /* TODO could just pre-generate command buffer, would simply submit to one memcpy */
77 cs->RS_CONFIG = VIVS_RS_CONFIG_SOURCE_FORMAT(rs->source_format) |
78 COND(rs->downsample_x, VIVS_RS_CONFIG_DOWNSAMPLE_X) |
79 COND(rs->downsample_y, VIVS_RS_CONFIG_DOWNSAMPLE_Y) |
80 COND(rs->source_tiling & 1, VIVS_RS_CONFIG_SOURCE_TILED) |
81 VIVS_RS_CONFIG_DEST_FORMAT(rs->dest_format) |
82 COND(rs->dest_tiling & 1, VIVS_RS_CONFIG_DEST_TILED) |
83 COND(rs->swap_rb, VIVS_RS_CONFIG_SWAP_RB) |
84 COND(rs->flip, VIVS_RS_CONFIG_FLIP);
85
86 cs->RS_SOURCE_STRIDE = (rs->source_stride << source_stride_shift) |
87 COND(rs->source_tiling & 2, VIVS_RS_SOURCE_STRIDE_TILING) |
88 COND(source_multi, VIVS_RS_SOURCE_STRIDE_MULTI);
89
90 /* Initially all pipes are set to the base address of the source and
91 * destination buffer respectively. This will be overridden below as
92 * necessary for the multi-pipe, multi-tiled case.
93 */
94 for (unsigned pipe = 0; pipe < ctx->specs.pixel_pipes; ++pipe) {
95 cs->source[pipe].bo = rs->source;
96 cs->source[pipe].offset = rs->source_offset;
97 cs->source[pipe].flags = ETNA_RELOC_READ;
98
99 cs->dest[pipe].bo = rs->dest;
100 cs->dest[pipe].offset = rs->dest_offset;
101 cs->dest[pipe].flags = ETNA_RELOC_WRITE;
102
103 cs->RS_PIPE_OFFSET[pipe] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(0);
104 }
105
106 cs->RS_DEST_STRIDE = (rs->dest_stride << dest_stride_shift) |
107 COND(rs->dest_tiling & 2, VIVS_RS_DEST_STRIDE_TILING) |
108 COND(dest_multi, VIVS_RS_DEST_STRIDE_MULTI);
109
110 if (ctx->specs.pixel_pipes == 1 || ctx->specs.single_buffer) {
111 cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
112 VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height);
113 } else if (ctx->specs.pixel_pipes == 2) {
114 assert((rs->height & 7) == 0); /* GPU hangs happen if height not 8-aligned */
115
116 if (source_multi)
117 cs->source[1].offset = rs->source_offset + rs->source_stride * rs->source_padded_height / 2;
118
119 if (dest_multi)
120 cs->dest[1].offset = rs->dest_offset + rs->dest_stride * rs->dest_padded_height / 2;
121
122 cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
123 VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height / 2);
124 cs->RS_PIPE_OFFSET[1] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(rs->height / 2);
125 } else {
126 abort();
127 }
128
129 cs->RS_DITHER[0] = rs->dither[0];
130 cs->RS_DITHER[1] = rs->dither[1];
131 cs->RS_CLEAR_CONTROL = VIVS_RS_CLEAR_CONTROL_BITS(rs->clear_bits) | rs->clear_mode;
132 cs->RS_FILL_VALUE[0] = rs->clear_value[0];
133 cs->RS_FILL_VALUE[1] = rs->clear_value[1];
134 cs->RS_FILL_VALUE[2] = rs->clear_value[2];
135 cs->RS_FILL_VALUE[3] = rs->clear_value[3];
136 cs->RS_EXTRA_CONFIG = VIVS_RS_EXTRA_CONFIG_AA(rs->aa) |
137 VIVS_RS_EXTRA_CONFIG_ENDIAN(rs->endian_mode);
138
139 /* If source the same as destination, and the hardware supports this,
140 * do an in-place resolve to fill in unrendered tiles.
141 */
142 if (ctx->specs.single_buffer && rs->source == rs->dest &&
143 rs->source_offset == rs->dest_offset &&
144 rs->source_format == rs->dest_format &&
145 rs->source_tiling == rs->dest_tiling &&
146 rs->source_stride == rs->dest_stride &&
147 !rs->downsample_x && !rs->downsample_y &&
148 !rs->swap_rb && !rs->flip &&
149 !rs->clear_mode && rs->source_padded_width) {
150 /* Total number of tiles (same as for autodisable) */
151 cs->RS_KICKER_INPLACE = rs->source_padded_width * rs->source_padded_height / 16;
152 }
153 cs->source_ts_valid = rs->source_ts_valid;
154 }
155
156 /* modify the clear bits value in the compiled RS state */
157 static void
158 etna_modify_rs_clearbits(struct compiled_rs_state *cs, uint32_t clear_bits)
159 {
160 cs->RS_CLEAR_CONTROL &= ~VIVS_RS_CLEAR_CONTROL_BITS__MASK;
161 cs->RS_CLEAR_CONTROL |= VIVS_RS_CLEAR_CONTROL_BITS(clear_bits);
162 }
163
164 #define EMIT_STATE(state_name, src_value) \
165 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
166
167 #define EMIT_STATE_FIXP(state_name, src_value) \
168 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
169
170 #define EMIT_STATE_RELOC(state_name, src_value) \
171 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
172
173 /* submit RS state, without any processing and no dependence on context
174 * except TS if this is a source-to-destination blit. */
175 static void
176 etna_submit_rs_state(struct etna_context *ctx,
177 const struct compiled_rs_state *cs)
178 {
179 struct etna_screen *screen = etna_screen(ctx->base.screen);
180 struct etna_cmd_stream *stream = ctx->stream;
181 struct etna_coalesce coalesce;
182
183 if (cs->RS_KICKER_INPLACE && !cs->source_ts_valid)
184 /* Inplace resolve is no-op if TS is not configured */
185 return;
186
187 ctx->stats.rs_operations++;
188
189 if (cs->RS_KICKER_INPLACE) {
190 etna_cmd_stream_reserve(stream, 6);
191 etna_coalesce_start(stream, &coalesce);
192 /* 0/1 */ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
193 /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
194 /* 4/5 */ EMIT_STATE(RS_KICKER_INPLACE, cs->RS_KICKER_INPLACE);
195 etna_coalesce_end(stream, &coalesce);
196 } else if (screen->specs.pixel_pipes == 1) {
197 etna_cmd_stream_reserve(stream, 22);
198 etna_coalesce_start(stream, &coalesce);
199 /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG);
200 /* 2 */ EMIT_STATE_RELOC(RS_SOURCE_ADDR, &cs->source[0]);
201 /* 3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
202 /* 4 */ EMIT_STATE_RELOC(RS_DEST_ADDR, &cs->dest[0]);
203 /* 5 */ EMIT_STATE(RS_DEST_STRIDE, cs->RS_DEST_STRIDE);
204 /* 6/7 */ EMIT_STATE(RS_WINDOW_SIZE, cs->RS_WINDOW_SIZE);
205 /* 8/9 */ EMIT_STATE(RS_DITHER(0), cs->RS_DITHER[0]);
206 /*10 */ EMIT_STATE(RS_DITHER(1), cs->RS_DITHER[1]);
207 /*11 - pad */
208 /*12/13*/ EMIT_STATE(RS_CLEAR_CONTROL, cs->RS_CLEAR_CONTROL);
209 /*14 */ EMIT_STATE(RS_FILL_VALUE(0), cs->RS_FILL_VALUE[0]);
210 /*15 */ EMIT_STATE(RS_FILL_VALUE(1), cs->RS_FILL_VALUE[1]);
211 /*16 */ EMIT_STATE(RS_FILL_VALUE(2), cs->RS_FILL_VALUE[2]);
212 /*17 */ EMIT_STATE(RS_FILL_VALUE(3), cs->RS_FILL_VALUE[3]);
213 /*18/19*/ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
214 /*20/21*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb);
215 etna_coalesce_end(stream, &coalesce);
216 } else if (screen->specs.pixel_pipes == 2) {
217 etna_cmd_stream_reserve(stream, 34); /* worst case - both pipes multi=1 */
218 etna_coalesce_start(stream, &coalesce);
219 /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG);
220 /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
221 /* 4/5 */ EMIT_STATE(RS_DEST_STRIDE, cs->RS_DEST_STRIDE);
222 /* 6/7 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(0), &cs->source[0]);
223 if (cs->RS_SOURCE_STRIDE & VIVS_RS_SOURCE_STRIDE_MULTI) {
224 /*8 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(1), &cs->source[1]);
225 /*9 - pad */
226 }
227 /*10/11*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(0), &cs->dest[0]);
228 if (cs->RS_DEST_STRIDE & VIVS_RS_DEST_STRIDE_MULTI) {
229 /*12*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(1), &cs->dest[1]);
230 /*13 - pad */
231 }
232 /*14/15*/ EMIT_STATE(RS_PIPE_OFFSET(0), cs->RS_PIPE_OFFSET[0]);
233 /*16 */ EMIT_STATE(RS_PIPE_OFFSET(1), cs->RS_PIPE_OFFSET[1]);
234 /*17 - pad */
235 /*18/19*/ EMIT_STATE(RS_WINDOW_SIZE, cs->RS_WINDOW_SIZE);
236 /*20/21*/ EMIT_STATE(RS_DITHER(0), cs->RS_DITHER[0]);
237 /*22 */ EMIT_STATE(RS_DITHER(1), cs->RS_DITHER[1]);
238 /*23 - pad */
239 /*24/25*/ EMIT_STATE(RS_CLEAR_CONTROL, cs->RS_CLEAR_CONTROL);
240 /*26 */ EMIT_STATE(RS_FILL_VALUE(0), cs->RS_FILL_VALUE[0]);
241 /*27 */ EMIT_STATE(RS_FILL_VALUE(1), cs->RS_FILL_VALUE[1]);
242 /*28 */ EMIT_STATE(RS_FILL_VALUE(2), cs->RS_FILL_VALUE[2]);
243 /*29 */ EMIT_STATE(RS_FILL_VALUE(3), cs->RS_FILL_VALUE[3]);
244 /*30/31*/ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
245 /*32/33*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb);
246 etna_coalesce_end(stream, &coalesce);
247 } else {
248 abort();
249 }
250 }
251
252 /* Generate clear command for a surface (non-fast clear case) */
253 void
254 etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface *surf,
255 uint32_t clear_value)
256 {
257 struct etna_resource *dst = etna_resource(surf->base.texture);
258 uint32_t format = translate_rs_format(surf->base.format);
259
260 if (format == ETNA_NO_MATCH) {
261 BUG("etna_rs_gen_clear_surface: Unhandled clear fmt %s", util_format_name(surf->base.format));
262 format = RS_FORMAT_A8R8G8B8;
263 assert(0);
264 }
265
266 /* use tiled clear if width is multiple of 16 */
267 bool tiled_clear = (surf->surf.padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
268 (surf->surf.padded_height & ETNA_RS_HEIGHT_MASK) == 0;
269
270 etna_compile_rs_state( ctx, &surf->clear_command, &(struct rs_state) {
271 .source_format = format,
272 .dest_format = format,
273 .dest = dst->bo,
274 .dest_offset = surf->surf.offset,
275 .dest_stride = surf->surf.stride,
276 .dest_padded_height = surf->surf.padded_height,
277 .dest_tiling = tiled_clear ? dst->layout : ETNA_LAYOUT_LINEAR,
278 .dither = {0xffffffff, 0xffffffff},
279 .width = surf->surf.padded_width, /* These must be padded to 16x4 if !LINEAR, otherwise RS will hang */
280 .height = surf->surf.padded_height,
281 .clear_value = {clear_value},
282 .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
283 .clear_bits = 0xffff
284 });
285 }
286
287 static void
288 etna_blit_clear_color_rs(struct pipe_context *pctx, struct pipe_surface *dst,
289 const union pipe_color_union *color)
290 {
291 struct etna_context *ctx = etna_context(pctx);
292 struct etna_surface *surf = etna_surface(dst);
293 uint32_t new_clear_value = etna_clear_blit_pack_rgba(surf->base.format, color->f);
294
295 if (surf->surf.ts_size) { /* TS: use precompiled clear command */
296 ctx->framebuffer.TS_COLOR_CLEAR_VALUE = new_clear_value;
297
298 if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
299 /* Set number of color tiles to be filled */
300 etna_set_state(ctx->stream, VIVS_TS_COLOR_AUTO_DISABLE_COUNT,
301 surf->surf.padded_width * surf->surf.padded_height / 16);
302 ctx->framebuffer.TS_MEM_CONFIG |= VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE;
303 }
304
305 surf->level->ts_valid = true;
306 ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
307 } else if (unlikely(new_clear_value != surf->level->clear_value)) { /* Queue normal RS clear for non-TS surfaces */
308 /* If clear color changed, re-generate stored command */
309 etna_rs_gen_clear_surface(ctx, surf, new_clear_value);
310 }
311
312 etna_submit_rs_state(ctx, &surf->clear_command);
313
314 surf->level->clear_value = new_clear_value;
315 resource_written(ctx, surf->base.texture);
316 etna_resource(surf->base.texture)->seqno++;
317 }
318
319 static void
320 etna_blit_clear_zs_rs(struct pipe_context *pctx, struct pipe_surface *dst,
321 unsigned buffers, double depth, unsigned stencil)
322 {
323 struct etna_context *ctx = etna_context(pctx);
324 struct etna_surface *surf = etna_surface(dst);
325 uint32_t new_clear_value = translate_clear_depth_stencil(surf->base.format, depth, stencil);
326 uint32_t new_clear_bits = 0, clear_bits_depth, clear_bits_stencil;
327
328 /* Get the channels to clear */
329 switch (surf->base.format) {
330 case PIPE_FORMAT_Z16_UNORM:
331 clear_bits_depth = 0xffff;
332 clear_bits_stencil = 0;
333 break;
334 case PIPE_FORMAT_X8Z24_UNORM:
335 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
336 clear_bits_depth = 0xeeee;
337 clear_bits_stencil = 0x1111;
338 break;
339 default:
340 clear_bits_depth = clear_bits_stencil = 0xffff;
341 break;
342 }
343
344 if (buffers & PIPE_CLEAR_DEPTH)
345 new_clear_bits |= clear_bits_depth;
346 if (buffers & PIPE_CLEAR_STENCIL)
347 new_clear_bits |= clear_bits_stencil;
348 /* FIXME: when tile status is enabled, this becomes more complex as
349 * we may separately clear the depth from the stencil. In this case,
350 * we want to resolve the surface, and avoid using the tile status.
351 * We may be better off recording the pending clear operation,
352 * delaying the actual clear to the first use. This way, we can merge
353 * consecutive clears together. */
354 if (surf->surf.ts_size) { /* TS: use precompiled clear command */
355 /* Set new clear depth value */
356 ctx->framebuffer.TS_DEPTH_CLEAR_VALUE = new_clear_value;
357 if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
358 /* Set number of depth tiles to be filled */
359 etna_set_state(ctx->stream, VIVS_TS_DEPTH_AUTO_DISABLE_COUNT,
360 surf->surf.padded_width * surf->surf.padded_height / 16);
361 ctx->framebuffer.TS_MEM_CONFIG |= VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE;
362 }
363
364 surf->level->ts_valid = true;
365 ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
366 } else {
367 if (unlikely(new_clear_value != surf->level->clear_value)) { /* Queue normal RS clear for non-TS surfaces */
368 /* If clear depth value changed, re-generate stored command */
369 etna_rs_gen_clear_surface(ctx, surf, new_clear_value);
370 }
371 /* Update the channels to be cleared */
372 etna_modify_rs_clearbits(&surf->clear_command, new_clear_bits);
373 }
374
375 etna_submit_rs_state(ctx, &surf->clear_command);
376
377 surf->level->clear_value = new_clear_value;
378 resource_written(ctx, surf->base.texture);
379 etna_resource(surf->base.texture)->seqno++;
380 }
381
382 static void
383 etna_clear_rs(struct pipe_context *pctx, unsigned buffers,
384 const union pipe_color_union *color, double depth, unsigned stencil)
385 {
386 struct etna_context *ctx = etna_context(pctx);
387
388 /* Flush color and depth cache before clearing anything.
389 * This is especially important when coming from another surface, as
390 * otherwise it may clear part of the old surface instead. */
391 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
392 etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
393
394 /* Preparation: Flush the TS if needed. This must be done after flushing
395 * color and depth, otherwise it can result in crashes */
396 bool need_ts_flush = false;
397 if ((buffers & PIPE_CLEAR_COLOR) && ctx->framebuffer_s.nr_cbufs) {
398 struct etna_surface *surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
399 if (surf->surf.ts_size)
400 need_ts_flush = true;
401 }
402 if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && ctx->framebuffer_s.zsbuf != NULL) {
403 struct etna_surface *surf = etna_surface(ctx->framebuffer_s.zsbuf);
404
405 if (surf->surf.ts_size)
406 need_ts_flush = true;
407 }
408
409 if (need_ts_flush)
410 etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
411
412 /* No need to set up the TS here as RS clear operations (in contrast to
413 * resolve and copy) do not require the TS state.
414 */
415 if (buffers & PIPE_CLEAR_COLOR) {
416 for (int idx = 0; idx < ctx->framebuffer_s.nr_cbufs; ++idx) {
417 etna_blit_clear_color_rs(pctx, ctx->framebuffer_s.cbufs[idx],
418 &color[idx]);
419 }
420 }
421
422 /* Flush the color and depth caches before each RS clear operation
423 * This fixes a hang on GC600. */
424 if (buffers & PIPE_CLEAR_DEPTHSTENCIL && buffers & PIPE_CLEAR_COLOR)
425 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
426 VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
427
428 if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && ctx->framebuffer_s.zsbuf != NULL)
429 etna_blit_clear_zs_rs(pctx, ctx->framebuffer_s.zsbuf, buffers, depth, stencil);
430
431 etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
432 }
433
434 static bool
435 etna_manual_blit(struct etna_resource *dst, struct etna_resource_level *dst_lev,
436 unsigned int dst_offset, struct etna_resource *src,
437 struct etna_resource_level *src_lev, unsigned int src_offset,
438 const struct pipe_blit_info *blit_info)
439 {
440 void *smap, *srow, *dmap, *drow;
441 size_t tile_size;
442
443 assert(src->layout == ETNA_LAYOUT_TILED);
444 assert(dst->layout == ETNA_LAYOUT_TILED);
445 assert(src->base.nr_samples == 0);
446 assert(dst->base.nr_samples == 0);
447
448 tile_size = util_format_get_blocksize(blit_info->src.format) * 4 * 4;
449
450 smap = etna_bo_map(src->bo);
451 if (!smap)
452 return false;
453
454 dmap = etna_bo_map(dst->bo);
455 if (!dmap)
456 return false;
457
458 srow = smap + src_offset;
459 drow = dmap + dst_offset;
460
461 etna_bo_cpu_prep(src->bo, DRM_ETNA_PREP_READ);
462 etna_bo_cpu_prep(dst->bo, DRM_ETNA_PREP_WRITE);
463
464 for (int y = 0; y < blit_info->src.box.height; y += 4) {
465 memcpy(drow, srow, tile_size * blit_info->src.box.width);
466 srow += src_lev->stride * 4;
467 drow += dst_lev->stride * 4;
468 }
469
470 etna_bo_cpu_fini(dst->bo);
471 etna_bo_cpu_fini(src->bo);
472
473 return true;
474 }
475
476 static inline size_t
477 etna_compute_tileoffset(const struct pipe_box *box, enum pipe_format format,
478 size_t stride, enum etna_surface_layout layout)
479 {
480 size_t offset;
481 unsigned int x = box->x, y = box->y;
482 unsigned int blocksize = util_format_get_blocksize(format);
483
484 switch (layout) {
485 case ETNA_LAYOUT_LINEAR:
486 offset = y * stride + x * blocksize;
487 break;
488 case ETNA_LAYOUT_MULTI_TILED:
489 y >>= 1;
490 /* fall-through */
491 case ETNA_LAYOUT_TILED:
492 assert(!(x & 0x03) && !(y & 0x03));
493 offset = (y & ~0x03) * stride + blocksize * ((x & ~0x03) << 2);
494 break;
495 case ETNA_LAYOUT_MULTI_SUPERTILED:
496 y >>= 1;
497 /* fall-through */
498 case ETNA_LAYOUT_SUPER_TILED:
499 assert(!(x & 0x3f) && !(y & 0x3f));
500 offset = (y & ~0x3f) * stride + blocksize * ((x & ~0x3f) << 6);
501 break;
502 default:
503 unreachable("invalid resource layout");
504 }
505
506 return offset;
507 }
508
509 static inline void
510 etna_get_rs_alignment_mask(const struct etna_context *ctx,
511 const enum etna_surface_layout layout,
512 unsigned int *width_mask, unsigned int *height_mask)
513 {
514 unsigned int h_align, w_align;
515
516 if (layout & ETNA_LAYOUT_BIT_SUPER) {
517 w_align = h_align = 64;
518 } else {
519 w_align = ETNA_RS_WIDTH_MASK + 1;
520 h_align = ETNA_RS_HEIGHT_MASK + 1;
521 }
522
523 h_align *= ctx->screen->specs.pixel_pipes;
524
525 *width_mask = w_align - 1;
526 *height_mask = h_align -1;
527 }
528
529 static bool
530 etna_try_rs_blit(struct pipe_context *pctx,
531 const struct pipe_blit_info *blit_info)
532 {
533 struct etna_context *ctx = etna_context(pctx);
534 struct etna_resource *src = etna_resource(blit_info->src.resource);
535 struct etna_resource *dst = etna_resource(blit_info->dst.resource);
536 struct compiled_rs_state copy_to_screen;
537 uint32_t ts_mem_config = 0;
538 int msaa_xscale = 1, msaa_yscale = 1;
539
540 /* Ensure that the level is valid */
541 assert(blit_info->src.level <= src->base.last_level);
542 assert(blit_info->dst.level <= dst->base.last_level);
543
544 if (!translate_samples_to_xyscale(src->base.nr_samples, &msaa_xscale, &msaa_yscale, NULL))
545 return FALSE;
546
547 /* The width/height are in pixels; they do not change as a result of
548 * multi-sampling. So, when blitting from a 4x multisampled surface
549 * to a non-multisampled surface, the width and height will be
550 * identical. As we do not support scaling, reject different sizes. */
551 if (blit_info->dst.box.width != blit_info->src.box.width ||
552 blit_info->dst.box.height != blit_info->src.box.height) {
553 DBG("scaling requested: source %dx%d destination %dx%d",
554 blit_info->src.box.width, blit_info->src.box.height,
555 blit_info->dst.box.width, blit_info->dst.box.height);
556 return FALSE;
557 }
558
559 /* No masks - RS can't copy specific channels */
560 unsigned mask = util_format_get_mask(blit_info->dst.format);
561 if ((blit_info->mask & mask) != mask) {
562 DBG("sub-mask requested: 0x%02x vs format mask 0x%02x", blit_info->mask, mask);
563 return FALSE;
564 }
565
566 unsigned src_format = etna_compatible_rs_format(blit_info->src.format);
567 unsigned dst_format = etna_compatible_rs_format(blit_info->dst.format);
568 if (translate_rs_format(src_format) == ETNA_NO_MATCH ||
569 translate_rs_format(dst_format) == ETNA_NO_MATCH ||
570 blit_info->scissor_enable ||
571 blit_info->dst.box.depth != blit_info->src.box.depth ||
572 blit_info->dst.box.depth != 1) {
573 return FALSE;
574 }
575
576 unsigned w_mask, h_mask;
577
578 etna_get_rs_alignment_mask(ctx, src->layout, &w_mask, &h_mask);
579 if ((blit_info->src.box.x & w_mask) || (blit_info->src.box.y & h_mask))
580 return FALSE;
581
582 etna_get_rs_alignment_mask(ctx, dst->layout, &w_mask, &h_mask);
583 if ((blit_info->dst.box.x & w_mask) || (blit_info->dst.box.y & h_mask))
584 return FALSE;
585
586 /* Ensure that the Z coordinate is sane */
587 if (dst->base.target != PIPE_TEXTURE_CUBE)
588 assert(blit_info->dst.box.z == 0);
589 if (src->base.target != PIPE_TEXTURE_CUBE)
590 assert(blit_info->src.box.z == 0);
591
592 assert(blit_info->src.box.z < src->base.array_size);
593 assert(blit_info->dst.box.z < dst->base.array_size);
594
595 struct etna_resource_level *src_lev = &src->levels[blit_info->src.level];
596 struct etna_resource_level *dst_lev = &dst->levels[blit_info->dst.level];
597
598 /* we may be given coordinates up to the padded width to avoid
599 * any alignment issues with different tiling formats */
600 assert((blit_info->src.box.x + blit_info->src.box.width) * msaa_xscale <= src_lev->padded_width);
601 assert((blit_info->src.box.y + blit_info->src.box.height) * msaa_yscale <= src_lev->padded_height);
602 assert(blit_info->dst.box.x + blit_info->dst.box.width <= dst_lev->padded_width);
603 assert(blit_info->dst.box.y + blit_info->dst.box.height <= dst_lev->padded_height);
604
605 unsigned src_offset = src_lev->offset +
606 blit_info->src.box.z * src_lev->layer_stride +
607 etna_compute_tileoffset(&blit_info->src.box,
608 blit_info->src.format,
609 src_lev->stride,
610 src->layout);
611 unsigned dst_offset = dst_lev->offset +
612 blit_info->dst.box.z * dst_lev->layer_stride +
613 etna_compute_tileoffset(&blit_info->dst.box,
614 blit_info->dst.format,
615 dst_lev->stride,
616 dst->layout);
617
618 if (src_lev->padded_width <= ETNA_RS_WIDTH_MASK ||
619 dst_lev->padded_width <= ETNA_RS_WIDTH_MASK ||
620 src_lev->padded_height <= ETNA_RS_HEIGHT_MASK ||
621 dst_lev->padded_height <= ETNA_RS_HEIGHT_MASK)
622 goto manual;
623
624 /* If the width is not aligned to the RS width, but is within our
625 * padding, adjust the width to suite the RS width restriction.
626 * Note: the RS width/height are converted to source samples here. */
627 unsigned int width = blit_info->src.box.width * msaa_xscale;
628 unsigned int height = blit_info->src.box.height * msaa_yscale;
629 unsigned int w_align = ETNA_RS_WIDTH_MASK + 1;
630 unsigned int h_align = (ETNA_RS_HEIGHT_MASK + 1) * ctx->specs.pixel_pipes;
631
632 if (width & (w_align - 1) && width >= src_lev->width * msaa_xscale && width >= dst_lev->width)
633 width = align(width, w_align);
634
635 if (height & (h_align - 1) && height >= src_lev->height * msaa_yscale && height >= dst_lev->height)
636 height = align(height, h_align);
637
638 /* The padded dimensions are in samples */
639 if (width > src_lev->padded_width ||
640 width > dst_lev->padded_width * msaa_xscale ||
641 height > src_lev->padded_height ||
642 height > dst_lev->padded_height * msaa_yscale ||
643 width & (w_align - 1) || height & (h_align - 1))
644 goto manual;
645
646 if (src->base.nr_samples > 1) {
647 uint32_t msaa_format = translate_msaa_format(src_format);
648 assert(msaa_format != ETNA_NO_MATCH);
649 ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION | msaa_format;
650 }
651
652 /* Always flush color and depth cache together before resolving. This works
653 * around artifacts that appear in some cases when scanning out a texture
654 * directly after it has been rendered to, such as rendering an animated web
655 * page in a QtWebEngine based WebView on GC2000. The artifacts look like
656 * the texture sampler samples zeroes instead of texture data in a small,
657 * irregular triangle in the lower right of each browser tile quad. Other
658 * attempts to avoid these artifacts, including a pipeline stall before the
659 * color flush or a TS cache flush afterwards, or flushing multiple times,
660 * with stalls before and after each flush, have shown no effect. */
661 if (src->base.bind & PIPE_BIND_RENDER_TARGET ||
662 src->base.bind & PIPE_BIND_DEPTH_STENCIL) {
663 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
664 VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
665 etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
666
667 if (src->levels[blit_info->src.level].ts_size &&
668 src->levels[blit_info->src.level].ts_valid)
669 etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
670 }
671
672 /* Set up color TS to source surface before blit, if needed */
673 bool source_ts_valid = false;
674 if (src->levels[blit_info->src.level].ts_size &&
675 src->levels[blit_info->src.level].ts_valid) {
676 struct etna_reloc reloc;
677 unsigned ts_offset =
678 src_lev->ts_offset + blit_info->src.box.z * src_lev->ts_layer_stride;
679
680 etna_set_state(ctx->stream, VIVS_TS_MEM_CONFIG,
681 VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR | ts_mem_config);
682
683 memset(&reloc, 0, sizeof(struct etna_reloc));
684 reloc.bo = src->ts_bo;
685 reloc.offset = ts_offset;
686 reloc.flags = ETNA_RELOC_READ;
687 etna_set_state_reloc(ctx->stream, VIVS_TS_COLOR_STATUS_BASE, &reloc);
688
689 memset(&reloc, 0, sizeof(struct etna_reloc));
690 reloc.bo = src->bo;
691 reloc.offset = src_lev->offset +
692 blit_info->src.box.z * src_lev->layer_stride;
693 reloc.flags = ETNA_RELOC_READ;
694 etna_set_state_reloc(ctx->stream, VIVS_TS_COLOR_SURFACE_BASE, &reloc);
695
696 etna_set_state(ctx->stream, VIVS_TS_COLOR_CLEAR_VALUE,
697 src->levels[blit_info->src.level].clear_value);
698
699 source_ts_valid = true;
700 } else {
701 etna_set_state(ctx->stream, VIVS_TS_MEM_CONFIG, ts_mem_config);
702 }
703 ctx->dirty |= ETNA_DIRTY_TS;
704
705 /* Kick off RS here */
706 etna_compile_rs_state(ctx, &copy_to_screen, &(struct rs_state) {
707 .source_format = translate_rs_format(src_format),
708 .source_tiling = src->layout,
709 .source = src->bo,
710 .source_offset = src_offset,
711 .source_stride = src_lev->stride,
712 .source_padded_width = src_lev->padded_width,
713 .source_padded_height = src_lev->padded_height,
714 .source_ts_valid = source_ts_valid,
715 .dest_format = translate_rs_format(dst_format),
716 .dest_tiling = dst->layout,
717 .dest = dst->bo,
718 .dest_offset = dst_offset,
719 .dest_stride = dst_lev->stride,
720 .dest_padded_height = dst_lev->padded_height,
721 .downsample_x = msaa_xscale > 1,
722 .downsample_y = msaa_yscale > 1,
723 .swap_rb = translate_rb_src_dst_swap(src->base.format, dst->base.format),
724 .dither = {0xffffffff, 0xffffffff}, // XXX dither when going from 24 to 16 bit?
725 .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_DISABLED,
726 .width = width,
727 .height = height
728 });
729
730 etna_submit_rs_state(ctx, &copy_to_screen);
731 resource_written(ctx, &dst->base);
732 dst->seqno++;
733 dst->levels[blit_info->dst.level].ts_valid = false;
734 ctx->dirty |= ETNA_DIRTY_DERIVE_TS;
735
736 return TRUE;
737
738 manual:
739 if (src->layout == ETNA_LAYOUT_TILED && dst->layout == ETNA_LAYOUT_TILED) {
740 if ((src->status & ETNA_PENDING_WRITE) ||
741 (dst->status & ETNA_PENDING_WRITE))
742 pctx->flush(pctx, NULL, 0);
743 return etna_manual_blit(dst, dst_lev, dst_offset, src, src_lev, src_offset, blit_info);
744 }
745
746 return FALSE;
747 }
748
749 static void
750 etna_blit_rs(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
751 {
752 /* This is a more extended version of resource_copy_region */
753 /* TODO Some cases can be handled by RS; if not, fall back to rendering or
754 * even CPU copy block of pixels from info->src to info->dst
755 * (resource, level, box, format);
756 * function is used for scaling, flipping in x and y direction (negative
757 * width/height), format conversion, mask and filter and even a scissor rectangle
758 *
759 * What can the RS do for us:
760 * convert between tiling formats (layouts)
761 * downsample 2x in x and y
762 * convert between a limited number of pixel formats
763 *
764 * For the rest, fall back to util_blitter
765 * XXX this goes wrong when source surface is supertiled. */
766 struct etna_context *ctx = etna_context(pctx);
767 struct pipe_blit_info info = *blit_info;
768
769 if (info.src.resource->nr_samples > 1 &&
770 info.dst.resource->nr_samples <= 1 &&
771 !util_format_is_depth_or_stencil(info.src.resource->format) &&
772 !util_format_is_pure_integer(info.src.resource->format)) {
773 DBG("color resolve unimplemented");
774 return;
775 }
776
777 if (etna_try_rs_blit(pctx, blit_info))
778 return;
779
780 if (util_try_blit_via_copy_region(pctx, blit_info))
781 return;
782
783 if (info.mask & PIPE_MASK_S) {
784 DBG("cannot blit stencil, skipping");
785 info.mask &= ~PIPE_MASK_S;
786 }
787
788 if (!util_blitter_is_blit_supported(ctx->blitter, &info)) {
789 DBG("blit unsupported %s -> %s",
790 util_format_short_name(info.src.resource->format),
791 util_format_short_name(info.dst.resource->format));
792 return;
793 }
794
795 etna_blit_save_state(ctx);
796 util_blitter_blit(ctx->blitter, &info);
797 }
798
799 void
800 etna_clear_blit_rs_init(struct pipe_context *pctx)
801 {
802 DBG("etnaviv: Using RS blit engine\n");
803 pctx->clear = etna_clear_rs;
804 pctx->blit = etna_blit_rs;
805 }