src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_blend.h"
  33 #include "etnaviv_clear_blit.h"
  34 #include "etnaviv_context.h"
  35 #include "etnaviv_format.h"
  36 #include "etnaviv_shader.h"
  37 #include "etnaviv_surface.h"
  38 #include "etnaviv_translate.h"
  39 #include "etnaviv_util.h"
  40 #include "util/u_framebuffer.h"
  41 #include "util/u_helpers.h"
  42 #include "util/u_inlines.h"
  43 #include "util/u_math.h"
  44 #include "util/u_memory.h"
  45 #include "util/u_upload_mgr.h"
  46
  47 static void
  48 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  49 {
  50    struct etna_context *ctx = etna_context(pctx);
  51    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  52
  53    ctx->stencil_ref_s = *sr;
  54
  55    for (unsigned i = 0; i < 2; i++) {
  56       cs->PE_STENCIL_CONFIG[i] =
  57          VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[i]);
  58       cs->PE_STENCIL_CONFIG_EXT[i] =
  59          VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[!i]);
  60    }
  61    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  62 }
  63
  64 static void
  65 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  66 {
  67    /* NOOP */
  68 }
  69
  70 static void
  71 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  72 {
  73    struct etna_context *ctx = etna_context(pctx);
  74
  75    ctx->sample_mask = sample_mask;
  76    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  77 }
  78
  79 static void
  80 etna_set_constant_buffer(struct pipe_context *pctx,
  81       enum pipe_shader_type shader, uint index,
  82       const struct pipe_constant_buffer *cb)
  83 {
  84    struct etna_context *ctx = etna_context(pctx);
  85
  86    assert(index < ETNA_MAX_CONST_BUF);
  87
  88    util_copy_constant_buffer(&ctx->constant_buffer[shader][index], cb);
  89
  90    /* Note that the state tracker can unbind constant buffers by
  91     * passing NULL here. */
  92    if (unlikely(!cb || (!cb->buffer && !cb->user_buffer)))
  93       return;
  94
  95    assert(index != 0 || cb->user_buffer != NULL);
  96
  97    if (!cb->buffer) {
  98       struct pipe_constant_buffer *cb = &ctx->constant_buffer[shader][index];
  99       u_upload_data(pctx->const_uploader, 0, cb->buffer_size, 16, cb->user_buffer, &cb->buffer_offset, &cb->buffer);
 100    }
 101
 102    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
 103 }
 104
 105 static void
 106 etna_update_render_resource(struct pipe_context *pctx, struct etna_resource *base)
 107 {
 108    struct etna_resource *to = base, *from = base;
 109
 110    if (base->texture && etna_resource_newer(etna_resource(base->texture), base))
 111       from = etna_resource(base->texture);
 112
 113    if (base->render)
 114       to = etna_resource(base->render);
 115
 116    if ((to != from) && etna_resource_older(to, from)) {
 117       etna_copy_resource(pctx, &to->base, &from->base, 0, base->base.last_level);
 118       to->seqno = from->seqno;
 119    }
 120 }
 121
 122 static void
 123 etna_set_framebuffer_state(struct pipe_context *pctx,
 124       const struct pipe_framebuffer_state *fb)
 125 {
 126    struct etna_context *ctx = etna_context(pctx);
 127    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 128    int nr_samples_color = -1;
 129    int nr_samples_depth = -1;
 130
 131    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 132    uint32_t ts_mem_config = 0;
 133    uint32_t pe_mem_config = 0;
 134    uint32_t pe_logic_op = 0;
 135
 136    if (fb->nr_cbufs > 0) { /* at least one color buffer? */
 137       struct etna_surface *cbuf = etna_surface(fb->cbufs[0]);
 138       struct etna_resource *res = etna_resource(cbuf->base.texture);
 139       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 140       uint32_t fmt = translate_pe_format(cbuf->base.format);
 141
 142       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 143       etna_update_render_resource(pctx, etna_resource(cbuf->prsc));
 144
 145       if (fmt >= PE_FORMAT_R16F)
 146           cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt) |
 147                                 VIVS_PE_COLOR_FORMAT_FORMAT_MASK;
 148       else
 149           cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt);
 150
 151       cs->PE_COLOR_FORMAT |=
 152          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 153          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 154          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) |
 155          COND(color_supertiled && ctx->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
 156       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 157        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 158        * but only if we set the bits above. */
 159       /* merged with depth_stencil_alpha */
 160       if ((cbuf->surf.offset & 63) ||
 161           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 162          /* XXX Must make temporary surface here.
 163           * Need the same mechanism on gc2000 when we want to do mipmap
 164           * generation by
 165           * rendering to levels > 1 due to multitiled / tiled conversion. */
 166          BUG("Alignment error, trying to render to offset %08x with tile "
 167              "stride %i",
 168              cbuf->surf.offset, cbuf->surf.stride * 4);
 169       }
 170
 171       if (ctx->specs.pixel_pipes == 1) {
 172          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 173          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 174       } else {
 175          /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
 176          assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer);
 177          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 178             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 179             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 180          }
 181       }
 182       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 183
 184       if (cbuf->surf.ts_size) {
 185          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 186          cs->TS_COLOR_CLEAR_VALUE_EXT = cbuf->level->clear_value >> 32;
 187
 188          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 189          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 190
 191          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 192          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 193
 194          pe_mem_config |= VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(cbuf->level->ts_mode);
 195
 196          if (cbuf->level->ts_compress_fmt >= 0) {
 197             /* overwrite bit breaks v1/v2 compression */
 198             if (!ctx->specs.v4_compression)
 199                cs->PE_COLOR_FORMAT &= ~VIVS_PE_COLOR_FORMAT_OVERWRITE;
 200
 201             ts_mem_config |=
 202                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
 203                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(cbuf->level->ts_compress_fmt);
 204          }
 205       }
 206
 207       nr_samples_color = cbuf->base.texture->nr_samples;
 208
 209       if (util_format_is_srgb(cbuf->base.format))
 210          pe_logic_op |= VIVS_PE_LOGIC_OP_SRGB;
 211
 212       cs->PS_CONTROL = COND(util_format_is_unorm(cbuf->base.format), VIVS_PS_CONTROL_SATURATE_RT0);
 213       cs->PS_CONTROL_EXT =
 214          VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(translate_output_mode(cbuf->base.format, ctx->specs.halti >= 5));
 215    } else {
 216       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 217        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 218        * color target */
 219       cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE;
 220       cs->PE_COLOR_STRIDE = 0;
 221       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 222       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 223
 224       cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc;
 225       for (int i = 0; i < ctx->specs.pixel_pipes; i++)
 226          cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
 227    }
 228
 229    if (fb->zsbuf != NULL) {
 230       struct etna_surface *zsbuf = etna_surface(fb->zsbuf);
 231       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 232
 233       etna_update_render_resource(pctx, etna_resource(zsbuf->prsc));
 234
 235       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 236
 237       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 238       unsigned depth_bits =
 239          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 240       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 241
 242       cs->PE_DEPTH_CONFIG =
 243          depth_format |
 244          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 245          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
 246          VIVS_PE_DEPTH_CONFIG_UNK18 | /* something to do with clipping? */
 247          COND(ctx->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */
 248          ;
 249       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 250       /* merged with depth_stencil_alpha */
 251
 252       if (ctx->specs.pixel_pipes == 1) {
 253          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 254          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 255       } else {
 256          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 257             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 258             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 259          }
 260       }
 261
 262       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 263       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 264       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 265
 266       if (zsbuf->surf.ts_size) {
 267          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 268
 269          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 270          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 271
 272          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 273          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 274
 275          pe_mem_config |= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf->level->ts_mode);
 276
 277          if (zsbuf->level->ts_compress_fmt >= 0) {
 278             ts_mem_config |=
 279                VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION |
 280                COND(zsbuf->level->ts_compress_fmt == COMPRESSION_FORMAT_D24S8,
 281                     VIVS_TS_MEM_CONFIG_STENCIL_ENABLE);
 282          }
 283       }
 284
 285       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 286
 287       nr_samples_depth = zsbuf->base.texture->nr_samples;
 288    } else {
 289       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 290       cs->PE_DEPTH_ADDR.bo = NULL;
 291       cs->PE_DEPTH_STRIDE = 0;
 292       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 293       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 294
 295       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 296          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 297    }
 298
 299    /* MSAA setup */
 300    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 301        nr_samples_depth != nr_samples_color) {
 302       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 303           nr_samples_color, nr_samples_depth);
 304    }
 305
 306    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 307    case 0:
 308    case 1: /* Are 0 and 1 samples allowed? */
 309       cs->GL_MULTI_SAMPLE_CONFIG =
 310          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 311       cs->msaa_mode = false;
 312       break;
 313    case 2:
 314       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 315       cs->msaa_mode = true; /* Add input to PS */
 316       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 317       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 318       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 319       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 320       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 321       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 322       break;
 323    case 4:
 324       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 325       cs->msaa_mode = true; /* Add input to PS */
 326       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 327       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 328       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 329       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 330       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 331       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 332       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 333       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 334       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 335       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 336       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 337       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 338       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 339       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 340       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 341       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 342       break;
 343    }
 344
 345    /* Scissor setup */
 346    cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
 347    cs->SE_SCISSOR_TOP = 0;
 348    cs->SE_SCISSOR_RIGHT = (fb->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 349    cs->SE_SCISSOR_BOTTOM = (fb->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 350    cs->SE_CLIP_RIGHT = (fb->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 351    cs->SE_CLIP_BOTTOM = (fb->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 352
 353    cs->TS_MEM_CONFIG = ts_mem_config;
 354    cs->PE_MEM_CONFIG = pe_mem_config;
 355
 356    /* Single buffer setup. There is only one switch for this, not a separate
 357     * one per color buffer / depth buffer. To keep the logic simple always use
 358     * single buffer when this feature is available.
 359     * note: the blob will use 2 in some situations, figure out why?
 360     */
 361    pe_logic_op |= VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 3 : 0);
 362    cs->PE_LOGIC_OP = pe_logic_op;
 363
 364    /* keep copy of original structure */
 365    util_copy_framebuffer_state(&ctx->framebuffer_s, fb);
 366    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
 367 }
 368
 369 static void
 370 etna_set_polygon_stipple(struct pipe_context *pctx,
 371       const struct pipe_poly_stipple *stipple)
 372 {
 373    /* NOP */
 374 }
 375
 376 static void
 377 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 378       unsigned num_scissors, const struct pipe_scissor_state *ss)
 379 {
 380    struct etna_context *ctx = etna_context(pctx);
 381    struct compiled_scissor_state *cs = &ctx->scissor;
 382    assert(ss->minx <= ss->maxx);
 383    assert(ss->miny <= ss->maxy);
 384
 385    /* note that this state is only used when rasterizer_state->scissor is on */
 386    ctx->scissor_s = *ss;
 387    cs->SE_SCISSOR_LEFT = (ss->minx << 16);
 388    cs->SE_SCISSOR_TOP = (ss->miny << 16);
 389    cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 390    cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 391    cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 392    cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 393
 394    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 395 }
 396
 397 static void
 398 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 399       unsigned num_scissors, const struct pipe_viewport_state *vs)
 400 {
 401    struct etna_context *ctx = etna_context(pctx);
 402    struct compiled_viewport_state *cs = &ctx->viewport;
 403
 404    ctx->viewport_s = *vs;
 405    /**
 406     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 407     * -1..1 to 0..1.
 408     * scaling and translation to 0..1 already happened, so remove that
 409     *
 410     * z' = (z * 2 - 1) * scale + translate
 411     *    = z * (2 * scale) + (translate - scale)
 412     *
 413     * scale' = 2 * scale
 414     * translate' = translate - scale
 415     */
 416
 417    /* must be fixp as v4 state deltas assume it is */
 418    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 419    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 420    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 421    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 422    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 423    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 424
 425    /* Compute scissor rectangle (fixp) from viewport.
 426     * Make sure left is always < right and top always < bottom.
 427     */
 428    cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
 429    cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
 430    uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 431    uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 432    cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 433    cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 434    cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
 435    cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
 436
 437    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 438    cs->PE_DEPTH_FAR = fui(1.0);
 439    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 440 }
 441
 442 static void
 443 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 444       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 445 {
 446    struct etna_context *ctx = etna_context(pctx);
 447    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 448
 449    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 450    so->count = util_last_bit(so->enabled_mask);
 451
 452    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 453       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 454       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 455
 456       assert(!vbi->is_user_buffer); /* XXX support user_buffer using
 457                                        etna_usermem_map */
 458
 459       if (vbi->buffer.resource) { /* GPU buffer */
 460          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
 461          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 462          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 463          cs->FE_VERTEX_STREAM_CONTROL =
 464             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 465       } else {
 466          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 467          cs->FE_VERTEX_STREAM_CONTROL = 0;
 468       }
 469    }
 470
 471    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 472 }
 473
 474 static void
 475 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 476 {
 477    struct etna_context *ctx = etna_context(pctx);
 478
 479    ctx->blend = bs;
 480    ctx->dirty |= ETNA_DIRTY_BLEND;
 481 }
 482
 483 static void
 484 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 485 {
 486    FREE(bs);
 487 }
 488
 489 static void
 490 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 491 {
 492    struct etna_context *ctx = etna_context(pctx);
 493
 494    ctx->rasterizer = rs;
 495    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 496 }
 497
 498 static void
 499 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 500 {
 501    FREE(rs);
 502 }
 503
 504 static void
 505 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 506 {
 507    struct etna_context *ctx = etna_context(pctx);
 508
 509    ctx->zsa = zs;
 510    ctx->dirty |= ETNA_DIRTY_ZSA;
 511 }
 512
 513 static void
 514 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 515 {
 516    FREE(zs);
 517 }
 518
 519 /** Create vertex element states, which define a layout for fetching
 520  * vertices for rendering.
 521  */
 522 static void *
 523 etna_vertex_elements_state_create(struct pipe_context *pctx,
 524       unsigned num_elements, const struct pipe_vertex_element *elements)
 525 {
 526    struct etna_context *ctx = etna_context(pctx);
 527    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 528
 529    if (!cs)
 530       return NULL;
 531
 532    if (num_elements > ctx->specs.vertex_max_elements) {
 533       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 534           ctx->specs.vertex_max_elements);
 535       return NULL;
 536    }
 537
 538    /* XXX could minimize number of consecutive stretches here by sorting, and
 539     * permuting the inputs in shader or does Mesa do this already? */
 540
 541    cs->num_elements = num_elements;
 542
 543    unsigned start_offset = 0; /* start of current consecutive stretch */
 544    bool nonconsecutive = true; /* previous value of nonconsecutive */
 545    uint32_t buffer_mask = 0; /* mask of buffer_idx already seen */
 546
 547    for (unsigned idx = 0; idx < num_elements; ++idx) {
 548       unsigned buffer_idx = elements[idx].vertex_buffer_index;
 549       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 550       unsigned end_offset = elements[idx].src_offset + element_size;
 551       uint32_t format_type, normalize;
 552
 553       if (nonconsecutive)
 554          start_offset = elements[idx].src_offset;
 555
 556       /* guaranteed by PIPE_CAP_MAX_VERTEX_BUFFERS */
 557       assert(buffer_idx < ctx->specs.stream_count);
 558
 559       /* maximum vertex size is 256 bytes */
 560       assert(element_size != 0 && (end_offset - start_offset) < 256);
 561
 562       /* check whether next element is consecutive to this one */
 563       nonconsecutive = (idx == (num_elements - 1)) ||
 564                        elements[idx + 1].vertex_buffer_index != buffer_idx ||
 565                        end_offset != elements[idx + 1].src_offset;
 566
 567       format_type = translate_vertex_format_type(elements[idx].src_format);
 568       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 569
 570       assert(format_type != ETNA_NO_MATCH);
 571       assert(normalize != ETNA_NO_MATCH);
 572
 573       if (ctx->specs.halti < 5) {
 574          cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 575             COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 576             format_type |
 577             VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 578             normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 579             VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(buffer_idx) |
 580             VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 581             VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 582       } else { /* HALTI5 spread vertex attrib config over two registers */
 583          cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] =
 584             format_type |
 585             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 586             normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 587             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(buffer_idx) |
 588             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset);
 589          cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] =
 590             COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) |
 591             VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset);
 592       }
 593
 594       if (util_format_is_pure_integer(elements[idx].src_format))
 595          cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 1;
 596       else
 597          cs->NFE_GENERIC_ATTRIB_SCALE[idx] = fui(1.0f);
 598
 599       /* instance_divisor is part of elements state but should be the same for all buffers */
 600       if (buffer_mask & 1 << buffer_idx)
 601          assert(cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] == elements[idx].instance_divisor);
 602       else
 603          cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] = elements[idx].instance_divisor;
 604
 605       buffer_mask |= 1 << buffer_idx;
 606       cs->num_buffers = MAX2(cs->num_buffers, buffer_idx + 1);
 607    }
 608
 609    return cs;
 610 }
 611
 612 static void
 613 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 614 {
 615    FREE(ve);
 616 }
 617
 618 static void
 619 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 620 {
 621    struct etna_context *ctx = etna_context(pctx);
 622
 623    ctx->vertex_elements = ve;
 624    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 625 }
 626
 627 static bool
 628 etna_update_ts_config(struct etna_context *ctx)
 629 {
 630    uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
 631
 632    if (ctx->framebuffer_s.nr_cbufs > 0) {
 633       struct etna_surface *c_surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
 634
 635       if(c_surf->level->ts_size && c_surf->level->ts_valid) {
 636          new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 637       } else {
 638          new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 639       }
 640    }
 641
 642    if (ctx->framebuffer_s.zsbuf) {
 643       struct etna_surface *zs_surf = etna_surface(ctx->framebuffer_s.zsbuf);
 644
 645       if(zs_surf->level->ts_size && zs_surf->level->ts_valid) {
 646          new_ts_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 647       } else {
 648          new_ts_config &= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 649       }
 650    }
 651
 652    if (new_ts_config != ctx->framebuffer.TS_MEM_CONFIG ||
 653        (ctx->dirty & ETNA_DIRTY_FRAMEBUFFER)) {
 654       ctx->framebuffer.TS_MEM_CONFIG = new_ts_config;
 655       ctx->dirty |= ETNA_DIRTY_TS;
 656    }
 657
 658    ctx->dirty &= ~ETNA_DIRTY_DERIVE_TS;
 659
 660    return true;
 661 }
 662
 663 struct etna_state_updater {
 664    bool (*update)(struct etna_context *ctx);
 665    uint32_t dirty;
 666 };
 667
 668 static const struct etna_state_updater etna_state_updates[] = {
 669    {
 670       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 671    },
 672    {
 673       etna_shader_link, ETNA_DIRTY_SHADER,
 674    },
 675    {
 676       etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
 677    },
 678    {
 679       etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER,
 680    },
 681    {
 682       etna_update_ts_config, ETNA_DIRTY_DERIVE_TS,
 683    }
 684 };
 685
 686 bool
 687 etna_state_update(struct etna_context *ctx)
 688 {
 689    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 690       if (ctx->dirty & etna_state_updates[i].dirty)
 691          if (!etna_state_updates[i].update(ctx))
 692             return false;
 693
 694    return true;
 695 }
 696
 697 void
 698 etna_state_init(struct pipe_context *pctx)
 699 {
 700    pctx->set_blend_color = etna_set_blend_color;
 701    pctx->set_stencil_ref = etna_set_stencil_ref;
 702    pctx->set_clip_state = etna_set_clip_state;
 703    pctx->set_sample_mask = etna_set_sample_mask;
 704    pctx->set_constant_buffer = etna_set_constant_buffer;
 705    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 706    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 707    pctx->set_scissor_states = etna_set_scissor_states;
 708    pctx->set_viewport_states = etna_set_viewport_states;
 709
 710    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 711
 712    pctx->bind_blend_state = etna_blend_state_bind;
 713    pctx->delete_blend_state = etna_blend_state_delete;
 714
 715    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 716    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 717
 718    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 719    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 720
 721    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 722    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 723    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 724 }