src/gallium/drivers/etnaviv/etnaviv_transfer.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  */
  26
  27 #include "etnaviv_transfer.h"
  28 #include "etnaviv_clear_blit.h"
  29 #include "etnaviv_context.h"
  30 #include "etnaviv_debug.h"
  31 #include "etnaviv_screen.h"
  32
  33 #include "pipe/p_defines.h"
  34 #include "pipe/p_format.h"
  35 #include "pipe/p_screen.h"
  36 #include "pipe/p_state.h"
  37 #include "util/u_format.h"
  38 #include "util/u_inlines.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_surface.h"
  41 #include "util/u_transfer.h"
  42
  43 #include <drm_fourcc.h>
  44
  45 /* Compute offset into a 1D/2D/3D buffer of a certain box.
  46  * This box must be aligned to the block width and height of the
  47  * underlying format. */
  48 static inline size_t
  49 etna_compute_offset(enum pipe_format format, const struct pipe_box *box,
  50                     size_t stride, size_t layer_stride)
  51 {
  52    return box->z * layer_stride +
  53           box->y / util_format_get_blockheight(format) * stride +
  54           box->x / util_format_get_blockwidth(format) *
  55              util_format_get_blocksize(format);
  56 }
  57
  58 static void
  59 etna_transfer_unmap(struct pipe_context *pctx, struct pipe_transfer *ptrans)
  60 {
  61    struct etna_context *ctx = etna_context(pctx);
  62    struct etna_transfer *trans = etna_transfer(ptrans);
  63    struct etna_resource *rsc = etna_resource(ptrans->resource);
  64
  65    /* XXX
  66     * When writing to a resource that is already in use, replace the resource
  67     * with a completely new buffer
  68     * and free the old one using a fenced free.
  69     * The most tricky case to implement will be: tiled or supertiled surface,
  70     * partial write, target not aligned to 4/64. */
  71    assert(ptrans->level <= rsc->base.last_level);
  72
  73    if (rsc->texture && !etna_resource_newer(rsc, etna_resource(rsc->texture)))
  74       rsc = etna_resource(rsc->texture); /* switch to using the texture resource */
  75
  76    /*
  77     * Temporary resources are always pulled into the CPU domain, must push them
  78     * back into GPU domain before the RS execs the blit to the base resource.
  79     */
  80    if (trans->rsc)
  81       etna_bo_cpu_fini(etna_resource(trans->rsc)->bo);
  82
  83    if (ptrans->usage & PIPE_TRANSFER_WRITE) {
  84       if (trans->rsc) {
  85          /* We have a temporary resource due to either tile status or
  86           * tiling format. Write back the updated buffer contents.
  87           * FIXME: we need to invalidate the tile status. */
  88          etna_copy_resource_box(pctx, ptrans->resource, trans->rsc, ptrans->level, &ptrans->box);
  89       } else if (trans->staging) {
  90          /* map buffer object */
  91          struct etna_resource_level *res_level = &rsc->levels[ptrans->level];
  92          void *mapped = etna_bo_map(rsc->bo) + res_level->offset;
  93
  94          if (rsc->layout == ETNA_LAYOUT_TILED) {
  95             etna_texture_tile(
  96                mapped + ptrans->box.z * res_level->layer_stride,
  97                trans->staging, ptrans->box.x, ptrans->box.y,
  98                res_level->stride, ptrans->box.width, ptrans->box.height,
  99                ptrans->stride, util_format_get_blocksize(rsc->base.format));
 100          } else if (rsc->layout == ETNA_LAYOUT_LINEAR) {
 101             util_copy_box(mapped, rsc->base.format, res_level->stride,
 102                           res_level->layer_stride, ptrans->box.x,
 103                           ptrans->box.y, ptrans->box.z, ptrans->box.width,
 104                           ptrans->box.height, ptrans->box.depth,
 105                           trans->staging, ptrans->stride,
 106                           ptrans->layer_stride, 0, 0, 0 /* src x,y,z */);
 107          } else {
 108             BUG("unsupported tiling %i", rsc->layout);
 109          }
 110
 111          FREE(trans->staging);
 112       }
 113
 114       rsc->seqno++;
 115
 116       if (rsc->base.bind & PIPE_BIND_SAMPLER_VIEW) {
 117          ctx->dirty |= ETNA_DIRTY_TEXTURE_CACHES;
 118       }
 119    }
 120
 121    /*
 122     * Transfers without a temporary are only pulled into the CPU domain if they
 123     * are not mapped unsynchronized. If they are, must push them back into GPU
 124     * domain after CPU access is finished.
 125     */
 126    if (!trans->rsc && !(ptrans->usage & PIPE_TRANSFER_UNSYNCHRONIZED))
 127       etna_bo_cpu_fini(rsc->bo);
 128
 129    pipe_resource_reference(&trans->rsc, NULL);
 130    pipe_resource_reference(&ptrans->resource, NULL);
 131    slab_free(&ctx->transfer_pool, trans);
 132 }
 133
 134 static void *
 135 etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc,
 136                   unsigned level,
 137                   unsigned usage,
 138                   const struct pipe_box *box,
 139                   struct pipe_transfer **out_transfer)
 140 {
 141    struct etna_context *ctx = etna_context(pctx);
 142    struct etna_resource *rsc = etna_resource(prsc);
 143    struct etna_transfer *trans;
 144    struct pipe_transfer *ptrans;
 145    enum pipe_format format = prsc->format;
 146
 147    trans = slab_alloc(&ctx->transfer_pool);
 148    if (!trans)
 149       return NULL;
 150
 151    /* slab_alloc() doesn't zero */
 152    memset(trans, 0, sizeof(*trans));
 153
 154    ptrans = &trans->base;
 155    pipe_resource_reference(&ptrans->resource, prsc);
 156    ptrans->level = level;
 157    ptrans->usage = usage;
 158    ptrans->box = *box;
 159
 160    assert(level <= prsc->last_level);
 161
 162    /* Upgrade DISCARD_RANGE to WHOLE_RESOURCE if the whole resource is
 163     * being mapped. If we add buffer reallocation to avoid CPU/GPU sync this
 164     * check needs to be extended to coherent mappings and shared resources.
 165     */
 166    if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 167        !(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 168        prsc->last_level == 0 &&
 169        prsc->width0 == box->width &&
 170        prsc->height0 == box->height &&
 171        prsc->depth0 == box->depth &&
 172        prsc->array_size == 1) {
 173       usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 174    }
 175
 176    if (rsc->texture && !etna_resource_newer(rsc, etna_resource(rsc->texture))) {
 177       /* We have a texture resource which is the same age or newer than the
 178        * render resource. Use the texture resource, which avoids bouncing
 179        * pixels between the two resources, and we can de-tile it in s/w. */
 180       rsc = etna_resource(rsc->texture);
 181    } else if (rsc->ts_bo ||
 182               (rsc->layout != ETNA_LAYOUT_LINEAR &&
 183                util_format_get_blocksize(format) > 1 &&
 184                /* HALIGN 4 resources are incompatible with the resolve engine,
 185                 * so fall back to using software to detile this resource. */
 186                rsc->halign != TEXTURE_HALIGN_FOUR)) {
 187       /* If the surface has tile status, we need to resolve it first.
 188        * The strategy we implement here is to use the RS to copy the
 189        * depth buffer, filling in the "holes" where the tile status
 190        * indicates that it's clear. We also do this for tiled
 191        * resources, but only if the RS can blit them. */
 192       if (usage & PIPE_TRANSFER_MAP_DIRECTLY) {
 193          slab_free(&ctx->transfer_pool, trans);
 194          BUG("unsupported transfer flags %#x with tile status/tiled layout", usage);
 195          return NULL;
 196       }
 197
 198       if (prsc->depth0 > 1) {
 199          slab_free(&ctx->transfer_pool, trans);
 200          BUG("resource has depth >1 with tile status");
 201          return NULL;
 202       }
 203
 204       struct pipe_resource templ = *prsc;
 205       templ.nr_samples = 0;
 206       templ.bind = PIPE_BIND_RENDER_TARGET;
 207
 208       trans->rsc = etna_resource_alloc(pctx->screen, ETNA_LAYOUT_LINEAR,
 209                                        DRM_FORMAT_MOD_LINEAR, &templ);
 210       if (!trans->rsc) {
 211          slab_free(&ctx->transfer_pool, trans);
 212          return NULL;
 213       }
 214
 215       /* Need to align the transfer region to satisfy RS restrictions, as we
 216        * really want to hit the RS blit path here.
 217        */
 218       unsigned w_align, h_align;
 219
 220       if (rsc->layout & ETNA_LAYOUT_BIT_SUPER) {
 221          w_align = h_align = 64;
 222       } else {
 223          w_align = ETNA_RS_WIDTH_MASK + 1;
 224          h_align = ETNA_RS_HEIGHT_MASK + 1;
 225       }
 226       h_align *= ctx->screen->specs.pixel_pipes;
 227
 228       ptrans->box.width += ptrans->box.x & (w_align - 1);
 229       ptrans->box.x = ptrans->box.x & ~(w_align - 1);
 230       ptrans->box.width = align(ptrans->box.width, (ETNA_RS_WIDTH_MASK + 1));
 231       ptrans->box.height += ptrans->box.y & (h_align - 1);
 232       ptrans->box.y = ptrans->box.y & ~(h_align - 1);
 233       ptrans->box.height = align(ptrans->box.height,
 234                                  (ETNA_RS_HEIGHT_MASK + 1) *
 235                                   ctx->screen->specs.pixel_pipes);
 236
 237       if (!(usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE))
 238          etna_copy_resource_box(pctx, trans->rsc, prsc, level, &ptrans->box);
 239
 240       /* Switch to using the temporary resource instead */
 241       rsc = etna_resource(trans->rsc);
 242    }
 243
 244    struct etna_resource_level *res_level = &rsc->levels[level];
 245
 246    /*
 247     * Always flush if we have the temporary resource and have a copy to this
 248     * outstanding. Otherwise infer flush requirement from resource access and
 249     * current GPU usage (reads must wait for GPU writes, writes must have
 250     * exclusive access to the buffer).
 251     */
 252    if ((trans->rsc && (etna_resource(trans->rsc)->status & ETNA_PENDING_WRITE)) ||
 253        (!trans->rsc &&
 254         (((usage & PIPE_TRANSFER_READ) && (rsc->status & ETNA_PENDING_WRITE)) ||
 255         ((usage & PIPE_TRANSFER_WRITE) && rsc->status))))
 256       pctx->flush(pctx, NULL, 0);
 257
 258    /* XXX we don't handle PIPE_TRANSFER_FLUSH_EXPLICIT; this flag can be ignored
 259     * when mapping in-place,
 260     * but when not in place we need to fire off the copy operation in
 261     * transfer_flush_region (currently
 262     * a no-op) instead of unmap. Need to handle this to support
 263     * ARB_map_buffer_range extension at least.
 264     */
 265    /* XXX we don't take care of current operations on the resource; which can
 266       be, at some point in the pipeline
 267       which is not yet executed:
 268
 269       - bound as surface
 270       - bound through vertex buffer
 271       - bound through index buffer
 272       - bound in sampler view
 273       - used in clear_render_target / clear_depth_stencil operation
 274       - used in blit
 275       - used in resource_copy_region
 276
 277       How do other drivers record this information over course of the rendering
 278       pipeline?
 279       Is it necessary at all? Only in case we want to provide a fast path and
 280       map the resource directly
 281       (and for PIPE_TRANSFER_MAP_DIRECTLY) and we don't want to force a sync.
 282       We also need to know whether the resource is in use to determine if a sync
 283       is needed (or just do it
 284       always, but that comes at the expense of performance).
 285
 286       A conservative approximation without too much overhead would be to mark
 287       all resources that have
 288       been bound at some point as busy. A drawback would be that accessing
 289       resources that have
 290       been bound but are no longer in use for a while still carry a performance
 291       penalty. On the other hand,
 292       the program could be using PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE or
 293       PIPE_TRANSFER_UNSYNCHRONIZED to
 294       avoid this in the first place...
 295
 296       A) We use an in-pipe copy engine, and queue the copy operation after unmap
 297       so that the copy
 298          will be performed when all current commands have been executed.
 299          Using the RS is possible, not sure if always efficient. This can also
 300       do any kind of tiling for us.
 301          Only possible when PIPE_TRANSFER_DISCARD_RANGE is set.
 302       B) We discard the entire resource (or at least, the mipmap level) and
 303       allocate new memory for it.
 304          Only possible when mapping the entire resource or
 305       PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE is set.
 306     */
 307
 308    /*
 309     * Pull resources into the CPU domain. Only skipped for unsynchronized
 310     * transfers without a temporary resource.
 311     */
 312    if (trans->rsc || !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 313       uint32_t prep_flags = 0;
 314
 315       if (usage & PIPE_TRANSFER_READ)
 316          prep_flags |= DRM_ETNA_PREP_READ;
 317       if (usage & PIPE_TRANSFER_WRITE)
 318          prep_flags |= DRM_ETNA_PREP_WRITE;
 319
 320       if (etna_bo_cpu_prep(rsc->bo, prep_flags))
 321          goto fail_prep;
 322    }
 323
 324    /* map buffer object */
 325    void *mapped = etna_bo_map(rsc->bo);
 326    if (!mapped)
 327       goto fail;
 328
 329    *out_transfer = ptrans;
 330
 331    if (rsc->layout == ETNA_LAYOUT_LINEAR) {
 332       ptrans->stride = res_level->stride;
 333       ptrans->layer_stride = res_level->layer_stride;
 334
 335       return mapped + res_level->offset +
 336              etna_compute_offset(prsc->format, box, res_level->stride,
 337                                  res_level->layer_stride);
 338    } else {
 339       unsigned divSizeX = util_format_get_blockwidth(format);
 340       unsigned divSizeY = util_format_get_blockheight(format);
 341
 342       /* No direct mappings of tiled, since we need to manually
 343        * tile/untile.
 344        */
 345       if (usage & PIPE_TRANSFER_MAP_DIRECTLY)
 346          goto fail;
 347
 348       mapped += res_level->offset;
 349       ptrans->stride = align(box->width, divSizeX) * util_format_get_blocksize(format); /* row stride in bytes */
 350       ptrans->layer_stride = align(box->height, divSizeY) * ptrans->stride;
 351       size_t size = ptrans->layer_stride * box->depth;
 352
 353       trans->staging = MALLOC(size);
 354       if (!trans->staging)
 355          goto fail;
 356
 357       if (usage & PIPE_TRANSFER_READ) {
 358          if (rsc->layout == ETNA_LAYOUT_TILED) {
 359             etna_texture_untile(trans->staging,
 360                                 mapped + ptrans->box.z * res_level->layer_stride,
 361                                 ptrans->box.x, ptrans->box.y, res_level->stride,
 362                                 ptrans->box.width, ptrans->box.height, ptrans->stride,
 363                                 util_format_get_blocksize(rsc->base.format));
 364          } else if (rsc->layout == ETNA_LAYOUT_LINEAR) {
 365             util_copy_box(trans->staging, rsc->base.format, ptrans->stride,
 366                           ptrans->layer_stride, 0, 0, 0, /* dst x,y,z */
 367                           ptrans->box.width, ptrans->box.height,
 368                           ptrans->box.depth, mapped, res_level->stride,
 369                           res_level->layer_stride, ptrans->box.x,
 370                           ptrans->box.y, ptrans->box.z);
 371          } else {
 372             /* TODO supertiling */
 373             BUG("unsupported tiling %i for reading", rsc->layout);
 374          }
 375       }
 376
 377       return trans->staging;
 378    }
 379
 380 fail:
 381    etna_bo_cpu_fini(rsc->bo);
 382 fail_prep:
 383    etna_transfer_unmap(pctx, ptrans);
 384    return NULL;
 385 }
 386
 387 static void
 388 etna_transfer_flush_region(struct pipe_context *pctx,
 389                            struct pipe_transfer *transfer,
 390                            const struct pipe_box *box)
 391 {
 392    /* NOOP for now */
 393 }
 394
 395 void
 396 etna_transfer_init(struct pipe_context *pctx)
 397 {
 398    pctx->transfer_map = etna_transfer_map;
 399    pctx->transfer_flush_region = etna_transfer_flush_region;
 400    pctx->transfer_unmap = etna_transfer_unmap;
 401    pctx->buffer_subdata = u_default_buffer_subdata;
 402    pctx->texture_subdata = u_default_texture_subdata;
 403 }