src/gallium/drivers/freedreno/a2xx/fd2_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd2_draw.h"
  38 #include "fd2_context.h"
  39 #include "fd2_emit.h"
  40 #include "fd2_program.h"
  41 #include "fd2_util.h"
  42 #include "fd2_zsa.h"
  43
  44
  45 static void
  46 emit_cacheflush(struct fd_ringbuffer *ring)
  47 {
  48         unsigned i;
  49
  50         for (i = 0; i < 12; i++) {
  51                 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
  52                 OUT_RING(ring, CACHE_FLUSH);
  53         }
  54 }
  55
  56 static void
  57 emit_vertexbufs(struct fd_context *ctx)
  58 {
  59         struct fd_vertex_stateobj *vtx = ctx->vtx.vtx;
  60         struct fd_vertexbuf_stateobj *vertexbuf = &ctx->vtx.vertexbuf;
  61         struct fd2_vertex_buf bufs[PIPE_MAX_ATTRIBS];
  62         unsigned i;
  63
  64         if (!vtx->num_elements)
  65                 return;
  66
  67         for (i = 0; i < vtx->num_elements; i++) {
  68                 struct pipe_vertex_element *elem = &vtx->pipe[i];
  69                 struct pipe_vertex_buffer *vb =
  70                                 &vertexbuf->vb[elem->vertex_buffer_index];
  71                 bufs[i].offset = vb->buffer_offset;
  72                 bufs[i].size = fd_bo_size(fd_resource(vb->buffer)->bo);
  73                 bufs[i].prsc = vb->buffer;
  74         }
  75
  76         // NOTE I believe the 0x78 (or 0x9c in solid_vp) relates to the
  77         // CONST(20,0) (or CONST(26,0) in soliv_vp)
  78
  79         fd2_emit_vertex_bufs(ctx->ring, 0x78, bufs, vtx->num_elements);
  80 }
  81
  82 static void
  83 fd2_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
  84 {
  85         struct fd_ringbuffer *ring = ctx->ring;
  86
  87         if (ctx->dirty & FD_DIRTY_VTXBUF)
  88                 emit_vertexbufs(ctx);
  89
  90         fd2_emit_state(ctx, ctx->dirty);
  91
  92         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  93         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
  94         OUT_RING(ring, info->start);
  95
  96         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  97         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
  98         OUT_RING(ring, 0x0000003b);
  99
 100         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 101         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 102
 103         OUT_WFI (ring);
 104
 105         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 106         OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 107         OUT_RING(ring, info->max_index);        /* VGT_MAX_VTX_INDX */
 108         OUT_RING(ring, info->min_index);        /* VGT_MIN_VTX_INDX */
 109
 110         fd_draw_emit(ctx, ring, IGNORE_VISIBILITY, info);
 111
 112         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 113         OUT_RING(ring, CP_REG(REG_A2XX_UNKNOWN_2010));
 114         OUT_RING(ring, 0x00000000);
 115
 116         emit_cacheflush(ring);
 117 }
 118
 119
 120 static void
 121 fd2_clear(struct fd_context *ctx, unsigned buffers,
 122                 const union pipe_color_union *color, double depth, unsigned stencil)
 123 {
 124         struct fd2_context *fd2_ctx = fd2_context(ctx);
 125         struct fd_ringbuffer *ring = ctx->ring;
 126         struct pipe_framebuffer_state *fb = &ctx->framebuffer;
 127         uint32_t reg, colr = 0;
 128
 129         if ((buffers & PIPE_CLEAR_COLOR) && fb->nr_cbufs)
 130                 colr  = pack_rgba(fb->cbufs[0]->format, color->f);
 131
 132         /* emit generic state now: */
 133         fd2_emit_state(ctx, ctx->dirty &
 134                         (FD_DIRTY_BLEND | FD_DIRTY_VIEWPORT |
 135                                         FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR));
 136
 137         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 138                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48 },
 139                 }, 1);
 140
 141         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 142         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 143         OUT_RING(ring, 0);
 144
 145         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 146         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 147         OUT_RING(ring, 0x0000028f);
 148
 149         fd2_program_emit(ring, &ctx->solid_prog);
 150
 151         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 152         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 153
 154         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 155         OUT_RING(ring, CP_REG(REG_A2XX_CLEAR_COLOR));
 156         OUT_RING(ring, colr);
 157
 158         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 159         OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
 160         OUT_RING(ring, 0x00000084);
 161
 162         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 163         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
 164         reg = 0;
 165         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 166                 reg |= A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE;
 167                 switch (fd_pipe2depth(fb->zsbuf->format)) {
 168                 case DEPTHX_24_8:
 169                         if (buffers & PIPE_CLEAR_DEPTH)
 170                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xe);
 171                         if (buffers & PIPE_CLEAR_STENCIL)
 172                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0x1);
 173                         break;
 174                 case DEPTHX_16:
 175                         if (buffers & PIPE_CLEAR_DEPTH)
 176                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xf);
 177                         break;
 178                 default:
 179                         assert(1);
 180                         break;
 181                 }
 182         }
 183         OUT_RING(ring, reg);
 184
 185         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 186         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTH_CLEAR));
 187         reg = 0;
 188         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 189                 switch (fd_pipe2depth(fb->zsbuf->format)) {
 190                 case DEPTHX_24_8:
 191                         reg = (((uint32_t)(0xffffff * depth)) << 8) |
 192                                 (stencil & 0xff);
 193                         break;
 194                 case DEPTHX_16:
 195                         reg = (uint32_t)(0xffffffff * depth);
 196                         break;
 197                 }
 198         }
 199         OUT_RING(ring, reg);
 200
 201         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 202         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 203         reg = 0;
 204         if (buffers & PIPE_CLEAR_DEPTH) {
 205                 reg |= A2XX_RB_DEPTHCONTROL_ZFUNC(FUNC_ALWAYS) |
 206                                 A2XX_RB_DEPTHCONTROL_Z_ENABLE |
 207                                 A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE |
 208                                 A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE;
 209         }
 210         if (buffers & PIPE_CLEAR_STENCIL) {
 211                 reg |= A2XX_RB_DEPTHCONTROL_STENCILFUNC(FUNC_ALWAYS) |
 212                                 A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE |
 213                                 A2XX_RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE);
 214         }
 215         OUT_RING(ring, reg);
 216
 217         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 218         OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
 219         OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
 220         OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 221
 222         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 223         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
 224         OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(FUNC_ALWAYS) |
 225                         A2XX_RB_COLORCONTROL_BLEND_DISABLE |
 226                         A2XX_RB_COLORCONTROL_ROP_CODE(12) |
 227                         A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
 228                         A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
 229
 230         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 231         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 232         OUT_RING(ring, 0x00000000);        /* PA_CL_CLIP_CNTL */
 233         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
 234                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 235                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 236
 237         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 238         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 239         OUT_RING(ring, 0x0000ffff);
 240
 241         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 242         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 243         OUT_RING(ring, xy2d(0,0));              /* PA_SC_WINDOW_SCISSOR_TL */
 244         OUT_RING(ring, xy2d(fb->width,      /* PA_SC_WINDOW_SCISSOR_BR */
 245                         fb->height));
 246
 247         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 248         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
 249         if (buffers & PIPE_CLEAR_COLOR) {
 250                 OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
 251                                 A2XX_RB_COLOR_MASK_WRITE_GREEN |
 252                                 A2XX_RB_COLOR_MASK_WRITE_BLUE |
 253                                 A2XX_RB_COLOR_MASK_WRITE_ALPHA);
 254         } else {
 255                 OUT_RING(ring, 0x0);
 256         }
 257
 258         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 259         OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 260         OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
 261         OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
 262
 263         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 264                         DI_SRC_SEL_AUTO_INDEX, 3, INDEX_SIZE_IGN, 0, 0, NULL);
 265
 266         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 267         OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
 268         OUT_RING(ring, 0x00000000);
 269
 270         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 271         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
 272         OUT_RING(ring, 0x00000000);
 273 }
 274
 275 void
 276 fd2_draw_init(struct pipe_context *pctx)
 277 {
 278         struct fd_context *ctx = fd_context(pctx);
 279         ctx->draw_vbo = fd2_draw_vbo;
 280         ctx->clear = fd2_clear;
 281 }