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227ba86ed81840eda0f091a6b442825e08b9a033
[mesa.git] / src / gallium / drivers / freedreno / a2xx / fd2_emit.c
1 /*
2 * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31
32 #include "freedreno_resource.h"
33
34 #include "fd2_emit.h"
35 #include "fd2_blend.h"
36 #include "fd2_context.h"
37 #include "fd2_program.h"
38 #include "fd2_rasterizer.h"
39 #include "fd2_texture.h"
40 #include "fd2_util.h"
41 #include "fd2_zsa.h"
42
43 /* NOTE: just define the position for const regs statically.. the blob
44 * driver doesn't seem to change these dynamically, and I can't really
45 * think of a good reason to so..
46 */
47 #define VS_CONST_BASE 0x20
48 #define PS_CONST_BASE 0x120
49
50 static void
51 emit_constants(struct fd_ringbuffer *ring, uint32_t base,
52 struct fd_constbuf_stateobj *constbuf,
53 struct fd2_shader_stateobj *shader)
54 {
55 uint32_t enabled_mask = constbuf->enabled_mask;
56 uint32_t start_base = base;
57 unsigned i;
58
59 /* emit user constants: */
60 while (enabled_mask) {
61 unsigned index = ffs(enabled_mask) - 1;
62 struct pipe_constant_buffer *cb = &constbuf->cb[index];
63 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
64
65 // I expect that size should be a multiple of vec4's:
66 assert(size == align(size, 4));
67
68 /* hmm, sometimes we still seem to end up with consts bound,
69 * even if shader isn't using them, which ends up overwriting
70 * const reg's used for immediates.. this is a hack to work
71 * around that:
72 */
73 if (shader && ((base - start_base) >= (shader->first_immediate * 4)))
74 break;
75
76 const uint32_t *dwords;
77
78 if (cb->user_buffer) {
79 dwords = cb->user_buffer;
80 } else {
81 struct fd_resource *rsc = fd_resource(cb->buffer);
82 dwords = fd_bo_map(rsc->bo);
83 }
84
85 dwords = (uint32_t *)(((uint8_t *)dwords) + cb->buffer_offset);
86
87 OUT_PKT3(ring, CP_SET_CONSTANT, size + 1);
88 OUT_RING(ring, base);
89 for (i = 0; i < size; i++)
90 OUT_RING(ring, *(dwords++));
91
92 base += size;
93 enabled_mask &= ~(1 << index);
94 }
95
96 /* emit shader immediates: */
97 if (shader) {
98 for (i = 0; i < shader->num_immediates; i++) {
99 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
100 OUT_RING(ring, start_base + (4 * (shader->first_immediate + i)));
101 OUT_RING(ring, shader->immediates[i].val[0]);
102 OUT_RING(ring, shader->immediates[i].val[1]);
103 OUT_RING(ring, shader->immediates[i].val[2]);
104 OUT_RING(ring, shader->immediates[i].val[3]);
105 base += 4;
106 }
107 }
108 }
109
110 typedef uint32_t texmask;
111
112 static texmask
113 emit_texture(struct fd_ringbuffer *ring, struct fd_context *ctx,
114 struct fd_texture_stateobj *tex, unsigned samp_id, texmask emitted)
115 {
116 unsigned const_idx = fd2_get_const_idx(ctx, tex, samp_id);
117 static const struct fd2_sampler_stateobj dummy_sampler = {};
118 static const struct fd2_pipe_sampler_view dummy_view = {};
119 const struct fd2_sampler_stateobj *sampler;
120 const struct fd2_pipe_sampler_view *view;
121 struct fd_resource *rsc;
122
123 if (emitted & (1 << const_idx))
124 return 0;
125
126 sampler = tex->samplers[samp_id] ?
127 fd2_sampler_stateobj(tex->samplers[samp_id]) :
128 &dummy_sampler;
129 view = tex->textures[samp_id] ?
130 fd2_pipe_sampler_view(tex->textures[samp_id]) :
131 &dummy_view;
132
133 rsc = view->base.texture ? fd_resource(view->base.texture) : NULL;
134
135 OUT_PKT3(ring, CP_SET_CONSTANT, 7);
136 OUT_RING(ring, 0x00010000 + (0x6 * const_idx));
137
138 OUT_RING(ring, sampler->tex0 | view->tex0);
139 if (rsc)
140 OUT_RELOC(ring, rsc->bo, fd_resource_offset(rsc, 0, 0), view->tex1, 0);
141 else
142 OUT_RING(ring, 0);
143
144 OUT_RING(ring, view->tex2);
145 OUT_RING(ring, sampler->tex3 | view->tex3);
146 OUT_RING(ring, sampler->tex4 | view->tex4);
147
148 if (rsc && rsc->base.last_level)
149 OUT_RELOC(ring, rsc->bo, fd_resource_offset(rsc, 1, 0), view->tex5, 0);
150 else
151 OUT_RING(ring, view->tex5);
152
153 return (1 << const_idx);
154 }
155
156 static void
157 emit_textures(struct fd_ringbuffer *ring, struct fd_context *ctx)
158 {
159 struct fd_texture_stateobj *fragtex = &ctx->tex[PIPE_SHADER_FRAGMENT];
160 struct fd_texture_stateobj *verttex = &ctx->tex[PIPE_SHADER_VERTEX];
161 texmask emitted = 0;
162 unsigned i;
163
164 for (i = 0; i < verttex->num_samplers; i++)
165 if (verttex->samplers[i])
166 emitted |= emit_texture(ring, ctx, verttex, i, emitted);
167
168 for (i = 0; i < fragtex->num_samplers; i++)
169 if (fragtex->samplers[i])
170 emitted |= emit_texture(ring, ctx, fragtex, i, emitted);
171 }
172
173 void
174 fd2_emit_vertex_bufs(struct fd_ringbuffer *ring, uint32_t val,
175 struct fd2_vertex_buf *vbufs, uint32_t n)
176 {
177 unsigned i;
178
179 OUT_PKT3(ring, CP_SET_CONSTANT, 1 + (2 * n));
180 OUT_RING(ring, (0x1 << 16) | (val & 0xffff));
181 for (i = 0; i < n; i++) {
182 struct fd_resource *rsc = fd_resource(vbufs[i].prsc);
183 OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 3, 0);
184 OUT_RING (ring, vbufs[i].size);
185 }
186 }
187
188 void
189 fd2_emit_state_binning(struct fd_context *ctx, const enum fd_dirty_3d_state dirty)
190 {
191 struct fd2_blend_stateobj *blend = fd2_blend_stateobj(ctx->blend);
192 struct fd_ringbuffer *ring = ctx->batch->binning;
193
194 /* subset of fd2_emit_state needed for hw binning on a20x */
195
196 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_VTXSTATE))
197 fd2_program_emit(ctx, ring, &ctx->prog);
198
199 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONST)) {
200 emit_constants(ring, VS_CONST_BASE * 4,
201 &ctx->constbuf[PIPE_SHADER_VERTEX],
202 (dirty & FD_DIRTY_PROG) ? ctx->prog.vs : NULL);
203 }
204
205 if (dirty & FD_DIRTY_VIEWPORT) {
206 OUT_PKT3(ring, CP_SET_CONSTANT, 9);
207 OUT_RING(ring, 0x00000184);
208 OUT_RING(ring, fui(ctx->viewport.translate[0]));
209 OUT_RING(ring, fui(ctx->viewport.translate[1]));
210 OUT_RING(ring, fui(ctx->viewport.translate[2]));
211 OUT_RING(ring, fui(0.0f));
212 OUT_RING(ring, fui(ctx->viewport.scale[0]));
213 OUT_RING(ring, fui(ctx->viewport.scale[1]));
214 OUT_RING(ring, fui(ctx->viewport.scale[2]));
215 OUT_RING(ring, fui(0.0f));
216 }
217
218 /* not sure why this is needed */
219 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
220 enum pipe_format format =
221 pipe_surface_format(ctx->batch->framebuffer.cbufs[0]);
222 bool has_alpha = util_format_has_alpha(format);
223
224 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
225 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
226 OUT_RING(ring, blend->rb_blendcontrol_alpha |
227 COND(has_alpha, blend->rb_blendcontrol_rgb) |
228 COND(!has_alpha, blend->rb_blendcontrol_no_alpha_rgb));
229
230 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
231 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
232 OUT_RING(ring, blend->rb_colormask);
233 }
234
235 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
236 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
237 OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE);
238 }
239
240 void
241 fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty)
242 {
243 struct fd2_blend_stateobj *blend = fd2_blend_stateobj(ctx->blend);
244 struct fd2_zsa_stateobj *zsa = fd2_zsa_stateobj(ctx->zsa);
245 struct fd2_shader_stateobj *fs = ctx->prog.fs;
246 struct fd_ringbuffer *ring = ctx->batch->draw;
247
248 /* NOTE: we probably want to eventually refactor this so each state
249 * object handles emitting it's own state.. although the mapping of
250 * state to registers is not always orthogonal, sometimes a single
251 * register contains bitfields coming from multiple state objects,
252 * so not sure the best way to deal with that yet.
253 */
254
255 if (dirty & FD_DIRTY_SAMPLE_MASK) {
256 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
257 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
258 OUT_RING(ring, ctx->sample_mask);
259 }
260
261 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF | FD_DIRTY_PROG)) {
262 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
263 uint32_t val = zsa->rb_depthcontrol;
264
265 if (fs->has_kill)
266 val &= ~A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE;
267
268 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
269 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
270 OUT_RING(ring, val);
271
272 OUT_PKT3(ring, CP_SET_CONSTANT, 4);
273 OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
274 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
275 A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[1]));
276 OUT_RING(ring, zsa->rb_stencilrefmask |
277 A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
278 OUT_RING(ring, zsa->rb_alpha_ref);
279 }
280
281 if (ctx->rasterizer && dirty & FD_DIRTY_RASTERIZER) {
282 struct fd2_rasterizer_stateobj *rasterizer =
283 fd2_rasterizer_stateobj(ctx->rasterizer);
284 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
285 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
286 OUT_RING(ring, rasterizer->pa_cl_clip_cntl);
287 OUT_RING(ring, rasterizer->pa_su_sc_mode_cntl |
288 A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE);
289
290 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
291 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POINT_SIZE));
292 OUT_RING(ring, rasterizer->pa_su_point_size);
293 OUT_RING(ring, rasterizer->pa_su_point_minmax);
294 OUT_RING(ring, rasterizer->pa_su_line_cntl);
295 OUT_RING(ring, rasterizer->pa_sc_line_stipple);
296
297 OUT_PKT3(ring, CP_SET_CONSTANT, 6);
298 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_VTX_CNTL));
299 OUT_RING(ring, rasterizer->pa_su_vtx_cntl);
300 OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_CLIP_ADJ */
301 OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_DISC_ADJ */
302 OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_CLIP_ADJ */
303 OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */
304
305 if (rasterizer->base.offset_tri) {
306 /* TODO: why multiply scale by 2 ? without it deqp test fails
307 * deqp/piglit tests aren't very precise
308 */
309 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
310 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE));
311 OUT_RING(ring, fui(rasterizer->base.offset_scale * 2.0f)); /* FRONT_SCALE */
312 OUT_RING(ring, fui(rasterizer->base.offset_units)); /* FRONT_OFFSET */
313 OUT_RING(ring, fui(rasterizer->base.offset_scale * 2.0f)); /* BACK_SCALE */
314 OUT_RING(ring, fui(rasterizer->base.offset_units)); /* BACK_OFFSET */
315 }
316 }
317
318 /* NOTE: scissor enabled bit is part of rasterizer state: */
319 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
320 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
321
322 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
323 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
324 OUT_RING(ring, xy2d(scissor->minx, /* PA_SC_WINDOW_SCISSOR_TL */
325 scissor->miny));
326 OUT_RING(ring, xy2d(scissor->maxx, /* PA_SC_WINDOW_SCISSOR_BR */
327 scissor->maxy));
328
329 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
330 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
331 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
332 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
333 }
334
335 if (dirty & FD_DIRTY_VIEWPORT) {
336 OUT_PKT3(ring, CP_SET_CONSTANT, 7);
337 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
338 OUT_RING(ring, fui(ctx->viewport.scale[0])); /* PA_CL_VPORT_XSCALE */
339 OUT_RING(ring, fui(ctx->viewport.translate[0])); /* PA_CL_VPORT_XOFFSET */
340 OUT_RING(ring, fui(ctx->viewport.scale[1])); /* PA_CL_VPORT_YSCALE */
341 OUT_RING(ring, fui(ctx->viewport.translate[1])); /* PA_CL_VPORT_YOFFSET */
342 OUT_RING(ring, fui(ctx->viewport.scale[2])); /* PA_CL_VPORT_ZSCALE */
343 OUT_RING(ring, fui(ctx->viewport.translate[2])); /* PA_CL_VPORT_ZOFFSET */
344
345 /* set viewport in C65/C66, for a20x hw binning and fragcoord.z */
346 OUT_PKT3(ring, CP_SET_CONSTANT, 9);
347 OUT_RING(ring, 0x00000184);
348
349 OUT_RING(ring, fui(ctx->viewport.translate[0]));
350 OUT_RING(ring, fui(ctx->viewport.translate[1]));
351 OUT_RING(ring, fui(ctx->viewport.translate[2]));
352 OUT_RING(ring, fui(0.0f));
353
354 OUT_RING(ring, fui(ctx->viewport.scale[0]));
355 OUT_RING(ring, fui(ctx->viewport.scale[1]));
356 OUT_RING(ring, fui(ctx->viewport.scale[2]));
357 OUT_RING(ring, fui(0.0f));
358 }
359
360 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_VTXSTATE | FD_DIRTY_TEXSTATE))
361 fd2_program_emit(ctx, ring, &ctx->prog);
362
363 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONST)) {
364 emit_constants(ring, VS_CONST_BASE * 4,
365 &ctx->constbuf[PIPE_SHADER_VERTEX],
366 (dirty & FD_DIRTY_PROG) ? ctx->prog.vs : NULL);
367 emit_constants(ring, PS_CONST_BASE * 4,
368 &ctx->constbuf[PIPE_SHADER_FRAGMENT],
369 (dirty & FD_DIRTY_PROG) ? ctx->prog.fs : NULL);
370 }
371
372 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_ZSA)) {
373 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
374 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
375 OUT_RING(ring, zsa->rb_colorcontrol | blend->rb_colorcontrol);
376 }
377
378 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
379 enum pipe_format format =
380 pipe_surface_format(ctx->batch->framebuffer.cbufs[0]);
381 bool has_alpha = util_format_has_alpha(format);
382
383 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
384 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
385 OUT_RING(ring, blend->rb_blendcontrol_alpha |
386 COND(has_alpha, blend->rb_blendcontrol_rgb) |
387 COND(!has_alpha, blend->rb_blendcontrol_no_alpha_rgb));
388
389 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
390 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
391 OUT_RING(ring, blend->rb_colormask);
392 }
393
394 if (dirty & FD_DIRTY_BLEND_COLOR) {
395 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
396 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED));
397 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[0]));
398 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[1]));
399 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[2]));
400 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[3]));
401 }
402
403 if (dirty & (FD_DIRTY_TEX | FD_DIRTY_PROG))
404 emit_textures(ring, ctx);
405 }
406
407 /* emit per-context initialization:
408 */
409 void
410 fd2_emit_restore(struct fd_context *ctx, struct fd_ringbuffer *ring)
411 {
412 if (is_a20x(ctx->screen)) {
413 OUT_PKT0(ring, REG_A2XX_RB_BC_CONTROL, 1);
414 OUT_RING(ring,
415 A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(3) |
416 A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP |
417 A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE |
418 A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(8) |
419 A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(3));
420
421 /* not sure why this is required */
422 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
423 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_VIZ_QUERY));
424 OUT_RING(ring, A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(16));
425
426 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
427 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
428 OUT_RING(ring, 0x00000002);
429
430 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
431 OUT_RING(ring, CP_REG(REG_A2XX_VGT_OUT_DEALLOC_CNTL));
432 OUT_RING(ring, 0x00000002);
433 } else {
434 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
435 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
436 OUT_RING(ring, 0x0000003b);
437 }
438
439 /* enable perfcntrs */
440 OUT_PKT0(ring, REG_A2XX_CP_PERFMON_CNTL, 1);
441 OUT_RING(ring, COND(fd_mesa_debug & FD_DBG_PERFC, 1));
442
443 /* note: perfcntrs don't work without the PM_OVERRIDE bit */
444 OUT_PKT0(ring, REG_A2XX_RBBM_PM_OVERRIDE1, 2);
445 OUT_RING(ring, 0xffffffff);
446 OUT_RING(ring, 0x00000fff);
447
448 OUT_PKT0(ring, REG_A2XX_TP0_CHICKEN, 1);
449 OUT_RING(ring, 0x00000002);
450
451 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
452 OUT_RING(ring, 0x00007fff);
453
454 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
455 OUT_RING(ring, CP_REG(REG_A2XX_SQ_VS_CONST));
456 OUT_RING(ring, A2XX_SQ_VS_CONST_BASE(VS_CONST_BASE) |
457 A2XX_SQ_VS_CONST_SIZE(0x100));
458
459 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
460 OUT_RING(ring, CP_REG(REG_A2XX_SQ_PS_CONST));
461 OUT_RING(ring, A2XX_SQ_PS_CONST_BASE(PS_CONST_BASE) |
462 A2XX_SQ_PS_CONST_SIZE(0xe0));
463
464 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
465 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
466 OUT_RING(ring, 0xffffffff); /* VGT_MAX_VTX_INDX */
467 OUT_RING(ring, 0x00000000); /* VGT_MIN_VTX_INDX */
468
469 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
470 OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
471 OUT_RING(ring, 0x00000000);
472
473 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
474 OUT_RING(ring, CP_REG(REG_A2XX_SQ_CONTEXT_MISC));
475 OUT_RING(ring, A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY));
476
477 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
478 OUT_RING(ring, CP_REG(REG_A2XX_SQ_INTERPOLATOR_CNTL));
479 OUT_RING(ring, 0xffffffff);
480
481 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
482 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_CONFIG));
483 OUT_RING(ring, 0x00000000);
484
485 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
486 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_LINE_CNTL));
487 OUT_RING(ring, 0x00000000);
488
489 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
490 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
491 OUT_RING(ring, 0x00000000);
492
493 // XXX we change this dynamically for draw/clear.. vs gmem<->mem..
494 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
495 OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
496 OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
497
498 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
499 OUT_RING(ring, CP_REG(REG_A2XX_RB_SAMPLE_POS));
500 OUT_RING(ring, 0x88888888);
501
502 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
503 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_DEST_MASK));
504 OUT_RING(ring, 0xffffffff);
505
506 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
507 OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_INFO));
508 OUT_RING(ring, A2XX_RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4) |
509 A2XX_RB_COPY_DEST_INFO_WRITE_RED |
510 A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
511 A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
512 A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
513
514 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
515 OUT_RING(ring, CP_REG(REG_A2XX_SQ_WRAPPING_0));
516 OUT_RING(ring, 0x00000000); /* SQ_WRAPPING_0 */
517 OUT_RING(ring, 0x00000000); /* SQ_WRAPPING_1 */
518
519 OUT_PKT3(ring, CP_SET_DRAW_INIT_FLAGS, 1);
520 OUT_RING(ring, 0x00000000);
521
522 OUT_PKT3(ring, CP_WAIT_REG_EQ, 4);
523 OUT_RING(ring, 0x000005d0);
524 OUT_RING(ring, 0x00000000);
525 OUT_RING(ring, 0x5f601000);
526 OUT_RING(ring, 0x00000001);
527
528 OUT_PKT0(ring, REG_A2XX_SQ_INST_STORE_MANAGMENT, 1);
529 OUT_RING(ring, 0x00000180);
530
531 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
532 OUT_RING(ring, 0x00000300);
533
534 OUT_PKT3(ring, CP_SET_SHADER_BASES, 1);
535 OUT_RING(ring, 0x80000180);
536
537 /* not sure what this form of CP_SET_CONSTANT is.. */
538 OUT_PKT3(ring, CP_SET_CONSTANT, 13);
539 OUT_RING(ring, 0x00000000);
540 OUT_RING(ring, 0x00000000);
541 OUT_RING(ring, 0x00000000);
542 OUT_RING(ring, 0x00000000);
543 OUT_RING(ring, 0x00000000);
544 OUT_RING(ring, 0x469c4000);
545 OUT_RING(ring, 0x3f800000);
546 OUT_RING(ring, 0x3f000000);
547 OUT_RING(ring, 0x00000000);
548 OUT_RING(ring, 0x40000000);
549 OUT_RING(ring, 0x3f400000);
550 OUT_RING(ring, 0x3ec00000);
551 OUT_RING(ring, 0x3e800000);
552
553 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
554 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
555 OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
556 A2XX_RB_COLOR_MASK_WRITE_GREEN |
557 A2XX_RB_COLOR_MASK_WRITE_BLUE |
558 A2XX_RB_COLOR_MASK_WRITE_ALPHA);
559
560 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
561 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED));
562 OUT_RING(ring, 0x00000000); /* RB_BLEND_RED */
563 OUT_RING(ring, 0x00000000); /* RB_BLEND_GREEN */
564 OUT_RING(ring, 0x00000000); /* RB_BLEND_BLUE */
565 OUT_RING(ring, 0x000000ff); /* RB_BLEND_ALPHA */
566
567 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
568 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
569 OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
570 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
571 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
572 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
573 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA |
574 A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA |
575 A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA);
576 }
577
578 void
579 fd2_emit_init_screen(struct pipe_screen *pscreen)
580 {
581 struct fd_screen *screen = fd_screen(pscreen);
582 screen->emit_ib = fd2_emit_ib;
583 }
584
585 void
586 fd2_emit_init(struct pipe_context *pctx)
587 {
588 }