1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_prim.h"
33 #include "util/u_format.h"
35 #include "freedreno_state.h"
36 #include "freedreno_resource.h"
39 #include "fd3_context.h"
41 #include "fd3_program.h"
47 draw_impl(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
48 struct fd3_emit
*emit
)
50 const struct pipe_draw_info
*info
= emit
->info
;
52 fd3_emit_state(ctx
, ring
, emit
);
54 if (emit
->dirty
& (FD_DIRTY_VTXBUF
| FD_DIRTY_VTXSTATE
))
55 fd3_emit_vertex_bufs(ring
, emit
);
57 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
58 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
60 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
61 OUT_RING(ring
, info
->min_index
); /* VFD_INDEX_MIN */
62 OUT_RING(ring
, info
->max_index
); /* VFD_INDEX_MAX */
63 OUT_RING(ring
, info
->start_instance
); /* VFD_INSTANCEID_OFFSET */
64 OUT_RING(ring
, info
->start
); /* VFD_INDEX_OFFSET */
66 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
67 OUT_RING(ring
, info
->primitive_restart
? /* PC_RESTART_INDEX */
68 info
->restart_index
: 0xffffffff);
70 fd_draw_emit(ctx
, ring
,
71 emit
->key
.binning_pass
? IGNORE_VISIBILITY
: USE_VISIBILITY
,
75 /* fixup dirty shader state in case some "unrelated" (from the state-
76 * tracker's perspective) state change causes us to switch to a
80 fixup_shader_state(struct fd_context
*ctx
, struct ir3_shader_key
*key
)
82 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
83 struct ir3_shader_key
*last_key
= &fd3_ctx
->last_key
;
85 if (!ir3_shader_key_equal(last_key
, key
)) {
86 ctx
->dirty
|= FD_DIRTY_PROG
;
88 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
89 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
90 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
91 (last_key
->vsaturate_r
!= key
->vsaturate_r
))
92 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_VP
;
94 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
95 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
96 (last_key
->fsaturate_r
!= key
->fsaturate_r
))
97 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
100 if (last_key
->color_two_side
!= key
->color_two_side
)
101 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
103 if (last_key
->half_precision
!= key
->half_precision
)
104 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
106 if (last_key
->alpha
!= key
->alpha
)
107 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
109 fd3_ctx
->last_key
= *key
;
114 fd3_draw(struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
116 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
117 struct fd3_emit emit
= {
122 /* do binning pass first: */
123 .binning_pass
= true,
124 .color_two_side
= ctx
->rasterizer
? ctx
->rasterizer
->light_twoside
: false,
125 .alpha
= util_format_is_alpha(pipe_surface_format(ctx
->framebuffer
.cbufs
[0])),
126 // TODO set .half_precision based on render target format,
127 // ie. float16 and smaller use half, float32 use full..
128 .half_precision
= !!(fd_mesa_debug
& FD_DBG_FRAGHALF
),
129 .has_per_samp
= fd3_ctx
->fsaturate
|| fd3_ctx
->vsaturate
,
130 .vsaturate_s
= fd3_ctx
->vsaturate_s
,
131 .vsaturate_t
= fd3_ctx
->vsaturate_t
,
132 .vsaturate_r
= fd3_ctx
->vsaturate_r
,
133 .fsaturate_s
= fd3_ctx
->fsaturate_s
,
134 .fsaturate_t
= fd3_ctx
->fsaturate_t
,
135 .fsaturate_r
= fd3_ctx
->fsaturate_r
,
137 .rasterflat
= ctx
->rasterizer
&& ctx
->rasterizer
->flatshade
,
141 fixup_shader_state(ctx
, &emit
.key
);
144 emit
.dirty
= dirty
& ~(FD_DIRTY_BLEND
);
145 draw_impl(ctx
, ctx
->binning_ring
, &emit
);
147 /* and now regular (non-binning) pass: */
148 emit
.key
.binning_pass
= false;
150 emit
.vp
= NULL
; /* we changed key so need to refetch vp */
151 draw_impl(ctx
, ctx
->ring
, &emit
);
154 /* clear operations ignore viewport state, so we need to reset it
155 * based on framebuffer state:
158 reset_viewport(struct fd_ringbuffer
*ring
, struct pipe_framebuffer_state
*pfb
)
160 float half_width
= pfb
->width
* 0.5f
;
161 float half_height
= pfb
->height
* 0.5f
;
163 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 4);
164 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(half_width
- 0.5));
165 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(half_width
));
166 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(half_height
- 0.5));
167 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(-half_height
));
170 /* binning pass cmds for a clear:
171 * NOTE: newer blob drivers don't use binning for clear, which is probably
172 * preferable since it is low vtx count. However that doesn't seem to
173 * actually work for me. Not sure if it is depending on support for
174 * clear pass (rather than using solid-fill shader), or something else
175 * that newer blob is doing differently. Once that is figured out, we
176 * can remove fd3_clear_binning().
179 fd3_clear_binning(struct fd_context
*ctx
, unsigned dirty
)
181 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
182 struct fd_ringbuffer
*ring
= ctx
->binning_ring
;
183 struct fd3_emit emit
= {
184 .vtx
= &fd3_ctx
->solid_vbuf_state
,
185 .prog
= &ctx
->solid_prog
,
187 .binning_pass
= true,
188 .half_precision
= true,
193 fd3_emit_state(ctx
, ring
, &emit
);
194 fd3_emit_vertex_bufs(ring
, &emit
);
195 reset_viewport(ring
, &ctx
->framebuffer
);
197 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
198 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
199 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
200 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
201 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
202 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
203 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
204 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
205 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
206 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
207 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
208 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
210 fd_event_write(ctx
, ring
, PERFCOUNTER_STOP
);
212 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
213 DI_SRC_SEL_AUTO_INDEX
, 2, INDEX_SIZE_IGN
, 0, 0, NULL
);
217 fd3_clear(struct fd_context
*ctx
, unsigned buffers
,
218 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
220 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
221 struct fd_ringbuffer
*ring
= ctx
->ring
;
222 unsigned dirty
= ctx
->dirty
;
224 struct fd3_emit emit
= {
225 .vtx
= &fd3_ctx
->solid_vbuf_state
,
226 .prog
= &ctx
->solid_prog
,
228 .half_precision
= true,
232 dirty
&= FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_SCISSOR
;
233 dirty
|= FD_DIRTY_PROG
;
236 fd3_clear_binning(ctx
, dirty
);
238 /* emit generic state now: */
239 fd3_emit_state(ctx
, ring
, &emit
);
240 reset_viewport(ring
, &ctx
->framebuffer
);
242 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_ALPHA
, 1);
243 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
244 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
246 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
247 OUT_RINGP(ring
, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
),
248 &fd3_ctx
->rbrc_patches
);
250 if (buffers
& PIPE_CLEAR_DEPTH
) {
251 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
252 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE
|
253 A3XX_RB_DEPTH_CONTROL_Z_ENABLE
|
254 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS
));
257 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_ZOFFSET
, 2);
258 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
259 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(depth
));
260 ctx
->dirty
|= FD_DIRTY_VIEWPORT
;
262 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
263 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
266 if (buffers
& PIPE_CLEAR_STENCIL
) {
267 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
268 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_STENCILREF(stencil
) |
269 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil
) |
270 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
271 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
272 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
273 0xff000000 | // XXX ???
274 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
276 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
277 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
278 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS
) |
279 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
280 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE
) |
281 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
282 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
283 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
284 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
285 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
287 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
288 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
289 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
290 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
291 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
292 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
293 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
295 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
296 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
297 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
298 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
299 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
300 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
301 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
302 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
303 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
306 if (buffers
& PIPE_CLEAR_COLOR
) {
312 for (i
= 0; i
< 4; i
++) {
313 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
314 OUT_RING(ring
, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
) |
315 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS
) |
316 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce
));
318 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
319 OUT_RING(ring
, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE
) |
320 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
321 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO
) |
322 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE
) |
323 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
324 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO
) |
325 A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE
);
328 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
329 OUT_RING(ring
, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
331 fd3_emit_vertex_bufs(ring
, &emit
);
333 fd3_emit_constant(ring
, SB_FRAG_SHADER
, 0, 0, 4, color
->ui
, NULL
);
335 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
336 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
337 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
338 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
339 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
340 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
341 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
342 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
343 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
344 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
345 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
346 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
348 fd_event_write(ctx
, ring
, PERFCOUNTER_STOP
);
350 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, USE_VISIBILITY
,
351 DI_SRC_SEL_AUTO_INDEX
, 2, INDEX_SIZE_IGN
, 0, 0, NULL
);
355 fd3_draw_init(struct pipe_context
*pctx
)
357 struct fd_context
*ctx
= fd_context(pctx
);
358 ctx
->draw
= fd3_draw
;
359 ctx
->clear
= fd3_clear
;