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a3xx: make sure to actually clamp depth as requested
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34 #include "util/u_viewport.h"
35
36 #include "freedreno_resource.h"
37 #include "freedreno_query_hw.h"
38
39 #include "fd3_emit.h"
40 #include "fd3_blend.h"
41 #include "fd3_context.h"
42 #include "fd3_program.h"
43 #include "fd3_rasterizer.h"
44 #include "fd3_texture.h"
45 #include "fd3_format.h"
46 #include "fd3_zsa.h"
47
48 static const enum adreno_state_block sb[] = {
49 [SHADER_VERTEX] = SB_VERT_SHADER,
50 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
51 };
52
53 /* regid: base const register
54 * prsc or dwords: buffer containing constant values
55 * sizedwords: size of const value buffer
56 */
57 void
58 fd3_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
59 uint32_t regid, uint32_t offset, uint32_t sizedwords,
60 const uint32_t *dwords, struct pipe_resource *prsc)
61 {
62 uint32_t i, sz;
63 enum adreno_state_src src;
64
65 debug_assert((regid % 4) == 0);
66 debug_assert((sizedwords % 4) == 0);
67
68 if (prsc) {
69 sz = 0;
70 src = SS_INDIRECT;
71 } else {
72 sz = sizedwords;
73 src = SS_DIRECT;
74 }
75
76 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
77 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
78 CP_LOAD_STATE_0_STATE_SRC(src) |
79 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
80 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
81 if (prsc) {
82 struct fd_bo *bo = fd_resource(prsc)->bo;
83 OUT_RELOC(ring, bo, offset,
84 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
85 } else {
86 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
87 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
88 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
89 }
90 for (i = 0; i < sz; i++) {
91 OUT_RING(ring, dwords[i]);
92 }
93 }
94
95 static void
96 fd3_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
97 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
98 {
99 uint32_t i;
100
101 debug_assert((regid % 4) == 0);
102 debug_assert((num % 4) == 0);
103
104 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
105 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
106 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
107 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
108 CP_LOAD_STATE_0_NUM_UNIT(num/2));
109 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
110 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
111
112 for (i = 0; i < num; i++) {
113 if (prscs[i]) {
114 if (write) {
115 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
116 } else {
117 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
118 }
119 } else {
120 OUT_RING(ring, 0xbad00000 | (i << 16));
121 }
122 }
123 }
124
125 #define VERT_TEX_OFF 0
126 #define FRAG_TEX_OFF 16
127 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
128
129 static void
130 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
131 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
132 {
133 static const unsigned tex_off[] = {
134 [SB_VERT_TEX] = VERT_TEX_OFF,
135 [SB_FRAG_TEX] = FRAG_TEX_OFF,
136 };
137 static const enum adreno_state_block mipaddr[] = {
138 [SB_VERT_TEX] = SB_VERT_MIPADDR,
139 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
140 };
141 static const uint32_t bcolor_reg[] = {
142 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
143 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
144 };
145 struct fd3_context *fd3_ctx = fd3_context(ctx);
146 bool needs_border = false;
147 unsigned i, j;
148
149 if (tex->num_samplers > 0) {
150 /* output sampler state: */
151 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
152 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
153 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
154 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
155 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
156 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
157 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
158 for (i = 0; i < tex->num_samplers; i++) {
159 static const struct fd3_sampler_stateobj dummy_sampler = {};
160 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
161 fd3_sampler_stateobj(tex->samplers[i]) :
162 &dummy_sampler;
163
164 OUT_RING(ring, sampler->texsamp0);
165 OUT_RING(ring, sampler->texsamp1);
166
167 needs_border |= sampler->needs_border;
168 }
169 }
170
171 if (tex->num_textures > 0) {
172 /* emit texture state: */
173 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
174 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
175 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
176 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
177 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
178 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
179 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
180 for (i = 0; i < tex->num_textures; i++) {
181 static const struct fd3_pipe_sampler_view dummy_view = {};
182 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
183 fd3_pipe_sampler_view(tex->textures[i]) :
184 &dummy_view;
185 OUT_RING(ring, view->texconst0);
186 OUT_RING(ring, view->texconst1);
187 OUT_RING(ring, view->texconst2 |
188 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
189 OUT_RING(ring, view->texconst3);
190 }
191
192 /* emit mipaddrs: */
193 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
194 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
195 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
196 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
197 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
198 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
199 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
200 for (i = 0; i < tex->num_textures; i++) {
201 static const struct fd3_pipe_sampler_view dummy_view = {
202 .base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
203 .base.u.tex.first_level = 1,
204 };
205 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
206 fd3_pipe_sampler_view(tex->textures[i]) :
207 &dummy_view;
208 struct fd_resource *rsc = fd_resource(view->base.texture);
209 if (rsc && rsc->base.b.target == PIPE_BUFFER) {
210 OUT_RELOC(ring, rsc->bo, view->base.u.buf.offset, 0, 0);
211 j = 1;
212 } else {
213 unsigned start = fd_sampler_first_level(&view->base);
214 unsigned end = fd_sampler_last_level(&view->base);
215
216 for (j = 0; j < (end - start + 1); j++) {
217 struct fd_resource_slice *slice =
218 fd_resource_slice(rsc, j + start);
219 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
220 }
221 }
222
223 /* pad the remaining entries w/ null: */
224 for (; j < BASETABLE_SZ; j++) {
225 OUT_RING(ring, 0x00000000);
226 }
227 }
228 }
229
230 if (needs_border) {
231 unsigned off;
232 void *ptr;
233
234 u_upload_alloc(fd3_ctx->border_color_uploader,
235 0, BORDER_COLOR_UPLOAD_SIZE,
236 BORDER_COLOR_UPLOAD_SIZE, &off,
237 &fd3_ctx->border_color_buf,
238 &ptr);
239
240 fd_setup_border_colors(tex, ptr, tex_off[sb]);
241
242 OUT_PKT0(ring, bcolor_reg[sb], 1);
243 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
244
245 u_upload_unmap(fd3_ctx->border_color_uploader);
246 }
247 }
248
249 /* emit texture state for mem->gmem restore operation.. eventually it would
250 * be good to get rid of this and use normal CSO/etc state for more of these
251 * special cases, but for now the compiler is not sufficient..
252 *
253 * Also, for using normal state, not quite sure how to handle the special
254 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
255 */
256 void
257 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
258 struct pipe_surface **psurf,
259 int bufs)
260 {
261 int i, j;
262
263 /* output sampler state: */
264 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
265 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
266 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
267 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
268 CP_LOAD_STATE_0_NUM_UNIT(bufs));
269 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
270 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
271 for (i = 0; i < bufs; i++) {
272 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
273 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
274 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
275 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
276 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
277 OUT_RING(ring, 0x00000000);
278 }
279
280 /* emit texture state: */
281 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
282 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
283 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
284 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
285 CP_LOAD_STATE_0_NUM_UNIT(bufs));
286 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
287 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
288 for (i = 0; i < bufs; i++) {
289 if (!psurf[i]) {
290 OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
291 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
292 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
293 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
294 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
295 OUT_RING(ring, 0x00000000);
296 OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
297 OUT_RING(ring, 0x00000000);
298 continue;
299 }
300
301 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
302 enum pipe_format format = fd3_gmem_restore_format(psurf[i]->format);
303 /* The restore blit_zs shader expects stencil in sampler 0, and depth
304 * in sampler 1
305 */
306 if (rsc->stencil && i == 0) {
307 rsc = rsc->stencil;
308 format = fd3_gmem_restore_format(rsc->base.b.format);
309 }
310
311 /* note: PIPE_BUFFER disallowed for surfaces */
312 unsigned lvl = psurf[i]->u.tex.level;
313 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
314
315 debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
316
317 OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
318 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
319 fd3_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
320 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
321 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
322 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
323 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
324 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
325 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
326 OUT_RING(ring, 0x00000000);
327 }
328
329 /* emit mipaddrs: */
330 OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
331 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
332 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
333 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
334 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
335 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
336 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
337 for (i = 0; i < bufs; i++) {
338 if (psurf[i]) {
339 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
340 /* Matches above logic for blit_zs shader */
341 if (rsc->stencil && i == 0)
342 rsc = rsc->stencil;
343 unsigned lvl = psurf[i]->u.tex.level;
344 uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
345 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
346 } else {
347 OUT_RING(ring, 0x00000000);
348 }
349
350 /* pad the remaining entries w/ null: */
351 for (j = 1; j < BASETABLE_SZ; j++) {
352 OUT_RING(ring, 0x00000000);
353 }
354 }
355 }
356
357 void
358 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
359 {
360 int32_t i, j, last = -1;
361 uint32_t total_in = 0;
362 const struct fd_vertex_state *vtx = emit->vtx;
363 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
364 unsigned vertex_regid = regid(63, 0);
365 unsigned instance_regid = regid(63, 0);
366 unsigned vtxcnt_regid = regid(63, 0);
367
368 /* Note that sysvals come *after* normal inputs: */
369 for (i = 0; i < vp->inputs_count; i++) {
370 if (!vp->inputs[i].compmask)
371 continue;
372 if (vp->inputs[i].sysval) {
373 switch(vp->inputs[i].slot) {
374 case SYSTEM_VALUE_BASE_VERTEX:
375 /* handled elsewhere */
376 break;
377 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
378 vertex_regid = vp->inputs[i].regid;
379 break;
380 case SYSTEM_VALUE_INSTANCE_ID:
381 instance_regid = vp->inputs[i].regid;
382 break;
383 case SYSTEM_VALUE_VERTEX_CNT:
384 vtxcnt_regid = vp->inputs[i].regid;
385 break;
386 default:
387 unreachable("invalid system value");
388 break;
389 }
390 } else if (i < vtx->vtx->num_elements) {
391 last = i;
392 }
393 }
394
395 for (i = 0, j = 0; i <= last; i++) {
396 assert(!vp->inputs[i].sysval);
397 if (vp->inputs[i].compmask) {
398 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
399 const struct pipe_vertex_buffer *vb =
400 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
401 struct fd_resource *rsc = fd_resource(vb->buffer);
402 enum pipe_format pfmt = elem->src_format;
403 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
404 bool switchnext = (i != last) ||
405 (vertex_regid != regid(63, 0)) ||
406 (instance_regid != regid(63, 0)) ||
407 (vtxcnt_regid != regid(63, 0));
408 bool isint = util_format_is_pure_integer(pfmt);
409 uint32_t fs = util_format_get_blocksize(pfmt);
410
411 debug_assert(fmt != ~0);
412
413 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
414 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
415 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
416 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
417 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
418 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
419 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
420 OUT_RELOC(ring, rsc->bo, vb->buffer_offset + elem->src_offset, 0, 0);
421
422 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
423 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
424 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
425 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
426 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
427 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
428 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
429 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
430 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
431 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
432
433 total_in += vp->inputs[i].ncomp;
434 j++;
435 }
436 }
437
438 /* hw doesn't like to be configured for zero vbo's, it seems: */
439 if (last < 0) {
440 /* just recycle the shader bo, we just need to point to *something*
441 * valid:
442 */
443 struct fd_bo *dummy_vbo = vp->bo;
444 bool switchnext = (vertex_regid != regid(63, 0)) ||
445 (instance_regid != regid(63, 0)) ||
446 (vtxcnt_regid != regid(63, 0));
447
448 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(0), 2);
449 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
450 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
451 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
452 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
453 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
454 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
455
456 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(0), 1);
457 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
458 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
459 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM) |
460 A3XX_VFD_DECODE_INSTR_SWAP(XYZW) |
461 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
462 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
463 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
464 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
465
466 total_in = 1;
467 j = 1;
468 }
469
470 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
471 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
472 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
473 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
474 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
475 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
476 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
477 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
478
479 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
480 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
481 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
482 }
483
484 void
485 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
486 struct fd3_emit *emit)
487 {
488 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
489 const struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
490 uint32_t dirty = emit->dirty;
491
492 emit_marker(ring, 5);
493
494 if (dirty & FD_DIRTY_SAMPLE_MASK) {
495 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
496 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
497 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
498 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
499 }
500
501 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG | FD_DIRTY_BLEND_DUAL)) &&
502 !emit->key.binning_pass) {
503 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control |
504 fd3_blend_stateobj(ctx->blend)->rb_render_control;
505
506 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
507 val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD |
508 A3XX_RB_RENDER_CONTROL_YCOORD |
509 A3XX_RB_RENDER_CONTROL_ZCOORD |
510 A3XX_RB_RENDER_CONTROL_WCOORD);
511
512 /* I suppose if we needed to (which I don't *think* we need
513 * to), we could emit this for binning pass too. But we
514 * would need to keep a different patch-list for binning
515 * vs render pass.
516 */
517
518 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
519 OUT_RINGP(ring, val, &ctx->batch->rbrc_patches);
520 }
521
522 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
523 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
524 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
525
526 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
527 OUT_RING(ring, zsa->rb_alpha_ref);
528
529 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
530 OUT_RING(ring, zsa->rb_stencil_control);
531
532 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
533 OUT_RING(ring, zsa->rb_stencilrefmask |
534 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
535 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
536 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
537 }
538
539 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
540 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
541 if (fp->writes_pos) {
542 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
543 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
544 }
545 if (fp->has_kill) {
546 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
547 }
548 if (!ctx->rasterizer->depth_clip) {
549 val |= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE;
550 }
551 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
552 OUT_RING(ring, val);
553 }
554
555 if (dirty & FD_DIRTY_RASTERIZER) {
556 struct fd3_rasterizer_stateobj *rasterizer =
557 fd3_rasterizer_stateobj(ctx->rasterizer);
558
559 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
560 OUT_RING(ring, rasterizer->gras_su_mode_control);
561
562 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
563 OUT_RING(ring, rasterizer->gras_su_point_minmax);
564 OUT_RING(ring, rasterizer->gras_su_point_size);
565
566 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
567 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
568 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
569 }
570
571 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
572 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
573 ->gras_cl_clip_cntl;
574 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
575 val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
576 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
577 /* TODO only use if prog doesn't use clipvertex/clipdist */
578 val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
579 MIN2(util_bitcount(ctx->rasterizer->clip_plane_enable), 6));
580 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
581 OUT_RING(ring, val);
582 }
583
584 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_UCP)) {
585 uint32_t planes = ctx->rasterizer->clip_plane_enable;
586 int count = 0;
587
588 while (planes && count < 6) {
589 int i = ffs(planes) - 1;
590
591 planes &= ~(1U << i);
592 fd_wfi(ctx->batch, ring);
593 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
594 OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
595 OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
596 OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
597 OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
598 }
599 }
600
601 /* NOTE: since primitive_restart is not actually part of any
602 * state object, we need to make sure that we always emit
603 * PRIM_VTX_CNTL.. either that or be more clever and detect
604 * when it changes.
605 */
606 if (emit->info) {
607 const struct pipe_draw_info *info = emit->info;
608 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
609 ->pc_prim_vtx_cntl;
610
611 if (!emit->key.binning_pass) {
612 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
613 if (stride_in_vpc > 0)
614 stride_in_vpc = MAX2(stride_in_vpc, 2);
615 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
616 }
617
618 if (info->indexed && info->primitive_restart) {
619 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
620 }
621
622 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
623
624 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
625 OUT_RING(ring, val);
626 }
627
628 if (dirty & FD_DIRTY_SCISSOR) {
629 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
630
631 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
632 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
633 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
634 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
635 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
636
637 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
638 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
639 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
640 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
641 }
642
643 if (dirty & FD_DIRTY_VIEWPORT) {
644 fd_wfi(ctx->batch, ring);
645 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
646 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
647 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
648 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
649 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
650 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
651 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
652 }
653
654 if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
655 float zmin, zmax;
656 int depth = 24;
657 if (ctx->batch->framebuffer.zsbuf) {
658 depth = util_format_get_component_bits(
659 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
660 UTIL_FORMAT_COLORSPACE_ZS, 0);
661 }
662 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
663 &zmin, &zmax);
664
665 OUT_PKT0(ring, REG_A3XX_RB_Z_CLAMP_MIN, 2);
666 if (depth == 32) {
667 OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));
668 OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));
669 } else if (depth == 16) {
670 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
671 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
672 } else {
673 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
674 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
675 }
676 }
677
678 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
679 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
680 int nr_cbufs = pfb->nr_cbufs;
681 if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
682 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
683 nr_cbufs++;
684 fd3_program_emit(ring, emit, nr_cbufs, pfb->cbufs);
685 }
686
687 /* TODO we should not need this or fd_wfi() before emit_constants():
688 */
689 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
690 OUT_RING(ring, HLSQ_FLUSH);
691
692 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
693 ir3_emit_consts(vp, ring, ctx, emit->info, dirty);
694 if (!emit->key.binning_pass)
695 ir3_emit_consts(fp, ring, ctx, emit->info, dirty);
696 }
697
698 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
699 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
700 uint32_t i;
701
702 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
703 enum pipe_format format =
704 pipe_surface_format(ctx->batch->framebuffer.cbufs[i]);
705 const struct util_format_description *desc =
706 util_format_description(format);
707 bool is_float = util_format_is_float(format);
708 bool is_int = util_format_is_pure_integer(format);
709 bool has_alpha = util_format_has_alpha(format);
710 uint32_t control = blend->rb_mrt[i].control;
711 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
712
713 if (is_int) {
714 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
715 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
716 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
717 }
718
719 if (format == PIPE_FORMAT_NONE)
720 control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
721
722 if (has_alpha) {
723 blend_control |= blend->rb_mrt[i].blend_control_rgb;
724 } else {
725 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
726 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
727 }
728
729 if (format && util_format_get_component_bits(
730 format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
731 const struct pipe_rt_blend_state *rt;
732 if (ctx->blend->independent_blend_enable)
733 rt = &ctx->blend->rt[i];
734 else
735 rt = &ctx->blend->rt[0];
736
737 if (!util_format_colormask_full(desc, rt->colormask))
738 control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
739 }
740
741 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
742 OUT_RING(ring, control);
743
744 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
745 OUT_RING(ring, blend_control |
746 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
747 }
748 }
749
750 if (dirty & FD_DIRTY_BLEND_COLOR) {
751 struct pipe_blend_color *bcolor = &ctx->blend_color;
752 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
753 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
754 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
755 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
756 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
757 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
758 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
759 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
760 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
761 }
762
763 if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
764 fd_wfi(ctx->batch, ring);
765
766 if (dirty & FD_DIRTY_VERTTEX) {
767 if (vp->has_samp)
768 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
769 else
770 dirty &= ~FD_DIRTY_VERTTEX;
771 }
772
773 if (dirty & FD_DIRTY_FRAGTEX) {
774 if (fp->has_samp)
775 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
776 else
777 dirty &= ~FD_DIRTY_FRAGTEX;
778 }
779
780 ctx->dirty &= ~dirty;
781 }
782
783 /* emit setup at begin of new cmdstream buffer (don't rely on previous
784 * state, there could have been a context switch between ioctls):
785 */
786 void
787 fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
788 {
789 struct fd_context *ctx = batch->ctx;
790 struct fd3_context *fd3_ctx = fd3_context(ctx);
791 int i;
792
793 if (ctx->screen->gpu_id == 320) {
794 OUT_PKT3(ring, CP_REG_RMW, 3);
795 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
796 OUT_RING(ring, 0xfffcffff);
797 OUT_RING(ring, 0x00000000);
798 }
799
800 fd_wfi(batch, ring);
801 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
802 OUT_RING(ring, 0x00007fff);
803
804 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
805 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
806 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
807 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
808
809 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
810 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
811 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
812 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
813
814 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
815 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
816
817 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
818 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
819 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
820 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
821
822 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
823 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
824 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
825 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
826 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
827
828 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
829 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
830 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
831
832 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
833 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
834
835 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
836 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
837 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
838 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
839
840 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
841 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
842 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
843 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
844
845 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
846 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
847 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
848
849 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
850 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
851
852 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
853 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
854
855 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
856 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
857
858 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
859 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
860
861 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
862 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
863
864 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
865 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
866 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
867 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
868 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
869
870 fd3_emit_cache_flush(batch, ring);
871
872 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
873 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
874
875 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
876 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
877 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
878
879 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
880 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
881
882 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
883 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
884 A3XX_RB_WINDOW_OFFSET_Y(0));
885
886 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
887 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
888 A3XX_RB_BLEND_RED_FLOAT(0.0));
889 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
890 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
891 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
892 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
893 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
894 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
895
896 for (i = 0; i < 6; i++) {
897 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
898 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
899 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
900 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
901 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
902 }
903
904 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
905 OUT_RING(ring, 0x00000000);
906
907 fd_event_write(batch, ring, CACHE_FLUSH);
908
909 if (is_a3xx_p0(ctx->screen)) {
910 OUT_PKT3(ring, CP_DRAW_INDX, 3);
911 OUT_RING(ring, 0x00000000);
912 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
913 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
914 OUT_RING(ring, 0); /* NumIndices */
915 }
916
917 OUT_PKT3(ring, CP_NOP, 4);
918 OUT_RING(ring, 0x00000000);
919 OUT_RING(ring, 0x00000000);
920 OUT_RING(ring, 0x00000000);
921 OUT_RING(ring, 0x00000000);
922
923 fd_wfi(batch, ring);
924
925 fd_hw_query_enable(batch, ring);
926 }
927
928 static void
929 fd3_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
930 {
931 __OUT_IB(ring, true, target);
932 }
933
934 void
935 fd3_emit_init(struct pipe_context *pctx)
936 {
937 struct fd_context *ctx = fd_context(pctx);
938 ctx->emit_const = fd3_emit_const;
939 ctx->emit_const_bo = fd3_emit_const_bo;
940 ctx->emit_ib = fd3_emit_ib;
941 }