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freedreno/a3xx,a4xx: silence some warnings
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd3_emit.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
49 */
50 void
51 fd3_emit_constant(struct fd_ringbuffer *ring,
52 enum adreno_state_block sb,
53 uint32_t regid, uint32_t offset, uint32_t sizedwords,
54 const uint32_t *dwords, struct pipe_resource *prsc)
55 {
56 uint32_t i, sz;
57 enum adreno_state_src src;
58
59 if (prsc) {
60 sz = 0;
61 src = SS_INDIRECT;
62 } else {
63 sz = sizedwords;
64 src = SS_DIRECT;
65 }
66
67 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
68 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
69 CP_LOAD_STATE_0_STATE_SRC(src) |
70 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
71 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
72 if (prsc) {
73 struct fd_bo *bo = fd_resource(prsc)->bo;
74 OUT_RELOC(ring, bo, offset,
75 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
76 } else {
77 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
78 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
79 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
80 }
81 for (i = 0; i < sz; i++) {
82 OUT_RING(ring, dwords[i]);
83 }
84 }
85
86 static void
87 emit_constants(struct fd_ringbuffer *ring,
88 enum adreno_state_block sb,
89 struct fd_constbuf_stateobj *constbuf,
90 struct ir3_shader_variant *shader)
91 {
92 uint32_t enabled_mask = constbuf->enabled_mask;
93 uint32_t first_immediate;
94 uint32_t base = 0;
95
96 // XXX TODO only emit dirty consts.. but we need to keep track if
97 // they are clobbered by a clear, gmem2mem, or mem2gmem..
98 constbuf->dirty_mask = enabled_mask;
99
100 /* in particular, with binning shader we may end up with unused
101 * consts, ie. we could end up w/ constlen that is smaller
102 * than first_immediate. In that case truncate the user consts
103 * early to avoid HLSQ lockup caused by writing too many consts
104 */
105 first_immediate = MIN2(shader->first_immediate, shader->constlen);
106
107 /* emit user constants: */
108 while (enabled_mask) {
109 unsigned index = ffs(enabled_mask) - 1;
110 struct pipe_constant_buffer *cb = &constbuf->cb[index];
111 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
112
113 // I expect that size should be a multiple of vec4's:
114 assert(size == align(size, 4));
115
116 /* gallium could leave const buffers bound above what the
117 * current shader uses.. don't let that confuse us.
118 */
119 if (base >= (4 * first_immediate))
120 break;
121
122 if (constbuf->dirty_mask & (1 << index)) {
123 /* and even if the start of the const buffer is before
124 * first_immediate, the end may not be:
125 */
126 size = MIN2(size, (4 * first_immediate) - base);
127 fd3_emit_constant(ring, sb, base,
128 cb->buffer_offset, size,
129 cb->user_buffer, cb->buffer);
130 constbuf->dirty_mask &= ~(1 << index);
131 }
132
133 base += size;
134 enabled_mask &= ~(1 << index);
135 }
136
137 /* emit shader immediates: */
138 if (shader) {
139 int size = shader->immediates_count;
140 base = shader->first_immediate;
141
142 /* truncate size to avoid writing constants that shader
143 * does not use:
144 */
145 size = MIN2(size + base, shader->constlen) - base;
146
147 /* convert out of vec4: */
148 base *= 4;
149 size *= 4;
150
151 if (size > 0) {
152 fd3_emit_constant(ring, sb, base,
153 0, size, shader->immediates[0].val, NULL);
154 }
155 }
156 }
157
158 #define VERT_TEX_OFF 0
159 #define FRAG_TEX_OFF 16
160 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
161
162 static void
163 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
164 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
165 {
166 static const unsigned tex_off[] = {
167 [SB_VERT_TEX] = VERT_TEX_OFF,
168 [SB_FRAG_TEX] = FRAG_TEX_OFF,
169 };
170 static const enum adreno_state_block mipaddr[] = {
171 [SB_VERT_TEX] = SB_VERT_MIPADDR,
172 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
173 };
174 static const uint32_t bcolor_reg[] = {
175 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
176 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
177 };
178 struct fd3_context *fd3_ctx = fd3_context(ctx);
179 unsigned i, j, off;
180 void *ptr;
181
182 u_upload_alloc(fd3_ctx->border_color_uploader,
183 0, 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, &off,
184 &fd3_ctx->border_color_buf,
185 &ptr);
186
187 if (tex->num_samplers > 0) {
188 /* output sampler state: */
189 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
190 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
191 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
192 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
193 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
194 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
195 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
196 for (i = 0; i < tex->num_samplers; i++) {
197 static const struct fd3_sampler_stateobj dummy_sampler = {};
198 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
199 fd3_sampler_stateobj(tex->samplers[i]) :
200 &dummy_sampler;
201 uint16_t *bcolor = (uint16_t *)((uint8_t *)ptr +
202 (BORDERCOLOR_SIZE * tex_off[sb]) +
203 (BORDERCOLOR_SIZE * i));
204
205 /*
206 * XXX HACK ALERT XXX
207 *
208 * The border colors need to be swizzled in a particular
209 * format-dependent order. Even though samplers don't know about
210 * formats, we can assume that with a GL state tracker, there's a
211 * 1:1 correspondence between sampler and texture. Take advantage
212 * of that knowledge.
213 */
214 if (i < tex->num_textures && tex->textures[i]) {
215 const struct util_format_description *desc =
216 util_format_description(tex->textures[i]->format);
217 for (j = 0; j < 4; j++) {
218 if (desc->swizzle[j] < 4)
219 bcolor[desc->swizzle[j]] =
220 util_float_to_half(sampler->base.border_color.f[j]);
221 }
222 }
223
224 OUT_RING(ring, sampler->texsamp0);
225 OUT_RING(ring, sampler->texsamp1);
226 }
227 }
228
229 if (tex->num_textures > 0) {
230 /* emit texture state: */
231 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
232 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
233 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
234 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
235 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
236 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
237 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
238 for (i = 0; i < tex->num_textures; i++) {
239 static const struct fd3_pipe_sampler_view dummy_view = {};
240 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
241 fd3_pipe_sampler_view(tex->textures[i]) :
242 &dummy_view;
243 OUT_RING(ring, view->texconst0);
244 OUT_RING(ring, view->texconst1);
245 OUT_RING(ring, view->texconst2 |
246 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
247 OUT_RING(ring, view->texconst3);
248 }
249
250 /* emit mipaddrs: */
251 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
252 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
253 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
254 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
255 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
256 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
257 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
258 for (i = 0; i < tex->num_textures; i++) {
259 static const struct fd3_pipe_sampler_view dummy_view = {
260 .base.u.tex.first_level = 1,
261 };
262 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
263 fd3_pipe_sampler_view(tex->textures[i]) :
264 &dummy_view;
265 struct fd_resource *rsc = view->tex_resource;
266 unsigned start = view->base.u.tex.first_level;
267 unsigned end = view->base.u.tex.last_level;
268
269 for (j = 0; j < (end - start + 1); j++) {
270 struct fd_resource_slice *slice =
271 fd_resource_slice(rsc, j + start);
272 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
273 }
274
275 /* pad the remaining entries w/ null: */
276 for (; j < BASETABLE_SZ; j++) {
277 OUT_RING(ring, 0x00000000);
278 }
279 }
280 }
281
282 OUT_PKT0(ring, bcolor_reg[sb], 1);
283 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
284
285 u_upload_unmap(fd3_ctx->border_color_uploader);
286 }
287
288 /* emit texture state for mem->gmem restore operation.. eventually it would
289 * be good to get rid of this and use normal CSO/etc state for more of these
290 * special cases, but for now the compiler is not sufficient..
291 *
292 * Also, for using normal state, not quite sure how to handle the special
293 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
294 */
295 void
296 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring, struct pipe_surface *psurf)
297 {
298 struct fd_resource *rsc = fd_resource(psurf->texture);
299 unsigned lvl = psurf->u.tex.level;
300 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
301 uint32_t offset = fd_resource_offset(rsc, lvl, psurf->u.tex.first_layer);
302 enum pipe_format format = fd3_gmem_restore_format(psurf->format);
303
304 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
305
306 /* output sampler state: */
307 OUT_PKT3(ring, CP_LOAD_STATE, 4);
308 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
309 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
310 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
311 CP_LOAD_STATE_0_NUM_UNIT(1));
312 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
313 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
314 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
315 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
316 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
317 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
318 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
319 OUT_RING(ring, 0x00000000);
320
321 /* emit texture state: */
322 OUT_PKT3(ring, CP_LOAD_STATE, 6);
323 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
324 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
325 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
326 CP_LOAD_STATE_0_NUM_UNIT(1));
327 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
328 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
329 OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
330 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
331 fd3_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
332 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
333 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
334 A3XX_TEX_CONST_1_WIDTH(psurf->width) |
335 A3XX_TEX_CONST_1_HEIGHT(psurf->height));
336 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
337 A3XX_TEX_CONST_2_INDX(0));
338 OUT_RING(ring, 0x00000000);
339
340 /* emit mipaddrs: */
341 OUT_PKT3(ring, CP_LOAD_STATE, 3);
342 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
343 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
344 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
345 CP_LOAD_STATE_0_NUM_UNIT(1));
346 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
347 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
348 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
349 }
350
351 void
352 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
353 {
354 int32_t i, j, last = -1;
355 uint32_t total_in = 0;
356 const struct fd_vertex_state *vtx = emit->vtx;
357 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
358 unsigned vertex_regid = regid(63, 0), instance_regid = regid(63, 0);
359
360 for (i = 0; i < vp->inputs_count; i++) {
361 uint8_t semantic = sem2name(vp->inputs[i].semantic);
362 if (semantic == TGSI_SEMANTIC_VERTEXID_NOBASE)
363 vertex_regid = vp->inputs[i].regid;
364 else if (semantic == TGSI_SEMANTIC_INSTANCEID)
365 instance_regid = vp->inputs[i].regid;
366 else if (i < vtx->vtx->num_elements && vp->inputs[i].compmask)
367 last = i;
368 }
369
370 /* hw doesn't like to be configured for zero vbo's, it seems: */
371 if (vtx->vtx->num_elements == 0 &&
372 vertex_regid == regid(63, 0) &&
373 instance_regid == regid(63, 0))
374 return;
375
376 for (i = 0, j = 0; i <= last; i++) {
377 assert(sem2name(vp->inputs[i].semantic) == 0);
378 if (vp->inputs[i].compmask) {
379 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
380 const struct pipe_vertex_buffer *vb =
381 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
382 struct fd_resource *rsc = fd_resource(vb->buffer);
383 enum pipe_format pfmt = elem->src_format;
384 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
385 bool switchnext = (i != last) ||
386 vertex_regid != regid(63, 0) ||
387 instance_regid != regid(63, 0);
388 bool isint = util_format_is_pure_integer(pfmt);
389 uint32_t fs = util_format_get_blocksize(pfmt);
390
391 debug_assert(fmt != ~0);
392
393 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
394 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
395 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
396 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
397 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
398 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
399 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
400 OUT_RELOC(ring, rsc->bo, vb->buffer_offset + elem->src_offset, 0, 0);
401
402 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
403 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
404 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
405 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
406 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
407 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
408 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
409 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
410 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
411 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
412
413 total_in += vp->inputs[i].ncomp;
414 j++;
415 }
416 }
417
418 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
419 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
420 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
421 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
422 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
423 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
424 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
425 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
426 }
427
428 void
429 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
430 struct fd3_emit *emit)
431 {
432 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
433 struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
434 uint32_t dirty = emit->dirty;
435
436 emit_marker(ring, 5);
437
438 if (dirty & FD_DIRTY_SAMPLE_MASK) {
439 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
440 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
441 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
442 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
443 }
444
445 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
446 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control;
447
448 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
449 val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD |
450 A3XX_RB_RENDER_CONTROL_YCOORD |
451 A3XX_RB_RENDER_CONTROL_ZCOORD |
452 A3XX_RB_RENDER_CONTROL_WCOORD);
453
454 /* I suppose if we needed to (which I don't *think* we need
455 * to), we could emit this for binning pass too. But we
456 * would need to keep a different patch-list for binning
457 * vs render pass.
458 */
459
460 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
461 OUT_RINGP(ring, val, &fd3_context(ctx)->rbrc_patches);
462 }
463
464 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
465 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
466 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
467
468 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
469 OUT_RING(ring, zsa->rb_alpha_ref);
470
471 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
472 OUT_RING(ring, zsa->rb_stencil_control);
473
474 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
475 OUT_RING(ring, zsa->rb_stencilrefmask |
476 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
477 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
478 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
479 }
480
481 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
482 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
483 if (fp->writes_pos) {
484 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
485 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
486 }
487 if (fp->has_kill) {
488 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
489 }
490 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
491 OUT_RING(ring, val);
492 }
493
494 if (dirty & FD_DIRTY_RASTERIZER) {
495 struct fd3_rasterizer_stateobj *rasterizer =
496 fd3_rasterizer_stateobj(ctx->rasterizer);
497
498 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
499 OUT_RING(ring, rasterizer->gras_su_mode_control);
500
501 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
502 OUT_RING(ring, rasterizer->gras_su_point_minmax);
503 OUT_RING(ring, rasterizer->gras_su_point_size);
504
505 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
506 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
507 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
508 }
509
510 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
511 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
512 ->gras_cl_clip_cntl;
513 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
514 val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
515 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
516 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
517 OUT_RING(ring, val);
518 }
519
520 /* NOTE: since primitive_restart is not actually part of any
521 * state object, we need to make sure that we always emit
522 * PRIM_VTX_CNTL.. either that or be more clever and detect
523 * when it changes.
524 */
525 if (emit->info) {
526 const struct pipe_draw_info *info = emit->info;
527 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
528 ->pc_prim_vtx_cntl;
529
530 if (!emit->key.binning_pass) {
531 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
532 if (stride_in_vpc > 0)
533 stride_in_vpc = MAX2(stride_in_vpc, 2);
534 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
535 }
536
537 if (info->indexed && info->primitive_restart) {
538 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
539 }
540
541 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
542
543 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
544 OUT_RING(ring, val);
545 }
546
547 if (dirty & FD_DIRTY_SCISSOR) {
548 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
549
550 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
551 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
552 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
553 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
554 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
555
556 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
557 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
558 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
559 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
560 }
561
562 if (dirty & FD_DIRTY_VIEWPORT) {
563 fd_wfi(ctx, ring);
564 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
565 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
566 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
567 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
568 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
569 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
570 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
571 }
572
573 if (dirty & FD_DIRTY_PROG)
574 fd3_program_emit(ring, emit);
575
576 /* TODO we should not need this or fd_wfi() before emit_constants():
577 */
578 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
579 OUT_RING(ring, HLSQ_FLUSH);
580
581 if ((dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) &&
582 /* evil hack to deal sanely with clear path: */
583 (emit->prog == &ctx->prog)) {
584 fd_wfi(ctx, ring);
585 emit_constants(ring, SB_VERT_SHADER,
586 &ctx->constbuf[PIPE_SHADER_VERTEX],
587 (emit->prog->dirty & FD_SHADER_DIRTY_VP) ? vp : NULL);
588 if (!emit->key.binning_pass) {
589 emit_constants(ring, SB_FRAG_SHADER,
590 &ctx->constbuf[PIPE_SHADER_FRAGMENT],
591 (emit->prog->dirty & FD_SHADER_DIRTY_FP) ? fp : NULL);
592 }
593 }
594
595 /* emit driver params every time */
596 if (emit->info && emit->prog == &ctx->prog) {
597 uint32_t vertex_params[4] = {
598 emit->info->indexed ? emit->info->index_bias : emit->info->start,
599 0,
600 0,
601 0
602 };
603 if (vp->constlen > vp->first_driver_param) {
604 fd3_emit_constant(ring, SB_VERT_SHADER, vp->first_driver_param * 4,
605 0, 4, vertex_params, NULL);
606 }
607 }
608
609 if ((dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) && ctx->blend) {
610 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
611 uint32_t i;
612
613 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
614 enum pipe_format format = pipe_surface_format(ctx->framebuffer.cbufs[i]);
615 bool is_float = util_format_is_float(format);
616 bool is_int = util_format_is_pure_integer(format);
617 bool has_alpha = util_format_has_alpha(format);
618 uint32_t control = blend->rb_mrt[i].control;
619 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
620
621 if (is_int) {
622 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
623 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
624 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
625 }
626
627 if (has_alpha) {
628 blend_control |= blend->rb_mrt[i].blend_control_rgb;
629 } else {
630 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
631 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
632 }
633
634 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
635 OUT_RING(ring, control);
636
637 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
638 OUT_RING(ring, blend_control |
639 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
640 }
641 }
642
643 if (dirty & FD_DIRTY_BLEND_COLOR) {
644 struct pipe_blend_color *bcolor = &ctx->blend_color;
645 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
646 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
647 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
648 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
649 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
650 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
651 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
652 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
653 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
654 }
655
656 if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
657 fd_wfi(ctx, ring);
658
659 if (dirty & FD_DIRTY_VERTTEX) {
660 if (vp->has_samp)
661 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
662 else
663 dirty &= ~FD_DIRTY_VERTTEX;
664 }
665
666 if (dirty & FD_DIRTY_FRAGTEX) {
667 if (fp->has_samp)
668 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
669 else
670 dirty &= ~FD_DIRTY_FRAGTEX;
671 }
672
673 ctx->dirty &= ~dirty;
674 }
675
676 /* emit setup at begin of new cmdstream buffer (don't rely on previous
677 * state, there could have been a context switch between ioctls):
678 */
679 void
680 fd3_emit_restore(struct fd_context *ctx)
681 {
682 struct fd3_context *fd3_ctx = fd3_context(ctx);
683 struct fd_ringbuffer *ring = ctx->ring;
684 int i;
685
686 if (ctx->screen->gpu_id == 320) {
687 OUT_PKT3(ring, CP_REG_RMW, 3);
688 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
689 OUT_RING(ring, 0xfffcffff);
690 OUT_RING(ring, 0x00000000);
691 }
692
693 fd_wfi(ctx, ring);
694 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
695 OUT_RING(ring, 0x00007fff);
696
697 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
698 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
699 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
700 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
701
702 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
703 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
704 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
705 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
706
707 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
708 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
709
710 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
711 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
712 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
713 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
714
715 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
716 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
717 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
718 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
719 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
720
721 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
722 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
723 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
724
725 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
726 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
727
728 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
729 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
730 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
731 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
732
733 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
734 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
735 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
736 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
737
738 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
739 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
740 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
741
742 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
743 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
744
745 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
746 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
747
748 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
749 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
750
751 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
752 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
753
754 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
755 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
756
757 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
758 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
759 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
760 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
761 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
762
763 OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
764 OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
765 OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
766 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
767 A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
768
769 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
770 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
771
772 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
773 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
774 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
775
776 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
777 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
778
779 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
780 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
781 A3XX_RB_WINDOW_OFFSET_Y(0));
782
783 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
784 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
785 A3XX_RB_BLEND_RED_FLOAT(0.0));
786 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
787 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
788 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
789 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
790 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
791 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
792
793 for (i = 0; i < 6; i++) {
794 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
795 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
796 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
797 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
798 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
799 }
800
801 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
802 OUT_RING(ring, 0x00000000);
803
804 fd_event_write(ctx, ring, CACHE_FLUSH);
805
806 if (is_a3xx_p0(ctx->screen)) {
807 OUT_PKT3(ring, CP_DRAW_INDX, 3);
808 OUT_RING(ring, 0x00000000);
809 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
810 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
811 OUT_RING(ring, 0); /* NumIndices */
812 }
813
814 OUT_PKT3(ring, CP_NOP, 4);
815 OUT_RING(ring, 0x00000000);
816 OUT_RING(ring, 0x00000000);
817 OUT_RING(ring, 0x00000000);
818 OUT_RING(ring, 0x00000000);
819
820 fd_wfi(ctx, ring);
821
822 ctx->needs_rb_fbd = true;
823 }