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1905839c8c22337c36b0e18d00b3c7ff585d9f7f
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_gmem.c
1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/format/u_format.h"
32
33 #include "freedreno_draw.h"
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
36
37 #include "fd3_gmem.h"
38 #include "fd3_context.h"
39 #include "fd3_emit.h"
40 #include "fd3_program.h"
41 #include "fd3_format.h"
42 #include "fd3_zsa.h"
43
44 static void
45 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
46 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w,
47 bool decode_srgb)
48 {
49 enum a3xx_tile_mode tile_mode;
50 unsigned i;
51
52 for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
53 enum pipe_format pformat = 0;
54 enum a3xx_color_fmt format = 0;
55 enum a3xx_color_swap swap = WZYX;
56 bool srgb = false;
57 struct fd_resource *rsc = NULL;
58 struct fdl_slice *slice = NULL;
59 uint32_t stride = 0;
60 uint32_t base = 0;
61 uint32_t offset = 0;
62
63 if (bin_w) {
64 tile_mode = TILE_32X32;
65 } else {
66 tile_mode = LINEAR;
67 }
68
69 if ((i < nr_bufs) && bufs[i]) {
70 struct pipe_surface *psurf = bufs[i];
71
72 rsc = fd_resource(psurf->texture);
73 pformat = psurf->format;
74 /* In case we're drawing to Z32F_S8, the "color" actually goes to
75 * the stencil
76 */
77 if (rsc->stencil) {
78 rsc = rsc->stencil;
79 pformat = rsc->base.format;
80 if (bases)
81 bases++;
82 }
83 slice = fd_resource_slice(rsc, psurf->u.tex.level);
84 format = fd3_pipe2color(pformat);
85 if (decode_srgb)
86 srgb = util_format_is_srgb(pformat);
87 else
88 pformat = util_format_linear(pformat);
89
90 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
91
92 offset = fd_resource_offset(rsc, psurf->u.tex.level,
93 psurf->u.tex.first_layer);
94 swap = rsc->layout.tile_mode ? WZYX : fd3_pipe2swap(pformat);
95
96 if (bin_w) {
97 stride = bin_w * rsc->layout.cpp;
98
99 if (bases) {
100 base = bases[i];
101 }
102 } else {
103 stride = slice->pitch * rsc->layout.cpp;
104 tile_mode = rsc->layout.tile_mode;
105 }
106 } else if (i < nr_bufs && bases) {
107 base = bases[i];
108 }
109
110 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
111 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
112 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
113 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
114 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
115 COND(srgb, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB));
116 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
117 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
118 } else {
119 OUT_RELOCW(ring, rsc->bo, offset, 0, -1);
120 }
121
122 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
123 OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
124 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
125 fd3_fs_output_format(pformat))));
126 }
127 }
128
129 static bool
130 use_hw_binning(struct fd_batch *batch)
131 {
132 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
133
134 /* workaround: combining scissor optimization and hw binning
135 * seems problematic. Seems like we end up with a mismatch
136 * between binning pass and rendering pass, wrt. where the hw
137 * thinks the vertices belong. And the blob driver doesn't
138 * seem to implement anything like scissor optimization, so
139 * not entirely sure what I might be missing.
140 *
141 * But scissor optimization is mainly for window managers,
142 * which don't have many vertices (and therefore doesn't
143 * benefit much from binning pass).
144 *
145 * So for now just disable binning if scissor optimization is
146 * used.
147 */
148 if (gmem->minx || gmem->miny)
149 return false;
150
151 if ((gmem->maxpw * gmem->maxph) > 32)
152 return false;
153
154 if ((gmem->maxpw > 15) || (gmem->maxph > 15))
155 return false;
156
157 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
158 }
159
160 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
161 static void update_vsc_pipe(struct fd_batch *batch);
162 static void
163 emit_binning_workaround(struct fd_batch *batch)
164 {
165 struct fd_context *ctx = batch->ctx;
166 struct fd_gmem_stateobj *gmem = &ctx->gmem;
167 struct fd_ringbuffer *ring = batch->gmem;
168 struct fd3_emit emit = {
169 .debug = &ctx->debug,
170 .vtx = &ctx->solid_vbuf_state,
171 .prog = &ctx->solid_prog,
172 .key = {
173 .half_precision = true,
174 },
175 };
176
177 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
178 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
179 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
180 A3XX_RB_MODE_CONTROL_MRT(0));
181 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
182 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
183 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
184
185 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
186 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
187 A3XX_RB_COPY_CONTROL_MODE(0) |
188 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
189 OUT_RELOCW(ring, fd_resource(ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
190 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
191 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
192 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
193 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
194 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
195 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
196
197 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
198 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
199 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
200 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
201
202 fd3_program_emit(ring, &emit, 0, NULL);
203 fd3_emit_vertex_bufs(ring, &emit);
204
205 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
206 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
207 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
208 A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
209 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
210 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
211 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
212 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
213 OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
214
215 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
216 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
217 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
218
219 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
220 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
221 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
222 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
223
224 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
225 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
226
227 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
228 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
229 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
230 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
231 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
232 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
233 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
234 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
235 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
236
237 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
238 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
239
240 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
241 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
242 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
243 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
244 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
245
246 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
247 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
248 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
249 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
250 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
251
252 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
253 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
254 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
255 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
256 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
257
258 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
259 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
260 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
261 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
262 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
263
264 fd_wfi(batch, ring);
265 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
266 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
267 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
268 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
269 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
270 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
271 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
272
273 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
274 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
275 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
276 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
277 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
278 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
279
280 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
281 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
282 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
283
284 OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
285 OUT_RING(ring, 0x00000000); /* viz query info. */
286 OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
287 INDEX_SIZE_32_BIT, IGNORE_VISIBILITY, 0));
288 OUT_RING(ring, 2); /* NumIndices */
289 OUT_RING(ring, 2);
290 OUT_RING(ring, 1);
291 fd_reset_wfi(batch);
292
293 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
294 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
295
296 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
297 OUT_RING(ring, 0x00000000);
298
299 fd_wfi(batch, ring);
300 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
301 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
302 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
303
304 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
305 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
306 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
307 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
308
309 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
310 OUT_RING(ring, 0x00000000);
311 }
312
313 /* transfer from gmem to system memory (ie. normal RAM) */
314
315 static void
316 emit_gmem2mem_surf(struct fd_batch *batch,
317 enum adreno_rb_copy_control_mode mode,
318 bool stencil,
319 uint32_t base, struct pipe_surface *psurf)
320 {
321 struct fd_ringbuffer *ring = batch->gmem;
322 struct fd_resource *rsc = fd_resource(psurf->texture);
323 enum pipe_format format = psurf->format;
324
325 if (!rsc->valid)
326 return;
327
328 if (stencil) {
329 rsc = rsc->stencil;
330 format = rsc->base.format;
331 }
332
333 struct fdl_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
334 uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
335 psurf->u.tex.first_layer);
336
337 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
338
339 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
340 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
341 A3XX_RB_COPY_CONTROL_MODE(mode) |
342 A3XX_RB_COPY_CONTROL_GMEM_BASE(base) |
343 COND(format == PIPE_FORMAT_Z32_FLOAT ||
344 format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
345 A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE));
346
347 OUT_RELOCW(ring, rsc->bo, offset, 0, -1); /* RB_COPY_DEST_BASE */
348 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->layout.cpp));
349 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(rsc->layout.tile_mode) |
350 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
351 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
352 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
353 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(format)));
354
355 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
356 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
357 }
358
359 static void
360 fd3_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
361 {
362 struct fd_context *ctx = batch->ctx;
363 struct fd_ringbuffer *ring = batch->gmem;
364 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
365 struct fd3_emit emit = {
366 .debug = &ctx->debug,
367 .vtx = &ctx->solid_vbuf_state,
368 .prog = &ctx->solid_prog,
369 .key = {
370 .half_precision = true,
371 },
372 };
373 int i;
374
375 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
376 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
377
378 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
379 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
380 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
381 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
382 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
383 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
384 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
385 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
386 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
387
388 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
389 OUT_RING(ring, 0xff000000 |
390 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
391 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
392 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
393 OUT_RING(ring, 0xff000000 |
394 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
395 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
396 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
397
398 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
399 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
400
401 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
402 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
403
404 fd_wfi(batch, ring);
405 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
406 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
407 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
408 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
409 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
410 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
411 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
412
413 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
414 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
415 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
416 A3XX_RB_MODE_CONTROL_MRT(0));
417
418 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
419 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
420 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
421 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
422 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
423
424 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
425 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
426 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
427 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
428
429 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
430 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
431 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
432 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
433 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
434
435 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
436 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
437 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
438 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
439 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
440
441 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
442 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
443 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
444 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
445 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
446
447 fd3_program_emit(ring, &emit, 0, NULL);
448 fd3_emit_vertex_bufs(ring, &emit);
449
450 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
451 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
452 if (!rsc->stencil || batch->resolve & FD_BUFFER_DEPTH)
453 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, false,
454 ctx->gmem.zsbuf_base[0], pfb->zsbuf);
455 if (rsc->stencil && batch->resolve & FD_BUFFER_STENCIL)
456 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, true,
457 ctx->gmem.zsbuf_base[1], pfb->zsbuf);
458 }
459
460 if (batch->resolve & FD_BUFFER_COLOR) {
461 for (i = 0; i < pfb->nr_cbufs; i++) {
462 if (!pfb->cbufs[i])
463 continue;
464 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
465 continue;
466 emit_gmem2mem_surf(batch, RB_COPY_RESOLVE, false,
467 ctx->gmem.cbuf_base[i], pfb->cbufs[i]);
468 }
469 }
470
471 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
472 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
473 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
474 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
475
476 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
477 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
478 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
479 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
480 }
481
482 /* transfer from system memory to gmem */
483
484 static void
485 emit_mem2gmem_surf(struct fd_batch *batch, uint32_t bases[],
486 struct pipe_surface **psurf, uint32_t bufs, uint32_t bin_w)
487 {
488 struct fd_ringbuffer *ring = batch->gmem;
489 struct pipe_surface *zsbufs[2];
490
491 assert(bufs > 0);
492
493 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
494 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
495 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
496 A3XX_RB_MODE_CONTROL_MRT(bufs - 1));
497
498 emit_mrt(ring, bufs, psurf, bases, bin_w, false);
499
500 if (psurf[0] && (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT ||
501 psurf[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
502 /* Depth is stored as unorm in gmem, so we have to write it in using a
503 * special blit shader which writes depth.
504 */
505 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
506 OUT_RING(ring, (A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z |
507 A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
508 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
509 A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE |
510 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)));
511
512 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
513 OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
514 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
515 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * batch->ctx->gmem.bin_w));
516
517 if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
518 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
519 OUT_RING(ring, 0);
520 } else {
521 /* The gmem_restore_tex logic will put the first buffer's stencil
522 * as color. Supply it with the proper information to make that
523 * happen.
524 */
525 zsbufs[0] = zsbufs[1] = psurf[0];
526 psurf = zsbufs;
527 bufs = 2;
528 }
529 } else {
530 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
531 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_MRT(bufs - 1));
532 }
533
534 fd3_emit_gmem_restore_tex(ring, psurf, bufs);
535
536 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
537 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
538 }
539
540 static void
541 fd3_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
542 {
543 struct fd_context *ctx = batch->ctx;
544 struct fd_gmem_stateobj *gmem = &ctx->gmem;
545 struct fd_ringbuffer *ring = batch->gmem;
546 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
547 struct fd3_emit emit = {
548 .debug = &ctx->debug,
549 .vtx = &ctx->blit_vbuf_state,
550 .sprite_coord_enable = 1,
551 /* NOTE: They all use the same VP, this is for vtx bufs. */
552 .prog = &ctx->blit_prog[0],
553 .key = {
554 .half_precision = fd_half_precision(pfb),
555 },
556 };
557 float x0, y0, x1, y1;
558 unsigned bin_w = tile->bin_w;
559 unsigned bin_h = tile->bin_h;
560 unsigned i;
561
562 /* write texture coordinates to vertexbuf: */
563 x0 = ((float)tile->xoff) / ((float)pfb->width);
564 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
565 y0 = ((float)tile->yoff) / ((float)pfb->height);
566 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
567
568 OUT_PKT3(ring, CP_MEM_WRITE, 5);
569 OUT_RELOCW(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
570 OUT_RING(ring, fui(x0));
571 OUT_RING(ring, fui(y0));
572 OUT_RING(ring, fui(x1));
573 OUT_RING(ring, fui(y1));
574
575 fd3_emit_cache_flush(batch, ring);
576
577 for (i = 0; i < 4; i++) {
578 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
579 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
580 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
581 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
582
583 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
584 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
585 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
586 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
587 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
588 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
589 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
590 }
591
592 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
593 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
594 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
595
596 fd_wfi(batch, ring);
597 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
598 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
599
600 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
601 OUT_RING(ring, 0);
602 OUT_RING(ring, 0);
603
604 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
605 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
606
607 fd_wfi(batch, ring);
608 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
609 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
610 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
611 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
612 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
613 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
614 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
615
616 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
617 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
618 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
619 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
620 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
621
622 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
623 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
624 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
625 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
626 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
627
628 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
629 OUT_RING(ring, 0x2 |
630 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
631 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
632 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
633 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
634 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
635 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
636 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
637 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
638
639 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
640 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
641 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
642
643 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
644 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
645 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
646 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
647
648 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
649 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
650 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
651 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
652 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
653
654 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
655 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
656 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
657 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
658 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
659
660 fd3_emit_vertex_bufs(ring, &emit);
661
662 /* for gmem pitch/base calculations, we need to use the non-
663 * truncated tile sizes:
664 */
665 bin_w = gmem->bin_w;
666 bin_h = gmem->bin_h;
667
668 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
669 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
670 emit.fs = NULL; /* frag shader changed so clear cache */
671 fd3_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
672 emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
673 }
674
675 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
676 if (pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
677 pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT) {
678 /* Non-float can use a regular color write. It's split over 8-bit
679 * components, so half precision is always sufficient.
680 */
681 emit.prog = &ctx->blit_prog[0];
682 emit.key.half_precision = true;
683 } else {
684 /* Float depth needs special blit shader that writes depth */
685 if (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT)
686 emit.prog = &ctx->blit_z;
687 else
688 emit.prog = &ctx->blit_zs;
689 emit.key.half_precision = false;
690 }
691 emit.fs = NULL; /* frag shader changed so clear cache */
692 fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
693 emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
694 }
695
696 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
697 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
698 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
699 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
700
701 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
702 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
703 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
704 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
705 }
706
707 static void
708 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
709 {
710 unsigned i;
711 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
712 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
713 *patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
714 }
715 util_dynarray_clear(&batch->draw_patches);
716 }
717
718 static void
719 patch_rbrc(struct fd_batch *batch, uint32_t val)
720 {
721 unsigned i;
722 for (i = 0; i < fd_patch_num_elements(&batch->rbrc_patches); i++) {
723 struct fd_cs_patch *patch = fd_patch_element(&batch->rbrc_patches, i);
724 *patch->cs = patch->val | val;
725 }
726 util_dynarray_clear(&batch->rbrc_patches);
727 }
728
729 /* for rendering directly to system memory: */
730 static void
731 fd3_emit_sysmem_prep(struct fd_batch *batch)
732 {
733 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
734 struct fd_ringbuffer *ring = batch->gmem;
735 uint32_t i, pitch = 0;
736
737 for (i = 0; i < pfb->nr_cbufs; i++) {
738 struct pipe_surface *psurf = pfb->cbufs[i];
739 if (!psurf)
740 continue;
741 struct fdl_slice *slice =
742 fd_resource_slice(fd_resource(psurf->texture),
743 psurf->u.tex.level);
744 pitch = slice->pitch;
745 }
746
747 fd3_emit_restore(batch, ring);
748
749 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
750 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
751 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
752
753 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
754
755 /* setup scissor/offset for current tile: */
756 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
757 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
758 A3XX_RB_WINDOW_OFFSET_Y(0));
759
760 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
761 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
762 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
763 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
764 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
765
766 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
767 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
768 A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
769 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
770 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
771
772 patch_draws(batch, IGNORE_VISIBILITY);
773 patch_rbrc(batch, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
774 }
775
776 static void
777 update_vsc_pipe(struct fd_batch *batch)
778 {
779 struct fd_context *ctx = batch->ctx;
780 struct fd3_context *fd3_ctx = fd3_context(ctx);
781 struct fd_ringbuffer *ring = batch->gmem;
782 int i;
783
784 OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
785 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
786
787 for (i = 0; i < 8; i++) {
788 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
789
790 if (!ctx->vsc_pipe_bo[i]) {
791 ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, 0x40000,
792 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
793 }
794
795 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
796 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
797 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
798 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
799 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
800 OUT_RELOCW(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
801 OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) - 32); /* VSC_PIPE[i].DATA_LENGTH */
802 }
803 }
804
805 static void
806 emit_binning_pass(struct fd_batch *batch)
807 {
808 struct fd_context *ctx = batch->ctx;
809 struct fd_gmem_stateobj *gmem = &ctx->gmem;
810 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
811 struct fd_ringbuffer *ring = batch->gmem;
812 int i;
813
814 uint32_t x1 = gmem->minx;
815 uint32_t y1 = gmem->miny;
816 uint32_t x2 = gmem->minx + gmem->width - 1;
817 uint32_t y2 = gmem->miny + gmem->height - 1;
818
819 if (ctx->screen->gpu_id == 320) {
820 emit_binning_workaround(batch);
821 fd_wfi(batch, ring);
822 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
823 OUT_RING(ring, 0x00007fff);
824 }
825
826 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
827 OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
828
829 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
830 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
831 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
832 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
833
834 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
835 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
836 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
837
838 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
839 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
840 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
841 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
842
843 /* setup scissor/offset for whole screen: */
844 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
845 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
846 A3XX_RB_WINDOW_OFFSET_Y(y1));
847
848 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
849 OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
850
851 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
852 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
853 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
854 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
855 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
856
857 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
858 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
859 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
860 A3XX_RB_MODE_CONTROL_MRT(0));
861
862 for (i = 0; i < 4; i++) {
863 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
864 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
865 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
866 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
867 }
868
869 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
870 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
871 A3XX_PC_VSTREAM_CONTROL_N(0));
872
873 /* emit IB to binning drawcmds: */
874 fd3_emit_ib(ring, batch->binning);
875 fd_reset_wfi(batch);
876
877 fd_wfi(batch, ring);
878
879 /* and then put stuff back the way it was: */
880
881 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
882 OUT_RING(ring, 0x00000000);
883
884 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
885 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
886 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
887 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
888 A3XX_SP_SP_CTRL_REG_L0MODE(0));
889
890 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
891 OUT_RING(ring, 0x00000000);
892
893 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
894 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
895 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
896 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
897
898 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
899 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
900 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
901 A3XX_RB_MODE_CONTROL_MRT(pfb->nr_cbufs - 1));
902 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
903 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
904 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
905
906 fd_event_write(batch, ring, CACHE_FLUSH);
907 fd_wfi(batch, ring);
908
909 if (ctx->screen->gpu_id == 320) {
910 /* dummy-draw workaround: */
911 OUT_PKT3(ring, CP_DRAW_INDX, 3);
912 OUT_RING(ring, 0x00000000);
913 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
914 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
915 OUT_RING(ring, 0); /* NumIndices */
916 fd_reset_wfi(batch);
917 }
918
919 OUT_PKT3(ring, CP_NOP, 4);
920 OUT_RING(ring, 0x00000000);
921 OUT_RING(ring, 0x00000000);
922 OUT_RING(ring, 0x00000000);
923 OUT_RING(ring, 0x00000000);
924
925 fd_wfi(batch, ring);
926
927 if (ctx->screen->gpu_id == 320) {
928 emit_binning_workaround(batch);
929 }
930 }
931
932 /* before first tile */
933 static void
934 fd3_emit_tile_init(struct fd_batch *batch)
935 {
936 struct fd_ringbuffer *ring = batch->gmem;
937 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
938 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
939 uint32_t rb_render_control;
940
941 fd3_emit_restore(batch, ring);
942
943 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
944 * at the right and bottom edge tiles
945 */
946 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
947 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
948 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
949
950 update_vsc_pipe(batch);
951
952 fd_wfi(batch, ring);
953 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
954 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
955 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
956
957 if (use_hw_binning(batch)) {
958 /* emit hw binning pass: */
959 emit_binning_pass(batch);
960
961 patch_draws(batch, USE_VISIBILITY);
962 } else {
963 patch_draws(batch, IGNORE_VISIBILITY);
964 }
965
966 rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
967 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
968
969 patch_rbrc(batch, rb_render_control);
970 }
971
972 /* before mem2gmem */
973 static void
974 fd3_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
975 {
976 struct fd_ringbuffer *ring = batch->gmem;
977 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
978
979 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
980 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
981 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
982 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
983 }
984
985 /* before IB to rendering cmds: */
986 static void
987 fd3_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
988 {
989 struct fd_context *ctx = batch->ctx;
990 struct fd3_context *fd3_ctx = fd3_context(ctx);
991 struct fd_ringbuffer *ring = batch->gmem;
992 struct fd_gmem_stateobj *gmem = &ctx->gmem;
993 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
994
995 uint32_t x1 = tile->xoff;
996 uint32_t y1 = tile->yoff;
997 uint32_t x2 = tile->xoff + tile->bin_w - 1;
998 uint32_t y2 = tile->yoff + tile->bin_h - 1;
999
1000 uint32_t reg;
1001
1002 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
1003 reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
1004 if (pfb->zsbuf) {
1005 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
1006 }
1007 OUT_RING(ring, reg);
1008 if (pfb->zsbuf) {
1009 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1010 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(rsc->layout.cpp * gmem->bin_w));
1011 if (rsc->stencil) {
1012 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
1013 OUT_RING(ring, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
1014 OUT_RING(ring, A3XX_RB_STENCIL_PITCH(rsc->stencil->layout.cpp * gmem->bin_w));
1015 }
1016 } else {
1017 OUT_RING(ring, 0x00000000);
1018 }
1019
1020 if (use_hw_binning(batch)) {
1021 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
1022 struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
1023
1024 assert(pipe->w && pipe->h);
1025
1026 fd_event_write(batch, ring, HLSQ_FLUSH);
1027 fd_wfi(batch, ring);
1028
1029 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1030 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
1031 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
1032
1033
1034 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
1035 OUT_RELOCW(ring, pipe_bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
1036 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
1037 (tile->p * 4), 0, 0);
1038 } else {
1039 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1040 OUT_RING(ring, 0x00000000);
1041 }
1042
1043 OUT_PKT3(ring, CP_SET_BIN, 3);
1044 OUT_RING(ring, 0x00000000);
1045 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
1046 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
1047
1048 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
1049
1050 /* setup scissor/offset for current tile: */
1051 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
1052 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
1053 A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
1054
1055 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
1056 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
1057 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
1058 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
1059 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
1060 }
1061
1062 void
1063 fd3_gmem_init(struct pipe_context *pctx)
1064 {
1065 struct fd_context *ctx = fd_context(pctx);
1066
1067 ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
1068 ctx->emit_tile_init = fd3_emit_tile_init;
1069 ctx->emit_tile_prep = fd3_emit_tile_prep;
1070 ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
1071 ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
1072 ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
1073 }