src/gallium/drivers/freedreno/a4xx/fd4_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd4_draw.h"
  38 #include "fd4_context.h"
  39 #include "fd4_emit.h"
  40 #include "fd4_program.h"
  41 #include "fd4_format.h"
  42 #include "fd4_zsa.h"
  43
  44
  45 static void
  46 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  47                 struct fd4_emit *emit)
  48 {
  49         const struct pipe_draw_info *info = emit->info;
  50         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
  51
  52         if (!(fd4_emit_get_vp(emit) && fd4_emit_get_fp(emit)))
  53                 return;
  54
  55         fd4_emit_state(ctx, ring, emit);
  56
  57         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  58                 fd4_emit_vertex_bufs(ring, emit);
  59
  60         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
  61         OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  62         OUT_RING(ring, info->start_instance);   /* ??? UNKNOWN_2209 */
  63
  64         OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
  65         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  66                         info->restart_index : 0xffffffff);
  67
  68         /* points + psize -> spritelist: */
  69         if (ctx->rasterizer->point_size_per_vertex &&
  70                         fd4_emit_get_vp(emit)->writes_psize &&
  71                         (info->mode == PIPE_PRIM_POINTS))
  72                 primtype = DI_PT_POINTLIST_PSIZE;
  73
  74         fd4_draw_emit(ctx, ring,
  75                         primtype,
  76                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  77                         info);
  78 }
  79
  80 /* fixup dirty shader state in case some "unrelated" (from the state-
  81  * tracker's perspective) state change causes us to switch to a
  82  * different variant.
  83  */
  84 static void
  85 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  86 {
  87         struct fd4_context *fd4_ctx = fd4_context(ctx);
  88         struct ir3_shader_key *last_key = &fd4_ctx->last_key;
  89
  90         if (!ir3_shader_key_equal(last_key, key)) {
  91                 ctx->dirty |= FD_DIRTY_PROG;
  92
  93                 if (last_key->has_per_samp || key->has_per_samp) {
  94                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
  95                                         (last_key->vsaturate_t != key->vsaturate_t) ||
  96                                         (last_key->vsaturate_r != key->vsaturate_r))
  97                                 ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
  98
  99                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
 100                                         (last_key->fsaturate_t != key->fsaturate_t) ||
 101                                         (last_key->fsaturate_r != key->fsaturate_r))
 102                                 ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 103                 }
 104
 105                 if (last_key->color_two_side != key->color_two_side)
 106                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 107
 108                 if (last_key->half_precision != key->half_precision)
 109                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 110
 111                 if (last_key->rasterflat != key->rasterflat)
 112                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 113
 114                 fd4_ctx->last_key = *key;
 115         }
 116 }
 117
 118 static void
 119 fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 120 {
 121         struct fd4_context *fd4_ctx = fd4_context(ctx);
 122         struct fd4_emit emit = {
 123                 .vtx  = &ctx->vtx,
 124                 .prog = &ctx->prog,
 125                 .info = info,
 126                 .key = {
 127                         /* do binning pass first: */
 128                         .binning_pass = true,
 129                         .color_two_side = ctx->rasterizer->light_twoside,
 130                         .rasterflat = ctx->rasterizer->flatshade,
 131                         // TODO set .half_precision based on render target format,
 132                         // ie. float16 and smaller use half, float32 use full..
 133                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 134                         .ucp_enables = ctx->rasterizer->clip_plane_enable,
 135                         .has_per_samp = (fd4_ctx->fsaturate || fd4_ctx->vsaturate),
 136                         .vsaturate_s = fd4_ctx->vsaturate_s,
 137                         .vsaturate_t = fd4_ctx->vsaturate_t,
 138                         .vsaturate_r = fd4_ctx->vsaturate_r,
 139                         .fsaturate_s = fd4_ctx->fsaturate_s,
 140                         .fsaturate_t = fd4_ctx->fsaturate_t,
 141                         .fsaturate_r = fd4_ctx->fsaturate_r,
 142                 },
 143                 .rasterflat = ctx->rasterizer->flatshade,
 144                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 145                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 146         };
 147         unsigned dirty;
 148
 149         fixup_shader_state(ctx, &emit.key);
 150
 151         dirty = ctx->dirty;
 152         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 153         draw_impl(ctx, ctx->binning_ring, &emit);
 154
 155         /* and now regular (non-binning) pass: */
 156         emit.key.binning_pass = false;
 157         emit.dirty = dirty;
 158         emit.vp = NULL;   /* we changed key so need to refetch vp */
 159         emit.fp = NULL;
 160
 161         if (ctx->rasterizer->rasterizer_discard) {
 162                 fd_wfi(ctx, ctx->ring);
 163                 OUT_PKT3(ctx->ring, CP_REG_RMW, 3);
 164                 OUT_RING(ctx->ring, REG_A4XX_RB_RENDER_CONTROL);
 165                 OUT_RING(ctx->ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 166                 OUT_RING(ctx->ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 167         }
 168
 169         draw_impl(ctx, ctx->ring, &emit);
 170
 171         if (ctx->rasterizer->rasterizer_discard) {
 172                 fd_wfi(ctx, ctx->ring);
 173                 OUT_PKT3(ctx->ring, CP_REG_RMW, 3);
 174                 OUT_RING(ctx->ring, REG_A4XX_RB_RENDER_CONTROL);
 175                 OUT_RING(ctx->ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 176                 OUT_RING(ctx->ring, 0);
 177         }
 178 }
 179
 180 /* clear operations ignore viewport state, so we need to reset it
 181  * based on framebuffer state:
 182  */
 183 static void
 184 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 185 {
 186         float half_width = pfb->width * 0.5f;
 187         float half_height = pfb->height * 0.5f;
 188
 189         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 4);
 190         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(half_width));
 191         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(half_width));
 192         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(half_height));
 193         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-half_height));
 194 }
 195
 196 /* TODO maybe we should just migrate u_blitter for clear and do it in
 197  * core (so we get normal draw pass state mgmt and binning).. That should
 198  * work well enough for a3xx/a4xx (but maybe not a2xx?)
 199  */
 200
 201 static void
 202 fd4_clear_binning(struct fd_context *ctx, unsigned dirty)
 203 {
 204         struct fd4_context *fd4_ctx = fd4_context(ctx);
 205         struct fd_ringbuffer *ring = ctx->binning_ring;
 206         struct fd4_emit emit = {
 207                 .vtx  = &fd4_ctx->solid_vbuf_state,
 208                 .prog = &ctx->solid_prog,
 209                 .key = {
 210                         .binning_pass = true,
 211                         .half_precision = true,
 212                 },
 213                 .dirty = dirty,
 214         };
 215
 216         fd4_emit_state(ctx, ring, &emit);
 217         fd4_emit_vertex_bufs(ring, &emit);
 218         reset_viewport(ring, &ctx->framebuffer);
 219
 220         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
 221         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_VAROUT(0) |
 222                         A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 223         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 224                         A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES));
 225
 226         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 227         OUT_RING(ring, 0x00000002);
 228
 229         fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 230                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 231 }
 232
 233 static void
 234 fd4_clear(struct fd_context *ctx, unsigned buffers,
 235                 const union pipe_color_union *color, double depth, unsigned stencil)
 236 {
 237         struct fd4_context *fd4_ctx = fd4_context(ctx);
 238         struct fd_ringbuffer *ring = ctx->ring;
 239         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 240         unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
 241         unsigned dirty = ctx->dirty;
 242         unsigned i;
 243         struct fd4_emit emit = {
 244                 .vtx  = &fd4_ctx->solid_vbuf_state,
 245                 .prog = &ctx->solid_prog,
 246                 .key = {
 247                         .half_precision = fd_half_precision(pfb),
 248                 },
 249         };
 250
 251         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 252         dirty |= FD_DIRTY_PROG;
 253         emit.dirty = dirty;
 254
 255         fd4_clear_binning(ctx, dirty);
 256
 257         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 258         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 259
 260         /* emit generic state now: */
 261         fd4_emit_state(ctx, ring, &emit);
 262         reset_viewport(ring, pfb);
 263
 264         if (buffers & PIPE_CLEAR_DEPTH) {
 265                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 266                 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 267                                 A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
 268                                 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 269
 270                 fd_wfi(ctx, ring);
 271                 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0, 2);
 272                 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 273                 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(depth));
 274                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 275         } else {
 276                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 277                 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 278         }
 279
 280         if (buffers & PIPE_CLEAR_STENCIL) {
 281                 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 282                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 283                                 A4XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 284                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 285                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 286                                 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 287                                 0xff000000 | // XXX ???
 288                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 289
 290                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 291                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 292                                 A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 293                                 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 294                                 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 295                                 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 296                                 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 297                                 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 298                                 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 299                                 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 300                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER);
 301         } else {
 302                 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 303                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 304                                 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 305                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 306                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 307                                 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 308                                 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 309
 310                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 311                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 312                                 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 313                                 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 314                                 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 315                                 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 316                                 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 317                                 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 318                                 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 319                 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 320         }
 321
 322         if (buffers & PIPE_CLEAR_COLOR) {
 323                 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
 324                 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
 325         }
 326
 327         for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
 328                 mrt_comp[i] = (buffers & (PIPE_CLEAR_COLOR0 << i)) ? 0xf : 0x0;
 329
 330                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 331                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 332                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 333
 334                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
 335                 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 336                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 337                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 338                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 339                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 340                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 341         }
 342
 343         OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
 344         OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
 345                         A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
 346                         A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
 347                         A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
 348                         A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
 349                         A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
 350                         A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
 351                         A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
 352
 353         fd4_emit_vertex_bufs(ring, &emit);
 354
 355         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 356         OUT_RING(ring, 0x0);          /* XXX GRAS_ALPHA_CONTROL */
 357
 358         OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
 359         OUT_RING(ring, 0x00000000);
 360
 361         /* until fastclear works: */
 362         fd4_emit_const(ring, SHADER_FRAGMENT, 0, 0, 4, color->ui, NULL);
 363
 364         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 365         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 366         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 367
 368         OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
 369         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 370
 371         OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 372         OUT_RING(ring, 0x00000001);
 373
 374         fd4_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 375                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 376
 377         OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 378         OUT_RING(ring, 0x00000000);
 379
 380         OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
 381         OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
 382
 383         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 384         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 385                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 386                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 387                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 388 }
 389
 390 void
 391 fd4_draw_init(struct pipe_context *pctx)
 392 {
 393         struct fd_context *ctx = fd_context(pctx);
 394         ctx->draw_vbo = fd4_draw_vbo;
 395         ctx->clear = fd4_clear;
 396 }