src/gallium/drivers/freedreno/a4xx/fd4_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd4_draw.h"
  38 #include "fd4_context.h"
  39 #include "fd4_emit.h"
  40 #include "fd4_program.h"
  41 #include "fd4_format.h"
  42 #include "fd4_zsa.h"
  43
  44
  45 static void
  46 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  47                 struct fd4_emit *emit)
  48 {
  49         const struct pipe_draw_info *info = emit->info;
  50
  51         fd4_emit_state(ctx, ring, emit);
  52
  53         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  54                 fd4_emit_vertex_bufs(ring, emit);
  55
  56         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
  57         OUT_RING(ring, info->start);            /* VFD_INDEX_OFFSET */
  58         OUT_RING(ring, info->start_instance);   /* ??? UNKNOWN_2209 */
  59
  60         OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
  61         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  62                         info->restart_index : 0xffffffff);
  63
  64         fd4_draw_emit(ctx, ring,
  65                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  66                         info);
  67 }
  68
  69 /* fixup dirty shader state in case some "unrelated" (from the state-
  70  * tracker's perspective) state change causes us to switch to a
  71  * different variant.
  72  */
  73 static void
  74 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  75 {
  76         struct fd4_context *fd4_ctx = fd4_context(ctx);
  77         struct ir3_shader_key *last_key = &fd4_ctx->last_key;
  78
  79         if (!ir3_shader_key_equal(last_key, key)) {
  80                 ctx->dirty |= FD_DIRTY_PROG;
  81
  82                 if (last_key->has_per_samp || key->has_per_samp) {
  83                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
  84                                         (last_key->vsaturate_t != key->vsaturate_t) ||
  85                                         (last_key->vsaturate_r != key->vsaturate_r))
  86                                 ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
  87
  88                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
  89                                         (last_key->fsaturate_t != key->fsaturate_t) ||
  90                                         (last_key->fsaturate_r != key->fsaturate_r))
  91                                 ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
  92                 }
  93
  94                 if (last_key->color_two_side != key->color_two_side)
  95                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
  96
  97                 if (last_key->half_precision != key->half_precision)
  98                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
  99
 100                 if (last_key->alpha != key->alpha)
 101                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 102
 103                 fd4_ctx->last_key = *key;
 104         }
 105 }
 106
 107 static void
 108 fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 109 {
 110         struct fd4_context *fd4_ctx = fd4_context(ctx);
 111         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 112         struct fd4_emit emit = {
 113                 .vtx  = &ctx->vtx,
 114                 .prog = &ctx->prog,
 115                 .info = info,
 116                 .key = {
 117                         /* do binning pass first: */
 118                         .binning_pass = true,
 119                         .color_two_side = ctx->rasterizer ? ctx->rasterizer->light_twoside : false,
 120                         .alpha = util_format_is_alpha(pipe_surface_format(pfb->cbufs[0])),
 121                         // TODO set .half_precision based on render target format,
 122                         // ie. float16 and smaller use half, float32 use full..
 123                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 124                         .has_per_samp = fd4_ctx->fsaturate || fd4_ctx->vsaturate,
 125                         .vsaturate_s = fd4_ctx->vsaturate_s,
 126                         .vsaturate_t = fd4_ctx->vsaturate_t,
 127                         .vsaturate_r = fd4_ctx->vsaturate_r,
 128                         .fsaturate_s = fd4_ctx->fsaturate_s,
 129                         .fsaturate_t = fd4_ctx->fsaturate_t,
 130                         .fsaturate_r = fd4_ctx->fsaturate_r,
 131                 },
 132                 .format = fd4_emit_format(pfb->cbufs[0]),
 133                 .rasterflat = ctx->rasterizer && ctx->rasterizer->flatshade,
 134         };
 135         unsigned dirty;
 136
 137         fixup_shader_state(ctx, &emit.key);
 138
 139         dirty = ctx->dirty;
 140         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 141         draw_impl(ctx, ctx->binning_ring, &emit);
 142
 143         /* and now regular (non-binning) pass: */
 144         emit.key.binning_pass = false;
 145         emit.dirty = dirty;
 146         emit.vp = NULL;   /* we changed key so need to refetch vp */
 147         draw_impl(ctx, ctx->ring, &emit);
 148 }
 149
 150 /* clear operations ignore viewport state, so we need to reset it
 151  * based on framebuffer state:
 152  */
 153 static void
 154 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 155 {
 156         float half_width = pfb->width * 0.5f;
 157         float half_height = pfb->height * 0.5f;
 158
 159         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 4);
 160         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(half_width));
 161         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(half_width));
 162         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(half_height));
 163         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-half_height));
 164 }
 165
 166 static void
 167 fd4_clear(struct fd_context *ctx, unsigned buffers,
 168                 const union pipe_color_union *color, double depth, unsigned stencil)
 169 {
 170         struct fd4_context *fd4_ctx = fd4_context(ctx);
 171         struct fd_ringbuffer *ring = ctx->ring;
 172         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 173         unsigned dirty = ctx->dirty;
 174         unsigned ce, i;
 175         struct fd4_emit emit = {
 176                 .vtx  = &fd4_ctx->solid_vbuf_state,
 177                 .prog = &ctx->solid_prog,
 178                 .key = {
 179                         .half_precision = true,
 180                 },
 181                 .format = fd4_emit_format(pfb->cbufs[0]),
 182         };
 183         uint32_t colr = 0;
 184
 185         if ((buffers & PIPE_CLEAR_COLOR) && pfb->nr_cbufs)
 186                 colr  = pack_rgba(pfb->cbufs[0]->format, color->f);
 187
 188         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 189         dirty |= FD_DIRTY_PROG;
 190         emit.dirty = dirty;
 191
 192         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 193         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 194
 195         /* emit generic state now: */
 196         fd4_emit_state(ctx, ring, &emit);
 197         reset_viewport(ring, pfb);
 198
 199         if (buffers & PIPE_CLEAR_DEPTH) {
 200                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 201                 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 202                                 A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
 203                                 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 204
 205                 fd_wfi(ctx, ring);
 206                 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0, 2);
 207                 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 208                 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(depth));
 209                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 210         } else {
 211                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 212                 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 213         }
 214
 215         if (buffers & PIPE_CLEAR_STENCIL) {
 216                 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 217                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 218                                 A4XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 219                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 220                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 221                                 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 222                                 0xff000000 | // XXX ???
 223                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 224
 225                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 226                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 227                                 A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 228                                 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 229                                 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 230                                 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 231                                 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 232                                 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 233                                 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 234                                 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 235                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER);
 236         } else {
 237                 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 238                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 239                                 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 240                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 241                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 242                                 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 243                                 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 244
 245                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 246                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 247                                 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 248                                 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 249                                 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 250                                 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 251                                 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 252                                 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 253                                 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 254                 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 255         }
 256
 257         if (buffers & PIPE_CLEAR_COLOR) {
 258                 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
 259                 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
 260                 ce = 0xf;
 261         } else {
 262                 ce = 0x0;
 263         }
 264
 265         for (i = 0; i < 8; i++) {
 266                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 267                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR |
 268                                 A4XX_RB_MRT_CONTROL_B11 |
 269                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce));
 270
 271                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
 272                 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 273                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 274                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 275                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 276                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 277                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 278         }
 279
 280         fd4_emit_vertex_bufs(ring, &emit);
 281
 282         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 283         OUT_RING(ring, 0x0);          /* XXX GRAS_ALPHA_CONTROL */
 284
 285         OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
 286         OUT_RING(ring, 0x00000000);
 287
 288         OUT_PKT0(ring, REG_A4XX_RB_CLEAR_COLOR_DW0, 4);
 289         OUT_RING(ring, colr);         /* RB_CLEAR_COLOR_DW0 */
 290         OUT_RING(ring, colr);         /* RB_CLEAR_COLOR_DW1 */
 291         OUT_RING(ring, colr);         /* RB_CLEAR_COLOR_DW2 */
 292         OUT_RING(ring, colr);         /* RB_CLEAR_COLOR_DW3 */
 293
 294         /* until fastclear works: */
 295         fd4_emit_constant(ring, SB_FRAG_SHADER, 0, 0, 4, color->ui, NULL);
 296
 297         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 298         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 299         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 300
 301         OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
 302         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 303
 304         OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 305         OUT_RING(ring, 0x00000001);
 306
 307         fd4_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 308                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 309
 310         OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 311         OUT_RING(ring, 0x00000000);
 312
 313         OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
 314         OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
 315
 316         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 317         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 318                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 319                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 320                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 321 }
 322
 323 void
 324 fd4_draw_init(struct pipe_context *pctx)
 325 {
 326         struct fd_context *ctx = fd_context(pctx);
 327         ctx->draw_vbo = fd4_draw_vbo;
 328         ctx->clear = fd4_clear;
 329 }