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[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
37
38 #include "fd4_emit.h"
39 #include "fd4_blend.h"
40 #include "fd4_context.h"
41 #include "fd4_program.h"
42 #include "fd4_rasterizer.h"
43 #include "fd4_texture.h"
44 #include "fd4_format.h"
45 #include "fd4_zsa.h"
46
47 static const enum adreno_state_block sb[] = {
48 [SHADER_VERTEX] = SB_VERT_SHADER,
49 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
50 };
51
52 /* regid: base const register
53 * prsc or dwords: buffer containing constant values
54 * sizedwords: size of const value buffer
55 */
56 void
57 fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
58 uint32_t regid, uint32_t offset, uint32_t sizedwords,
59 const uint32_t *dwords, struct pipe_resource *prsc)
60 {
61 uint32_t i, sz;
62 enum adreno_state_src src;
63
64 debug_assert((regid % 4) == 0);
65 debug_assert((sizedwords % 4) == 0);
66
67 if (prsc) {
68 sz = 0;
69 src = 0x2; // TODO ??
70 } else {
71 sz = sizedwords;
72 src = SS_DIRECT;
73 }
74
75 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
76 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
77 CP_LOAD_STATE_0_STATE_SRC(src) |
78 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
79 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/4));
80 if (prsc) {
81 struct fd_bo *bo = fd_resource(prsc)->bo;
82 OUT_RELOC(ring, bo, offset,
83 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
84 } else {
85 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
86 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
87 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
88 }
89 for (i = 0; i < sz; i++) {
90 OUT_RING(ring, dwords[i]);
91 }
92 }
93
94 static void
95 fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
96 uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
97 {
98 uint32_t i;
99
100 debug_assert((regid % 4) == 0);
101 debug_assert((num % 4) == 0);
102
103 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
104 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
105 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
106 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
107 CP_LOAD_STATE_0_NUM_UNIT(num/4));
108 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
109 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
110
111 for (i = 0; i < num; i++) {
112 if (bos[i]) {
113 if (write) {
114 OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
115 } else {
116 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
117 }
118 } else {
119 OUT_RING(ring, 0xbad00000 | (i << 16));
120 }
121 }
122 }
123
124 static void
125 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
126 enum adreno_state_block sb, struct fd_texture_stateobj *tex,
127 const struct ir3_shader_variant *v)
128 {
129 static const uint32_t bcolor_reg[] = {
130 [SB_VERT_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
131 [SB_FRAG_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
132 };
133 struct fd4_context *fd4_ctx = fd4_context(ctx);
134 unsigned i, off;
135 void *ptr;
136
137 u_upload_alloc(fd4_ctx->border_color_uploader,
138 0, BORDER_COLOR_UPLOAD_SIZE,
139 BORDER_COLOR_UPLOAD_SIZE, &off,
140 &fd4_ctx->border_color_buf,
141 &ptr);
142
143 fd_setup_border_colors(tex, ptr, 0);
144
145 if (tex->num_samplers > 0) {
146 int num_samplers;
147
148 /* not sure if this is an a420.0 workaround, but we seem
149 * to need to emit these in pairs.. emit a final dummy
150 * entry if odd # of samplers:
151 */
152 num_samplers = align(tex->num_samplers, 2);
153
154 /* output sampler state: */
155 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * num_samplers));
156 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
157 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
158 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
159 CP_LOAD_STATE_0_NUM_UNIT(num_samplers));
160 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
161 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
162 for (i = 0; i < tex->num_samplers; i++) {
163 static const struct fd4_sampler_stateobj dummy_sampler = {};
164 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
165 fd4_sampler_stateobj(tex->samplers[i]) :
166 &dummy_sampler;
167 OUT_RING(ring, sampler->texsamp0);
168 OUT_RING(ring, sampler->texsamp1);
169 }
170
171 for (; i < num_samplers; i++) {
172 OUT_RING(ring, 0x00000000);
173 OUT_RING(ring, 0x00000000);
174 }
175 }
176
177 if (tex->num_textures > 0) {
178 unsigned num_textures = tex->num_textures + v->astc_srgb.count;
179
180 /* emit texture state: */
181 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * num_textures));
182 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
183 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
184 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
185 CP_LOAD_STATE_0_NUM_UNIT(num_textures));
186 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
187 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
188 for (i = 0; i < tex->num_textures; i++) {
189 static const struct fd4_pipe_sampler_view dummy_view = {};
190 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
191 fd4_pipe_sampler_view(tex->textures[i]) :
192 &dummy_view;
193
194 OUT_RING(ring, view->texconst0);
195 OUT_RING(ring, view->texconst1);
196 OUT_RING(ring, view->texconst2);
197 OUT_RING(ring, view->texconst3);
198 if (view->base.texture) {
199 struct fd_resource *rsc = fd_resource(view->base.texture);
200 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
201 } else {
202 OUT_RING(ring, 0x00000000);
203 }
204 OUT_RING(ring, 0x00000000);
205 OUT_RING(ring, 0x00000000);
206 OUT_RING(ring, 0x00000000);
207 }
208
209 for (i = 0; i < v->astc_srgb.count; i++) {
210 static const struct fd4_pipe_sampler_view dummy_view = {};
211 const struct fd4_pipe_sampler_view *view;
212 unsigned idx = v->astc_srgb.orig_idx[i];
213
214 view = tex->textures[idx] ?
215 fd4_pipe_sampler_view(tex->textures[idx]) :
216 &dummy_view;
217
218 debug_assert(view->texconst0 & A4XX_TEX_CONST_0_SRGB);
219
220 OUT_RING(ring, view->texconst0 & ~A4XX_TEX_CONST_0_SRGB);
221 OUT_RING(ring, view->texconst1);
222 OUT_RING(ring, view->texconst2);
223 OUT_RING(ring, view->texconst3);
224 if (view->base.texture) {
225 struct fd_resource *rsc = fd_resource(view->base.texture);
226 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
227 } else {
228 OUT_RING(ring, 0x00000000);
229 }
230 OUT_RING(ring, 0x00000000);
231 OUT_RING(ring, 0x00000000);
232 OUT_RING(ring, 0x00000000);
233 }
234 } else {
235 debug_assert(v->astc_srgb.count == 0);
236 }
237
238 OUT_PKT0(ring, bcolor_reg[sb], 1);
239 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
240
241 u_upload_unmap(fd4_ctx->border_color_uploader);
242 }
243
244 /* emit texture state for mem->gmem restore operation.. eventually it would
245 * be good to get rid of this and use normal CSO/etc state for more of these
246 * special cases..
247 */
248 void
249 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
250 struct pipe_surface **bufs)
251 {
252 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
253 int i;
254
255 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
256 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
257 }
258
259 /* output sampler state: */
260 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * nr_bufs));
261 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
262 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
263 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
264 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs));
265 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
266 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
267 for (i = 0; i < nr_bufs; i++) {
268 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
269 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
270 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
271 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
272 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
273 OUT_RING(ring, 0x00000000);
274 }
275
276 /* emit texture state: */
277 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * nr_bufs));
278 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
279 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
280 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
281 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs));
282 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
283 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
284 for (i = 0; i < nr_bufs; i++) {
285 if (bufs[i]) {
286 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
287 enum pipe_format format = fd4_gmem_restore_format(bufs[i]->format);
288
289 /* The restore blit_zs shader expects stencil in sampler 0,
290 * and depth in sampler 1
291 */
292 if (rsc->stencil && (i == 0)) {
293 rsc = rsc->stencil;
294 format = fd4_gmem_restore_format(rsc->base.b.format);
295 }
296
297 /* note: PIPE_BUFFER disallowed for surfaces */
298 unsigned lvl = bufs[i]->u.tex.level;
299 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
300 unsigned offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
301
302 /* z32 restore is accomplished using depth write. If there is
303 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
304 * then no render target:
305 *
306 * (The same applies for z32_s8x24, since for stencil sampler
307 * state the above 'if' will replace 'format' with s8)
308 */
309 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
310 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
311 mrt_comp[i] = 0;
312
313 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
314
315 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
316 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
317 fd4_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
318 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
319 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
320 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
321 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
322 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
323 OUT_RING(ring, 0x00000000);
324 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
325 OUT_RING(ring, 0x00000000);
326 OUT_RING(ring, 0x00000000);
327 OUT_RING(ring, 0x00000000);
328 } else {
329 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
330 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
331 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
332 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
333 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
334 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
335 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) |
336 A4XX_TEX_CONST_1_HEIGHT(0));
337 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
338 OUT_RING(ring, 0x00000000);
339 OUT_RING(ring, 0x00000000);
340 OUT_RING(ring, 0x00000000);
341 OUT_RING(ring, 0x00000000);
342 OUT_RING(ring, 0x00000000);
343 }
344 }
345
346 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
347 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
348 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
349 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
350 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
351 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
352 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
353 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
354 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
355 }
356
357 void
358 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
359 {
360 int32_t i, j, last = -1;
361 uint32_t total_in = 0;
362 const struct fd_vertex_state *vtx = emit->vtx;
363 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
364 unsigned vertex_regid = regid(63, 0);
365 unsigned instance_regid = regid(63, 0);
366 unsigned vtxcnt_regid = regid(63, 0);
367
368 /* Note that sysvals come *after* normal inputs: */
369 for (i = 0; i < vp->inputs_count; i++) {
370 if (!vp->inputs[i].compmask)
371 continue;
372 if (vp->inputs[i].sysval) {
373 switch(vp->inputs[i].slot) {
374 case SYSTEM_VALUE_BASE_VERTEX:
375 /* handled elsewhere */
376 break;
377 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
378 vertex_regid = vp->inputs[i].regid;
379 break;
380 case SYSTEM_VALUE_INSTANCE_ID:
381 instance_regid = vp->inputs[i].regid;
382 break;
383 case SYSTEM_VALUE_VERTEX_CNT:
384 vtxcnt_regid = vp->inputs[i].regid;
385 break;
386 default:
387 unreachable("invalid system value");
388 break;
389 }
390 } else if (i < vtx->vtx->num_elements) {
391 last = i;
392 }
393 }
394
395 for (i = 0, j = 0; i <= last; i++) {
396 assert(!vp->inputs[i].sysval);
397 if (vp->inputs[i].compmask) {
398 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
399 const struct pipe_vertex_buffer *vb =
400 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
401 struct fd_resource *rsc = fd_resource(vb->buffer);
402 enum pipe_format pfmt = elem->src_format;
403 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
404 bool switchnext = (i != last) ||
405 (vertex_regid != regid(63, 0)) ||
406 (instance_regid != regid(63, 0)) ||
407 (vtxcnt_regid != regid(63, 0));
408 bool isint = util_format_is_pure_integer(pfmt);
409 uint32_t fs = util_format_get_blocksize(pfmt);
410 uint32_t off = vb->buffer_offset + elem->src_offset;
411 uint32_t size = fd_bo_size(rsc->bo) - off;
412 debug_assert(fmt != ~0);
413
414 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
415 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
416 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
417 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
418 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
419 OUT_RELOC(ring, rsc->bo, off, 0, 0);
420 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
421 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
422
423 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
424 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
425 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
426 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
427 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
428 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
429 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
430 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
431 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
432 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
433
434 total_in += vp->inputs[i].ncomp;
435 j++;
436 }
437 }
438
439 /* hw doesn't like to be configured for zero vbo's, it seems: */
440 if (last < 0) {
441 /* just recycle the shader bo, we just need to point to *something*
442 * valid:
443 */
444 struct fd_bo *dummy_vbo = vp->bo;
445 bool switchnext = (vertex_regid != regid(63, 0)) ||
446 (instance_regid != regid(63, 0)) ||
447 (vtxcnt_regid != regid(63, 0));
448
449 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(0), 4);
450 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
451 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
452 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
453 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
454 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
455 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
456
457 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(0), 1);
458 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
459 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
460 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM) |
461 A4XX_VFD_DECODE_INSTR_SWAP(XYZW) |
462 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
463 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
464 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
465 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
466
467 total_in = 1;
468 j = 1;
469 }
470
471 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
472 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
473 0xa0000 | /* XXX */
474 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
475 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
476 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
477 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
478 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
479 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
480 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
481 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
482
483 /* cache invalidate, otherwise vertex fetch could see
484 * stale vbo contents:
485 */
486 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
487 OUT_RING(ring, 0x00000000);
488 OUT_RING(ring, 0x00000012);
489 }
490
491 void
492 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
493 struct fd4_emit *emit)
494 {
495 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
496 const struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
497 uint32_t dirty = emit->dirty;
498
499 emit_marker(ring, 5);
500
501 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
502 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
503 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
504
505 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
506 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
507 }
508
509 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
510 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
511 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
512 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
513 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
514 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
515 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
516 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
517 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
518 }
519
520 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
521 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
522 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
523 uint32_t rb_alpha_control = zsa->rb_alpha_control;
524
525 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
526 rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
527
528 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
529 OUT_RING(ring, rb_alpha_control);
530
531 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
532 OUT_RING(ring, zsa->rb_stencil_control);
533 OUT_RING(ring, zsa->rb_stencil_control2);
534 }
535
536 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
537 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
538 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
539
540 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
541 OUT_RING(ring, zsa->rb_stencilrefmask |
542 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
543 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
544 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
545 }
546
547 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
548 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
549 bool fragz = fp->has_kill | fp->writes_pos;
550
551 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
552 OUT_RING(ring, zsa->rb_depth_control |
553 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
554 COND(fragz && fp->frag_coord, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
555
556 /* maybe this register/bitfield needs a better name.. this
557 * appears to be just disabling early-z
558 */
559 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
560 OUT_RING(ring, zsa->gras_alpha_control |
561 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
562 COND(fragz && fp->frag_coord, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
563 }
564
565 if (dirty & FD_DIRTY_RASTERIZER) {
566 struct fd4_rasterizer_stateobj *rasterizer =
567 fd4_rasterizer_stateobj(ctx->rasterizer);
568
569 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
570 OUT_RING(ring, rasterizer->gras_su_mode_control |
571 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
572
573 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
574 OUT_RING(ring, rasterizer->gras_su_point_minmax);
575 OUT_RING(ring, rasterizer->gras_su_point_size);
576
577 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
578 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
579 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
580
581 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
582 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
583 }
584
585 /* NOTE: since primitive_restart is not actually part of any
586 * state object, we need to make sure that we always emit
587 * PRIM_VTX_CNTL.. either that or be more clever and detect
588 * when it changes.
589 */
590 if (emit->info) {
591 const struct pipe_draw_info *info = emit->info;
592 struct fd4_rasterizer_stateobj *rast =
593 fd4_rasterizer_stateobj(ctx->rasterizer);
594 uint32_t val = rast->pc_prim_vtx_cntl;
595
596 if (info->indexed && info->primitive_restart)
597 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
598
599 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
600
601 if (fp->total_in > 0) {
602 uint32_t varout = align(fp->total_in, 16) / 16;
603 if (varout > 1)
604 varout = align(varout, 2);
605 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
606 }
607
608 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
609 OUT_RING(ring, val);
610 OUT_RING(ring, rast->pc_prim_vtx_cntl2);
611 }
612
613 if (dirty & FD_DIRTY_SCISSOR) {
614 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
615
616 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
617 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
618 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
619 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
620 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
621
622 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
623 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
624 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
625 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
626 }
627
628 if (dirty & FD_DIRTY_VIEWPORT) {
629 fd_wfi(ctx, ring);
630 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
631 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
632 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
633 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
634 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
635 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
636 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
637 }
638
639 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
640 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
641 unsigned n = pfb->nr_cbufs;
642 /* if we have depth/stencil, we need at least on MRT: */
643 if (pfb->zsbuf)
644 n = MAX2(1, n);
645 fd4_program_emit(ring, emit, n, pfb->cbufs);
646 }
647
648 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
649 ir3_emit_consts(vp, ring, ctx, emit->info, dirty);
650 if (!emit->key.binning_pass)
651 ir3_emit_consts(fp, ring, ctx, emit->info, dirty);
652 }
653
654 if ((dirty & FD_DIRTY_BLEND)) {
655 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
656 uint32_t i;
657
658 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
659 enum pipe_format format = pipe_surface_format(
660 ctx->framebuffer.cbufs[i]);
661 bool is_int = util_format_is_pure_integer(format);
662 bool has_alpha = util_format_has_alpha(format);
663 uint32_t control = blend->rb_mrt[i].control;
664 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
665
666 if (is_int) {
667 control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
668 control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
669 }
670
671 if (has_alpha) {
672 blend_control |= blend->rb_mrt[i].blend_control_rgb;
673 } else {
674 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
675 control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
676 }
677
678 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
679 OUT_RING(ring, control);
680
681 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
682 OUT_RING(ring, blend_control);
683 }
684
685 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
686 OUT_RING(ring, blend->rb_fs_output |
687 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
688 }
689
690 if (dirty & FD_DIRTY_BLEND_COLOR) {
691 struct pipe_blend_color *bcolor = &ctx->blend_color;
692
693 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 8);
694 OUT_RING(ring, A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
695 A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
696 A4XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
697 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[0]));
698 OUT_RING(ring, A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
699 A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
700 A4XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
701 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[1]));
702 OUT_RING(ring, A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
703 A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
704 A4XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
705 OUT_RING(ring, A4XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
706 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
707 A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
708 A4XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
709 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
710 }
711
712 if (dirty & FD_DIRTY_VERTTEX) {
713 if (vp->has_samp)
714 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex, vp);
715 else
716 dirty &= ~FD_DIRTY_VERTTEX;
717 }
718
719 if (dirty & FD_DIRTY_FRAGTEX) {
720 if (fp->has_samp)
721 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex, fp);
722 else
723 dirty &= ~FD_DIRTY_FRAGTEX;
724 }
725
726 ctx->dirty &= ~dirty;
727 }
728
729 /* emit setup at begin of new cmdstream buffer (don't rely on previous
730 * state, there could have been a context switch between ioctls):
731 */
732 void
733 fd4_emit_restore(struct fd_context *ctx)
734 {
735 struct fd4_context *fd4_ctx = fd4_context(ctx);
736 struct fd_ringbuffer *ring = ctx->ring;
737
738 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
739 OUT_RING(ring, 0x00000001);
740
741 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
742 OUT_RING(ring, 0x00000000);
743
744 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
745 OUT_RING(ring, 0x00000006);
746
747 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
748 OUT_RING(ring, 0x0000003a);
749
750 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
751 OUT_RING(ring, 0x00000001);
752
753 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
754 OUT_RING(ring, 0x00000000);
755
756 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
757 OUT_RING(ring, 0x00000007);
758
759 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
760 OUT_RING(ring, 0x00000000);
761
762 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
763 OUT_RING(ring, 0x00000000);
764 OUT_RING(ring, 0x00000012);
765
766 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
767 OUT_RING(ring, 0x00000000);
768
769 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
770 OUT_RING(ring, 0x00000006);
771
772 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
773 OUT_RING(ring, 0x00000000);
774
775 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
776 OUT_RING(ring, 0x00040000);
777
778 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
779 OUT_RING(ring, 0x00000000);
780
781 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
782 OUT_RING(ring, 0x00001000);
783
784 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
785 OUT_RING(ring, 0x00000000);
786
787 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
788 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
789 A4XX_RB_BLEND_RED_FLOAT(0.0));
790 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
791 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
792 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
793 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
794 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
795 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
796
797 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
798 OUT_RING(ring, 0x00000000);
799
800 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
801 OUT_RING(ring, 0x00000000);
802
803 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
804 OUT_RING(ring, 0x00000000);
805
806 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
807 OUT_RING(ring, 0x00000000);
808
809 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
810 OUT_RING(ring, 0x00000000);
811
812 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
813 OUT_RING(ring, 0x00000000);
814
815 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
816 OUT_RING(ring, 0x0000001d);
817
818 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
819 OUT_RING(ring, 0x00000000);
820
821 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
822 OUT_RING(ring, 0x00000001);
823
824 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
825 OUT_RING(ring, 0x00000000);
826
827 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
828 OUT_RING(ring, 0x00000000);
829
830 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
831 OUT_RING(ring, 0x00000000);
832
833 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
834 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
835 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
836 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
837 A4XX_TPL1_TP_TEX_COUNT_GS(0));
838
839 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
840 OUT_RING(ring, 16);
841
842 /* we don't use this yet.. probably best to disable.. */
843 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
844 OUT_RING(ring, CP_SET_DRAW_STATE_0_COUNT(0) |
845 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS |
846 CP_SET_DRAW_STATE_0_GROUP_ID(0));
847 OUT_RING(ring, CP_SET_DRAW_STATE_1_ADDR(0));
848
849 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
850 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
851 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
852
853 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
854 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
855 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
856
857 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
858 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
859 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
860 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
861 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
862
863 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
864 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
865 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
866
867 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
868 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
869 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
870
871 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
872 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
873
874 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
875 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
876
877 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
878 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
879
880 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
881 OUT_RING(ring, 0x0);
882
883 fd_hw_query_enable(ctx, ring);
884
885 ctx->needs_rb_fbd = true;
886 }
887
888 static void
889 fd4_emit_ib(struct fd_ringbuffer *ring, struct fd_ringmarker *start,
890 struct fd_ringmarker *end)
891 {
892 __OUT_IB(ring, true, start, end);
893 }
894
895 void
896 fd4_emit_init(struct pipe_context *pctx)
897 {
898 struct fd_context *ctx = fd_context(pctx);
899 ctx->emit_const = fd4_emit_const;
900 ctx->emit_const_bo = fd4_emit_const_bo;
901 ctx->emit_ib = fd4_emit_ib;
902 }