src/gallium/drivers/freedreno/a4xx/fd4_gmem.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "pipe/p_state.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_inlines.h"
  31 #include "util/format/u_format.h"
  32
  33 #include "freedreno_draw.h"
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd4_gmem.h"
  38 #include "fd4_context.h"
  39 #include "fd4_draw.h"
  40 #include "fd4_emit.h"
  41 #include "fd4_program.h"
  42 #include "fd4_format.h"
  43 #include "fd4_zsa.h"
  44
  45 static void
  46 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
  47                 struct pipe_surface **bufs, const uint32_t *bases,
  48                 uint32_t bin_w, bool decode_srgb)
  49 {
  50         enum a4xx_tile_mode tile_mode;
  51         unsigned i;
  52
  53         if (bin_w) {
  54                 tile_mode = 2;
  55         } else {
  56                 tile_mode = TILE4_LINEAR;
  57         }
  58
  59         for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
  60                 enum a4xx_color_fmt format = 0;
  61                 enum a3xx_color_swap swap = WZYX;
  62                 bool srgb = false;
  63                 struct fd_resource *rsc = NULL;
  64                 struct fdl_slice *slice = NULL;
  65                 uint32_t stride = 0;
  66                 uint32_t base = 0;
  67                 uint32_t offset = 0;
  68
  69                 if ((i < nr_bufs) && bufs[i]) {
  70                         struct pipe_surface *psurf = bufs[i];
  71                         enum pipe_format pformat = psurf->format;
  72
  73                         rsc = fd_resource(psurf->texture);
  74
  75                         /* In case we're drawing to Z32F_S8, the "color" actually goes to
  76                          * the stencil
  77                          */
  78                         if (rsc->stencil) {
  79                                 rsc = rsc->stencil;
  80                                 pformat = rsc->base.format;
  81                                 if (bases)
  82                                         bases++;
  83                         }
  84
  85                         slice = fd_resource_slice(rsc, psurf->u.tex.level);
  86                         format = fd4_pipe2color(pformat);
  87                         swap = fd4_pipe2swap(pformat);
  88
  89                         if (decode_srgb)
  90                                 srgb = util_format_is_srgb(pformat);
  91                         else
  92                                 pformat = util_format_linear(pformat);
  93
  94                         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
  95
  96                         offset = fd_resource_offset(rsc, psurf->u.tex.level,
  97                                         psurf->u.tex.first_layer);
  98
  99                         if (bin_w) {
 100                                 stride = bin_w << fdl_cpp_shift(&rsc->layout);
 101
 102                                 if (bases) {
 103                                         base = bases[i];
 104                                 }
 105                         } else {
 106                                 stride = slice->pitch * rsc->layout.cpp;
 107                         }
 108                 } else if ((i < nr_bufs) && bases) {
 109                         base = bases[i];
 110                 }
 111
 112                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
 113                 OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
 114                                 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
 115                                 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
 116                                 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
 117                                 COND(srgb, A4XX_RB_MRT_BUF_INFO_COLOR_SRGB));
 118                 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
 119                         OUT_RING(ring, base);
 120                         OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
 121                 } else {
 122                         OUT_RELOCW(ring, rsc->bo, offset, 0, 0);
 123                         /* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
 124                          * not sure if we need to skip it for bypass or
 125                          * not.
 126                          */
 127                         OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(0));
 128                 }
 129         }
 130 }
 131
 132 static bool
 133 use_hw_binning(struct fd_batch *batch)
 134 {
 135         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 136
 137         if ((gmem->maxpw * gmem->maxph) > 32)
 138                 return false;
 139
 140         if ((gmem->maxpw > 15) || (gmem->maxph > 15))
 141                 return false;
 142
 143         return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
 144 }
 145
 146 /* transfer from gmem to system memory (ie. normal RAM) */
 147
 148 static void
 149 emit_gmem2mem_surf(struct fd_batch *batch, bool stencil,
 150                 uint32_t base, struct pipe_surface *psurf)
 151 {
 152         struct fd_ringbuffer *ring = batch->gmem;
 153         struct fd_resource *rsc = fd_resource(psurf->texture);
 154         enum pipe_format pformat = psurf->format;
 155         struct fdl_slice *slice;
 156         uint32_t offset;
 157
 158         if (!rsc->valid)
 159                 return;
 160
 161         if (stencil) {
 162                 debug_assert(rsc->stencil);
 163                 rsc = rsc->stencil;
 164                 pformat = rsc->base.format;
 165         }
 166
 167         slice = fd_resource_slice(rsc, psurf->u.tex.level);
 168         offset = fd_resource_offset(rsc, psurf->u.tex.level,
 169                         psurf->u.tex.first_layer);
 170
 171         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
 172
 173         OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4);
 174         OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 175                         A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
 176                         A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
 177         OUT_RELOCW(ring, rsc->bo, offset, 0, 0);   /* RB_COPY_DEST_BASE */
 178         OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->layout.cpp));
 179         OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
 180                         A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(pformat)) |
 181                         A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 182                         A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
 183                         A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat)));
 184
 185         fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 186                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX4_SIZE_8_BIT, 0, 0, NULL);
 187 }
 188
 189 static void
 190 fd4_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
 191 {
 192         struct fd_context *ctx = batch->ctx;
 193         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 194         struct fd_ringbuffer *ring = batch->gmem;
 195         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 196         struct fd4_emit emit = {
 197                         .debug = &ctx->debug,
 198                         .vtx = &ctx->solid_vbuf_state,
 199                         .prog = &ctx->solid_prog,
 200                         .key = {
 201                                 .half_precision = true,
 202                         },
 203         };
 204
 205         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 206         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 207
 208         OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 209         OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 210                         A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 211                         A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 212                         A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 213                         A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 214                         A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 215                         A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 216                         A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 217         OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 218
 219         OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 220         OUT_RING(ring, 0xff000000 |
 221                         A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 222                         A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 223                         A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 224         OUT_RING(ring, 0xff000000 |
 225                         A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 226                         A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 227                         A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
 228
 229         OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
 230         OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 231
 232         fd_wfi(batch, ring);
 233
 234         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 235         OUT_RING(ring, 0x80000);      /* GRAS_CL_CLIP_CNTL */
 236
 237         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
 238         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width/2.0));
 239         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width/2.0));
 240         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height/2.0));
 241         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height/2.0));
 242         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 243         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
 244
 245         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 246         OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 247                         0xa);       /* XXX */
 248
 249         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 250         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 251                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 252                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 253                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 254
 255         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 256         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 257
 258         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 259         OUT_RING(ring, 0x00000002);
 260
 261         OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
 262         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
 263                         A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
 264         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 265                         A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 266
 267         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 268         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 269         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 270
 271         fd4_program_emit(ring, &emit, 0, NULL);
 272         fd4_emit_vertex_bufs(ring, &emit);
 273
 274         if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 275                 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
 276                 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH))
 277                         emit_gmem2mem_surf(batch, false, gmem->zsbuf_base[0], pfb->zsbuf);
 278                 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL))
 279                         emit_gmem2mem_surf(batch, true, gmem->zsbuf_base[1], pfb->zsbuf);
 280         }
 281
 282         if (batch->resolve & FD_BUFFER_COLOR) {
 283                 unsigned i;
 284                 for (i = 0; i < pfb->nr_cbufs; i++) {
 285                         if (!pfb->cbufs[i])
 286                                 continue;
 287                         if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
 288                                 continue;
 289                         emit_gmem2mem_surf(batch, false, gmem->cbuf_base[i], pfb->cbufs[i]);
 290                 }
 291         }
 292
 293         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 294         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 295                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 296                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 297                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 298 }
 299
 300 /* transfer from system memory to gmem */
 301
 302 static void
 303 emit_mem2gmem_surf(struct fd_batch *batch, const uint32_t *bases,
 304                 struct pipe_surface **bufs, uint32_t nr_bufs, uint32_t bin_w)
 305 {
 306         struct fd_ringbuffer *ring = batch->gmem;
 307         struct pipe_surface *zsbufs[2];
 308
 309         emit_mrt(ring, nr_bufs, bufs, bases, bin_w, false);
 310
 311         if (bufs[0] && (bufs[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
 312                 /* The gmem_restore_tex logic will put the first buffer's stencil
 313                  * as color. Supply it with the proper information to make that
 314                  * happen.
 315                  */
 316                 zsbufs[0] = zsbufs[1] = bufs[0];
 317                 bufs = zsbufs;
 318                 nr_bufs = 2;
 319         }
 320
 321         fd4_emit_gmem_restore_tex(ring, nr_bufs, bufs);
 322
 323         fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 324                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX4_SIZE_8_BIT, 0, 0, NULL);
 325 }
 326
 327 static void
 328 fd4_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
 329 {
 330         struct fd_context *ctx = batch->ctx;
 331         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 332         struct fd_ringbuffer *ring = batch->gmem;
 333         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 334         struct fd4_emit emit = {
 335                         .debug = &ctx->debug,
 336                         .vtx = &ctx->blit_vbuf_state,
 337                         .sprite_coord_enable = 1,
 338                         /* NOTE: They all use the same VP, this is for vtx bufs. */
 339                         .prog = &ctx->blit_prog[0],
 340                         .key = {
 341                                 .half_precision = fd_half_precision(pfb),
 342                         },
 343                         .no_decode_srgb = true,
 344         };
 345         unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
 346         float x0, y0, x1, y1;
 347         unsigned bin_w = tile->bin_w;
 348         unsigned bin_h = tile->bin_h;
 349         unsigned i;
 350
 351         /* write texture coordinates to vertexbuf: */
 352         x0 = ((float)tile->xoff) / ((float)pfb->width);
 353         x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
 354         y0 = ((float)tile->yoff) / ((float)pfb->height);
 355         y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 356
 357         OUT_PKT3(ring, CP_MEM_WRITE, 5);
 358         OUT_RELOCW(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
 359         OUT_RING(ring, fui(x0));
 360         OUT_RING(ring, fui(y0));
 361         OUT_RING(ring, fui(x1));
 362         OUT_RING(ring, fui(y1));
 363
 364         for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
 365                 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
 366
 367                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 368                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 369                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 370
 371                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
 372                 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 373                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 374                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 375                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 376                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 377                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 378         }
 379
 380         OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
 381         OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
 382                         A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
 383                         A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
 384                         A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
 385                         A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
 386                         A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
 387                         A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
 388                         A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
 389
 390         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 391         OUT_RING(ring, 0x8);          /* XXX RB_RENDER_CONTROL */
 392
 393         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 394         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
 395
 396         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 397         OUT_RING(ring, 0x280000);     /* XXX GRAS_CL_CLIP_CNTL */
 398
 399         OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
 400         OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
 401                         A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
 402
 403         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
 404         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w/2.0));
 405         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w/2.0));
 406         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h/2.0));
 407         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h/2.0));
 408         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 409         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
 410
 411         OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
 412         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
 413                         A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
 414         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 415                         A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 416
 417         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 418         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 419                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 420         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
 421                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
 422
 423         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 424         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 425                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
 426
 427         OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 428         OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 429                         A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 430                         A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 431                         A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 432                         A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
 433                         A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 434                         A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 435                         A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 436         OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 437
 438         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 439         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 440                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 441                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 442                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 443
 444         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 445         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
 446                         A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
 447
 448         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 449         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 450         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 451
 452         fd4_emit_vertex_bufs(ring, &emit);
 453
 454         /* for gmem pitch/base calculations, we need to use the non-
 455          * truncated tile sizes:
 456          */
 457         bin_w = gmem->bin_w;
 458         bin_h = gmem->bin_h;
 459
 460         if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
 461                 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
 462                 emit.fs = NULL;      /* frag shader changed so clear cache */
 463                 fd4_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
 464                 emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
 465         }
 466
 467         if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 468                 switch (pfb->zsbuf->format) {
 469                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 470                 case PIPE_FORMAT_Z32_FLOAT:
 471                         emit.prog = (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT) ?
 472                                         &ctx->blit_z : &ctx->blit_zs;
 473                         emit.key.half_precision = false;
 474
 475                         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 476                         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
 477                                         A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 478                                         A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS) |
 479                                         A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE);
 480
 481                         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 482                         OUT_RING(ring, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE);
 483
 484                         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 485                         OUT_RING(ring, 0x80000);   /* GRAS_CL_CLIP_CNTL */
 486
 487                         break;
 488                 default:
 489                         /* Non-float can use a regular color write. It's split over 8-bit
 490                          * components, so half precision is always sufficient.
 491                          */
 492                         emit.prog = &ctx->blit_prog[0];
 493                         emit.key.half_precision = true;
 494                         break;
 495                 }
 496                 emit.fs = NULL;      /* frag shader changed so clear cache */
 497                 fd4_program_emit(ring, &emit, 1, &pfb->zsbuf);
 498                 emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
 499         }
 500
 501         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 502         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 503                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 504                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 505
 506         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 507         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 508                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
 509                         0x00010000);  /* XXX */
 510 }
 511
 512 static void
 513 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
 514 {
 515         unsigned i;
 516         for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
 517                 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
 518                 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
 519         }
 520         util_dynarray_clear(&batch->draw_patches);
 521 }
 522
 523 /* for rendering directly to system memory: */
 524 static void
 525 fd4_emit_sysmem_prep(struct fd_batch *batch)
 526 {
 527         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 528         struct fd_ringbuffer *ring = batch->gmem;
 529
 530         fd4_emit_restore(batch, ring);
 531
 532         OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
 533         OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 534                         A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 535
 536         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
 537
 538         /* setup scissor/offset for current tile: */
 539         OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
 540         OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(0) |
 541                         A4XX_RB_BIN_OFFSET_Y(0));
 542
 543         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 544         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 545                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 546         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
 547                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
 548
 549         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 550         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(0) |
 551                         A4XX_RB_MODE_CONTROL_HEIGHT(0) |
 552                         0x00c00000);  /* XXX */
 553
 554         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 555         OUT_RING(ring, 0x8);
 556
 557         patch_draws(batch, IGNORE_VISIBILITY);
 558 }
 559
 560 static void
 561 update_vsc_pipe(struct fd_batch *batch)
 562 {
 563         struct fd_context *ctx = batch->ctx;
 564         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 565         struct fd4_context *fd4_ctx = fd4_context(ctx);
 566         struct fd_ringbuffer *ring = batch->gmem;
 567         int i;
 568
 569         OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
 570         OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
 571
 572         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
 573         for (i = 0; i < 8; i++) {
 574                 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
 575                 OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
 576                                 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
 577                                 A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
 578                                 A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
 579         }
 580
 581         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
 582         for (i = 0; i < 8; i++) {
 583                 if (!ctx->vsc_pipe_bo[i]) {
 584                         ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, 0x40000,
 585                                         DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
 586                 }
 587                 OUT_RELOCW(ring, ctx->vsc_pipe_bo[i], 0, 0, 0);       /* VSC_PIPE_DATA_ADDRESS[i] */
 588         }
 589
 590         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
 591         for (i = 0; i < 8; i++) {
 592                 OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
 593         }
 594 }
 595
 596 static void
 597 emit_binning_pass(struct fd_batch *batch)
 598 {
 599         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 600         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 601         struct fd_ringbuffer *ring = batch->gmem;
 602         int i;
 603
 604         uint32_t x1 = gmem->minx;
 605         uint32_t y1 = gmem->miny;
 606         uint32_t x2 = gmem->minx + gmem->width - 1;
 607         uint32_t y2 = gmem->miny + gmem->height - 1;
 608
 609         OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
 610         OUT_RING(ring, A4XX_PC_BINNING_COMMAND_BINNING_ENABLE);
 611
 612         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 613         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
 614                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 615                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 616                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 617
 618         OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
 619         OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 620                         A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 621
 622         /* setup scissor/offset for whole screen: */
 623         OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
 624         OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(x1) |
 625                         A4XX_RB_BIN_OFFSET_Y(y1));
 626
 627         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 628         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 629                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 630         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 631                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 632
 633         for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
 634                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 635                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
 636                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 637         }
 638
 639         /* emit IB to binning drawcmds: */
 640         fd4_emit_ib(ring, batch->binning);
 641
 642         fd_reset_wfi(batch);
 643         fd_wfi(batch, ring);
 644
 645         /* and then put stuff back the way it was: */
 646
 647         OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
 648         OUT_RING(ring, 0x00000000);
 649
 650         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 651         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 652                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 653                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 654                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 655
 656         fd_event_write(batch, ring, CACHE_FLUSH);
 657         fd_wfi(batch, ring);
 658 }
 659
 660 /* before first tile */
 661 static void
 662 fd4_emit_tile_init(struct fd_batch *batch)
 663 {
 664         struct fd_ringbuffer *ring = batch->gmem;
 665         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 666         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 667
 668         fd4_emit_restore(batch, ring);
 669
 670         OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
 671         OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 672                         A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 673
 674         update_vsc_pipe(batch);
 675
 676         fd_wfi(batch, ring);
 677         OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
 678         OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 679                         A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 680
 681         if (use_hw_binning(batch)) {
 682                 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 683                 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 684                                 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
 685
 686                 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 687                 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_BINNING_PASS |
 688                                 A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 689                                 0x8);
 690
 691                 /* emit hw binning pass: */
 692                 emit_binning_pass(batch);
 693
 694                 patch_draws(batch, USE_VISIBILITY);
 695         } else {
 696                 patch_draws(batch, IGNORE_VISIBILITY);
 697         }
 698
 699         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 700         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 701                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
 702                         A4XX_RB_MODE_CONTROL_ENABLE_GMEM);
 703 }
 704
 705 /* before mem2gmem */
 706 static void
 707 fd4_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
 708 {
 709         struct fd_ringbuffer *ring = batch->gmem;
 710         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 711         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 712
 713         if (pfb->zsbuf) {
 714                 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
 715                 uint32_t cpp = rsc->layout.cpp;
 716
 717                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
 718                 OUT_RING(ring, A4XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]) |
 719                                 A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb->zsbuf->format)));
 720                 OUT_RING(ring, A4XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
 721                 OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(cpp * gmem->bin_w));
 722
 723                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
 724                 if (rsc->stencil) {
 725                         OUT_RING(ring, A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL |
 726                                         A4XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
 727                         OUT_RING(ring, A4XX_RB_STENCIL_PITCH(rsc->stencil->layout.cpp * gmem->bin_w));
 728                 } else {
 729                         OUT_RING(ring, 0x00000000);
 730                         OUT_RING(ring, 0x00000000);
 731                 }
 732         } else {
 733                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
 734                 OUT_RING(ring, 0x00000000);
 735                 OUT_RING(ring, 0x00000000);
 736                 OUT_RING(ring, 0x00000000);
 737
 738                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
 739                 OUT_RING(ring, 0);            /* RB_STENCIL_INFO */
 740                 OUT_RING(ring, 0);            /* RB_STENCIL_PITCH */
 741         }
 742
 743         OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
 744         if (pfb->zsbuf) {
 745                 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
 746                                 fd4_pipe2depth(pfb->zsbuf->format)));
 747         } else {
 748                 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
 749         }
 750 }
 751
 752 /* before IB to rendering cmds: */
 753 static void
 754 fd4_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
 755 {
 756         struct fd_context *ctx = batch->ctx;
 757         struct fd4_context *fd4_ctx = fd4_context(ctx);
 758         struct fd_ringbuffer *ring = batch->gmem;
 759         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 760         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 761
 762         uint32_t x1 = tile->xoff;
 763         uint32_t y1 = tile->yoff;
 764         uint32_t x2 = tile->xoff + tile->bin_w - 1;
 765         uint32_t y2 = tile->yoff + tile->bin_h - 1;
 766
 767         if (use_hw_binning(batch)) {
 768                 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
 769                 struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
 770
 771                 assert(pipe->w && pipe->h);
 772
 773                 fd_event_write(batch, ring, HLSQ_FLUSH);
 774                 fd_wfi(batch, ring);
 775
 776                 OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
 777                 OUT_RING(ring, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
 778                                 A4XX_PC_VSTREAM_CONTROL_N(tile->n));
 779
 780                 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
 781                 OUT_RELOCW(ring, pipe_bo, 0, 0, 0);     /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
 782                 OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
 783                                 (tile->p * 4), 0, 0);
 784         } else {
 785                 OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
 786                 OUT_RING(ring, 0x00000000);
 787         }
 788
 789         OUT_PKT3(ring, CP_SET_BIN, 3);
 790         OUT_RING(ring, 0x00000000);
 791         OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
 792         OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
 793
 794         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
 795
 796         /* setup scissor/offset for current tile: */
 797         OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
 798         OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(tile->xoff) |
 799                         A4XX_RB_BIN_OFFSET_Y(tile->yoff));
 800
 801         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 802         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 803                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 804         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 805                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 806
 807         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 808         OUT_RING(ring, 0x8);
 809 }
 810
 811 void
 812 fd4_gmem_init(struct pipe_context *pctx)
 813 {
 814         struct fd_context *ctx = fd_context(pctx);
 815
 816         ctx->emit_sysmem_prep = fd4_emit_sysmem_prep;
 817         ctx->emit_tile_init = fd4_emit_tile_init;
 818         ctx->emit_tile_prep = fd4_emit_tile_prep;
 819         ctx->emit_tile_mem2gmem = fd4_emit_tile_mem2gmem;
 820         ctx->emit_tile_renderprep = fd4_emit_tile_renderprep;
 821         ctx->emit_tile_gmem2mem = fd4_emit_tile_gmem2mem;
 822 }