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freedreno: OUT_RELOC vs OUT_RELOCW fixes
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
38
39 #include "fd4_gmem.h"
40 #include "fd4_context.h"
41 #include "fd4_draw.h"
42 #include "fd4_emit.h"
43 #include "fd4_program.h"
44 #include "fd4_format.h"
45 #include "fd4_zsa.h"
46
47 static void
48 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
49 struct pipe_surface **bufs, uint32_t *bases,
50 uint32_t bin_w, bool decode_srgb)
51 {
52 enum a4xx_tile_mode tile_mode;
53 unsigned i;
54
55 if (bin_w) {
56 tile_mode = 2;
57 } else {
58 tile_mode = TILE4_LINEAR;
59 }
60
61 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
62 enum a4xx_color_fmt format = 0;
63 enum a3xx_color_swap swap = WZYX;
64 bool srgb = false;
65 struct fd_resource *rsc = NULL;
66 struct fd_resource_slice *slice = NULL;
67 uint32_t stride = 0;
68 uint32_t base = 0;
69 uint32_t offset = 0;
70
71 if ((i < nr_bufs) && bufs[i]) {
72 struct pipe_surface *psurf = bufs[i];
73 enum pipe_format pformat = psurf->format;
74
75 rsc = fd_resource(psurf->texture);
76
77 /* In case we're drawing to Z32F_S8, the "color" actually goes to
78 * the stencil
79 */
80 if (rsc->stencil) {
81 rsc = rsc->stencil;
82 pformat = rsc->base.b.format;
83 bases++;
84 }
85
86 slice = fd_resource_slice(rsc, psurf->u.tex.level);
87 format = fd4_pipe2color(pformat);
88 swap = fd4_pipe2swap(pformat);
89
90 if (decode_srgb)
91 srgb = util_format_is_srgb(pformat);
92 else
93 pformat = util_format_linear(pformat);
94
95 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
96
97 offset = fd_resource_offset(rsc, psurf->u.tex.level,
98 psurf->u.tex.first_layer);
99
100 if (bin_w) {
101 stride = bin_w * rsc->cpp;
102
103 if (bases) {
104 base = bases[i];
105 }
106 } else {
107 stride = slice->pitch * rsc->cpp;
108 }
109 } else if ((i < nr_bufs) && bases) {
110 base = bases[i];
111 }
112
113 OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
114 OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
115 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
116 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
117 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
118 COND(srgb, A4XX_RB_MRT_BUF_INFO_COLOR_SRGB));
119 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
120 OUT_RING(ring, base);
121 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
122 } else {
123 OUT_RELOCW(ring, rsc->bo, offset, 0, 0);
124 /* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
125 * not sure if we need to skip it for bypass or
126 * not.
127 */
128 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(0));
129 }
130 }
131 }
132
133 static bool
134 use_hw_binning(struct fd_context *ctx)
135 {
136 struct fd_gmem_stateobj *gmem = &ctx->gmem;
137 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
138
139 /* this seems to be a hw bug.. but this hack fixes piglit fbo-maxsize: */
140 if ((pfb->width > 4096) && (pfb->height > 4096))
141 return false;
142
143 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
144 }
145
146 /* transfer from gmem to system memory (ie. normal RAM) */
147
148 static void
149 emit_gmem2mem_surf(struct fd_context *ctx, bool stencil,
150 uint32_t base, struct pipe_surface *psurf)
151 {
152 struct fd_ringbuffer *ring = ctx->ring;
153 struct fd_resource *rsc = fd_resource(psurf->texture);
154 enum pipe_format pformat = psurf->format;
155 struct fd_resource_slice *slice;
156 uint32_t offset;
157
158 if (stencil) {
159 debug_assert(rsc->stencil);
160 rsc = rsc->stencil;
161 pformat = rsc->base.b.format;
162 }
163
164 slice = &rsc->slices[psurf->u.tex.level];
165 offset = fd_resource_offset(rsc, psurf->u.tex.level,
166 psurf->u.tex.first_layer);
167
168 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
169
170 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4);
171 OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
172 A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
173 A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
174 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_COPY_DEST_BASE */
175 OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
176 OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
177 A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(pformat)) |
178 A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
179 A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
180 A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat)));
181
182 fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
183 DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
184 }
185
186 static void
187 fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
188 {
189 struct fd4_context *fd4_ctx = fd4_context(ctx);
190 struct fd_gmem_stateobj *gmem = &ctx->gmem;
191 struct fd_ringbuffer *ring = ctx->ring;
192 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
193 struct fd4_emit emit = {
194 .vtx = &fd4_ctx->solid_vbuf_state,
195 .prog = &ctx->solid_prog,
196 .key = {
197 .half_precision = true,
198 },
199 };
200
201 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
202 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
203
204 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
205 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
206 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
207 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
208 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
209 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
210 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
211 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
212 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
213 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
214
215 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
216 OUT_RING(ring, 0xff000000 |
217 A4XX_RB_STENCILREFMASK_STENCILREF(0) |
218 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
219 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
220 OUT_RING(ring, 0xff000000 |
221 A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
222 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
223 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
224
225 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
226 OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
227
228 fd_wfi(ctx, ring);
229
230 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
231 OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
232
233 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
234 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width/2.0));
235 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width/2.0));
236 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height/2.0));
237 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height/2.0));
238 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
239 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
240
241 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
242 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
243 0xa); /* XXX */
244
245 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
246 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
247 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
248 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
249 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
250
251 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
252 OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
253
254 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
255 OUT_RING(ring, 0x00000002);
256
257 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
258 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
259 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
260 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
261 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
262
263 OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
264 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
265 OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
266
267 fd4_program_emit(ring, &emit, 0, NULL);
268 fd4_emit_vertex_bufs(ring, &emit);
269
270 if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
271 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
272 if (!rsc->stencil || (ctx->resolve & FD_BUFFER_DEPTH))
273 emit_gmem2mem_surf(ctx, false, ctx->gmem.zsbuf_base[0], pfb->zsbuf);
274 if (rsc->stencil && (ctx->resolve & FD_BUFFER_STENCIL))
275 emit_gmem2mem_surf(ctx, true, ctx->gmem.zsbuf_base[1], pfb->zsbuf);
276 }
277
278 if (ctx->resolve & FD_BUFFER_COLOR) {
279 unsigned i;
280 for (i = 0; i < pfb->nr_cbufs; i++) {
281 if (!pfb->cbufs[i])
282 continue;
283 if (!(ctx->resolve & (PIPE_CLEAR_COLOR0 << i)))
284 continue;
285 emit_gmem2mem_surf(ctx, false, gmem->cbuf_base[i], pfb->cbufs[i]);
286 }
287 }
288
289 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
290 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
291 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
292 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
293 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
294 }
295
296 /* transfer from system memory to gmem */
297
298 static void
299 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t *bases,
300 struct pipe_surface **bufs, uint32_t nr_bufs, uint32_t bin_w)
301 {
302 struct fd_ringbuffer *ring = ctx->ring;
303 struct pipe_surface *zsbufs[2];
304
305 emit_mrt(ring, nr_bufs, bufs, bases, bin_w, false);
306
307 if (bufs[0] && (bufs[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
308 /* The gmem_restore_tex logic will put the first buffer's stencil
309 * as color. Supply it with the proper information to make that
310 * happen.
311 */
312 zsbufs[0] = zsbufs[1] = bufs[0];
313 bufs = zsbufs;
314 nr_bufs = 2;
315 }
316
317 fd4_emit_gmem_restore_tex(ring, nr_bufs, bufs);
318
319 fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
320 DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
321 }
322
323 static void
324 fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
325 {
326 struct fd4_context *fd4_ctx = fd4_context(ctx);
327 struct fd_gmem_stateobj *gmem = &ctx->gmem;
328 struct fd_ringbuffer *ring = ctx->ring;
329 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
330 struct fd4_emit emit = {
331 .vtx = &fd4_ctx->blit_vbuf_state,
332 .sprite_coord_enable = 1,
333 /* NOTE: They all use the same VP, this is for vtx bufs. */
334 .prog = &ctx->blit_prog[0],
335 .key = {
336 .half_precision = fd_half_precision(pfb),
337 },
338 .no_decode_srgb = true,
339 };
340 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
341 float x0, y0, x1, y1;
342 unsigned bin_w = tile->bin_w;
343 unsigned bin_h = tile->bin_h;
344 unsigned i;
345
346 /* write texture coordinates to vertexbuf: */
347 x0 = ((float)tile->xoff) / ((float)pfb->width);
348 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
349 y0 = ((float)tile->yoff) / ((float)pfb->height);
350 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
351
352 OUT_PKT3(ring, CP_MEM_WRITE, 5);
353 OUT_RELOCW(ring, fd_resource(fd4_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
354 OUT_RING(ring, fui(x0));
355 OUT_RING(ring, fui(y0));
356 OUT_RING(ring, fui(x1));
357 OUT_RING(ring, fui(y1));
358
359 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
360 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
361
362 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
363 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
364 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
365
366 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
367 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
368 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
369 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
370 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
371 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
372 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
373 }
374
375 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
376 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
377 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
378 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
379 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
380 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
381 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
382 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
383 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
384
385 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
386 OUT_RING(ring, 0x8); /* XXX RB_RENDER_CONTROL */
387
388 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
389 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
390
391 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
392 OUT_RING(ring, 0x280000); /* XXX GRAS_CL_CLIP_CNTL */
393
394 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
395 OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
396 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
397
398 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
399 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w/2.0));
400 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w/2.0));
401 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h/2.0));
402 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h/2.0));
403 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
404 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
405
406 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
407 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
408 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
409 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
410 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
411
412 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
413 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
414 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
415 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
416 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
417
418 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
419 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
420 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
421
422 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
423 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
424 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
425 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
426 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
427 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
428 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
429 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
430 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
431 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
432
433 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
434 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
435 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
436 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
437 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
438
439 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
440 OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
441 A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
442
443 OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
444 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
445 OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
446
447 fd4_emit_vertex_bufs(ring, &emit);
448
449 /* for gmem pitch/base calculations, we need to use the non-
450 * truncated tile sizes:
451 */
452 bin_w = gmem->bin_w;
453 bin_h = gmem->bin_h;
454
455 if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR)) {
456 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
457 emit.fp = NULL; /* frag shader changed so clear cache */
458 fd4_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
459 emit_mem2gmem_surf(ctx, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
460 }
461
462 if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
463 switch (pfb->zsbuf->format) {
464 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
465 case PIPE_FORMAT_Z32_FLOAT:
466 emit.prog = (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT) ?
467 &ctx->blit_z : &ctx->blit_zs;
468 emit.key.half_precision = false;
469
470 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
471 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
472 A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
473 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS) |
474 A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE);
475
476 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
477 OUT_RING(ring, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE);
478
479 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
480 OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
481
482 break;
483 default:
484 /* Non-float can use a regular color write. It's split over 8-bit
485 * components, so half precision is always sufficient.
486 */
487 emit.prog = &ctx->blit_prog[0];
488 emit.key.half_precision = true;
489 break;
490 }
491 emit.fp = NULL; /* frag shader changed so clear cache */
492 fd4_program_emit(ring, &emit, 1, &pfb->zsbuf);
493 emit_mem2gmem_surf(ctx, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
494 }
495
496 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
497 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
498 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
499 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
500
501 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
502 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
503 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
504 0x00010000); /* XXX */
505 }
506
507 static void
508 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
509 {
510 unsigned i;
511 for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
512 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
513 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
514 }
515 util_dynarray_resize(&ctx->draw_patches, 0);
516 }
517
518 /* for rendering directly to system memory: */
519 static void
520 fd4_emit_sysmem_prep(struct fd_context *ctx)
521 {
522 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
523 struct fd_ringbuffer *ring = ctx->ring;
524
525 fd4_emit_restore(ctx);
526
527 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
528 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
529 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
530
531 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
532
533 /* setup scissor/offset for current tile: */
534 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
535 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(0) |
536 A4XX_RB_BIN_OFFSET_Y(0));
537
538 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
539 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
540 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
541 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
542 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
543
544 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
545 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(0) |
546 A4XX_RB_MODE_CONTROL_HEIGHT(0) |
547 0x00c00000); /* XXX */
548
549 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
550 OUT_RING(ring, 0x8);
551
552 patch_draws(ctx, IGNORE_VISIBILITY);
553 }
554
555 static void
556 update_vsc_pipe(struct fd_context *ctx)
557 {
558 struct fd4_context *fd4_ctx = fd4_context(ctx);
559 struct fd_ringbuffer *ring = ctx->ring;
560 int i;
561
562 OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
563 OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
564
565 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
566 for (i = 0; i < 8; i++) {
567 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
568 OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
569 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
570 A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
571 A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
572 }
573
574 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
575 for (i = 0; i < 8; i++) {
576 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
577 if (!pipe->bo) {
578 pipe->bo = fd_bo_new(ctx->dev, 0x40000,
579 DRM_FREEDRENO_GEM_TYPE_KMEM);
580 }
581 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
582 }
583
584 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
585 for (i = 0; i < 8; i++) {
586 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
587 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
588 }
589 }
590
591 static void
592 emit_binning_pass(struct fd_context *ctx)
593 {
594 struct fd_gmem_stateobj *gmem = &ctx->gmem;
595 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
596 struct fd_ringbuffer *ring = ctx->ring;
597 int i;
598
599 uint32_t x1 = gmem->minx;
600 uint32_t y1 = gmem->miny;
601 uint32_t x2 = gmem->minx + gmem->width - 1;
602 uint32_t y2 = gmem->miny + gmem->height - 1;
603
604 OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
605 OUT_RING(ring, A4XX_PC_BINNING_COMMAND_BINNING_ENABLE);
606
607 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
608 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
609 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
610 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
611 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
612
613 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
614 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
615 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
616
617 /* setup scissor/offset for whole screen: */
618 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
619 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(x1) |
620 A4XX_RB_BIN_OFFSET_Y(y1));
621
622 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
623 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
624 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
625 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
626 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
627
628 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
629 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
630 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
631 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
632 }
633
634 /* emit IB to binning drawcmds: */
635 ctx->emit_ib(ring, ctx->binning_start, ctx->binning_end);
636
637 fd_reset_wfi(ctx);
638 fd_wfi(ctx, ring);
639
640 /* and then put stuff back the way it was: */
641
642 OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
643 OUT_RING(ring, 0x00000000);
644
645 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
646 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
647 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
648 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
649 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
650
651 fd_event_write(ctx, ring, CACHE_FLUSH);
652 fd_wfi(ctx, ring);
653 }
654
655 /* before first tile */
656 static void
657 fd4_emit_tile_init(struct fd_context *ctx)
658 {
659 struct fd_ringbuffer *ring = ctx->ring;
660 struct fd_gmem_stateobj *gmem = &ctx->gmem;
661
662 fd4_emit_restore(ctx);
663
664 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
665 OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
666 A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
667
668 update_vsc_pipe(ctx);
669
670 if (use_hw_binning(ctx)) {
671 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
672 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
673 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
674
675 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
676 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_BINNING_PASS |
677 A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
678 0x8);
679
680 /* emit hw binning pass: */
681 emit_binning_pass(ctx);
682
683 patch_draws(ctx, USE_VISIBILITY);
684 } else {
685 patch_draws(ctx, IGNORE_VISIBILITY);
686 }
687
688 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
689 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
690 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
691 A4XX_RB_MODE_CONTROL_ENABLE_GMEM);
692 }
693
694 /* before mem2gmem */
695 static void
696 fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
697 {
698 struct fd_ringbuffer *ring = ctx->ring;
699 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
700 struct fd_gmem_stateobj *gmem = &ctx->gmem;
701
702 if (pfb->zsbuf) {
703 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
704 uint32_t cpp = rsc->cpp;
705
706 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
707 OUT_RING(ring, A4XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]) |
708 A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb->zsbuf->format)));
709 OUT_RING(ring, A4XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
710 OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(cpp * gmem->bin_w));
711
712 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
713 if (rsc->stencil) {
714 OUT_RING(ring, A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL |
715 A4XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
716 OUT_RING(ring, A4XX_RB_STENCIL_PITCH(rsc->stencil->cpp * gmem->bin_w));
717 } else {
718 OUT_RING(ring, 0x00000000);
719 OUT_RING(ring, 0x00000000);
720 }
721 } else {
722 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
723 OUT_RING(ring, 0x00000000);
724 OUT_RING(ring, 0x00000000);
725 OUT_RING(ring, 0x00000000);
726
727 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
728 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
729 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
730 }
731
732 OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
733 if (pfb->zsbuf) {
734 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
735 fd4_pipe2depth(pfb->zsbuf->format)));
736 } else {
737 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
738 }
739
740 if (ctx->needs_rb_fbd) {
741 fd_wfi(ctx, ring);
742 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
743 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
744 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
745 ctx->needs_rb_fbd = false;
746 }
747 }
748
749 /* before IB to rendering cmds: */
750 static void
751 fd4_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
752 {
753 struct fd4_context *fd4_ctx = fd4_context(ctx);
754 struct fd_ringbuffer *ring = ctx->ring;
755 struct fd_gmem_stateobj *gmem = &ctx->gmem;
756 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
757
758 uint32_t x1 = tile->xoff;
759 uint32_t y1 = tile->yoff;
760 uint32_t x2 = tile->xoff + tile->bin_w - 1;
761 uint32_t y2 = tile->yoff + tile->bin_h - 1;
762
763 if (use_hw_binning(ctx)) {
764 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
765
766 assert(pipe->w * pipe->h);
767
768 fd_event_write(ctx, ring, HLSQ_FLUSH);
769 fd_wfi(ctx, ring);
770
771 OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
772 OUT_RING(ring, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
773 A4XX_PC_VSTREAM_CONTROL_N(tile->n));
774
775 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
776 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
777 OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
778 (tile->p * 4), 0, 0);
779 } else {
780 OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
781 OUT_RING(ring, 0x00000000);
782 }
783
784 OUT_PKT3(ring, CP_SET_BIN, 3);
785 OUT_RING(ring, 0x00000000);
786 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
787 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
788
789 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
790
791 /* setup scissor/offset for current tile: */
792 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
793 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(tile->xoff) |
794 A4XX_RB_BIN_OFFSET_Y(tile->yoff));
795
796 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
797 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
798 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
799 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
800 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
801
802 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
803 OUT_RING(ring, 0x8);
804 }
805
806 void
807 fd4_gmem_init(struct pipe_context *pctx)
808 {
809 struct fd_context *ctx = fd_context(pctx);
810
811 ctx->emit_sysmem_prep = fd4_emit_sysmem_prep;
812 ctx->emit_tile_init = fd4_emit_tile_init;
813 ctx->emit_tile_prep = fd4_emit_tile_prep;
814 ctx->emit_tile_mem2gmem = fd4_emit_tile_mem2gmem;
815 ctx->emit_tile_renderprep = fd4_emit_tile_renderprep;
816 ctx->emit_tile_gmem2mem = fd4_emit_tile_gmem2mem;
817 }