src/gallium/drivers/freedreno/a4xx/fd4_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_draw.h"
  36 #include "freedreno_state.h"
  37 #include "freedreno_resource.h"
  38
  39 #include "fd4_gmem.h"
  40 #include "fd4_context.h"
  41 #include "fd4_draw.h"
  42 #include "fd4_emit.h"
  43 #include "fd4_program.h"
  44 #include "fd4_format.h"
  45 #include "fd4_zsa.h"
  46
  47 static void
  48 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
  49                 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w)
  50 {
  51         enum a4xx_tile_mode tile_mode;
  52         unsigned i;
  53
  54         if (bin_w) {
  55                 tile_mode = 2;
  56         } else {
  57                 tile_mode = TILE4_LINEAR;
  58         }
  59
  60         for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
  61                 enum a4xx_color_fmt format = 0;
  62                 enum a3xx_color_swap swap = WZYX;
  63                 struct fd_resource *rsc = NULL;
  64                 struct fd_resource_slice *slice = NULL;
  65                 uint32_t stride = 0;
  66                 uint32_t base = 0;
  67                 uint32_t offset = 0;
  68
  69                 if ((i < nr_bufs) && bufs[i]) {
  70                         struct pipe_surface *psurf = bufs[i];
  71
  72                         rsc = fd_resource(psurf->texture);
  73                         slice = fd_resource_slice(rsc, psurf->u.tex.level);
  74                         format = fd4_pipe2color(psurf->format);
  75                         swap = fd4_pipe2swap(psurf->format);
  76
  77                         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
  78
  79                         offset = fd_resource_offset(rsc, psurf->u.tex.level,
  80                                         psurf->u.tex.first_layer);
  81
  82                         if (bin_w) {
  83                                 stride = bin_w * rsc->cpp;
  84
  85                                 if (bases) {
  86                                         base = bases[i];
  87                                 }
  88                         } else {
  89                                 stride = slice->pitch * rsc->cpp;
  90                         }
  91                 } else if ((i < nr_bufs) && bases) {
  92                         base = bases[i];
  93                 }
  94
  95                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
  96                 OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
  97                                 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
  98                                 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
  99                                 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
 100                 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
 101                         OUT_RING(ring, base);
 102                         OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
 103                 } else {
 104                         OUT_RELOCW(ring, rsc->bo, offset, 0, 0);
 105                         /* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
 106                          * not sure if we need to skip it for bypass or
 107                          * not.
 108                          */
 109                         OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(0));
 110                 }
 111         }
 112 }
 113
 114 /* transfer from gmem to system memory (ie. normal RAM) */
 115
 116 static void
 117 emit_gmem2mem_surf(struct fd_context *ctx,
 118                 uint32_t base, struct pipe_surface *psurf)
 119 {
 120         struct fd_ringbuffer *ring = ctx->ring;
 121         struct fd_resource *rsc = fd_resource(psurf->texture);
 122         struct fd_resource_slice *slice = &rsc->slices[psurf->u.tex.level];
 123         uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
 124                         psurf->u.tex.first_layer);
 125
 126         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
 127
 128         OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4);
 129         OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 130                         A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
 131                         A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
 132         OUT_RELOCW(ring, rsc->bo, offset, 0, 0);   /* RB_COPY_DEST_BASE */
 133         OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
 134         OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
 135                         A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(psurf->format)) |
 136                         A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 137                         A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
 138                         A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(psurf->format)));
 139
 140         fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 141                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 142 }
 143
 144 static void
 145 fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 146 {
 147         struct fd4_context *fd4_ctx = fd4_context(ctx);
 148         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 149         struct fd_ringbuffer *ring = ctx->ring;
 150         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 151         struct fd4_emit emit = {
 152                         .vtx = &fd4_ctx->solid_vbuf_state,
 153                         .prog = &ctx->solid_prog,
 154                         .key = {
 155                                 .half_precision = true,
 156                         },
 157         };
 158
 159         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 160         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 161
 162         OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 163         OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 164                         A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 165                         A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 166                         A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 167                         A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 168                         A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 169                         A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 170                         A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 171         OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 172
 173         OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 174         OUT_RING(ring, 0xff000000 |
 175                         A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 176                         A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 177                         A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 178         OUT_RING(ring, 0xff000000 |
 179                         A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 180                         A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 181                         A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
 182
 183         OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
 184         OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 185
 186         fd_wfi(ctx, ring);
 187
 188         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 189         OUT_RING(ring, 0x80000);      /* GRAS_CL_CLIP_CNTL */
 190
 191         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
 192         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width/2.0));
 193         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width/2.0));
 194         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height/2.0));
 195         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height/2.0));
 196         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 197         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
 198
 199         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 200         OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 201                         0xa);       /* XXX */
 202
 203         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 204         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 205                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 206                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 207                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 208
 209         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 210         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 211
 212         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 213         OUT_RING(ring, 0x00000002);
 214
 215         OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
 216         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
 217                         A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
 218         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 219                         A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 220
 221         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 222         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 223         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 224
 225         fd4_program_emit(ring, &emit, 0, NULL);
 226         fd4_emit_vertex_bufs(ring, &emit);
 227
 228         if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 229                 emit_gmem2mem_surf(ctx, gmem->zsbuf_base[0], pfb->zsbuf);
 230         }
 231
 232         if (ctx->resolve & FD_BUFFER_COLOR) {
 233                 unsigned i;
 234                 for (i = 0; i < pfb->nr_cbufs; i++) {
 235                         if (!pfb->cbufs[i])
 236                                 continue;
 237                         if (!(ctx->resolve & (PIPE_CLEAR_COLOR0 << i)))
 238                                 continue;
 239                         emit_gmem2mem_surf(ctx, gmem->cbuf_base[i], pfb->cbufs[i]);
 240                 }
 241         }
 242
 243         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 244         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 245                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 246                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 247                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 248 }
 249
 250 /* transfer from system memory to gmem */
 251
 252 static void
 253 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t *bases,
 254                 struct pipe_surface **bufs, uint32_t nr_bufs, uint32_t bin_w)
 255 {
 256         struct fd_ringbuffer *ring = ctx->ring;
 257
 258         emit_mrt(ring, nr_bufs, bufs, bases, bin_w);
 259
 260         fd4_emit_gmem_restore_tex(ring, nr_bufs, bufs);
 261
 262         fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 263                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 264 }
 265
 266 static void
 267 fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 268 {
 269         struct fd4_context *fd4_ctx = fd4_context(ctx);
 270         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 271         struct fd_ringbuffer *ring = ctx->ring;
 272         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 273         struct fd4_emit emit = {
 274                         .vtx = &fd4_ctx->blit_vbuf_state,
 275                         /* NOTE: They all use the same VP, this is for vtx bufs. */
 276                         .prog = &ctx->blit_prog[0],
 277                         .key = {
 278                                 .half_precision = fd_half_precision(pfb),
 279                         },
 280         };
 281         unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
 282         float x0, y0, x1, y1;
 283         unsigned bin_w = tile->bin_w;
 284         unsigned bin_h = tile->bin_h;
 285         unsigned i;
 286
 287         /* write texture coordinates to vertexbuf: */
 288         x0 = ((float)tile->xoff) / ((float)pfb->width);
 289         x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
 290         y0 = ((float)tile->yoff) / ((float)pfb->height);
 291         y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 292
 293         OUT_PKT3(ring, CP_MEM_WRITE, 5);
 294         OUT_RELOCW(ring, fd_resource(fd4_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
 295         OUT_RING(ring, fui(x0));
 296         OUT_RING(ring, fui(y0));
 297         OUT_RING(ring, fui(x1));
 298         OUT_RING(ring, fui(y1));
 299
 300         for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
 301                 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
 302
 303                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 304                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR |
 305                                 A4XX_RB_MRT_CONTROL_B11 |
 306                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 307
 308                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
 309                 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 310                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 311                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 312                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 313                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 314                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 315         }
 316
 317         OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
 318         OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
 319                         A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
 320                         A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
 321                         A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
 322                         A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
 323                         A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
 324                         A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
 325                         A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
 326
 327         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 328         OUT_RING(ring, 0x8);          /* XXX RB_RENDER_CONTROL */
 329
 330         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 331         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
 332
 333         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 334         OUT_RING(ring, 0x280000);     /* XXX GRAS_CL_CLIP_CNTL */
 335
 336         OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
 337         OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
 338                         A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
 339
 340         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
 341         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w/2.0));
 342         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w/2.0));
 343         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h/2.0));
 344         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h/2.0));
 345         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 346         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
 347
 348         OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
 349         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
 350                         A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
 351         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 352                         A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 353
 354         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 355         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 356                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 357         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
 358                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
 359
 360         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 361         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 362                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
 363
 364         OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 365         OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 366                         A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 367                         A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 368                         A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 369                         A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
 370                         A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 371                         A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 372                         A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 373         OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 374
 375         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 376         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 377                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 378                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 379                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 380
 381         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 382         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
 383                         A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
 384
 385         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 386         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 387         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 388
 389         fd4_emit_vertex_bufs(ring, &emit);
 390
 391         /* for gmem pitch/base calculations, we need to use the non-
 392          * truncated tile sizes:
 393          */
 394         bin_w = gmem->bin_w;
 395         bin_h = gmem->bin_h;
 396
 397         if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 398                 emit.prog = &ctx->blit_prog[0];
 399                 fd4_program_emit(ring, &emit, 1, &pfb->zsbuf);
 400                 emit_mem2gmem_surf(ctx, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
 401         }
 402
 403         if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR)) {
 404                 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
 405                 fd4_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
 406                 emit_mem2gmem_surf(ctx, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
 407         }
 408
 409         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 410         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 411                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 412                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 413
 414         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 415         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 416                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
 417                         0x00010000);  /* XXX */
 418 }
 419
 420 static void
 421 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
 422 {
 423         unsigned i;
 424         for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
 425                 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
 426                 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
 427         }
 428         util_dynarray_resize(&ctx->draw_patches, 0);
 429 }
 430
 431 static void
 432 patch_rbrc(struct fd_context *ctx, uint32_t val)
 433 {
 434         struct fd4_context *fd4_ctx = fd4_context(ctx);
 435         unsigned i;
 436         for (i = 0; i < fd_patch_num_elements(&fd4_ctx->rbrc_patches); i++) {
 437                 struct fd_cs_patch *patch = fd_patch_element(&fd4_ctx->rbrc_patches, i);
 438                 *patch->cs = patch->val | val;
 439         }
 440         util_dynarray_resize(&fd4_ctx->rbrc_patches, 0);
 441 }
 442
 443 /* for rendering directly to system memory: */
 444 static void
 445 fd4_emit_sysmem_prep(struct fd_context *ctx)
 446 {
 447         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 448         struct fd_ringbuffer *ring = ctx->ring;
 449
 450         fd4_emit_restore(ctx);
 451
 452         OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
 453         OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 454                         A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 455
 456         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0);
 457
 458         /* setup scissor/offset for current tile: */
 459         OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
 460         OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(0) |
 461                         A4XX_RB_BIN_OFFSET_Y(0));
 462
 463         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 464         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 465                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 466         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
 467                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
 468
 469         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 470         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(0) |
 471                         A4XX_RB_MODE_CONTROL_HEIGHT(0) |
 472                         0x00c00000);  /* XXX */
 473
 474         patch_draws(ctx, IGNORE_VISIBILITY);
 475         patch_rbrc(ctx, 0);  // XXX
 476 }
 477
 478 static void
 479 update_vsc_pipe(struct fd_context *ctx)
 480 {
 481         struct fd4_context *fd4_ctx = fd4_context(ctx);
 482         struct fd_ringbuffer *ring = ctx->ring;
 483         int i;
 484
 485         OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
 486         OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
 487
 488         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
 489         for (i = 0; i < 8; i++) {
 490                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 491                 OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
 492                                 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
 493                                 A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
 494                                 A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
 495         }
 496
 497         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
 498         for (i = 0; i < 8; i++) {
 499                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 500                 if (!pipe->bo) {
 501                         pipe->bo = fd_bo_new(ctx->dev, 0x40000,
 502                                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 503                 }
 504                 OUT_RELOCW(ring, pipe->bo, 0, 0, 0);       /* VSC_PIPE_DATA_ADDRESS[i] */
 505         }
 506
 507         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
 508         for (i = 0; i < 8; i++) {
 509                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 510                 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
 511         }
 512 }
 513
 514 /* before first tile */
 515 static void
 516 fd4_emit_tile_init(struct fd_context *ctx)
 517 {
 518         struct fd_ringbuffer *ring = ctx->ring;
 519         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 520         uint32_t rb_render_control;
 521
 522         fd4_emit_restore(ctx);
 523
 524         OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
 525         OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 526                         A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 527
 528         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 529         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 530                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
 531                         0x00010000);  /* XXX */
 532
 533         update_vsc_pipe(ctx);
 534         patch_draws(ctx, IGNORE_VISIBILITY);
 535
 536         rb_render_control = 0; // XXX or BINNING_PASS.. but maybe we can emit only from gmem
 537         patch_rbrc(ctx, rb_render_control);
 538 }
 539
 540 /* before mem2gmem */
 541 static void
 542 fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
 543 {
 544         struct fd_ringbuffer *ring = ctx->ring;
 545         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 546         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 547         uint32_t reg;
 548
 549         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
 550         reg = A4XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
 551         if (pfb->zsbuf) {
 552                 reg |= A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb->zsbuf->format));
 553         }
 554         OUT_RING(ring, reg);
 555         if (pfb->zsbuf) {
 556                 uint32_t cpp = util_format_get_blocksize(pfb->zsbuf->format);
 557                 OUT_RING(ring, A4XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
 558                 OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(cpp * gmem->bin_w));
 559         } else {
 560                 OUT_RING(ring, 0x00000000);
 561                 OUT_RING(ring, 0x00000000);
 562         }
 563
 564         OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
 565         if (pfb->zsbuf) {
 566                 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
 567                                 fd4_pipe2depth(pfb->zsbuf->format)));
 568         } else {
 569                 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
 570         }
 571
 572         if (ctx->needs_rb_fbd) {
 573                 fd_wfi(ctx, ring);
 574                 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
 575                 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 576                                 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 577                 ctx->needs_rb_fbd = false;
 578         }
 579 }
 580
 581 /* before IB to rendering cmds: */
 582 static void
 583 fd4_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
 584 {
 585         struct fd_ringbuffer *ring = ctx->ring;
 586         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 587         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 588
 589         uint32_t x1 = tile->xoff;
 590         uint32_t y1 = tile->yoff;
 591         uint32_t x2 = tile->xoff + tile->bin_w - 1;
 592         uint32_t y2 = tile->yoff + tile->bin_h - 1;
 593
 594         OUT_PKT3(ring, CP_SET_BIN, 3);
 595         OUT_RING(ring, 0x00000000);
 596         OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
 597         OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
 598
 599         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w);
 600
 601         /* setup scissor/offset for current tile: */
 602         OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
 603         OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(tile->xoff) |
 604                         A4XX_RB_BIN_OFFSET_Y(tile->yoff));
 605
 606         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 607         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 608                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 609         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 610                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 611 }
 612
 613 void
 614 fd4_gmem_init(struct pipe_context *pctx)
 615 {
 616         struct fd_context *ctx = fd_context(pctx);
 617
 618         ctx->emit_sysmem_prep = fd4_emit_sysmem_prep;
 619         ctx->emit_tile_init = fd4_emit_tile_init;
 620         ctx->emit_tile_prep = fd4_emit_tile_prep;
 621         ctx->emit_tile_mem2gmem = fd4_emit_tile_mem2gmem;
 622         ctx->emit_tile_renderprep = fd4_emit_tile_renderprep;
 623         ctx->emit_tile_gmem2mem = fd4_emit_tile_gmem2mem;
 624 }